Semiconductor device

Abstract

A semiconductor device includes: a substrate including an active region extending in a first direction; a gate structure extending on the substrate in a second direction intersecting the active region; a source / drain region located in a recessed region of the active region on at least one side of the gate structure; a first conductive structure connected to the source / drain region; and a first contact spacer. The first conductive structure includes a first interconnect portion, a first via portion extending from a lower surface of the first interconnect portion, and a first contact barrier layer located on the lower surface of the first interconnect portion and on a side surface and a lower surface of the first via portion. The first contact spacer extends below the first interconnect portion along at least a portion of the side surface of the first via portion.

Description

Technical Field

[0001] Example embodiments of this disclosure relate to a semiconductor device, such as a semiconductor device including a contact plug connected to a peripheral transistor and a conductive structure located on the contact plug. Background Technology

[0002] Studies have been conducted on reducing the size of components included in semiconductor devices and improving their performance. For example, for dynamic random access memory (DRAM), studies have been conducted on reliably and stably forming components with reduced dimensions; however, as the size of the components decreases, the performance of the semiconductor device tends to deteriorate accordingly. Summary of the Invention

[0003] The exemplary embodiments disclosed herein provide semiconductor devices with improved reliability.

[0004] According to an example embodiment of this disclosure, a semiconductor device includes: a first structure including a memory region; and a second structure perpendicularly overlapping the first structure and including a peripheral circuit region perpendicularly overlapping the memory region. The first structure includes: memory cells located within the memory region, each memory cell including a vertical channel transistor and a data storage structure; and a cell routing interconnect structure connected to the memory cells. The second structure includes: a peripheral transistor including a gate structure and a source / drain region; a first contact plug connected to the source / drain region; and a first conductive structure connected to the first contact plug. The first conductive structure includes a first pass portion contacting the first contact plug and a first interconnect portion extending from the first pass portion on the first pass portion, wherein the width of the first pass portion in a first direction is smaller than the width of the first interconnect portion in the first direction.

[0005] According to an example embodiment of this disclosure, a semiconductor device includes: a substrate including an active region extending in a first direction; a gate structure extending on the substrate in a second direction intersecting the active region; a source / drain region located in a recessed region of the active region on at least one side of the gate structure; a first conductive structure connected to the source / drain region; and a first contact spacer. The first conductive structure includes a first interconnect portion, a first passage portion extending from a lower surface of the first interconnect portion, and a first contact barrier layer located on the lower surface of the first interconnect portion and on the side and lower surfaces of the first passage portion. The first contact spacer extends relative to the substrate below the first interconnect portion along at least a portion of the side surface of the first passage portion.

[0006] According to an example embodiment of this disclosure, a semiconductor device includes: a first structure having a storage region; and a second structure perpendicularly overlapping the first structure and including a peripheral circuit region perpendicularly overlapping the storage region. The first structure includes: storage cells located in the storage region, each storage cell including a vertical channel transistor and a data storage structure; and a cell routing interconnect structure connected to the storage cells. The second structure includes: a substrate including an active region extending in a first direction; a peripheral gate structure extending on the substrate in a second direction intersecting the active region; a source / drain region located in a recessed region of the active region on at least one side of the peripheral gate structure; a first contact plug connected to the source / drain region; a second contact plug connected to the peripheral gate structure; a first conductive structure connected to the first contact plug; a second conductive structure connected to the second contact plug; a first contact spacer; and a second contact spacer. The first conductive structure includes a first pass portion contacting the first contact plug and a first interconnect portion extending from the first pass portion in the second direction on the first pass portion. The second conductive structure includes a second pass portion contacting the second contact plug and a second interconnect portion extending from the second pass portion in the second direction on the second pass portion and spaced apart from the first interconnect portion in the first direction. The first contact spacer is located between the first contact plug and the first interconnect portion of the first conductive structure and is located on the side surface of the first passage portion. The second contact spacer is located between the second contact plug and the second interconnect portion of the second conductive structure and is located on the side surface of the second passage portion. Attached Figure Description

[0007] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A This is a perspective view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 1B It is shown Figure 1A A perspective view of the memory cell of the semiconductor device shown; Figure 1C It is shown Figure 1A The circuit diagram of the first structure in the memory cell array region of the semiconductor device shown; Figure 2A It is shown Figure 1A A top view of the peripheral circuitry of the semiconductor device and the interconnection structure connected to the peripheral circuitry. Figure 2B It is shown Figure 2A A top view of a portion of an element in the semiconductor device shown; Figure 2C It is shown Figure 2A A top view of other parts of the semiconductor device shown; Figure 3 This shows the section intercepted along line I-I'. Figure 2A A cross-sectional view of the semiconductor device shown; Figure 4 This shows the section taken along line II-II'. Figure 2A A cross-sectional view of the semiconductor device shown; Figure 5 This shows the section intercepted along line III-III'. Figure 2A A cross-sectional view of the second structure of the semiconductor device shown; Figure 6 It is shown Figure 3 An enlarged view of region "A" of the semiconductor device shown; Figure 7 It is shown Figure 4 An enlarged view of region "B" of the semiconductor device shown; Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E These are examples illustrating other exemplary embodiments according to this disclosure. Figure 3 An enlarged view of region "A" of the semiconductor device shown; Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H and Figure 9I This is a diagram illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F and Figure 10G This is a diagram illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present disclosure; Figure 11A , Figure 11Band Figure 11C This is a diagram illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present disclosure; Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E and Figure 12F This is a diagram illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment of the present disclosure. Detailed Implementation

[0008] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0009] Figure 1A This is a perspective view showing a semiconductor device according to an example embodiment. Figure 1B It is shown Figure 1A A perspective view of the memory cell of the semiconductor device shown. Figure 1C It is shown Figure 1A The circuit diagram shows the first structure in the memory cell array region of the semiconductor device.

[0010] refer to Figure 1A and Figure 1B The semiconductor device 1 may include a first structure ST1 and a second structure ST2 that overlaps the first structure ST1 perpendicularly. The second structure ST2 may be disposed on the first structure ST1.

[0011] The first structure ST1 can be configured as a first chip structure including memory cells, and the second structure ST2 can be configured as a second chip structure including peripheral circuitry capable of operating the memory cells. The first structure ST1 and the second structure ST2 can be bonded to each other via a bonding process such as a wafer bonding process. Therefore, the first structure ST1 can contact and be bonded to the second structure ST2.

[0012] Semiconductor device 1 may include multiple memory banks BA and peripheral regions PERI. The peripheral regions PERI may include a first peripheral region PERI1 located in a first structure ST1 and a second peripheral region PERI2 located in a second structure ST2. The peripheral regions PERI may be configured to house peripheral circuitry for inputting and outputting data or commands, or for inputting power / ground.

[0013] Each of the multiple memory banks BA may include a first memory bank region BA1 located in the first structure ST1 and a second memory bank region BA2 located in the second structure ST2.

[0014] refer to Figure 1B and Figure 1CThe first storage area BA1 located in the first structure ST1 may include a storage cell array area CA. The storage cell array area CA may include storage cells. In the example embodiment, the storage cell array area CA may be referred to as a storage area.

[0015] The memory cell array region CA can be arranged in a first direction (X direction) and a second direction (Y direction). Each memory cell array region CA may include memory cells MC arranged in the first direction (X direction) and the second direction (Y direction), word lines WL connected to memory cells MC and extending in the first direction X, and bit lines BL connected to memory cells MC and extending in the second direction Y.

[0016] Each memory cell MC may include a cell transistor cTR and a data storage structure DS that functions as data storage. In memories such as DRAM, the data storage structure DS may be constructed as a cell capacitor capable of storing data.

[0017] Each memory cell array region CA may also include a back gate line BG. Each back gate line BG may be disposed between a pair of adjacent word lines WL in the second direction (Y direction). Each back gate line BG may be disposed between the channel regions of the cell transistor cTR.

[0018] The second memory cell region BA2 located in the second structure ST2 may include a peripheral circuit region PC. The peripheral circuit region PC may be arranged in a first direction (X direction) and a second direction (Y direction). The peripheral circuit region PC may overlap with the memory cell array region CA in the vertical direction (Z direction). Each peripheral circuit region PC may include sense amplifier regions SAR1 and SAR2, a sub-word line driver region SWDR, and an inner peripheral region CONR. In each peripheral circuit region PC, sense amplifier regions SAR1 and SAR2 may be a first sense amplifier region SAR1 and a second sense amplifier region SAR2 spaced apart from each other in the second direction (Y direction). In each peripheral circuit region PC, the sub-word line driver region SWDR and the inner peripheral region CONR may be located between the first sense amplifier region SAR1 and the second sense amplifier region SAR2. In each peripheral circuit region PC, the inner peripheral region CONR may include control circuitry that can control the sense amplifiers of sense amplifier regions SAR1 and SAR2 and the sub-word line driver of the sub-word line driver region SWDR.

[0019] The first direction (X-direction) and the second direction (Y-direction) can be perpendicular to each other. The first direction (X-direction) and the second direction (Y-direction) can be referred to as horizontal directions, and the third direction (Z-direction) can be referred to as vertical directions.

[0020] Figure 2A It is shown Figure 1A A top view of the peripheral circuitry of the semiconductor device and the interconnection structure connected to the peripheral circuitry. Figure 2B It is shown Figure 2A A top view of a portion of an element of the semiconductor device shown. Figure 2C It is shown Figure 2A A top view of another part of the components of the semiconductor device shown.

[0021] Figure 2A Show Figure 1A The layout of the peripheral circuit and the interconnect structure connected to the peripheral circuit of the second structure ST2 of the semiconductor device 1. Figure 2B The layout of a substrate 101 including an active region, a first contact plug 160, and a gate electrode 130 is shown. Figure 2C The layout of conductive structures 140 connected to the peripheral circuit area and interconnect structures 170, 171 and 173 is shown.

[0022] refer to Figure 2A , Figure 2B and Figure 2C The semiconductor device 1 may include a substrate 101 having an active region 105, a second bonding and adhesion layer 109 disposed below the substrate 101, a gate electrode 130 disposed on the substrate 101, and a source / drain region disposed between the gate electrodes 130 and connected to the source / drain region (e.g., Figure 3 The source / drain region 150 in the middle has a first contact plug 160, a second contact plug 160g connected to the gate electrode 130, a conductive structure 140 connected to the first contact plug 160 and the second contact plug 160g, and interconnect structures 170, 171 and 173 connected to the conductive structure 140.

[0023] Substrate 101 may have an upper surface extending in a first direction (X direction) and a second direction (Y direction). Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0024] Substrate 101 may include an active region 105 disposed thereon. The active region 105 may have a fin structure. The active region 105 may be separated by a device isolation layer (e.g., in the substrate 101). Figure 4The device isolation layer 110 in the substrate is defined and can extend in a first direction (X direction). However, this disclosure fully contemplates that the active region 105 can be constructed separately from the substrate 101.

[0025] Substrate 101 may include a first region R1 and a second region R2 spaced apart from the first region R1 in a second direction (Y direction). In an example, each of the first region R1 and the second region R2 may include an active region 105 extending in the first direction. For example, each of the first region R1 and the second region R2 may have a first active region 105a to a fourth active region 105d. The first active regions 105a to the fourth active regions 105d disposed in the first region R1 and the first active regions 105a to the fourth active regions 105d disposed in the second region R2 may be formed by a trench structure (e.g., Figure 5 The groove structure 107 in the middle is used for separation.

[0026] The gate electrode 130 may intersect with the active region 105 and may extend in the active region 105 in a second direction (Y direction). The active region 105 intersecting with the gate electrode 130 may form the functional channel region of the peripheral transistor.

[0027] The gate electrodes 130, which are respectively disposed in the first region R1 and the second region R2, can extend in the second direction (Y direction) and can be spaced apart from each other in the first direction (X direction).

[0028] The gate electrode 130 may include a dummy gate electrode 130m that is not electrically connected. For example, in the gate electrode 130 disposed in the first region R1, the gate electrode disposed at both ends in the first direction (X direction) may be a dummy gate electrode 130m. The dummy gate electrode 130m may be disposed between the gate electrodes 130 that are electrically connected to each other in the gate electrode 130 disposed in the second region R2.

[0029] The second contact plug 160g can be disposed on the gate electrode 130 and can be electrically connected to the gate electrode 130. The gate electrode 130 not connected to the second contact plug 160g can be referred to as the dummy gate electrode 130m. The second contact plug 160g may not overlap with the active region 105.

[0030] The first contact plug 160 can be disposed between the gate electrodes 130 and can be connected to the source / drain region (e.g., Figure 3The source / drain regions 150 in the first region R1 and the second region R2 are respectively disposed in the first region R1 and the second region R2. The first contact plugs 160 can extend in the second direction (Y direction) and can be spaced apart from each other in the first direction (X direction). Each first contact plug 160 can be disposed across the first active region 105a to the fourth active region 105d. In the example, the first contact plugs 160 can be disposed between the gate electrodes 130 disposed in the first region R1. The first contact plugs 160 can be disposed between the gate electrodes 130 disposed in the second region R2, and the first contact plugs 160 may not be disposed between a portion of the gate electrodes 130 disposed in the second region R2. In the example, the length of each first contact plug 160 in the second direction (Y direction) can be less than the length of each gate electrode 130 in the second direction (Y direction).

[0031] The conductive structure 140 can be disposed on the first contact plug 160 and the second contact plug 160g. The conductive structure 140 can extend throughout the first region R1 and the second region R2 in the second direction (Y direction) and can be spaced apart from each other in the first direction (X direction).

[0032] The conductive structure 140 may include a first conductive structure 140a and a second conductive structure 140b. The first conductive structure 140a and the second conductive structure 140b may be alternately arranged in a first direction (X direction).

[0033] Each first conductive structure 140a may be disposed throughout the first region R1 and the second region R2, and may overlap with the first contact plug 160 disposed in the first region R1 and the second region R2 in the vertical direction (Z direction). The second conductive structure 140b may be disposed throughout the first region R1 and the second region R2, and may overlap with the gate electrode 130 disposed in the first region R1 and the second region R2 in the vertical direction (Z direction).

[0034] refer to Figure 2C The conductive structure 140 may further include a third conductive structure 140c and fourth conductive structures 140a_2 and 140b_2. Each third conductive structure 140c may be disposed between a first conductive structure 140a and a second conductive structure 140b.

[0035] The third conductive structure 140c may be disposed throughout the first region R1 and the second region R2, and may include a first extension portion 141c that overlaps with one of the first contact plugs 160 disposed in the first region R1 and extends in the second direction (Y direction), a curved portion 142c that extends from the first extension portion 141c and extends in the first direction (X direction), and a second extension portion 143c that extends from the curved portion 142c, overlaps with the dummy gate electrode 130m of the second region R2, and extends in the second direction (Y direction).

[0036] The fourth conductive structures 140a_2 and 140b_2 may include a fourth-first conductive structure 140a_2 disposed in the second region R2 and a fourth-second conductive structure 140b_2 disposed in the first region R1. The fourth-first conductive structure 140a_2 may be spaced apart from the first extension portion 141c of the third conductive structure 140c in the first direction (X direction) and from the second extension portion 143c in the second direction (Y direction), and may overlap with the first contact plug 160. The fourth-second conductive structure 140b_2 may be spaced apart from the second extension portion 143c of the third conductive structure 140c in the first direction (X direction) and from the first extension portion 141c in the second direction (Y direction), and may overlap with the gate electrode 130.

[0037] Interconnect structures 170, 171, and 173 may include a first interconnect structure 170 and second interconnect structures 171 and 173. The first interconnect structure 170 may be disposed on the conductive structure 140 and may extend in a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction). In an example, the first interconnect structure 170 may be disposed on the conductive structure 140 in a direction intersecting the conductive structure 140. The second interconnect structures 171 and 173 may be disposed between the first interconnect structures 170 spaced apart from each other along the second direction (Y direction). Each of the second interconnect structures 171 and 173 disposed between the first interconnect structures 170 may extend in the first direction (X direction). The second interconnect structures 171 and 173 may include a second-first interconnect structure 171 and a second-second interconnect structure 173 spaced apart from the second-first interconnect structure 171 in the first direction (X direction). The length of each of the second interconnect structures 171 and 173 in the first direction (X direction) may be less than the length of the first interconnect structure 170 in the first direction (X direction).

[0038] A portion of the first interconnect structure 170 and portions of the second interconnect structures 171 and 173 can be connected to the first conductive structure 140a and the fourth-1st conductive structure 140a_2 via the third contact plug 166. A portion of the first interconnect structure 170 can be connected to the second conductive structure 140b and the fourth-2nd conductive structure 140b_2 via the fourth contact plug 167.

[0039] Figure 3 It is shown Figure 2A The diagram shows a cross-sectional view of the semiconductor device taken along line I-I'. Figure 4 This shows the section taken along line II-II'. Figure 2A The diagram shows a cross-sectional view of the semiconductor device. Figure 5 This shows the section intercepted along line III-III'. Figure 2A A cross-sectional view of the second structure of the semiconductor device shown. Figure 6 This illustrates an example embodiment. Figure 3 An enlarged view of region "A" of the semiconductor device shown. Figure 7 It is shown Figure 4 An enlarged view of region "B" of the semiconductor device shown.

[0040] Together Figure 1C Let's refer to each other. Figure 3 , Figure 4 and Figure 5 Semiconductor device 1 may include a first structure ST1 and a second structure ST2 in contact with the first structure ST1. In an example, the first structure ST1 may include a cell transistor cTR, a data storage structure DS, and a cell routing interconnect CR electrically connected to the cell transistor cTR and the data storage structure DS, located in the memory cell array region CA.

[0041] The cell transistor cTR may include a bit line BL extending in a first direction (X direction), a word line WL extending in a second direction (Y direction), a back gate line BG extending in the second direction (Y direction), and a cell active region cACT.

[0042] The cell active region cACT may include a semiconductor material that can be used as a channel for a transistor. The cell active region cACT may include at least one of a silicon layer, an oxide semiconductor layer, and a two-dimensional material layer with semiconductor properties. For example, each cell active region cACT may include monocrystalline silicon or polycrystalline silicon. The cell active region cACT may be a strip shape extending in a first direction (X direction) and a second direction (Y direction). Each cell active region cACT may include a first cell source / drain region cSD1, a second cell source / drain region cSD2 disposed at a height higher than the first cell source / drain region cSD1, and a cell channel region cCH located between the first cell source / drain region cSD1 and the second cell source / drain region cSD2. The cell active region cACT may be referred to as a cell semiconductor layer or a vertical channel layer. Each cell transistor cTR may also include a cell gate dielectric layer in contact with the side surface of the cell channel region cCH and the side surface of the word line WL. The portion of the word line WL opposite to the cell channel region cCH may be a gate electrode. The vertical length of each character line WL in the vertical direction (Z direction) can be greater than its width in the first direction (X direction).

[0043] The back gate line BG can be opposite to the side surface of the cell channel region cCH. A back gate dielectric layer can be disposed between the back gate line BG and the cell channel region cCH. The cell channel region cCH can be disposed between the word line WL and the back gate line BG. A pair of adjacent cell active regions cACT can be disposed between a pair of adjacent word lines WL. The back gate line BG can be disposed between a pair of cell active regions cACT. The back gate line BG can be configured as a back gate electrode. The back gate line BG can control the charge accumulated in the cell channel region cCH. The cell channel region cCH can be a floating body disposed between the first cell source / drain region cSD1 and the second cell source / drain region cSD2, and the back gate line BG can suppress or prevent the performance of the cell transistor cTR from deteriorating due to the floating body effect, and can improve the performance of the cell transistor cTR.

[0044] The word line WL can be formed from, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof, but this disclosure is not limited thereto. Each word line WL may comprise a single layer or multiple layers formed of the aforementioned conductive materials. The back gate line BG may comprise at least one conductive material. For example, each back gate line BG can be formed from, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof, but this disclosure is not limited thereto. Each back gate line BG may comprise a single layer or multiple layers formed of the materials described above.

[0045] Bit line BL can be electrically connected to the cell active region cACT. For example, bit line BL can be electrically connected to the first cell source / drain region cSD1 of the cell active region cACT.

[0046] Each bit line BL may be formed from, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof, but this disclosure is not limited thereto. Each bit line BL may comprise a single layer or multiple layers formed of the aforementioned conductive materials. For example, each bit line BL may comprise a first conductive layer 250 and a second conductive layer 252 located on the first conductive layer 250. The first conductive layer 250 may comprise doped silicon, and the second conductive layer 252 may comprise a conductive material among the aforementioned conductive materials whose resistivity is lower than that of the doped silicon.

[0047] The first structure ST1 may further include a shielding conductive structure SL, which includes line portions LP arranged alternately with the bit lines BL and a connecting portion PP covering the upper surface of the bit lines BL. The connecting portion PP may be plate-shaped. The shielding conductive structure SL may be spaced apart from the bit lines BL. The shielding conductive structure SL can mask capacitive coupling between the bit lines BL. For example, the shielding conductive structure SL can reduce the RC delay of the bit lines BL by reducing or preventing parasitic capacitance between the bit lines BL.

[0048] The first structure ST1 may further include a cell routing interconnect CR, word line contact structures 271 and 272, and bit line contact structures 273 and 274. The cell routing interconnect CR may include a first interconnect 270, a second interconnect 237, a first conductive path 275 connecting the first interconnect 270 to each other, and a first through-hole plug 260 connecting the first interconnect 270 below the bit line BL and the second interconnect 237 located on the data storage structure DS to each other. Word line contact structures 271 and 272 can electrically connect the word line WL to the cell routing interconnect CR. Bit line contact structures 273 and 274 can electrically connect the bit line BL to the cell routing interconnect CR.

[0049] The data storage structure DS can be set at a height higher than the word line WL. The data storage structure DS may include a first electrode 261 extending in the vertical direction (Z direction), a second electrode 263 covering the side surface and the bottom surface of the first electrode 261, and a dielectric layer 262 located between the first electrode 261 and the second electrode 263.

[0050] The data storage structure DS may include, for example, cell capacitors for storing data in a memory such as DRAM, but this disclosure is not limited thereto. For example, the data storage structure DS may be configured as a data storage structure of MRAM or a data storage structure of FeRAM.

[0051] The first structure ST1 may further include a contact structure 233 that electrically connects the second cell source / drain region cSD2 to the first electrode 261. Each contact structure 233 may include a plug portion 234 that contacts the cell active region cACT and a pad portion 235 located below the plug portion 234. The data storage structure DS may be disposed on the pad portion 235.

[0052] The first structure ST1 may also include a capacitor interconnect 239 disposed on the capacitor path 236 and a capacitor interconnect 239 disposed on the capacitor path 236 and extending to the outside of the data storage structure DS.

[0053] The first structure ST1 may further include a substrate 10, a first insulating structure 11, a second insulating structure 22, a third insulating layer 21, a fourth insulating layer 20, a fifth insulating structure 15, and a first bonding and adhesion layer 19 located on the substrate 10.

[0054] The first insulating structure 11 can be disposed on the substrate 10. Bit lines BL, shielding conductive structures SL, word line contact structures 271 and 272, bit line contact structures 273 and 274, the first interconnect 270, and the first conductive path 275 can be disposed in the first insulating structure 11. The unit transistor cTR and the back gate line BG can be disposed in the second insulating structure 22. The third insulating layer 21 can be disposed on the side surface of the plug portion 234. The fourth insulating layer 20 can be disposed on the side surface of the pad portion 235. The data storage structure DS and the second interconnect 237 can be disposed in the fifth insulating structure 15. The first through plug 260 can penetrate the first insulating structure 11, the second insulating structure 22, the third insulating layer 21, the fourth insulating layer 20, and a portion of the fifth insulating structure 15. The first bonding adhesive layer 19 can be disposed on the fifth insulating structure 15. The first bonding adhesive layer 19 can be a part of the fifth insulating structure 15, and the upper surface of the first bonding adhesive layer 19 can be bonded to the second bonding adhesive layer 109 of the second structure ST2. Therefore, the upper surface of the first structure ST1 and the lower surface of the second structure ST2 can join each other and form a joining surface.

[0055] refer to Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 The second structure ST2 may include: a second bonding and adhesion layer 109; a substrate 101 including an active region 105 located on the second bonding and adhesion layer 109; a gate structure GS including a gate electrode 130 extending alternately with the active region 105; a source / drain region 150; a first contact plug 160 connected to the source / drain region 150; a second contact plug 160g connected to the gate electrode 130; a first conductive structure 140a disposed on the first contact plug 160; a second conductive structure 140b disposed on the second contact plug 160g; a third contact plug 166 disposed on the first conductive structure 140a; a fourth contact plug (e.g., a fourth contact plug 167) located on the second conductive structure 140b; a first interconnect structure 170 disposed on the third contact plug 166 and the fourth contact plug 167; and second interconnect structures 171 and 173.

[0056] The substrate 101 may include an active region 105 disposed on its upper side. The active region 105 may have a fin structure. The active region 105 may partially protrude from the device isolation layer 110, such that the upper surface of the active region 105 may be at a height higher than the upper surface of the device isolation layer 110. The active region 105 may be formed as part of the substrate 101, or may include an epitaxial layer grown from the substrate 101. The active region 105 may be partially recessed on both sides of the gate structure GS and may form recessed regions, and the source / drain region 150 may be disposed in the recessed regions.

[0057] The active region 105 may or may not include a well region containing impurities. For example, for a P-type transistor pFET, the well region may include N-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), and for an N-type transistor nFET, the well region may include P-type impurities such as boron (B), gallium (Ga), or indium (In). The well region may be located at a predetermined depth from, for example, the upper surface of the active region 105.

[0058] Device isolation layer 110 may define an active region 105 in substrate 101. Device isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. Device isolation layer 110 may expose the upper surface of active region 105, and may also expose a portion of the upper part of active region 105. Device isolation layer 110 may be formed of an insulating material. Device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0059] The second structure ST2 may include a device isolation pattern 107 for separating the active region 105 in the first region R1 and the active region 105 in the second region R2 between the first region R1 and the second region R2. The device isolation pattern 107 may have a trench shape buried from the upper surface to the lower surface of the substrate 101. The device isolation pattern 107 may extend in a first direction (X direction) and its width may decrease downward.

[0060] Each gate structure GS may include: a gate electrode 130; a gate dielectric layer 132 located between the gate electrode 130 and the active region 105; a gate cover pad 134 surrounding the side surface of the gate dielectric layer 132, the upper surface of the gate electrode 130, and the side surface of the gate electrode 130; and a gate spacer 135 located on the side surface of the gate electrode 130. The gate cover pad 134 of the gate structure GS may not be provided.

[0061] The gate electrodes 130 may be spaced apart from each other in a first direction (X direction) and may extend in a second direction (Y direction).

[0062] The gate electrode 130 may include: a conductive material, such as a metal nitride like titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN) and / or a metallic material like aluminum (Al), tungsten (W), or molybdenum (Mo); or a semiconductor material, such as doped polycrystalline silicon. In an example embodiment, the gate electrode 130 may include two or more multilayers.

[0063] The gate structure GS may overlap with four active regions 105 having fin structures in the vertical direction (Z direction). However, exemplary embodiments thereof are not limited to this, and for example, the gate structure GS may overlap with two or three active regions 105 having fin structures in the vertical direction (Z direction).

[0064] A gate dielectric layer 132 may be disposed between the active region 105 and the gate electrode 130. The gate dielectric layer 132 may include oxides, nitrides, or high-k materials. High-k materials can refer to dielectric materials with a dielectric constant higher than that of silicon oxide (SiO2) films. High-k materials can also refer to dielectric materials with a higher dielectric constant compared to silicon oxide (SiO2) films. Examples of high-k materials include, for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y At least one of praseodymium oxide (Pr₂O₃) and praseodymium oxide (Pr₂O₃). In an example embodiment, the gate dielectric layer 132 may be formed of a multilayer film.

[0065] The gate cover pad 134 may cover the upper surface of the gate electrode 130 and may extend to the region between the side surface of the gate electrode 130 and the gate spacer 135, and between the side surface of the gate dielectric layer 132 and the gate spacer 135, up to the upper surface of the active region 105. The gate spacer 135 may surround the side surface of the gate electrode 130 and the side surface of the gate dielectric layer 132. The gate cover pad 134 and the gate spacer 135 may be formed of at least one of oxides, nitrides, and oxide oxynitrides (e.g., a low-k film).

[0066] The source / drain region 150 may be disposed in a recessed region formed by recessing a portion of the active region 105 on both sides of the gate structure GS. The source / drain region 150 may include a semiconductor material, such as at least one of silicon (Si) and germanium (Ge), and may also include a dopant. For example, when the semiconductor device 1 is configured as a pFET, the dopant may be at least one of boron (B), gallium (Ga), and indium (In). The source / drain region 150 may be formed from an epitaxial layer.

[0067] The second structure ST2 may further include an insulating structure 190 disposed between the gate structures GS. The insulating structure 190 may include an insulating pad 192 and a spacer 194. The insulating pad 192 may extend from a side surface of the gate structure GS to the source / drain region 150, and the spacer 194 may be disposed on the insulating pad 192. Each of the insulating pad 192 and the spacer 194 may include at least one of oxides, nitrides, and oxynitrides. The insulating pad 192 may include a material different from, for example, the material of the spacer 194, but this disclosure is not limited thereto. For example, the insulating pad 192 may include silicon nitride, and the spacer 194 may include silicon oxide.

[0068] The second structure ST2 may further include a first insulating pad 111 located on the gate structure GS and the insulating structure 190, a first insulating layer 113 located on the first insulating pad 111, and a second insulating pad 115 located on the first insulating layer 113. In an example, the first insulating pad 111 and the second insulating pad 115 may include a first insulating material, and the first insulating layer 113 may include a second insulating material different from the first insulating material. For example, the first insulating material may be formed of at least one of nitrides and oxynitrides. The second insulating material may include silicon oxide. In an example, the first insulating pad 111 and the second insulating pad 115 may include different insulating materials.

[0069] The first contact plug 160 can penetrate the insulating structure 190 and the first insulating pad 111, can connect to the source / drain region 150, and can apply an electrical signal to the source / drain region 150. In an example, the first contact plug 160 can be recessed into the source / drain region 150 and can extend into the source / drain region 150. In an example, each first contact plug 160 may include a first conductive pattern 161 and a first conductive barrier layer 163 surrounding the side and bottom surfaces of the first conductive pattern 161.

[0070] The second contact plug 160g can penetrate the insulating structure 190 and the first insulating pad 111, can be connected to the gate electrode 130, and can apply an electrical signal to the gate electrode 130. In the example, the second contact plug 160g can penetrate the first insulating pad 111, can be recessed into the gate electrode 130, and can extend into the gate electrode 130. In the example, each second contact plug 160g may include a second conductive pattern 161g and a second conductive barrier layer 163g surrounding the side and bottom surfaces of the second conductive pattern 161g. In the example, each of the first conductive pattern 161 and the second conductive pattern 161g may include a metallic material such as tungsten, aluminum, or copper. The first conductive barrier layer 163 and the second conductive barrier layer 163g may include metal nitrides such as titanium nitride, tantalum nitride, and tungsten nitride.

[0071] The upper surface of the first contact plug 160 and the upper surface of the second contact plug 160g may be disposed at the same height. The lower surface of the first contact plug 160 may be disposed at a height lower than the lower surface of the second contact plug 160g. As used herein, the term "height" may refer to the distance of an element or layer (or its surface) from or relative to a reference element or layer (or its surface) (e.g., substrate 101). Elements at the same height may have substantially coplanar surfaces.

[0072] The upper surface of the first contact plug 160 and the upper surface of the second contact plug 160g can be disposed between the lower surface of the first insulating layer 113 and the upper surface of the first insulating layer 113. The side surface of the first contact plug 160 can be surrounded by the insulating structure 190, the first insulating gasket 111, and the first insulating layer 113. The side surface of the second contact plug 160g can be surrounded by the first insulating gasket 111 and the first insulating layer 113.

[0073] Each first conductive structure 140a may be connected to the first contact plug 160 and may extend in a second direction (Y direction). Each first conductive structure 140a may include a first passage portion 141a disposed on the first contact plug 160, a first interconnect portion 142a extending from the first passage portion 141a on a second insulating pad 115 in the second direction (Y direction), and a first contact barrier layer 143a covering the side surface and lower surface of the first passage portion 141a and disposed on the lower surface of the first interconnect portion 142a.

[0074] The first passage portion 141a of the first conductive structure 140a may penetrate the first insulating layer 113 and the second insulating pad 115 on the first contact plug 160, and may have a lower surface that contacts the upper surface of the first contact plug 160.

[0075] The horizontal width of the first pass portion 141a of the first conductive structure 140a in the first direction (X direction) may be smaller than the horizontal width of the first pass portion 141a in the second direction (Y direction).

[0076] The first interconnect portion 142a of the first conductive structure 140a may extend from the first pass portion 141a on the first pass portion 141a. The first interconnect portion 142a of the first conductive structure 140a may extend in the second direction (Y direction) on the second insulating pad 115. The width of the first pass portion 141a in the first direction (X direction) may be smaller than the width of the first interconnect portion 142a in the first direction (X direction).

[0077] Each second conductive structure 140b can be connected to the second contact plug 160g and can extend in a second direction (Y direction). Each second conductive structure 140b may include a second passage portion 141b disposed on the second contact plug 160g, a second interconnect portion 142b extending from the second passage portion 141b on the second insulating gasket 115 and extending in the second direction (Y direction), and a second contact barrier layer 143b covering the side surface and lower surface of the second passage portion 141b and disposed on the lower surface of the second interconnect portion 142b. In the example, the lower surface of the second passage portion 141b of the second conductive structure 140b may be disposed at the same height as the lower surface of the first passage portion 141a of the first conductive structure 140a. The upper surface of the second interconnect portion 142b of the second conductive structure 140b may be coplanar with the upper surface of the first interconnect portion 142a of the first conductive structure 140a.

[0078] The first pass portion 141a and the first interconnect portion 142a of the first conductive structure 140a, and the second pass portion 141b and the second interconnect portion 142b of the second conductive structure 140b may include metal nitrides such as titanium nitride, tantalum nitride, or tungsten nitride. The first contact barrier layer 143a of the first conductive structure 140a and the second contact barrier layer 143b of the second conductive structure 140b may include metal nitrides such as titanium nitride, tantalum nitride, or tungsten nitride.

[0079] The second passage portion 141b of the second conductive structure 140b may penetrate the first insulating layer 113 and the second insulating pad 115 on the second contact plug 160g, and may have a lower surface that contacts the upper surface of the second contact plug 160g.

[0080] The second interconnect portion 142b of the second conductive structure 140b may extend from the second passage portion 141b on the second passage portion 141b. The second interconnect portion 142b of the second conductive structure 140b may be disposed on the second insulating pad 115 and may extend in the second direction (Y direction). The width of the second passage portion 141b in the first direction (X direction) may be smaller than the width of the second interconnect portion 142b in the first direction (X direction).

[0081] The first conductive structure 140a and the second conductive structure 140b can be alternately arranged in the first direction (X direction).

[0082] The second structure ST2 may further include a first insulating pattern 117 disposed between the first interconnect portion 142a of the first conductive structure 140a and the second interconnect portion 142b of the second conductive structure 140b. The first insulating pattern 117 may be disposed on the side surfaces of the first interconnect portion 142a and the second interconnect portion 142b. The upper surface of the first insulating pattern 117 may be coplanar with the upper surfaces of the first conductive structure 140a and the second conductive structure 140b.

[0083] The upper surface of the first conductive structure 140a can be set at the same height as the upper surface of the second conductive structure 140b. The lower surface of the first conductive structure 140a can be set at a lower height than the lower surface of the second conductive structure 140b.

[0084] The second structure ST2 may further include a first contact spacer 145 disposed on the side surface of the first passage portion 141a of the first conductive structure 140a and a second contact spacer 146 disposed on the side surface of the second passage portion 141b of the second conductive structure 140b.

[0085] The first contact spacer 145 can penetrate the second insulating gasket 115 and can be disposed on the side surface of the first passage portion 141a between the first contact plug 160a and the first interconnection portion 142a of the first conductive structure 140a. The second contact spacer 146 can penetrate the second insulating gasket 115 and can be disposed on the side surface of the second passage portion 141b between the second contact plug 160a and the second interconnection portion 142b of the second conductive structure 140b.

[0086] The first contact spacer 145 may overlap with the first contact plug 160a in the vertical direction (Z direction). The second contact spacer 146 may overlap with the second contact plug 160g in the vertical direction (Z direction).

[0087] The side surface of the first contact spacer 145 may contact the first insulating layer 113, the second insulating pad 115 and the first insulating pattern 117.

[0088] The side surface of the first contact spacer 145 may be disposed on a line extending upward from the side surface of the first contact plug 160. The side surface of the first contact spacer 145 may contact the first insulating layer 113 and the second insulating pad 115, and the side surface of the upper region of the first contact spacer 145 may be exposed from the second insulating pad 115. The side surface of the upper region of the first contact spacer 145 exposed from the second insulating pad 115 may contact the first insulating pattern 117. In the example, the side surface of the second contact spacer 146 may be disposed on a line extending upward from the side surface of the second contact plug 160g. The side surface of the second contact spacer 146 may contact the first insulating layer 113 and the second insulating pad 115, and the side surface of the upper region of the second contact spacer 146 may be exposed from the second insulating pad 115.

[0089] The second insulating pad 115 may include a first portion overlapping the first insulating pattern 117 and a second portion overlapping the first conductive structure 140a and the second conductive structure 140b. The second portion of the second insulating pad 115 may overlap with a first interconnect portion 142a of the first conductive structure 140a and a second interconnect portion 142b of the second conductive structure 140b. In this example, the thickness of the first portion of the second insulating pad 115 may be less than the thickness of the second portion. The upper surface of the first portion of the second insulating pad 115 may be at a height lower than the height of the upper surface of the second portion.

[0090] The width of the lower surface of the first passage portion 141a of the first conductive structure 140a in the first direction (X direction) may be smaller than the width of the upper surface of the first contact plug 160 in the first direction (X direction). The width of the lower surface of the second passage portion 141b of the second conductive structure 140b in the first direction (X direction) may be smaller than the width of the upper surface of the second contact plug 160g in the first direction (X direction).

[0091] The upper surface of the first contact plug 160 and the lower surface of the first passage portion 141a of the first conductive structure 140a can be disposed between the lower surface and the upper surface of the first insulating layer 113. In the example, the upper surface of the first contact plug 160 and the lower surface of the first passage portion 141a of the first conductive structure 140a can be disposed adjacent to the lower surface of the first insulating layer 113 between the lower surface and the upper surface of the first insulating layer 113. However, the example embodiment is not limited to this, and the upper surface of the first contact plug 160 and the lower surface of the first passage portion 141a of the first conductive structure 140a can be disposed adjacent to the upper surface of the first insulating layer 113. The position of the upper surface of the first contact plug 160 and the position of the lower surface of the first passage portion 141a of the first conductive structure 140a can vary between the lower surface and the upper surface of the first insulating layer 113.

[0092] According to an example embodiment, the semiconductor device 1 may include a first contact plug 160 connected to a source / drain region 150, a second contact plug 160g connected to a gate structure GS, a first conductive structure 140a connected to the first contact plug 160, and a second conductive structure 140b connected to the second contact plug 160g and alternately disposed with the first conductive structure 140a in a first direction (X direction). The semiconductor device 1 may also include a first contact spacer 145 disposed on the side surface of a first pass portion 141a of the first conductive structure 140a and a second contact spacer 146 disposed on the side surface of a second pass portion 141b of the second conductive structure 140b, thereby ensuring a spacing distance between a first interconnect portion 142a of the first conductive structure 140a and a second interconnect portion 142b of the second conductive structure 140b adjacent to the first conductive structure 140a, and ensuring a spacing distance between the first pass portion 141a of the first conductive structure 140a and the second interconnect portion 142b of the second conductive structure 140b. Therefore, using the first contact spacer 145 and the second contact spacer 146 to ensure the spacing between structures is advantageous in preventing or significantly reducing the possibility of bridging, especially for bridging between the first conductive structure 140a and the second conductive structure 140b. This disclosure can thus prevent or otherwise limit the potential for bridging that affects operation, which can provide semiconductor devices with improved reliability and electrical properties.

[0093] The second structure ST2 may further include a third insulating pad 119 disposed on the first conductive structure 140a, the second conductive structure 140b, and the first insulating pattern 117, and a second insulating layer 121 disposed on the third insulating pad 119. The third insulating pad 119 may include a first insulating material, and the second insulating layer 121 may include a second insulating material different from the first insulating material. For example, the third insulating pad 119 may include silicon nitride and / or silicon oxynitride, and the second insulating layer 121 may include silicon oxide.

[0094] The third contact plug 166 can penetrate the third insulating pad 119 and the second insulating layer 121, and can be disposed on and connected to the first conductive structure 140a. The fourth contact plug 167 can penetrate the third insulating pad 119 and the second insulating layer 121, and can be disposed on and connected to the second conductive structure 140b.

[0095] In the example, the third contact plug 166 may include a third conductive pattern 166a and a third conductive barrier layer 166b covering the side and bottom surfaces of the third conductive pattern 166a. The fourth contact plug 167 may have the same structure as the third contact plug 166.

[0096] The first interconnect structure 170 and the second interconnect structures 171 and 173 may be disposed on the third contact plug 166 and the fourth contact plug 167. Each of the first interconnect structure 170 and the second interconnect structures 171 and 173 may extend in a first direction (X direction). At least one interconnect structure of the first interconnect structure 170 may be connected to the first conductive structure 140a via the third contact plug 166, and at least another interconnect structure of the first interconnect structure 170 may be connected to the second conductive structure 140b via the fourth contact plug 167.

[0097] The second structure ST2 may also include a second insulating pattern 122, a first interlayer insulating layer 123 to a fifth interlayer insulating layer 127, a first vertical passage 174 and a second vertical passage 178, a first horizontal interconnect 172 and a second horizontal interconnect 176, an upper interconnect 180, and a second through plug 60.

[0098] The second insulating pattern 122 may be disposed between the first interconnect structure 170 and the second interconnect structures 171 and 173. The first interlayer insulating layer 123 to the fifth interlayer insulating layer 127 may be stacked sequentially on the first interconnect structure 170 and the second interconnect structures 171 and 173 in the vertical direction (Z direction).

[0099] The first horizontal interconnect 172 can penetrate the second insulating pattern 122. The second through-plug 60 can be connected to the first horizontal interconnect 172 and can penetrate the second insulating layer 121, the first insulating pad 111, the second insulating pad 115, the third insulating pad 119, the first insulating pattern 117, the first insulating layer 113, the insulating structure 190, the substrate 101, and the second bonding adhesion layer 109. The second through-plug 60 can also penetrate the first bonding adhesion layer 19 and the fifth insulating structure 15 of the first structure ST1 and can be connected to at least one second interconnect 237 of the first structure ST1. The first structure ST1 and the second structure ST2 can be electrically connected via the first through-plug 260, the second through-plug 60, and the second interconnect 237.

[0100] The second through plug 60 may include a conductive post 62 and a conductive barrier layer 64 covering the side and bottom surfaces of the conductive post 62.

[0101] A first vertical path 174 can be disposed on and connected to the first interconnect structure 170 and the second interconnect structures 171 and 173. The first vertical path 174 can penetrate the first interlayer insulating layer 123. A second horizontal interconnect 176 can be disposed on the first vertical path 174. The second interlayer insulating layer 124 can cover the side surface of the second horizontal interconnect 176, and the second vertical path 178 can penetrate the second interlayer insulating layer 124, the third interlayer insulating layer 125, the fourth interlayer insulating layer 126, and the fifth interlayer insulating layer 127 and can be connected to the second horizontal interconnect 176. An upper interconnect 180 can be disposed on the fifth interlayer insulating layer 127. The upper interconnect 180 can be connected to the second horizontal interconnect 176 via the second vertical path 178.

[0102] Each of the first vertical path 174 and the second vertical path 175, the first horizontal interconnect 172 and the second horizontal interconnect 176, and the upper interconnect 180 may be formed of, for example, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof, but this disclosure is not limited thereto. However, exemplary embodiments may include a single layer or multiple layers formed of the aforementioned materials.

[0103] Figures 8A to 8E This illustrates an embodiment based on other example embodiments. Figure 3 An enlarged view of region "A" of the semiconductor device shown.

[0104] refer to Figure 8AIt is possible to omit the other components of semiconductor device 1a besides the first contact plug 160'. Figure 6 Descriptions of identical or overlapping components. Figure 8A The semiconductor device 1a in the middle may include those that do not provide Figure 6 The gate structure GS of the gate cover pad 134 of the semiconductor device 1.

[0105] The gate structure GS may include a gate electrode 130, a gate dielectric layer 132 disposed between the gate electrode 130 and the active region 105, and gate spacers 135 disposed on the side surfaces of the gate electrode 130 and the gate dielectric layer 132. The gate spacers 135 may contact the side surfaces of the gate electrode 130, the side surfaces of the gate dielectric layer 132, the upper surface of the active region 105, and the upper surface of the source / drain region 150.

[0106] The insulating structure 190 can be disposed between the gate structures GS.

[0107] The first contact plug 160' can penetrate the first insulating gasket 111 and the spacer 194 and can be connected to the source / drain region 150. The first contact plug 160' can be recessed into the source / drain region 150 and can extend into the source / drain region 150. In an example, the first contact plug 160' can have a single conductive pattern structure without a conductive barrier layer. The first contact plug 160' can include a metallic material such as aluminum or copper other than tungsten.

[0108] refer to Figure 8B As for semiconductor device 1b, it may not be necessary to provide connections to other elements besides the first conductive structure 140a' and the first contact spacer 145'. Figure 6 The overlapping description of elements that are the same or corresponding to each other.

[0109] The second structure ST2 of the semiconductor device 1b may include a substrate 101 having an active region 105, a gate structure GS having a gate electrode 130 alternately extending to the active region 105, a source / drain region 150, a first conductive structure 140a' connected to the source / drain region 150, a second conductive structure 140b' connected to the gate electrode 130, a third contact plug 166 disposed on the first conductive structure 140a', a fourth contact plug (e.g., a fourth contact plug 167) located on the second conductive structure 140b', and second interconnect structures 171 and 173 located on the third contact plug 166.

[0110] The first conductive structure 140a' may include: a first lower region 144a' in contact with the source / drain region 150; a first intermediate region 141a' extending from the first lower region 144a' on the first lower region 144a'; a first upper region 142a' extending from the first intermediate region 141a' on the first intermediate region 141a'; and a first contact barrier layer 143a' covering the side surface and lower surface of the first lower region 144a', the side surface of the first intermediate region 141a', and the lower surface of the first upper region 142a'.

[0111] The first lower region 144a' may be disposed below the first insulating pad 111 and may have a side surface in contact with the insulating structure 190. The first intermediate region 141a' may penetrate the first insulating pad 111, the first insulating layer 113 and the second insulating pad 115, and may extend from the first lower region 144a'. The first upper region 142a' may extend from the first intermediate region 141a', may be disposed on the second insulating pad 115, and may extend in a second direction (Y direction).

[0112] The lower surface of the first lower region 144a' may be recessed into and extend into the source / drain region 150. The first lower region 144a' may be a region that extends further than the first intermediate region 141a' in the first direction (X direction). The width of the first lower region 144a' on the substrate 101 in the first direction (X direction) may be greater than the width of the first intermediate region 141a' in the first direction (X direction). For example, the first lower region 144a' may include a portion whose width in the first direction (X direction) is greater than the width of the first intermediate region 141a'. For example, the lower surface of the first intermediate region 141a' may be connected to the upper surface of the first lower region 144a', and the width of the lower surface of the first intermediate region 141a' in the first direction (X direction) may be less than the width of the upper surface of the first lower region 144a' in the first direction (X direction). The width of the first upper region 142a' in the first direction (X direction) may be greater than the width of the first intermediate region 141a' in the first direction (X direction).

[0113] In the example, the first conductive structure 140a' may include a seam extending in the vertical direction (Z direction) in the first lower region 144a'.

[0114] The second conductive structure 140b' may include: a second lower region (not shown) in contact with the gate electrode 130; a second intermediate region (not shown) extending from the second lower region on the second lower region; a second upper region 142b' extending from the second intermediate region on the second intermediate region; and a second contact barrier layer 143b' covering the side and lower surfaces of the second lower region, the side surface of the second intermediate region, and the lower surface of the second upper region. The width of the second lower region in the first direction (X direction) may be greater than the width of the second intermediate region in the first direction (X direction). The width of the second upper region 142b' in the first direction (X direction) may be greater than the width of the second intermediate region in the first direction (X direction).

[0115] The first conductive structure 140a' and the second conductive structure 140b' can be alternately arranged in the first direction (X direction).

[0116] The second structure ST2 of the semiconductor device 1b may further include a first contact spacer 145' disposed between the first lower region 144a' and the first upper region 142a' of the first conductive structure 140a' and on the side surface of the first intermediate region 141a'. The first contact spacer 145' may penetrate the first insulating pad 111, the first insulating layer 113, and the second insulating pad 115. For example, the first contact spacer 145' may include a portion that overlaps with the first lower region 144a' and the first upper region 142a' in the vertical direction (Z direction).

[0117] The first insulating pattern 117 may be disposed between the first upper region 142a' of the first conductive structure 140a' and the second upper region 142b' of the second conductive structure 140b'.

[0118] refer to Figure 8C As for semiconductor device 1c, it may not be necessary to provide connections to components other than the first contact plug 160" connected to the source / drain region 150 and the first conductive structure 140a" and the second conductive structure 140b". Figure 6 The overlapping description of elements that are the same or corresponding to each other.

[0119] The second structure ST2 of the semiconductor device 1c may include a substrate 101 having a source region 105, a gate structure GS having a gate electrode 130 extending alternately with the active region 105, a source / drain region 150, a first contact plug 160" connected to the source / drain region 150, a second contact plug (not shown) connected to the gate electrode 130, a first conductive structure 140a" located on the first contact plug 160", a second conductive structure 140b" located on the second contact plug (not shown), a third contact plug 166 disposed on the first conductive structure 140a", a fourth contact plug (e.g., a fourth contact plug 167) located on the second conductive structure 140b', and second interconnect structures 171 and 173 located on the third contact plug 166.

[0120] The first contact plug 160" can be disposed between the gate electrodes 130 and can be connected to the source / drain region 150. The first contact plug 160" can penetrate the insulating structure 190, the first insulating pad 111, the first insulating layer 113 and the second insulating pad 115, can be connected to the source / drain region 150, and can apply an electrical signal to the source / drain region 150.

[0121] The first contact plug 160" may include a first conductive pattern 161", a first conductive barrier layer 163" disposed on the lower surface of the first conductive pattern 161" and the lower region of the side surface of the first conductive pattern 161", and a first gap region gap1 disposed on the upper region of the side surface of the first conductive pattern 161".

[0122] The first conductive barrier layer 163" can cover the side surface of the first conductive pattern 161" disposed below the first insulating pad 111 and the lower surface of the first conductive pattern 161".

[0123] The first gap region gap1 may be an air gap extending into the first conductive barrier layer 163". The first gap region gap1 may be a region corresponding to the area exposed from the first conductive barrier layer 163" on the side surface of the first conductive pattern 161". The first gap region gap1 may be disposed on the first conductive barrier layer 163" between the first conductive pattern 161" and the insulating structure 190, between the first conductive pattern 161" and the first insulating pad 111, between the first conductive pattern 161" and the first insulating layer 113, and between the first conductive pattern 161" and the second insulating pad 115.

[0124] In another example embodiment, the first conductive barrier layer 163" may cover the lower surface of the first conductive pattern 161" and may extend to the side surface of the first conductive pattern 161" disposed on the first insulating pad 111. In this case, the lower surface of the first gap region gap1 may be disposed on the first conductive barrier layer 163" extending toward the first insulating pad 111.

[0125] The first conductive structure 140a" can be electrically connected to the first contact plug 160" on the second insulating pad 115. The lower surface of the first conductive structure 140a" can contact the upper surface of the first conductive pattern 161" of the first contact plug 160".

[0126] The first conductive structure 140a" and the second conductive structure 140b" can be alternately arranged in the first direction (X direction). The second conductive structure 140b" can be disposed on the second insulating pad 115 and can be disposed on the second contact plug (not shown) connected to the gate electrode 130.

[0127] A second contact plug (not shown) connected to the gate electrode 130 may penetrate the first insulating pad 111, the first insulating layer 113, and the second insulating pad 115, and may have a lower surface in contact with the gate electrode 130. The second contact plug (not shown) may include a second conductive pattern (not shown), a second conductive barrier layer (not shown) surrounding a lower region of the lower surface of the second conductive pattern and a side surface of the second conductive pattern, and a second gap region (not shown) located on the second conductive barrier layer. The second gap region may correspond to a region exposed from the second conductive barrier layer on a side surface of the second conductive pattern.

[0128] The upper surfaces of the first conductive structure 140a" and the second conductive structure 140b" can be coplanar. The first insulating pattern 117 can be disposed between the first conductive structure 140a" and the second conductive structure 140b".

[0129] According to an example embodiment, the semiconductor device 1c may include a first contact plug 160" having a first gap region gap1, thereby reducing the capacitance between the gate electrode 130 and the first contact plug 160" and providing a semiconductor device with improved electrical properties.

[0130] refer to Figure 8D As for the semiconductor device 1d, it may not be necessary to provide the same contact spacers as those provided in the components other than the auxiliary contact spacers 155 located on the side surface of the first contact plug 160 and the first contact spacers 145" disposed on the first passage portion 141a of the first conductive structure 140a. Figure 6 The overlapping description of elements that are the same or corresponding to each other.

[0131] The auxiliary contact spacer 155 may be disposed on the side surface of the first contact plug 160. The auxiliary contact spacer 155 may include at least one of oxides, nitrides, and oxynitrides.

[0132] The first contact spacer 145" may be disposed on the side surface of the first passage portion 141a between the auxiliary contact spacer 155 and the first interconnect portion 142a. The width of the lower surface of the first contact spacer 145" in the first direction (X direction) may be greater than the width of the upper surface of the first contact plug 160 in the first direction (X direction). The first contact spacer 145" may include portions on the first contact plug 160 and the auxiliary contact spacer 155 that protrude toward the first insulating layer 113.

[0133] refer to Figure 8E In the semiconductor device 1e, it is not necessary to provide connections to components other than the first contact plug 160_1 and the first conductive structure 140a_1 connected to the first contact plug 160_1. Figure 6 The overlapping description of elements that are the same or corresponding to each other.

[0134] The first contact plug 160_1 may be disposed below the first insulating pad 111, may be disposed between the gate electrodes 130, and may be connected to the source / drain region 150. Each first contact plug 160_1 may include a first conductive pattern 161_1, a first conductive barrier layer 163_1 covering a portion of the lower surface and side surface of the first conductive pattern 161_1, and a second gap region gap2 disposed on the lower surface of the first insulating pad 111 on the side surface of the first conductive barrier layer 163_1 and the exposed side surfaces of the first-1 contact spacers 145a and 1-2 contact spacers 145b.

[0135] The second gap region gap2 may be the region between the side surface of the gate spacer 135 and the side surface of the first conductive barrier layer 163_1, and the air gap between the side surfaces of the first-1 contact spacer 145a and the first-2 contact spacer 145b protruding below the first insulating pad 111 and the side surface of the gate spacer 135.

[0136] The first conductive structure 140a_1 can penetrate the first insulating pad 111 and can be partially recessed into the upper surface of the first contact plug 160_1, and can be connected to the first contact plug 160_1.

[0137] The first conductive structure 140a_1 may include a first pass portion 141a_1, a first interconnect portion 142a_1 extending from the first pass portion 141a_1, and a first contact barrier layer 143a_1 covering the lower surface and side surfaces of the first pass portion 141a_1 and the lower surface of the first interconnect portion 142a_1. In an example, the first conductive structure 140a_1 may be spaced apart from the first conductive barrier layer 163_1 of the first contact plug 160_1 in the vertical direction (Z direction).

[0138] The lower surface of the first conductive structure 140a_1 can be positioned at a height lower than that of the first insulating pad 111. The first passage portion 141a_1 can penetrate the first insulating pad 111, the first insulating layer 113, and the second insulating pad 115. The first passage portion 141a_1 can contact the upper surface of the first contact plug 160_1, which is positioned at a height lower than that of the first insulating pad 111.

[0139] The first passage portion 141a_1 may have a lower surface that contacts the upper surface of the first conductive pattern 161_1 of the first contact plug 160_1. The first interconnect portion 142a_1 may extend from the first passage portion 141a_1 to the second insulating pad 115 in a second direction (Y direction). The width of the first passage portion 141a_1 in the first direction (X direction) may be smaller than the width of the first interconnect portion 142a_1 in the first direction (X direction).

[0140] The first-1 contact spacer 145a and the first-2 contact spacer 145b may be disposed on the side surface of the first passage portion 141a_1. The first-2 contact spacer 145b may surround the first passage portion 141a_1 on the side surface of the first passage portion 141a_1 between the first conductive pattern 161_1 and the first interconnect portion 142a_1. The first-1 contact spacer 145a may surround the first-2 contact spacer 145b and may be spaced apart from the upper surface of the first conductive pattern 161_1. The first-2 contact spacer 145b may protrude further downward on the lower surface of the first insulating pad 111 than the first-1 contact spacer 145a. The first-1 contact spacer 145a may not contact the upper surface of the first conductive pattern 161_1. In the example, the first-1 contact spacer 145a may be disposed between the second gap region gap2 of the first contact plug 160_1 and the first interconnect portion 142a_1. In the example, the first contact spacer 145a may not overlap with the first conductive pattern 161_1 of the first contact plug 160_1 in the vertical direction (Z direction).

[0141] The second conductive structure 140b_1 may include: a second passage portion (not shown) in contact with the gate electrode 130b_1; a second interconnect portion 142b_1 extending from the second passage portion to the second insulating pad 115; and a second contact barrier layer 143b_1 covering the lower surface and side surface of the second passage portion and the lower surface of the second interconnect portion 142b_1.

[0142] The first conductive structure 140a_1 and the second conductive structure 140b_1 can be alternately arranged in the first direction (X direction), and the first insulating pattern 117 can be disposed between the first interconnection portion 142a_1 of the first conductive structure 140a_1 and the second interconnection portion 142b_1 of the second conductive structure 140b_1.

[0143] Figures 9A to 9I This is a diagram illustrating a method for manufacturing a semiconductor device according to an example embodiment. See also... Figures 9A to 9I Description of manufacturing Figure 6 The method of semiconductor device 1.

[0144] refer to Figure 9A A method of manufacturing a semiconductor device may include: forming an active region 105 by removing a portion of a substrate 101; forming a gate structure GS on the active region 105; forming a recessed region by removing a portion of the active region 105 exposed between the gate structures GS, and forming a source / drain region 150 in the recessed region; forming an insulating structure 190 between the gate structures GS on the substrate 101; sequentially forming a first insulating pad 111, a first insulating layer 113, and a second insulating pad 115 in the vertical direction (Z direction) on the gate structure GS and the insulating structure 190; and forming a first contact hole OPN1 by removing a portion of each of the insulating structure 190, the first insulating pad 111, the first insulating layer 113, and the second insulating pad 115.

[0145] Forming a gate structure GS may include forming a sacrificial gate structure (not shown), forming a gate spacer 135 on the side surface of each sacrificial gate structure, removing the sacrificial gate structure, and forming a gate dielectric layer 132 and a gate electrode 130 in the region from which the sacrificial gate structure has been removed.

[0146] The formation of a first insulating pad 111, a first insulating layer 113, and a second insulating pad 115 may sequentially include forming the first insulating pad 111 on the gate structure GS and the insulating structure 190, forming the first insulating layer 113 on the first insulating pad 111, and forming the second insulating pad 115 on the first insulating layer 113. The first insulating pad 111 and the second insulating pad 115 may comprise silicon nitride, and the first insulating layer 113 may comprise silicon oxide. The thickness of the first insulating layer 113 in the vertical direction (Z direction) may be greater than the thickness of each of the first insulating pad 111 and the second insulating pad 115.

[0147] The first contact hole OPN1 can be formed by sequentially etching down the second insulating pad 115, the first insulating layer 113, the first insulating pad 111, and the insulating structure 190, and partially recessing the upper surface of the exposed source / drain region 150.

[0148] refer to Figure 9B A first preliminary contact plug 160P can be formed in the first contact hole OPN1. Forming the first preliminary contact plug 160P may include forming a first preliminary conductive barrier layer 163P conformally according to the surface profile of the first contact hole OPN1 and forming a first preliminary conductive pattern 161P on the first preliminary conductive barrier layer 163P.

[0149] refer to Figure 9C The second contact hole OPN2 can be formed by removing a portion of each first preliminary contact plug 160P. Forming the second contact hole OPN2 may include etching each first preliminary contact plug 160P downwards, and may expose the side surface of the first insulating layer 113 and the side surface of the second insulating pad 115. The first preliminary contact plug 160P can be formed by removing a portion of each of the first insulating layer 113 and the second insulating pad 115, thereby forming a first contact plug 160 having an upper surface exposed from the side surface of the first insulating layer 113 and the side surface of the second insulating pad 115.

[0150] refer to Figure 9D A first preliminary spacer layer 145P can be formed covering the upper surface of the second insulating pad 115 and the inner surface of the second contact hole OPN2. The first preliminary spacer layer 145P can be formed conformally along the upper surface of the second insulating pad 115 and the inner surface of the second contact hole OPN2. The first preliminary spacer layer 145P may include at least one of oxides, nitrides, and oxynitrides.

[0151] refer to Figure 9EA third contact hole OPN3, exposing a portion of the upper surface of the first contact plug 160, can be formed by removing the lower surface of the first preliminary spacer layer 145P formed in the second contact hole OPN2. The first contact spacer 145 can be conformally formed on the side surface of the third contact hole OPN3 on the first contact plug 160. During the process of removing the lower surface of the first preliminary spacer layer 145P formed in the second contact hole OPN2, the first preliminary spacer layer 145P formed on the upper surface of the second insulating gasket 115 can also be removed.

[0152] refer to Figure 9F A preliminary conductive structure 140P can be formed on the upper surface of the second insulating pad 115 and the inner surface of the third contact hole OPN3. Forming the preliminary conductive structure 140P may include conformally forming a preliminary contact barrier layer 143P according to the surface profiles of the upper surface of the second insulating pad 115 and the inner surface of the third contact hole OPN3, and forming a preliminary contact conductive layer 141P on the preliminary contact barrier layer 143P. The preliminary contact barrier layer 143P may include metal nitrides such as titanium nitride, tantalum nitride, and tungsten nitride, and the preliminary contact conductive layer 141P may include metallic materials such as tungsten, aluminum, and copper.

[0153] refer to Figure 9G By removing the portion of the preliminary conductive structure 140P formed on the second insulating pad 115 that is located in the upper region between the first contact plugs 160, a fourth opening OPN4 that exposes the upper surface of the second insulating pad 115 can be formed.

[0154] First conductive structures 140a and second conductive structures 140b, which are spaced apart from each other and alternately arranged in the first direction (X direction), can be formed by partially removing the initial conductive structure 140P. Each first conductive structure 140a can be electrically connected to a first contact plug 160, and each second conductive structure 140b can be connected to a second contact plug (e.g., Figure 4 The second contact plug (160g).

[0155] In the process of partially removing the initial conductive structure 140P, the portion of the upper surface of the second insulating pad 115 formed below the initial conductive structure 140P can also be removed. The thickness of the second insulating pad 115 overlapping with the first conductive structure 140a and the second conductive structure 140b can be greater than the thickness of the second insulating pad 115 exposed through the fourth opening OPN4.

[0156] The first conductive structure 140a may include: formed in Figure 9EThe third contact hole OPN3 is surrounded by a first passage portion 141a; a first interconnect portion 142a is formed on the second insulating pad 115 extending from the first passage portion 141a; and a first contact barrier layer 143a is formed on the lower and side surfaces of the first passage portion 141a and the lower surface of the first interconnect portion 142a. The second conductive structure 140b can also be formed by a process similar to that used to form the first conductive structure 140a.

[0157] refer to Figure 9H A first insulating pattern 117 can be formed to fill the fourth opening OPN4. The first insulating pattern 117 can fill the fourth opening OPN4 exposed on the upper surface of the second insulating pad 115 between the first interconnect portion 142a of the first conductive structure 140a and the second interconnect portion 142b of the second conductive structure 140b.

[0158] refer to Figure 9I A third insulating pad 119 and a second insulating layer 121 may be sequentially formed on the first conductive structure 140a, the second conductive structure 140b, and the first insulating pattern 117, and a third contact plug 166 may be formed that penetrates the third insulating pad 119 and the second insulating layer 121 and is connected to the first conductive structure 140a.

[0159] Forming the third contact plug 166 may include forming a contact hole that partially exposes the upper surface of the first conductive structure 140a by partially removing the third insulating liner 119 and the second insulating layer 121, conformally forming a third conductive barrier layer 166b in the contact hole, and forming a third conductive pattern 166a on the third conductive barrier layer 166b.

[0160] From now on, let's refer to each other. Figure 3 and Figure 6 The second interconnect structures 171 and 173 can be formed on the third contact plug 166 (or Figure 2CThe first interconnect structure 170 can be formed, and second interconnect structures 171 and 173 can be formed. A second bonding adhesion layer 109 can be formed on the lower surface of the substrate 101, and the second structure ST2 can be bonded to the pre-formed first structure ST1. After the first structure ST1 and the second structure ST2 are bonded to each other, a second through plug 60 can be formed that penetrates the second insulating layer 121, the first insulating pad 111, the second insulating pad 115, the third insulating pad 119, the first insulating pattern 117, the first insulating layer 113, the insulating structure 190, the substrate 101, the second bonding adhesion layer 109, and the first bonding adhesion layer 19 and the fifth insulating structure 15 of the first structure ST1 and interconnects to at least one second interconnect member 237. After the second through plug 60 is formed, interconnect structures (e.g., ...) are formed on the first horizontal interconnect member 172 and the second interconnect structures 171 and 173. Figure 3 The second horizontal interconnect 176, the first vertical path 174, the second vertical path 178, and the upper interconnect 180 are used to manufacture the semiconductor device 1.

[0161] Figures 10A to 10G This is a diagram illustrating a method of manufacturing a semiconductor device according to another example embodiment. See also... Figures 10A to 10G Description of manufacturing Figure 8B Method of semiconductor device 1b in the process.

[0162] refer to Figure 10A A method of manufacturing a semiconductor device may include: forming an active region 105 by removing a portion of a substrate 101; forming a gate structure GS on the active region 105; forming a recessed region by removing a portion of the active region 105 exposed between the gate structures GS, and forming a source / drain region 150 in the recessed region; forming an insulating structure 190 between the gate structures GS on the substrate 101; sequentially forming a first insulating pad 111, a first insulating layer 113, and a second insulating pad 115 in the vertical direction (Z direction) on the gate structure GS and the insulating structure 190; and forming a first contact hole OPN1a exposing the upper surface of the insulating structure 190 by removing a portion of each of the first insulating pad 111, the first insulating layer 113, and the second insulating pad 115.

[0163] The first contact hole OPN1a can be formed by sequentially etching the second insulating pad 115, the first insulating layer 113, and the first insulating pad 111 downwards. The upper surface of the insulating structure 190 can be exposed through the first contact hole OPN1a.

[0164] refer to Figure 10BA first preliminary spacer layer 145P can be formed to cover the upper surface of the second insulating pad 115 and the inner surface of the first contact hole OPN1a. The first preliminary spacer layer 145P can be formed conformally along the upper surface of the second insulating pad 115 and the inner surface of the first contact hole OPN1a.

[0165] refer to Figure 10C The second contact hole OPN2a can be formed by removing the lower surface of the first preliminary spacer layer 145P and a portion of the insulating structure 190 formed in the first contact hole OPN1a. The second contact hole OPN2a can be formed by etching the lower surface of the first preliminary spacer layer 145P and the insulating structure 190 overlapping with the first preliminary spacer layer 145P and partially recessing the upper surface of the exposed source / drain region 150.

[0166] The first contact spacer 145' can be conformally formed on the side surface of the second contact hole OPN2a on the insulating structure 190. (The text abruptly ends here, seemingly mid-sentence.) Figure 10A In the process of removing the lower surface of the first preliminary spacer layer 145P in the first contact hole OPN1a, the first preliminary spacer layer 145P formed on the upper surface of the second insulating pad 115 can be removed together.

[0167] refer to Figure 10D The third contact hole OPN3a can be formed by removing a portion of the side surface of the insulating structure 190 in the first direction (X direction). The third contact hole OPN3a can be configured as an extended contact hole extending in the first direction (X direction) and exposing the side surface of the insulating structure 190. The first contact spacer 145' can overlap with the extended contact hole in the vertical direction (Z direction). Figure 10D The thickness of each insulating structure 190 in the structure can be less than Figure 10C The thickness of each insulating structure 190. The distance between the side surfaces of the insulating structures 190 exposed through the third contact hole OPN3a in the first direction (X direction) can be greater than the distance between the first contact spacers 145' that are opposite each other.

[0168] refer to Figure 10E A preliminary conductive structure 140P' can be formed on the upper surface of the second insulating pad 115 and the inner surface of the third contact hole OPN3a. Forming the preliminary conductive structure 140P' may include conformally forming a preliminary contact barrier layer 143P' according to the surface profile of the upper surface of the second insulating pad 115 and the surface profile of the inner surface of the third contact hole OPN3a, and forming a preliminary contact conductive layer 141P' on the preliminary contact barrier layer 143P. Figure 10DA seam is formed during the process of filling the extended contact hole with the initial contact conductive layer 141P'. The seam can be configured to extend in the vertical direction (Z direction).

[0169] refer to Figure 10F It can be done in Figure 10D In the upper region between the third contact hole OPN3a, the preliminary conductive structure 140P' formed on the second insulating pad 115 is partially removed to form a fourth opening OPN4a that exposes the upper surface of the second insulating pad 115.

[0170] A first conductive structure 140a' and a second conductive structure 140b' spaced apart from each other and alternately arranged in the first direction (X direction) can be formed by partially removing the initial conductive structure 140P'. Each first conductive structure 140a' can be electrically connected to the source / drain region 150, and each second conductive structure 140b' can be connected to the gate electrode 130.

[0171] The first conductive structure 140a' may include a seam and may include a first lower region 144a' in contact with the source / drain region 150, a first intermediate region 141a' surrounded on the first lower region 144a' by a first contact spacer 145', a first upper region 142a' extending on the first intermediate region 141a' from the first intermediate region 141a', and a first contact barrier layer 143a' covering the side surface of the first intermediate region 141a' and the lower surface of the first lower region 144a'.

[0172] refer to Figure 10G A first insulating pattern 117 can be formed to fill the fourth opening OPN4a. The first insulating pattern 117 can fill the fourth opening OPN4a exposed on the upper surface of the second insulating pad 115 between the first upper region 142a' of the first conductive structure 140a' and the second upper region 142b' of the second conductive structure 140b.

[0173] The reference can be applied in the same way. Figure 9I The described operation.

[0174] Figures 11A to 11C This is a diagram illustrating a method of manufacturing a semiconductor device according to another example embodiment. See also... Figures 11A to 11C Description of manufacturing Figure 8C Method of semiconductor device 1c.

[0175] refer to Figure 11A as well as Figure 9A and Figure 9BA method of manufacturing a semiconductor device may include: forming an active region 105 by removing a portion of a substrate 101; forming a gate structure GS on the active region 105; forming a recessed region by removing a portion of the active region 105 exposed between the gate structures GS; forming a source / drain region 150 in the recessed region; forming an insulating structure 190 between the gate structures GS on the substrate 101; sequentially forming a first insulating pad 111, a first insulating layer 113, and a second insulating pad 115 in the vertical direction (Z direction) on the gate structure GS and the insulating structure 190; forming a first contact hole OPN1 by removing a portion of each of the insulating structure 190, the first insulating pad 111, the first insulating layer 113, and the second insulating pad 115; forming a first preliminary contact plug 160P in the first contact hole OPN1; and forming a first contact plug 160" including a first gap region gap1 by removing a portion of the first preliminary conductive barrier layer 163P.

[0176] The first contact plug 160" may include a first conductive pattern 161", a first conductive barrier layer 163" covering a portion of the lower surface and side surface of the first conductive pattern 161", and a first gap region gap1 exposing the remaining portion of the side surface of the first conductive pattern 161".

[0177] Remove in Figure 9B A portion of the first preliminary conductive barrier layer 163P can be removed by a dry etching process or a wet etching process from the first insulating pad 111 and the second insulating pad 115 with the first conductive pattern 161, and from the first insulating layer 113 with the first conductive pattern 161. However, exemplary embodiments thereof are not limited thereto, and the height to which the first preliminary conductive barrier layer 163P is removed can be determined differently. A portion of the side surface of the first conductive pattern 161" can be exposed through the first gap region gap1.

[0178] refer to Figure 11B A preliminary conductive structure 140P" can be formed on the second insulating gasket 115 and the first contact plug 160". The preliminary conductive structure 140P" can be formed as a single conductive layer. However, exemplary embodiments thereof are not limited thereto, and for example, the preliminary conductive structure 140P" can be formed on the second insulating gasket 115 and the first contact plug 160" as a preliminary contact barrier layer and a preliminary conductive layer located on the preliminary contact barrier layer.

[0179] refer to Figure 11CAn opening exposing the upper surface of the second insulating pad 115 can be formed by removing a portion of the preliminary conductive structure 140P" formed on the upper region between the first contact plugs 160", and a first insulating pattern 117 filling the opening can be formed. This can be achieved as shown in the reference... Figure 9I The same method described applies to subsequent process operations.

[0180] Figures 12A to 12F This is a diagram illustrating a method of manufacturing a semiconductor device according to another example embodiment. See also... Figures 12A to 12F Description of manufacturing Figure 8E Method for semiconductor device 1e in the process.

[0181] refer to Figure 12A as well as Figure 9A and Figure 9B A method of manufacturing a semiconductor device may include: forming an active region 105 by removing a portion of a substrate 101; forming a gate structure GS on the active region 105; forming a recessed region by removing a portion of the active region 105 exposed between the gate structures GS; forming a source / drain region 150 in the recessed region; forming an insulating structure 190 between the gate structures GS on the substrate 101; sequentially forming a first insulating pad 111, a first insulating layer 113, and a second insulating pad 115 in the vertical direction (Z direction) on the gate structure GS and the insulating structure 190; forming a first contact hole OPN1 by removing a portion of each of the insulating structure 190, the first insulating pad 111, the first insulating layer 113, and the second insulating pad 115; forming a first preliminary contact plug 160P in the first contact hole OPN1; and forming a first contact hole OPN1b by removing a portion of each of the first preliminary contact plugs 160P.

[0182] Forming the first contact hole OPN1b may include etching each first preliminary contact plug 160P downwards to have a height lower than the height of the first insulating pad 111. The side surfaces of the second insulating pad 115, the first insulating layer 113, and the first insulating pad 111 may be exposed through the first contact hole OPN1b. The side surfaces of the upper region of the insulating structure 190 may be exposed through the first contact hole OPN1b. The first preliminary contact plug 160_1P can be formed by etching each first preliminary contact plug 160P to have a height lower than the height of the first insulating pad 111. The first preliminary contact plug 160_1P may include a first preliminary conductive pattern 161_1P disposed below the first insulating pad 111 and a first preliminary conductive barrier layer 163_1P covering the lower and side surfaces of the first preliminary conductive pattern 161_1P.

[0183] refer to Figure 12BA first contact spacer 145a can be formed, and a second contact hole OPN2b can be formed that exposes the upper surface of the recessed first conductive pattern 161_1.

[0184] Forming the first-1 contact spacer 145a may include in Figure 12A A first preliminary contact spacer layer is conformally formed on the inner surface of the first contact hole OPN1b, and the lower surface of the first preliminary contact spacer layer located on the inner surface of the first contact hole OPN1b is removed. Forming the second contact hole OPN2b may include partially exposing the side surface of the first preliminary conductive barrier layer 163_1P by recessing a portion of the upper surface of the first preliminary conductive pattern 161_1P that overlaps with the first preliminary contact spacer layer. The first conductive pattern 161_1 can be formed by recessing a portion of the upper surface of the first preliminary conductive pattern 161_1P.

[0185] refer to Figure 12C The first gap portion gap2a can be formed by removing a portion of the side surface of the first preliminary conductive barrier layer 163_1P exposed through the second contact hole OPN2b. A portion of the side surface of the insulating structure 190 can be exposed through the first gap portion gap2a. The first conductive barrier layer 163_1 can be formed by removing a portion of the side surface of the first preliminary conductive barrier layer 163_1P.

[0186] refer to Figure 12D The second gap portion gap2b can be formed by removing the portion of the side surface of the insulating structure 190 exposed through the first gap portion gap2a. The gate spacer 135 can be exposed through the second gap portion gap2b. The insulating structure 190 can be a material with higher etch selectivity than the gate spacer 135.

[0187] refer to Figure 12E The first-second contact spacer 145b can be formed on the side surface of the first-first contact spacer 145a exposed through the second contact hole OPN2b.

[0188] Forming the first-second contact spacer 145b may include forming a second contact spacer layer (not shown) on the inner surface of the first-first contact spacer 145a exposed through the second contact hole OPN2b, removing the lower surface of the second contact spacer layer disposed on the first conductive pattern 161_1, and forming a third contact hole OPN3b that exposes the upper surface of the first conductive pattern 161_1.

[0189] The lower surface of the first-second contact spacer 145b can contact the upper surface of the first conductive pattern 161_1. The lower surface of the first-second contact spacer 145b can be positioned at a height lower than the lower surface of the first-first contact spacer 145a. By forming the first-second contact spacer 145b, a second gap region gap2 can be defined around the side surface of the first conductive pattern 161_1 and the side surface of the first conductive barrier layer 163_1. Therefore, a first contact plug 160_1 including the second gap region gap2 can be formed.

[0190] refer to Figure 12F A first conductive structure 140a_1 and a second conductive structure 140b_1 alternately disposed with the first conductive structure 140a_1 can be formed. The first conductive structure 140a_1 includes a first pass portion 141a_1, a first interconnect portion 142a_1 extending from the first pass portion 141a_1 on the first pass portion 141a_1, and a first contact barrier layer 143a_1 covering the lower surface and side surface of the first pass portion 141a_1 and the lower surface of the first interconnect portion 142a_1. A first insulating pattern 117 disposed between the first conductive structure 140a_1 and the second conductive structure 140b_1 can also be formed.

[0191] Forming the first conductive structure 140a_1 and the second conductive structure 140b_1 may include forming a preliminary conductive structure (not shown) on the upper surface of the second insulating pad 115 and in the third contact hole OPN3b, as well as removing a portion of the preliminary conductive structure. The preliminary conductive structure may include a preliminary contact barrier layer and a preliminary contact conductive layer formed on the preliminary contact barrier layer.

[0192] The reference can be applied in the same way. Figure 9I The described process operation.

[0193] According to the foregoing example embodiments, the semiconductor device may include contact plugs connected to the source / drain regions of a peripheral transistor, conductive structures located on the contact plugs, and contact spacers surrounding contact pathways of the conductive structures between the contact plugs and contact interconnects of the conductive structures. Therefore, bridging between contact interconnects of the conductive structures and another adjacent conductive structure, or bridging between contact pathways of the conductive structures and contact interconnects of another conductive structure adjacent to the conductive structure, can be reduced or prevented, thereby providing a semiconductor device with improved reliability.

[0194] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, a first element, component, region, layer, or portion described herein may be referred to as a second element, component, region, layer, or portion.

[0195] It will be understood that, unless otherwise indicated, spatial relative terms such as “above,” “upper,” “superior,” “upper surface,” “below,” “lower,” “lower part,” “lower surface,” “side surface,” etc., may be indicated by reference to the accompanying drawings and figure references. It will be understood that, in addition to the orientation depicted in the figures, such spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features will then be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0196] Components or layers described with reference to being “sequential” or “stacked sequentially” in a particular direction or manner may be layered, adjacent, close to, oriented, or otherwise arranged relative to each other to achieve the relativity shown or envisioned, optionally with other components, layers, etc., between them. Components or layers described with reference to being “overlapping” in a particular direction may at least partially obscure each other when viewed along a line extending in a particular direction or in a plane perpendicular to the particular direction. The terms “around,” “cover,” or “fill,” as may be used herein, do not require complete surrounding, covering, or filling of the described element or layer, but may refer, for example, to partial surrounding, covering, or filling of the described element or layer, such as the presence of gaps, spaces, or other discontinuities at various points. The term “exposed” may be used to describe the relationship between elements and / or specific intermediate processes in a finished semiconductor device, but does not necessarily require exposure of specific regions, layers, structures, or other elements in the context of the finished device.

[0197] It will be understood that when an element is referred to as "on" or "set on" another element, it may be directly on the other element, or there may be an intermediate element present. In contrast, when an element is referred to as "directly on" another element, there is no intermediate element present. It will also be understood that when an element is referred to as "connected" or "joined" to another element, it may be directly connected to or joined to the other element, or there may be an intermediate element present. In contrast, when an element is referred to as "directly connected" or "directly joined" to another element, there is no intermediate element present. Other terms used to describe relationships between elements should be interpreted in the same way (i.e., "between" and "directly between," "adjacent" and "directly adjacent," etc.). The term "connected" may be used herein to refer to physical connections and / or electrical connections.

[0198] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, said semiconductor device comprising: A first structure, the first structure including a storage area; as well as A second structure, which overlaps perpendicularly with the first structure and includes a peripheral circuit region that overlaps perpendicularly with the storage region. The first structure includes: Storage cells, each located within the storage region, including a vertical channel transistor and a data storage structure; and A cell routing interconnect structure, wherein the cell routing interconnect structure is connected to the storage cell. The second structure includes: A peripheral transistor, the peripheral transistor including a gate structure and a source / drain region; A first contact plug, the first contact plug being located on and connected to the source / drain region; and A first conductive structure is located on and connected to the first contact plug. The first conductive structure includes a first passage portion that contacts the first contact plug and a first interconnect portion located on and extending from the first passage portion; and Wherein, the width of the first passage portion in the first direction is smaller than the width of the first interconnect portion in the first direction.

2. The semiconductor device according to claim 1, further comprising: A first contact spacer is located between the first contact plug and the first interconnect portion of the first conductive structure and on the side surface of the first passage portion.

3. The semiconductor device according to claim 1, further comprising: A second contact plug is located on and connected to the gate structure; A second conductive structure is located on and connected to the second contact plug, and is spaced apart from the first conductive structure in the first direction; and The second conductive structure includes a second pass portion that contacts the gate structure and a second interconnect portion located on and extending from the second pass portion.

4. The semiconductor device according to claim 3, wherein, The second conductive structure further includes a second contact spacer located between the second contact plug and the second interconnect portion of the second conductive structure, and extending along the side surface of the second passage portion.

5. The semiconductor device according to claim 3, wherein, The upper surface of the first conductive structure is coplanar with the upper surface of the second conductive structure.

6. The semiconductor device according to claim 3, wherein, The lower surface of the first passage portion of the first conductive structure is coplanar with the lower surface of the second passage portion of the second conductive structure.

7. The semiconductor device according to claim 1, wherein: The first contact plug includes a first conductive pattern and a first conductive barrier layer extending along the side and lower surfaces of the first conductive pattern; and The first conductive structure further includes a first contact barrier layer located on the side and lower surfaces of the first pass portion and on the lower surface of the first interconnect portion.

8. The semiconductor device according to claim 1, further comprising: A first insulating pad is located on the gate structure of the peripheral transistor; A first insulating layer is located on the first insulating pad; as well as The second insulating pad is located on the first insulating layer. In this configuration, the first interconnect portion of the first conductive structure is located on the second insulating pad, and the first through portion of the first conductive structure penetrates the second insulating pad. Wherein, the first insulating pad and the second insulating pad include a first insulating material, and The first insulating layer includes a second insulating material that is different from the first insulating material.

9. The semiconductor device according to claim 8, wherein, The upper surface of the first contact plug and the lower surface of the first passage portion of the first conductive structure are located between the lower surface of the first insulating layer and the upper surface of the first insulating layer.

10. The semiconductor device according to claim 8, wherein: The first conductive structure's first via portion penetrates both the first insulating pad and the first insulating layer; and The upper surface of the first contact plug is defined below the first insulating pad.

11. The semiconductor device of claim 8, further comprising: The first contact spacer is located between the first contact plug and the first interconnection portion of the first conductive structure and is located on the side surface of the first passage portion. as well as An insulating pattern is located on the second insulating pad. The side surface of the first contact spacer is in contact with the first insulating layer, the second insulating pad, and the insulating pattern.

12. The semiconductor device according to claim 1, wherein, The width of the upper surface of the first contact plug in the first direction is greater than the width of the lower surface of the first passage portion of the first conductive structure in the first direction.

13. A semiconductor device, said semiconductor device comprising: A substrate, the substrate including an active region extending in a first direction; A gate structure extending on the substrate in a second direction intersecting the active region; Source / drain regions, wherein the source / drain regions are located in the recessed region of the active region on at least one side of the gate structure; A first conductive structure is located on and connected to the source / drain region; as well as First contact spacer, The first conductive structure includes a first interconnect portion, a first passage portion extending from the lower surface of the first interconnect portion, and a first contact barrier layer located on the lower surface of the first interconnect portion and the side and lower surfaces of the first passage portion. Wherein, the first contact spacer extends relative to the substrate below the first interconnect portion along at least a portion of the side surface of the first passage portion.

14. The semiconductor device of claim 13, further comprising: A second conductive structure is located on and electrically connected to the gate structure, and is spaced apart from the first conductive structure in the first direction; and The second conductive structure includes a second interconnect portion, a second passage portion extending from the lower surface of the second interconnect portion, and a second contact barrier layer, wherein the second contact barrier layer is located on the lower surface of the second interconnect portion and the side and lower surfaces of the second passage portion.

15. The semiconductor device of claim 14, further comprising: The second contact spacer extends relative to the substrate below the second interconnect portion along the side surface of the second passage portion.

16. The semiconductor device according to claim 13, wherein, The width of the first passage portion in the first direction is smaller than the width of the first passage portion in the second direction.

17. The semiconductor device according to claim 13, in, The first conductive structure includes a first portion that contacts the source / drain region and a second portion located on and extending from the first portion. Wherein, the width of the first portion in the first direction is greater than the width of the second portion in the first direction, and the first contact spacer extends along the side surface of the second portion.

18. The semiconductor device of claim 13, further comprising: A first contact plug is located between the source / drain region and the first via portion of the first conductive structure, and includes a conductive pattern and conductive barrier layers extending along the side and bottom surfaces of the conductive pattern. The first contact spacer overlaps with the first contact plug in a direction perpendicular to the first and second directions.

19. The semiconductor device of claim 13, further comprising: A dummy gate structure is provided, wherein the dummy gate structure is spaced apart from the gate structure on the substrate in the second direction. The first interconnect portion of the first conductive structure includes a first extension portion that overlaps with the source / drain region in a vertical direction intersecting the first and second directions and extends in the second direction, a curved portion that extends from the first extension portion to the region between the gate structure and the dummy gate structure, and a second extension portion that overlaps with the dummy gate structure in the vertical direction and extends in the second direction.

20. A semiconductor device, said semiconductor device comprising: A first structure, wherein the first structure has a storage area; as well as A second structure, which overlaps perpendicularly with the first structure and includes a peripheral circuit region that overlaps perpendicularly with the storage region. The first structure includes: Storage cells, each located within the storage region, including a vertical channel transistor and a data storage structure; and A cell routing interconnect structure, wherein the cell routing interconnect structure is connected to the storage cell. The second structure includes: A substrate, the substrate including an active region extending in a first direction; A peripheral gate structure, the peripheral gate structure extending on the substrate in a second direction intersecting the active region; The source / drain region is located in the recessed region of the active region on at least one side of the peripheral gate structure; A first contact plug is located on and connected to the source / drain region; A second contact plug is located on and connected to the peripheral gate structure; A first conductive structure is located on and connected to the first contact plug; A second conductive structure is located on and connected to the second contact plug; First contact spacer; and Second contact spacer, The first conductive structure includes a first passage portion that contacts the first contact plug and a first interconnect portion located on the first passage portion and extending from the first passage portion in the second direction. The second conductive structure includes a second passage portion and a second interconnect portion. The second passage portion contacts the second contact plug, and the second interconnect portion is located on the second passage portion and extends from the second passage portion in the second direction, and is spaced apart from the first interconnect portion in the first direction. The first contact spacer is located between the first contact plug and the first interconnection portion of the first conductive structure and is located on the side surface of the first passage portion. The second contact spacer is located between the second contact plug and the second interconnect portion of the second conductive structure and is located on the side surface of the second passage portion.

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