Semiconductor memory device and method of manufacturing the same

Abstract

This embodiment relates to a semiconductor memory device and a method for manufacturing the same. The memory includes a first stack of electrode films and a first insulating film alternately stacked in a first direction. A second stack is disposed adjacent to the first stack, in which the first insulating film and the second insulating film are alternately stacked in the first direction. A third stack extends from an end of the first stack in a second direction within a first plane orthogonal to the first direction, in which the electrode film and the first insulating film are alternately stacked in the first direction. A first columnar body includes a semiconductor layer disposed through the first stack in the first direction. The first columnar body forms a plurality of memory cells at its intersection with the electrode films, with the electrode films serving as gate electrodes. Contacts extend in the first direction within the second stack or the third insulating film, reaching the respective depths of the plurality of electrode films in the third stack. A connection layer electrically connects the plurality of contacts to their respective plurality of electrode films.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] Semiconductor memory devices such as NAND flash memory sometimes have a memory cell array arranged in three dimensions. Such a memory cell array includes electrode films that function as multiple word lines and multiple insulating films. The electrode films and insulating layers are stacked alternately. The electrode films are formed by replacing the sacrificial films with conductive material from a stack of multiple sacrificial films and multiple insulating films. During this replacement process, when the sacrificial films are removed, the stack may flex due to its own weight. Summary of the Invention

[0003] The semiconductor memory device of this embodiment includes a first stack of electrode films and a first insulating film alternately stacked in a first direction. A second stack is disposed adjacent to the first stack and is formed by alternately stacking a first insulating film and a second insulating film in the first direction. A third stack extends from the end of the first stack in a second direction within a first plane orthogonal to the first direction and is formed by alternately stacking an electrode film and a first insulating film in the first direction. A first columnar body includes a semiconductor layer disposed through the first stack in the first direction. At the intersection portions where the first columnar body intersects with multiple electrode films, multiple memory cells are formed, with the multiple electrode films serving as gate electrodes. Multiple contacts extend in the first direction within the second stack or within the third insulating film disposed above the second stack, up to the respective depths of the multiple electrode films of the third stack. Multiple interconnecting layers electrically connect the multiple contacts to the multiple electrode films corresponding to each of the multiple contacts.

[0004] According to this embodiment, a semiconductor memory device and its manufacturing method can be provided, which can suppress the depression of the laminate when the sacrificial film is replaced with a conductive material in a laminate composed of multiple sacrificial films and multiple insulating films. Attached Figure Description

[0005] Figure 1 This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment.

[0006] Figure 2 This is an enlarged cross-sectional view showing an example of the configuration of the memory cell array according to the first embodiment.

[0007] Figure 3 This is a cross-sectional view showing the manufacturing process from the bonding of the array wafer and the circuit wafer to the completion of the semiconductor memory device.

[0008] Figure 4 It is a continuation Figure 3 The diagram shows a cross-sectional view of the manufacturing process.

[0009] Figure 5 It is a continuation Figure 4 The diagram shows a cross-sectional view of the manufacturing process.

[0010] Figure 6 It is a continuation Figure 5 The diagram shows a cross-sectional view of the manufacturing process.

[0011] Figure 7 This is a top view showing an example of the configuration of the memory cell array according to the first embodiment.

[0012] Figure 8 This is a cross-sectional view showing a configuration example of the memory cell array according to the first embodiment.

[0013] Figure 9 This is a top view illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0014] Figure 10 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0015] Figure 11 It is a continuation Figure 10 A cross-sectional view showing an example of the manufacturing method.

[0016] Figure 12 It is a continuation Figure 11 A cross-sectional view showing an example of the manufacturing method.

[0017] Figure 13 It is a continuation Figure 12 A top view showing an example of a manufacturing method.

[0018] Figure 14 It is a continuation Figure 12 A cross-sectional view showing an example of the manufacturing method.

[0019] Figure 15 It is a continuation Figure 14 A cross-sectional view showing an example of the manufacturing method.

[0020] Figure 16 It is a continuation Figure 15 A cross-sectional view showing an example of the manufacturing method.

[0021] Figure 17 It is a continuation Figure 16 A cross-sectional view showing an example of the manufacturing method.

[0022] Figure 18 It is a continuation Figure 17 A top view showing an example of a manufacturing method.

[0023] Figure 19 It is a continuation Figure 17 A cross-sectional view showing an example of the manufacturing method.

[0024] Figure 20 It is a continuation Figure 18 A top view showing an example of a manufacturing method.

[0025] Figure 21 It is a continuation Figure 19 A cross-sectional view showing an example of the manufacturing method.

[0026] Figure 22 It is a continuation Figure 21 A cross-sectional view showing an example of the manufacturing method.

[0027] Figure 23 It is a continuation Figure 22 A top view showing an example of a manufacturing method.

[0028] Figure 24 It is a continuation Figure 22 A cross-sectional view showing an example of the manufacturing method.

[0029] Figure 25 It is a continuation Figure 23 A top view showing an example of a manufacturing method.

[0030] Figure 26 It is a continuation Figure 24 A cross-sectional view showing an example of the manufacturing method.

[0031] Figure 27 It is a continuation Figure 25 A top view showing an example of a manufacturing method.

[0032] Figure 28 It is a continuation Figure 26 A cross-sectional view showing an example of the manufacturing method.

[0033] Figure 29 It is a continuation Figure 28 A cross-sectional view showing an example of the manufacturing method.

[0034] Figure 30 It is a continuation Figure 29 A cross-sectional view showing an example of the manufacturing method.

[0035] Figure 31 It is a continuation Figure 30 A cross-sectional view showing an example of the manufacturing method.

[0036] Figure 32 This is a top view showing an example of the configuration of the memory cell array according to the second embodiment.

[0037] Figure 33This is a top view illustrating an example of a method for manufacturing a semiconductor memory device according to the second embodiment.

[0038] Figure 34 It is a continuation Figure 33 A top view showing an example of a manufacturing method.

[0039] Figure 35 It is a continuation Figure 34 A top view showing an example of a manufacturing method.

[0040] Figure 36 It is a continuation Figure 35 A top view showing an example of a manufacturing method.

[0041] Figure 37 It is a continuation Figure 36 A top view showing an example of a manufacturing method.

[0042] Figure 38 It is a continuation Figure 37 A top view showing an example of a manufacturing method.

[0043] Figure 39 It is a continuation Figure 38 A top view showing an example of a manufacturing method.

[0044] Figure 40 This is a top view showing an example configuration of a semiconductor memory device according to the third embodiment.

[0045] Figure 41 It is along Figure 40 A cross-sectional view of line AA.

[0046] Figure 42 It is along Figure 40 A cross-sectional view of the BB line.

[0047] Figure 43 This is a top view showing an example configuration of a semiconductor memory device according to the fourth embodiment.

[0048] Figure 44 This is a top view showing an example configuration of a semiconductor memory device according to the fourth embodiment.

[0049] Figure 45 It is along Figure 44 A cross-sectional view of line AA.

[0050] Figure 46 It is along Figure 44 A cross-sectional view of the BB line. Detailed Implementation

[0051] The embodiments of the present invention will now be described with reference to the accompanying drawings. These embodiments do not limit the scope of the invention. The drawings are illustrative or conceptual. In the specification and drawings, the same reference numerals are used for the same elements.

[0052] (First Implementation)

[0053] Figure 1 This is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment.

[0054] The semiconductor memory device of this embodiment is, for example, a NAND flash memory having a memory cell array in which memory cells are arranged in three dimensions. The semiconductor memory device of this embodiment is manufactured by bonding an array wafer containing an array chip 1 and a circuit wafer containing a circuit chip 2 at a bonding surface S.

[0055] The array chip 1 includes a memory cell array 11 containing multiple memory cells and an interlayer insulating film 12 under the memory cell array 11. The interlayer insulating film 12 is, for example, a laminate containing a silicon oxide film (e.g., a SiO2 film) containing silicon and oxygen and other insulating films.

[0056] Circuit chip 2 is disposed below array chip 1. Circuit chip 2 includes an interlayer insulating film 13 below interlayer insulating film 12 and a substrate 14 below interlayer insulating film 13. Interlayer insulating film 13 is, for example, a laminate containing a silicon oxide film (e.g., SiO2 film) and other insulating films. Substrate 14 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Substrate 14 is an example of a second substrate.

[0057] Figure 1 The X and Y directions, which are parallel to and perpendicular to the surface of the substrate 14, and the Z direction, which is perpendicular to the surface of the substrate 14, are shown. The X, Y, and Z directions intersect each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not be aligned with the direction of gravity. The Z direction is an example of the first direction. The X direction is an example of the second direction. The Y direction is an example of the third direction.

[0058] The array chip 1 has multiple word lines (WL), source-side select lines (SGS), and drain-side select lines (SGD) as multiple electrode films within the memory cell array 11. The source-side select lines (SGS) are disposed above these word lines (WL), and the drain-side select lines (SGD) are disposed below these word lines (WL). The array chip 1 includes a cell region (Rmc) where the memory cell array 11 is disposed, and a word line connection region (hereinafter also referred to as the WLHU region) (Rwlhu) where word line contacts 23 are disposed.

[0059] Each of the multiple word lines WL is connected to a multiple word line contact 23, and is electrically connected to a multiple word line wiring 24 via the multiple word line contact 23 (hereinafter also referred to as word line contact WLC).

[0060] Multiple cylindrical bodies CL, passing through multiple word lines WL, source-side select line SGS, and drain-side select line SGD, are electrically connected to bit line BL and source line SL via through-hole plugs 25. The cylindrical bodies CL are disposed along the Z-direction through the stack of the memory cell array 11, forming multiple memory cells MC at their intersections with the multiple word lines WL. Source line SL is positioned above source-side select line SGS, and bit line BL is positioned below drain-side select line SGD.

[0061] Alternatively, it can be only Figure 1 The topmost electrode film can be the source-side selection line (SGS), but multiple electrode films located on the topmost side can also serve as source-side selection lines (SGS). The number of electrode films serving as source-side selection lines (SGS) can be arbitrary. Similarly, only the bottommost electrode film can be the drain-side selection line (SGD), but multiple electrode films located on the bottommost side can also serve as drain-side selection lines (SGD). The number of electrode films serving as drain-side selection lines (SGD) can be arbitrary.

[0062] The array chip 1 also includes metal pads 41 and 47, through-hole plugs 42, 45 and 46, wiring layers 43 and 44, and a passivation insulating film 48.

[0063] Metal pad 41 is bonded to metal pad 37 of circuit chip 2. Metal pad 41 is, for example, a metal layer containing Cu (copper). The CMOS (Complementary Metal Oxide Semiconductor) circuit of circuit chip 2 is electrically connected to memory cell array 11 via metal pads 41, 37, etc., controlling the operation of memory cell array 11. Through-hole plug 42 is disposed on metal pad 41. Wiring layer 43 is disposed on through-hole plug 42, containing multiple wirings. Wiring layer 44 is disposed on wiring layer 43, containing multiple wirings. Bit line BL is formed on the same layer as wiring layer 44. Through-hole plug 45 is disposed on wiring layer 44. Through-hole plug 46 is disposed on through-hole plug 45.

[0064] Metal pads 47 are disposed on the through-hole plugs 46 and the interlayer insulating film 12. The metal pads 47 are, for example, a metal layer containing Al (aluminum) and function as external connection pads (e.g., bonding pads). Passivation insulating film 48 is disposed on the metal pads 47 and the interlayer insulating film 12. The passivation insulating film 48 is, for example, a laminate containing a silicon oxide film (e.g., SiO2 film) containing silicon and oxygen and a silicon nitride film (e.g., SiN film) containing silicon and nitrogen, exposing a portion of the upper surface of the metal pads 47. The metal pads 47 can be connected to a mounting substrate or other devices via bonding wires, solder balls, metal bumps, etc.

[0065] The circuit chip 2 includes a transistor 31, a contact plug 32, a wiring layer 33, a wiring layer 34, a wiring layer 35, a through-hole plug 36, and a metal pad 37.

[0066] The transistor 31 includes: a gate insulating film 31a disposed on the substrate 14, a gate electrode 31b disposed on the gate insulating film 31a, a source region (not shown) disposed on the substrate 14, and a drain region (not shown) disposed on the substrate 14.

[0067] Contact plugs 32 are disposed on the gate electrode 31b, source region, and drain region of transistor 31. A wiring layer 33 is disposed on the contact plugs 32 and contains multiple wirings. A wiring layer 34 is disposed on the wiring layer 33 and contains multiple wirings. A wiring layer 35 is disposed on the wiring layer 34 and contains multiple wirings. A via plug 36 is disposed on the wiring layer 35. A metal pad 37 is disposed on the via plug 36. The metal pad 37 is, for example, a metal layer containing a Cu layer. The circuit chip 2 has a CMOS circuit for controlling the operation of the array chip 1. This CMOS circuit is composed of transistors 31, etc., and is electrically connected to the array chip 1 via the metal pad 37.

[0068] Figure 2 This is an enlarged cross-sectional view showing an example of the configuration of the memory cell array according to the first embodiment. Figure 2 A columnar body CL is shown.

[0069] The memory cell array 11 includes a stack 51 comprising alternating electrode films 51a and insulating films 51b stacked in the Z direction. The electrode films 51a function, for example, as word lines (WL), source-side select lines (SGS), or drain-side select lines (SGD). Figure 2 In this configuration, the uppermost electrode film 51a becomes the source-side select line (SGS), the lowermost electrode film 51a becomes the drain-side select line (SGD), and the other electrode films 51a become word lines (WL). The word lines (WL) function as the gate electrodes of the memory cells (MC). The electrode films 51a are, for example, metal layers containing W (tungsten, molybdenum). The insulating film 51b is, for example, a silicon oxide film (e.g., a SiO2 film) containing silicon and oxygen. The insulating film 51b is an example of a first insulating film.

[0070] A columnar body CL is disposed through the laminate 51 along the Z-direction and has a columnar shape. The columnar body CL is disposed within a memory aperture MH that penetrates the laminate 51 along the Z-direction. The columnar body CL includes: a barrier insulating film 52 disposed on the inner surface of the memory aperture MH; a charge storage layer 53 disposed on the inner surface of the barrier insulating film 52; a tunnel insulating film 54 disposed on the inner surface of the charge storage layer 53; a channel semiconductor layer 55 disposed on the inner surface of the tunnel insulating film 54; and a core insulating film 56 disposed on the inner surface of the channel semiconductor layer 55. The columnar body CL forms a memory cell MC at the intersection with the word line WL, a source-side selection transistor at the intersection with the source-side select line SGS, and a drain-side selection transistor at the intersection with the drain-side select line SGD. The memory cell MC is also referred to as a cell transistor.

[0071] The barrier insulating film 52 is, for example, a silicon oxide film containing silicon and oxygen (e.g., a SiO2 film). The charge storage layer 53 is capable of storing the charge logically corresponding to the data. The charge storage layer 53 is, for example, an insulating film containing silicon and nitrogen, such as a silicon nitride film (e.g., a SiN film). The tunnel insulating film 54 is, for example, a silicon oxide film containing silicon and oxygen (e.g., a SiO2 film) or a silicon nitride film containing silicon and nitrogen (e.g., a SiON film). The channel semiconductor layer 55 functions as the channel of the memory cell MC. The channel semiconductor layer 55 is, for example, a silicon-containing film (e.g., a polycrystalline silicon layer). The core insulating film 56 is, for example, a silicon oxide film containing silicon and oxygen (e.g., a SiO2 film). The channel semiconductor layer 55 is an example of a semiconductor layer.

[0072] Figures 3-6 This is a cross-sectional view showing the manufacturing process from the bonding of array wafer W1 and circuit wafer W2 to the completion of the semiconductor memory device.

[0073] Figure 3 An array wafer W1 containing multiple array chips 1 and a circuit wafer W2 containing multiple circuit chips 2 are shown. Figure 3 In the diagram, the orientation of the Z-direction of the array wafer W1 is... Figure 1 The Z-direction orientations of array chip 1 are opposite. Array chip 1 and circuit chip 2 are electrically connected by bonding array wafer W1 to circuit wafer W2. Figure 3 The image shows an array wafer W1 that has been reversed in orientation for bonding purposes.

[0074] In this embodiment, such as Figure 3As shown, a memory cell array 11, an interlayer insulating film 12a, metal pads 41, and via plugs 45 are formed on the substrate 15 of the array wafer W1. Meanwhile, a transistor 31, an interlayer insulating film 13, and metal pads 37 are formed on the substrate 14 of the circuit wafer W2. The substrates 14 and 15 are, for example, semiconductor substrates such as silicon substrates.

[0075] Next, as Figure 4 As shown, the array wafer W1 and the circuit wafer W2 are bonded together such that the upper surface S1 of the array wafer W1 faces the upper surface S2 of the circuit wafer W2. Thus, the interlayer insulating film 12a and the interlayer insulating film 13 are bonded at the bonding surface S.

[0076] Next, the array wafer W1 and the circuit wafer W2 are annealed. As a result, the metal pads 41 and 37 are bonded together. In this way, the array wafer W1 and the circuit wafer W2 are bonded together with interlayer insulating films 12a and 13 sandwiched between them.

[0077] Next, as Figure 5 As shown, the substrate 15 is removed by CMP (Chemical Mechanical Polishing) or wet etching. As a result, the interlayer insulating film 12a, the columnar body CL, the through-hole plug 45, etc. are exposed.

[0078] Next, as Figure 6 As shown, a source line SL is formed on the interlayer insulating film 12a and the columnar body CL, and an interlayer insulating film 12b is formed on the interlayer insulating film 12a across the source line SL.

[0079] Next, a through-hole plug 46 is formed on the through-hole plug 45, penetrating the interlayer insulating film 12b, and a metal pad 47 is formed on the interlayer insulating film 12b and the through-hole plug 46.

[0080] Next, a passivation insulating film 48 is formed on the interlayer insulating film 12b and the metal pad 47, and the passivation insulating film 48 is processed to expose a portion of the metal pad 47.

[0081] Then, the array wafer W1 and the circuit wafer W2 are cut into multiple chips. This process creates... Figure 1 The semiconductor memory device shown.

[0082] In addition, although Figure 1 The boundary surfaces of interlayer insulating film 12 and interlayer insulating film 13, and the boundary surfaces of metal pad 41 and metal pad 37 (adhesion surfaces S) are shown, but these boundary surfaces are usually not visible after the above-described annealing. However, the location of these boundary surfaces can be identified, for example, by the tilt of the side surface of metal pad 41, the side surface of metal pad 37, or the positional offset between the side surface of metal pad 41 and the side surface of metal pad 37.

[0083] Figure 7 This is a top view showing a configuration example of the storage cell array 11 according to the first embodiment. Figure 8 This is a cross-sectional view showing a configuration example of the memory cell array 11 according to the first embodiment. Figure 7 The end of the storage cell array 11 is shown. Figure 8 AA shows along Figure 7 The cross section of line AA. Figure 8 BB shows along Figure 7 The cross section of the BB line. Figure 8 CC indicates along Figure 7 The cross section of the CC line. Figure 8 DD shows along Figure 7 The cross section of the DD line. Figure 8 The EE shows along Figure 7 The cross section of the EE line. Figure 8 FF shows along Figure 7 The cross section of the FF line. Figure 8 GG shows along Figure 7 The cross-section of the GG line.

[0084] like Figure 7 As shown, the storage cell array 11 has a cell region Rmc and a WLHU region Rwlhu.

[0085] Within the stack 51, a first stack 51_1 is provided in the element region Rmc. For example... Figure 8 As shown, the first laminate 51_1 is composed of electrode film 51a and insulating film 51b alternately laminated in the Z direction. Figure 7 As shown, multiple columnar bodies CL are provided in the first stack 51_1. Additionally, multiple slits ST_CELL are provided in the first stack 51_1.

[0086] Slit ST_CELL Figure 8 As shown, it penetrates the first layer 51_1 along the Z direction, and as... Figure 7 As shown, it is arranged extending along the X direction. The slit ST_CELL divides the first stack 51_1 into multiple blocks BLK. A portion of the first stack 51_1 sandwiched between two slit ST_CELLs is called a block BLK. Block BLKs, for example, constitute units of data erasure. The slit ST_cell electrically isolates the first stack 51_1 for each block BLK.

[0087] The inner wall of the slit ST_CELL is covered with an insulating film such as a silicon oxide film, and a conductive material is further embedded inside the insulating film. The conductive material is connected to the source line SL, enabling it to function as a source wiring. When not used as a source line, the slit ST_CELL can also be filled with an insulating film containing silicon and oxygen, such as a silicon oxide film (e.g., a SiO2 film).

[0088] Within the stacked body 51, the WLHU region Rwlhu is disposed adjacent to the element region Rmc. A second stacked body 51_2 and a third stacked body 51_3 are disposed within the WLHU region Rwlhu.

[0089] like Figure 8 As shown, in the second laminate 51_2, insulating films 51b (e.g., silicon oxide films) and insulating films 51c (e.g., silicon nitride films) are alternately laminated in the Z direction. Figure 7 As shown, the second stack 51_2 is adjacent to the first stack 51_1 across a slit ST_WLC. Furthermore, the second stack 51_2 is adjacent to the third stack 51_3. Multiple word line contacts WLC are provided in the second stack 51_2.

[0090] like Figure 8 As shown, the slit ST_WLC penetrates either the first stack 51_1 or the second stack 51_2 along the Z direction between the first stack 51_1 and the second stack 51_2. The slit ST_WLC is as follows... Figure 7 As shown, it extends discontinuously along the Y direction in the XY plane. The slit ST_WLC is filled with an insulating film (e.g., a silicon oxide film). This physically separates the first stack 51_1 from the second stack 51_2, preventing the insulating film 51c of the second stack 51_2 in the WLHU region Rwlhu from being replaced by the conductive material of the electrode film 51a. On the other hand, the slit ST_WLC has an opening OP that connects a portion of the first stack 51_1 of the cell region Rmc to the third stack 51_3 of the WLHU region Rwlhu for each block BLK.

[0091] like Figure 8 As shown, in the third stack 51_3, electrode films 51a (e.g., tungsten, molybdenum) and insulating films 51b (e.g., silicon oxide films) are alternately stacked in the Z direction. Figure 7As shown, the third stack 51_3 is connected to the first stack 51_1 from its end via an opening OP, and extends in the XY plane from the end of the first stack 51_1 in the +X direction. The electrode film 51a and insulating film 51b of the third stack 51_3 are continuously connected to the electrode film 51a and insulating film 51b of the first stack 51_1 in each layer. In addition, a dummy columnar body DMC is provided at the end of the third stack 51_3 on the cell region Rmc side. The dummy columnar body DMC is formed simultaneously with the CL in the first stack, but does not function as a storage cell. The dummy columnar body DMC is provided to suppress the bending of the insulating film 51b at the connection between the first stack 51_1 and the third stack 51_3 due to its own weight when the insulating film 51c of the first stack 51_1 and the third stack 51_3 is replaced with the conductive material of the electrode film 51a. Furthermore, a slit ST_LWI is provided in the third layer 51_3. Additionally, a dummy columnar body DMC can be configured around the slit ST_LWI to prevent deflection.

[0092] Slit ST_LWI Figure 8 As shown, the slit ST_LWI penetrates the third stack 51_3 along the Z direction within the third stack 51_3. Figure 7 As shown, it extends in the X direction along the extension direction of the third stack 51_3 in the XY plane. The inner wall of the slit ST_LWI is covered by an insulating film such as a silicon oxide film, and a conductive material is further embedded inside the insulating film. Thus, the slit ST_LWI can be formed simultaneously with the slit ST_CELL. However, the conductive material does not need to be connected to the source line SL. Therefore, the slit ST_LWI can also be filled with an insulating film such as a silicon oxide film instead.

[0093] like Figure 7 As shown, multiple word line contacts WLCs are provided extending along the Z direction within the second stack 51_2. Figure 8 As shown, multiple word line contacts WLC are positioned to the respective depths of multiple electrode films 51a (i.e., word lines WL).

[0094] The word line contact WLC is embedded inside the spacer 26 (e.g., a silicon oxide film) disposed on the inner wall of the contact hole. The word line contact WLC is, for example, made of tungsten.

[0095] For example, along Figure 7 In the cross section of the DD line, such as Figure 8As shown, the word line contact WLCd extends to the electrode film 51a of the second layer below the first laminate 51_1 or the third laminate 51_3, and is not disposed below it (in the -Z direction). The word line contact WLCd is electrically connected to the electrode film 51a of the second layer below via the connecting layer 27d. The word line contact WLCd is electrically insulated from the electrode film 51a other than the electrode film 51a of the second layer below by the spacer 26 and the insulating film 51c.

[0096] Along Figure 7 In the cross-section of the EE line, such as Figure 8 As shown, the word line contact WLCe extends to the electrode film 51a of the third layer below the first stack 51_1 or the third stack 51_3, and is not disposed below it (in the -Z direction). The word line contact WLCe is electrically connected to the electrode film 51a of the third layer below via the connecting layer 27e. The word line contact WLCe is electrically insulated from the electrode film 51a other than the electrode film 51a of the third layer below by the spacer 26 and the insulating film 51c.

[0097] Along Figure 7 In the cross-section of the FF line, such as Figure 8 As shown, the word line contact WLCf extends to the electrode film 51a of the fourth layer below the first laminate 51_1 or the third laminate 51_3, and is not disposed below it (in the -Z direction). The word line contact WLCf is electrically connected to the electrode film 51a of the fourth layer below via the connecting layer 27f. The word line contact WLCf is electrically insulated from the electrode film 51a other than the electrode film 51a of the fourth layer below by the spacer 26 and the insulating film 51c.

[0098] Along Figure 7 In the cross-section of the GG line, such as Figure 8 As shown, the word line contact WLCg extends to the electrode film 51a of the fifth layer below the first laminate 51_1 or the third laminate 51_3, and is not disposed below it (in the -Z direction). The word line contact WLCg is electrically connected to the electrode film 51a of the fifth layer below via the connecting layer 27g. The word line contact WLCg is electrically insulated from the electrode film 51a other than the electrode film 51a of the fifth layer below by the spacer 26 and the insulating film 51c.

[0099] Although not shown, the other word line contacts WLC are also set on the other electrode films 51a to their respective depths and are electrically connected to their respective electrode films 51a.

[0100] In this way, each word line contact WLC is electrically connected to the corresponding electrode film 51a via a connecting layer 27.

[0101] Multiple connection layers 27 are disposed between multiple word line contacts WLCs and their respective corresponding multiple electrode films 51a, electrically connecting them. The connection layers 27 are formed by isotropically etching a second insulating film 51c from the bottom of each word line contact WLC. Therefore, the connection layers 27 extend approximately evenly from the bottom of each word line contact WLC outwards. The connection layers 27 may be made of conductive materials such as tungsten or molybdenum.

[0102] For example, a connecting layer 27d is disposed between the word line contact WLCd and the electrode film 51a, which is the second layer from the bottom of the first laminate 51_1 or the third laminate 51_3, electrically connecting them. No connecting layer 27d is disposed on layers other than the electrode film 51a, which is the second layer from the bottom.

[0103] A connecting layer 27e is disposed between the word line contact WLCe and the electrode film 51a, which is the third layer from the bottom of the first stack 51_1 or the third stack 51_3, and electrically connects them. No connecting layer 27e is disposed on layers other than the electrode film 51a, which is the third layer from the bottom.

[0104] A connecting layer 27f is disposed between the word line contact WLCf and the electrode film 51a, which is the fourth layer from the bottom of the first stack 51_1 or the third stack 51_3, electrically connecting them. No connecting layer 27f is disposed on layers other than the electrode film 51a, which is the fourth layer from the bottom.

[0105] A connecting layer 27g is disposed between the word line contact WLCg and the electrode film 51a, which is the fifth layer from the bottom of the first stack 51_1 or the third stack 51_3, and electrically connects them. No connecting layer 27g is disposed on layers other than the electrode film 51a, which is the fifth layer from the bottom.

[0106] like Figure 8 As shown, interlayer insulating films 57 and 58 are provided in the first stack 51_1 to the third stack 51_3. The interlayer insulating films 57 and 58 are, for example, insulating films (e.g., silicon oxide films). Slits ST_CELL, ST_WLC, ST_LWI and word line contact WLC penetrate the interlayer insulating films 57 and 58 and extend along the Z direction.

[0107] Thus, according to the first embodiment, the plurality of word line contacts WLC are disposed in the second stack 51_2 up to the respective depths of the plurality of electrode films 51a, and are electrically connected to the respective electrode films 51a of the third stack 51_3 via the connecting layer 27.

[0108] The plurality of electrode films 51a of the first laminate 51_1 correspond to and are electrically connected to the plurality of electrode films 51a of the third laminate 51_3. Furthermore, the plurality of insulating films 51b of the first laminate 51_1 correspond to the plurality of insulating films 51b of the third laminate 51_3, electrically separating adjacent electrode films 51a in the Z direction. Thus, the plurality of word line contacts WLC can maintain electrical insulation from each other while being electrically connected to the plurality of electrode films 51a of the first laminate 51_1 and the third laminate 51_3, respectively.

[0109] On the other hand, a first insulating film 51b and a second insulating film 51c are provided in the second laminate 51_2. The plurality of first insulating films 51b of the second laminate 51_2 correspond to the plurality of first insulating films 51b of the first laminate 51_1 and the third laminate 51_3, respectively. The plurality of second insulating films 51c of the second laminate 51_2 correspond to the plurality of electrode films 51a of the first laminate 51_1 and the third laminate 51_3, respectively. Therefore, in the WLHU region Rwlhu, the plurality of word line contacts WLC are electrically separated from the electrode films 51a and the connecting layer 27, except for their respective corresponding electrode films 51a and connecting layers 27.

[0110] Therefore, voltage can be applied individually from each word line contact WLC to each electrode film 51a (each word line WL).

[0111] Furthermore, in the manufacturing process described later, when the second insulating film 51c of the first laminate 51_1 and the third laminate 51_3 is replaced with the electrode film 51a, the second insulating film 51c of the second laminate 51_2 is not replaced and remains. Therefore, in the WLHU region Rwlhu, it is possible to suppress the first insulating film 51b from bending or denting due to its own weight without the need for support pillars.

[0112] In addition, Figure 7 In this example, one opening (OP) and one slot (ST_LWI) are set for a single block (BLK). However, multiple openings (OP) and multiple slots (ST_LWI) can also be set for a single block (BLK). In this case, word line contacts (WLCs) can also be set around each slot (ST_LWI).

[0113] Next, the manufacturing method of the semiconductor memory device according to this embodiment will be described.

[0114] Figures 9 to 31 This is a diagram illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 9 , Figure 13 , Figure 18 , Figure 20 , Figure 23 , Figure 25 and Figure 27The plane of the storage cell array 11 is shown. Figures 10-12 , Figures 14-17 , Figure 19 , Figure 21 , Figure 22 , Figure 24 , Figure 26 , Figures 28-31 A cross-section of the storage cell array 11 is shown.

[0115] In addition, along Figure 9 The cross sections of lines AA, Bb, CC, and DD in the top view are respectively as follows: Figure 10 The isosectional views are shown as AA, BB, CC, and DD. Figure 10 The part about "along" is omitted in the text. Figure 7 The diagram shows the construction of the cross-sections corresponding to the EE line, FF line, and GG line.

[0116] like Figure 10 As shown, a first insulating film 51b (e.g., a silicon oxide film) and a second insulating film 51c (e.g., a silicon nitride film) are alternately stacked along the Z direction on a substrate 15 to form a laminate 51. Further, an interlayer insulating film 57 (e.g., a silicon oxide film) is deposited on the laminate 51.

[0117] Next, using photolithography and etching techniques, the slit hole (trench) H_ST_WLC of the slit ST_WLC and the contact hole H_WLC of the word line contact WLC are formed. The slit hole H_ST_WLC is located between the cell region Rmc and the WLHU region Rwlhu. The slit hole H_ST_WLC is shown below. Figure 9 As shown, while separating the element region Rmc from the WLHU region Rwlhu, an opening OP is provided to connect a portion of the element region Rmc to the WLHU region Rwlhu. Figure 10 As shown, contact holes H_WLC are formed in the WLHU region Rwlhu up to the depth of the second insulating film 51c corresponding to the depth of the electrically connected electrode film 51a. Multiple contact holes H_WLC are formed up to different depths of the second insulating films 51c. Furthermore, the first laminate 51_1 and the third laminate 51_3 are composed of laminates that also include multiple first insulating films 51b and multiple second insulating films 51c.

[0118] Next, as Figure 11As shown, spacers 26 (e.g., silicon oxide films) are formed on the inner walls of the slit hole H_ST_WLC and the contact hole H_WLC. Next, a sacrificial film SAC1 is embedded inside the spacers 26 within the slit hole H_ST_WLC and the contact hole H_WLC. The sacrificial film SAC1 is made of a material (e.g., polysilicon, carbon) that can be etched relative to the spacers 26 and the laminate 51. Then, by covering the laminate 51 with a silicon oxide film 57, the upper ends of the slit hole H_ST_WLC and the contact hole H_WLC are not exposed to the outside.

[0119] Next, using photolithography and etching techniques, the interlayer insulating film 57 on the slit hole H_ST_WLC is removed, and the sacrificial film SAC1 within the slit hole H_ST_WLC is selectively removed. An insulating film (e.g., a silicon oxide film) is then embedded within the slit hole H_ST_WLC. Thus, as... Figure 12 The slit ST_WLC is formed as shown.

[0120] Next, as Figure 13 As shown, multiple memory holes MH are formed in the cell region Rmc of the stacked body 51, penetrating the stacked body 51 along the Z direction. Then, on the inner wall of the memory holes MH, [the following structures are sequentially formed]. Figure 2 The barrier insulating film 52, charge storage layer 53, tunnel insulating film 54, channel semiconductor layer 55, and core insulating film 56 are shown. Thus, a columnar body CL is formed within the memory hole MH.

[0121] Simultaneously with the formation of the memory hole MH, a dummy hole DMH is formed near the opening OP of the WLHU region Rwlhu. The dummy hole DMH also penetrates the laminate 51 along the Z direction. Furthermore, simultaneously with the formation of the columnar body CL, a barrier insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56 are sequentially formed on the inner wall of the dummy hole DMH. Thus, a dummy columnar body DMC is formed within the dummy hole DMH. The dummy columnar body DMC is a columnar body with the same structure as the columnar body CL, but it does not function as a memory cell. The dummy columnar body DMC is provided to support the first insulating film 51b near the opening OP in the replacement process described later.

[0122] Next, as Figure 13 and Figure 14 As shown, slit holes H_ST_CELL for slit ST_CELL and H_ST_LWI for slit ST_LWI are formed using photolithography and etching techniques. Slit hole H_ST_CELL penetrates the unit region Rmc of the laminate 51 along the Z direction and extends along the X direction in the XY plane. Slit hole H_ST_LWI penetrates the WLHU region Rwlhu of the laminate 51 along the Z direction and extends along the X direction in the XY plane.

[0123] Next, using methods such as plasma CVD (Chemical Vapor Deposition), an insulating film 58 is deposited on the insulating film 57 under conditions of poor coverage. For example... Figure 15 As shown, the insulating film 58 is formed in such a way that it does not fill the slit holes H_ST_CELL and H_ST_WLI and blocks their openings.

[0124] Next, photolithography and etching techniques are used to remove the insulating films 57 and 58 on the contact hole H_WLC, exposing the surface of the sacrificial film SAC1.

[0125] Next, as Figure 16 As shown, the sacrificial film SAC1 inside the contact hole H_WLC is selectively removed using a wet etching method or an ashing method. Furthermore, the spacer 26 located at the bottom of the contact hole H_WLC is removed using anisotropic etching. Thus, while leaving the spacer 26 on the sidewalls of each contact hole H_WLC, the spacer 26 at the bottom is removed, exposing the second insulating film 51c at the bottom.

[0126] Next, photolithography and etching techniques are used, such as... Figure 17 Remove the insulating film 58 on the slit hole H_ST_LWI as shown.

[0127] Next, as Figure 18 and Figure 19 As shown, the second insulating film 51c of the laminate 51 in the WLHU region Rwlhu is isotropically etched using wet etching or CDE (Chemical Dry Etching) via contact hole H_WLC and slit hole H_ST_LWI. This results in a recess in the second insulating film 51c within the XY plane. Figure 18 As shown by the arrows, each of the second insulating films 51c of the laminate 51 is recessed via the slit hole H_ST_LWI, forming a recessed region RCS. At this time, the second insulating film 51c exposed at the bottom of the contact hole H_WLC is etched from the contact hole H_WLC side and also from the slit hole H_ST_LWI side. That is, as... Figure 19 As indicated by arrow A27, the second insulating film 51c exposed at the bottom of the contact hole H_WLC is etched from both the contact hole H_WLC side and the slit hole H_ST_LWI side. Thus, the contact hole H_WLC and the slit hole H_ST_LWI are connected via the cavity H27.

[0128] The inner sidewalls of the contact hole H_WLC, except for the bottom, are protected by spacers 26. Therefore, the second insulating film 51c is not exposed on the inner sidewalls of the contact hole H_WLC and will not be etched. Thus, although the contact hole H_WLC and the slit hole H_ST_LWI are connected in the layer of the second insulating film 51c exposed at the bottom of the contact hole H_WLC, they are not connected in the other layers of the second insulating film 51c.

[0129] exist Figure 19 Although not illustrated, the same applies to other contact holes H_WLC. For example, in Figure 18 For convenience, the four contact holes are shown as H_WLCd to H_WLCg, and the four corresponding cavities are shown as H27d to H27g. Contact hole H_WLCd is connected to slit hole H_ST_LWI via cavity H27d in the second insulating film 51c of the second layer below the laminate 51. Contact hole H_WLCe is connected to slit hole H_ST_LWI via cavity H27e in the second insulating film 51c of the third layer below the laminate 51. Contact hole H_WLCf is connected to slit hole H_ST_LWI via cavity H27f in the second insulating film 51c of the fourth layer below the laminate 51. Contact hole H_WLCg is connected to slit hole H_ST_LWI via cavity H27g in the second insulating film 51c of the fifth layer below the laminate 51.

[0130] Thus, although the contact hole H_WLC and the slit hole H_ST_LWI are connected in the second insulating film 51c at different depths exposed at the bottom of each contact hole H_WLC, they are not connected in the other layers of the second insulating film 51c. Therefore, the multiple contact holes H_WLC are connected to the slit hole H_ST_LWI in the second insulating film 51c of different layers via the void H27.

[0131] Next, as Figure 20 and Figure 21 As shown, a sacrificial film SAC2 is formed within the contact hole H_WLC and the slit hole H_ST_LWI. The sacrificial film SAC2 is made of a material (e.g., polysilicon, carbon) that can be selectively etched relative to the spacer 26 and the laminate 51.

[0132] Next, photolithography and etching techniques are used, such as... Figure 22 Remove the interlayer insulating film 58 on the slit hole H_ST_CELL as shown.

[0133] Next, as Figure 23 and Figure 24 As shown, the second insulating film 51c of the stack 51 of the cell region Rmc is isotropically etched through the slit hole H_ST_CELL using either wet etching or CDE. Thus, as... Figure 23 As shown, multiple second insulating films 51c within the cell region Rmc are removed in the XY plane via the slit hole H_ST_CELL. Within the cell region Rmc, the second insulating film 51c surrounding the columnar body CL is removed.

[0134] The etching of the second insulating film 51c stops at the slit ST_WLC. However, the etching of the second insulating film 51c continues from the opening OP towards the WLHU region Rwlhu, reaching the slit hole H_ST_LWI. Thus, as... Figure 23 As shown, the slit hole H_ST_CELL is connected to the slit hole H_ST_LWI and the contact hole H_WLC via the opening OP. Furthermore, at this time, the slit hole H_ST_LWI and the contact hole H_WLC are filled with a sacrificial membrane SAC2.

[0135] like Figure 24 As shown, a space SP is formed at the location where the second insulating film 51c once existed. At this time, in the unit region Rmc, since the columnar body CL supports the first insulating film 51b, the deflection or denting of the first insulating film 51b can be suppressed. Furthermore, in the WLHU region Rwlhu, no support pillars are provided except for the dummy columnar body DMC. However, in the WLHU region Rwlhu, except near the slit hole H_ST_LWI and the contact hole H_WLC, the second insulating film 51c remains, and no space SP is formed. Therefore, in the WLHU region Rwlhu, even without support pillars, the deflection or denting of the laminate 51 can be suppressed.

[0136] Next, as Figure 25 and Figure 26 As shown, the sacrificial film SAC2 is selectively removed using a wet etching method or an ashing method. Thus, the slit aperture H_ST_CELL communicates with the slit aperture H_ST_LWI via the spaces SP formed by the removal of the multiple second insulating films 51c.

[0137] Next, a thin barrier insulating film (e.g., an aluminum oxide film) is formed on the inner wall of the space SP formed between the first insulating films 51b via contact hole H_WLC, slit hole H_ST_CELL, and slit hole H_ST_LWI. Further, a titanium nitride film (not shown) is formed inside the barrier insulating film, and a conductive material is further embedded inside it. The conductive material may be, for example, tungsten or molybdenum. Thus, an electrode film 51a is formed between adjacent first insulating films 51b in the Z direction. The first laminate 51_1 and the third laminate 51_3 become a laminate containing multiple first insulating films 51b and multiple electrode films 51a. The second laminate 51_2 becomes a laminate containing multiple first insulating films 51b and multiple second insulating films 51c. Thus, in the first laminate 51_1 and the third laminate 51_3, the second insulating film 51c is replaced with the electrode film 51a (replacement process).

[0138] Next, the material of the electrode films 51a formed on the inner walls of the contact holes H_WLC, H_ST_CELL, and H_ST_LWI is etched using a wet etching method to remove short-circuit paths between adjacent electrode films 51a in the Z direction, thereby obtaining... Figure 27 and Figure 28 The structure shown.

[0139] Next, a sacrificial film SAC3, such as polysilicon or carbon, is filled into the contact hole H_WLC, slit hole H_ST_CELL, and slit hole H_ST_LWI. Then, after removing the top portion of the sacrificial film SAC3 using CMP or RIE etching-back method, an interlayer insulating film 58 is deposited on the surface. Next, the interlayer insulating film 58 on the slit holes H_ST_CELL and H_ST_LWI is removed using photolithography, and the sacrificial film SAC3 within the slit holes H_ST_CELL and H_ST_LWI is selectively removed using wet etching or ashing methods. At this point, the sacrificial film SAC3 remains within the contact hole H_WLC. Thus, the desired result is obtained. Figure 29 The structure shown.

[0140] Next, as Figure 30 As shown, spacers 26 are formed on the inner walls of slit holes H_ST_CELL and H_ST_LWI.

[0141] Next, photolithography and etching techniques are used to remove the interlayer insulating film 58 located on the contact hole H_WLC, exposing the sacrificial film SAC3. Then, wet etching or ashing methods are used, such as... Figure 31 Remove the sacrificial membrane SAC3 as shown.

[0142] Next, conductive material is embedded in the contact hole H_WLC, the slit hole H_ST_CELL, and the slit hole H_ST_LWI. This yields... Figure 7 and Figure 8 The structure shown.

[0143] Then, multiple wiring layers (not shown) are formed on the interlayer insulating film 58, after reference. Figures 3-6 The semiconductor memory device of this embodiment is completed by following the described processes.

[0144] According to the manufacturing method of this embodiment, when the second insulating film 51c of the first laminate 51_1 and the third laminate 51_3 is replaced with the electrode film 51a, the second insulating film 51c of the second laminate 51_2 is not replaced and remains. Therefore, in the WLHU region Rwlhu, it is possible to suppress the first insulating film 51b from bending or denting due to its own weight without the need for support pillars.

[0145] (Second Implementation)

[0146] Figure 32 This is a top view showing a configuration example of the memory cell array 11 according to the second embodiment. In the second embodiment, slits ST_CELL, ST_WLC, and ST_LWI are formed using a plurality of holes H_ST_CELL, H_ST_WLC, and H_ST_LWI arranged in the X direction. Therefore, slits ST_CELL, ST_WLC, and ST_LWI each extend along the arrangement direction of the plurality of holes (H_ST_CELL, H_ST_WLC, and H_ST_LWI). Slits ST_CELL and ST_WLC are formed by filling the area around the plurality of holes (H_ST_CELL and H_ST_WLC) with an insulating film, such as a silicon oxide film, and connecting the plurality of holes with the insulating film. Slits ST_LWI are formed by filling the area around the plurality of holes (H_ST_LWI) with a conductive material, such as tungsten, and connecting the plurality of holes with the conductive material.

[0147] For example, the slit ST_CELL includes a plurality of holes H_ST_CELLs that penetrate the first laminate 51_1 along the Z direction and are arranged in the X direction. The slit ST_CELL is formed by selectively removing the second insulating film 51c between adjacent first insulating films 51b in the Z direction via the plurality of holes H_ST_CELLs and filling it with an insulating film such as a silicon oxide film. Thus, the slit ST_CELL is formed in such a way that adjacent holes H_ST_CELLs in the X direction are connected through the insulating film. Therefore, the slit ST_CELL extends along the X direction in which the plurality of holes H_ST_CELLs are arranged, electrically isolating the first laminate 51_1 for each block BLK.

[0148] Furthermore, the slit ST_CELL also extends from the adjacent blocks BLK in the X direction to the second stack 51_2 of the WLHU region Rwlhu, separating the adjacent word line contacts WLC in the Y direction.

[0149] The slit ST_WLC includes a plurality of first insulating films 51b extending along the Z-direction between the first laminate 51_1 and the second laminate 51_2, and a plurality of holes H_ST_WLC arranged along the Y-direction. The slit ST_WLC fills the spaces between adjacent first insulating films 51b in the Z-direction with an insulating film, such as a silicon oxide film, through the plurality of holes H_ST_WLC. Thus, the slit ST_WLC is formed such that adjacent holes H_ST_WLC in the Y-direction are connected through the insulating film. Therefore, the slit ST_WLC extends along the Y-direction with the plurality of holes H_ST_WLC arranged therein, separating the cell region Rmc and the WLHU region Rwlhu.

[0150] In addition, similar to the first embodiment, the slit ST_WLC has an opening OP, at which the cell region Rmc is connected to the WLHU region Rwlhu.

[0151] The slit ST_LWI includes a plurality of holes H_ST_LWI extending through the third laminate 51_3 in the Z direction and arranged in the X direction. The slit ST_LWI is formed by selectively removing the second insulating film 51c between adjacent first insulating films 51b in the Z direction via the plurality of holes H_ST_LWI and filling it with a conductive material such as tungsten. Thus, the slit ST_LWI is formed such that adjacent holes H_ST_LWI in the X direction are connected by a conductive material. Therefore, the slit ST_LWI extends along the X direction where the plurality of holes H_ST_LWI are arranged, electrically connecting the electrode film 51a of the first laminate 51_1 to the word line contact WLC. The electrode film 51a of the slit ST_LWI functions as a path connecting to the word line contact WLC via the opening OP.

[0152] In addition, spacers 26 are provided on the inner walls of the multiple holes H_ST_LWI, and the holes H_ST_LWI themselves are electrically insulated from the third stack 51_3. Therefore, the electrode films 51a adjacent to each other in the Z direction of the third stack 51_3 are electrically separated from each other.

[0153] Furthermore, in the second embodiment, a slit ST_WLC2 is provided. The slit ST_WLC2 extends along the Y direction from the slit ST_CELL toward the slit ST_LWI between multiple word line contacts WLCs adjacent to each other in the X direction. The slit ST_WLC2 includes multiple holes H_ST_WLC2 that penetrate the second laminate 51_2 in the Z direction and are arranged in the Y direction. The slit ST_WLC2 is formed by selectively removing the second insulating film 51c between the first insulating films 51b via the multiple holes H_ST_WLC2 and filling it with an insulating film such as a silicon oxide film. Thus, the slit ST_WLC2 is formed in such a way that adjacent holes H_ST_WLC2 in the Y direction are connected by the insulating film. Therefore, the slit ST_WLC2 extends along the Y direction in which the multiple holes H_ST_WLC2 are arranged, separating adjacent word line contacts WLCs in the X direction.

[0154] In the unit region Rmc, multiple holes H_REP are arranged on both sides of the slit ST_CELL in the X direction. The holes H_REP penetrate the slit ST_CELL or the first laminate 51_1 in the Z direction at the boundary between the slit ST_CELL and the first laminate 51_1. Spacers 26 are provided on the inner wall of the holes H_REP, and conductive material is provided inside the spacers 26. The holes H_REP are used when the second insulating film 51c of the first laminate 51_1 is replaced with the electrode film 51a.

[0155] Multiple dummy columnar DMCs are arranged on both sides of the third stack 51_3 in the WLHU region Rwlhu, in the X direction. The dummy columnar DMCs penetrate the second stack 51_2 or the third stack 51_3 in the Z direction at the boundary between the second stack 51_2 and the third stack 51_3. The dummy columnar DMCs have the same structure as columnar CLs, but do not function as memory cells (MCs). The dummy columnar DMCs are used as supports for the first insulating film 51b of the third stack 51_3 when the second insulating film 51c of the third stack 51_3 is replaced with an electrode film 51a. Alternatively, it is not always necessary to include dummy columnar DMCs.

[0156] Multiple word line contacts (WLCs) extend along the Z-direction in the second stack 51_2, reaching the depth of each of the multiple electrode films 51a (i.e., word lines WL). Each word line contact (WLC) is electrically connected to one of the electrode films 51a in the third stack 51_3 via a connecting layer 27 located at its bottom. The third stack 51_3 has multiple electrode films 51a extending along the X-direction in the WLHU region Rwlhu, and is electrically connected to the multiple electrode films 51a of the first stack 51_1 at the opening OP. Therefore, the voltage of each word line WL can be controlled via each word line contact (WLC).

[0157] The other components of the second embodiment can be the same as those of the first embodiment. Therefore, the second embodiment can also achieve the same effects as the first embodiment.

[0158] Next, the manufacturing method of the semiconductor memory device according to the second embodiment will be described.

[0159] Figures 33-39 This is a top view illustrating an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Similar to the first embodiment, a plurality of first insulating films 51b (e.g., silicon oxide films) and a plurality of second insulating films 51c (e.g., silicon nitride films) are stacked to form a laminate 51.

[0160] Next, as Figure 33 As shown, contact holes H_WLC for word line contacts WLC are formed in the laminate 51. Multiple contact holes H_WLC are formed at different depths in the WLHU region Rwlhu, each reaching multiple second insulating films 51c of the laminate 51. Then, a sacrificial film SAC1 (e.g., polycrystalline silicon or carbon) is filled into the contact holes H_WLC.

[0161] Next, as Figure 34 As shown, multiple memory holes MH are formed in the cell region Rmc. The memory holes MH are formed in a manner that penetrates the laminate 51. Simultaneously, holes H_REP, H_ST_CELL, H_ST_WLC, H_ST_WLC2, and DMH are also formed in a manner that penetrates the laminate 51. Sacrificial film SAC1 is also filled within the memory holes MH and the holes H_REP, H_ST_CELL, H_ST_WLC, H_ST_WLC2, and DMH.

[0162] Next, a silicon oxide film 58 is deposited on the surface of the stack 51. Photolithography and etching techniques are used to remove the silicon oxide film 58 on the holes H_ST_CELL, H_ST_WLC, and H_ST_WLC2. The sacrificial film SAC1 is selectively removed using wet etching or ashing methods.

[0163] Next, a portion of each of the multiple second insulating films 51c of the laminate 51 is etched isotropically through holes H_ST_CELL, H_ST_WLC, and H_ST_WLC2 using a wet etching method. As a result, holes H_ST_CELL, H_ST_WLC, and H_ST_WLC2 are connected in the space after the second insulating films 51c have been removed.

[0164] Next, a fourth insulating film is embedded in the space left after the second insulating film 51c has been removed via holes H_ST_CELL, H_ST_WLC, and H_ST_WLC2. The fourth insulating film may be made of an insulating material such as silicon oxide. Thus, as... Figure 35 As shown, slits ST_CELL, ST_WLC, and ST_WLC2 are composed of a laminate of the first insulating film 51b and the fourth insulating film.

[0165] Next, an interlayer insulating film 58 is deposited on the surface of the stack 51. The interlayer insulating film 58 on the memory hole MH and the dummy hole DMH is removed using photolithography and etching techniques. The internal sacrificial film SAC1 is selectively removed using wet etching or ashing.

[0166] Next, as Figure 36 As shown, a columnar body CL is formed within the memory hole MH, and a dummy columnar body DMC is formed within the dummy hole DMH. The columnar body CL and the dummy columnar body DMC have the same configuration as in the first embodiment and are formed through the same process.

[0167] Next, an interlayer insulating film 58 is deposited on the surface of the laminate 51, and the interlayer insulating film 58 on the hole H_REP is removed using photolithography and etching techniques. The internal sacrificial film SAC1 is selectively removed using wet etching or ashing methods.

[0168] Next, the second insulating film 51c of the cell region Rmc is etched isotropically through the aperture H_REP using a wet etching method. Thus, as... Figure 37 As shown, the second insulating film 51c surrounding the columnar body CL in the unit region Rmc is removed, forming a space SP between the first insulating films 51b. The space SP extends to the vicinity of the opening OP. The second insulating film 51c in the WLHU region Rwlhu remains.

[0169] Next, an interlayer insulating film 58 is deposited on the surface of the laminate 51. The interlayer insulating film 58 on the contact hole H_WLC is removed using photolithography and etching techniques. The internal sacrificial film SAC1 is selectively removed using wet etching or ashing methods.

[0170] Next, a spacer 26 (e.g., a silicon oxide film) is formed on the inner wall of the contact hole H_WLC. Then, the spacer 26 at the bottom of the contact hole H_WLC is anisotropically etched away. Thus, while leaving the spacer 26 on the sidewall of the contact hole H_WLC, the spacer 26 at the bottom is removed, exposing the second insulating film 51c at the bottom.

[0171] Using wet etching or CDE, the second insulating film 51c of the laminate 51 in the WLHU region Rwlhu is isotropically etched from the bottom of the contact hole H_WLC through the contact hole H_WLC. Thus, as... Figure 38As shown, in the XY plane, the second insulating film 51c is etched from the bottom of the contact hole H_WLC toward the slits ST_CELL, ST_WLC, and ST_WLC2. A space SP is formed at the etched portion of the second insulating film 51c. The slits ST_CELL, ST_WLC, and ST_WLC2 function as etching stops.

[0172] Here, multiple contact holes H_WLCs are formed at different depths in the WLHU region Rwlhu, each reaching multiple second insulating films 51c of the laminate 51. Therefore, the multiple contact holes H_WLCs form spaces SP in multiple layers of different heights. The second insulating films 51c of the contact holes H_WLCs, except for the bottom, are not etched because they are covered by the spacer 26. Figure 38 In the diagram, only one space SP formed at the bottom of one contact hole H_WL is shown.

[0173] Next, an interlayer insulating film 58 is deposited on the surface of the laminate 51. The interlayer insulating film 58 on multiple holes H_ST_LWI is removed using photolithography and etching techniques. The internal sacrificial film SAC1 is selectively removed using wet etching or ashing methods.

[0174] Next, using wet etching or CDE, the second insulating film 51c of the laminate 51 in the WLHU region Rwlhu is etched isotropically through multiple vias H_ST_LWI. The multiple vias H_ST_LWI are interconnected along the X-direction in the space SP after the second insulating film 51c has been removed. Thus, as... Figure 39 As shown, the space SP is continuously connected from the opening OP along the arrangement direction (X direction) of the plurality of holes H_ST_LWI. Furthermore, the space SP originating from the holes H_ST_LWI communicates with the space SP originating from each contact hole H_WLC. Additionally, the space SP originating from the holes H_ST_LWI is formed by etching the second insulating film 51c of each layer of the laminate 51. At this time, the dummy pillar DMC functions as a support pillar to prevent the first insulating film 51b between the contact holes H_WLC and the holes H_ST_LWI from bending.

[0175] The spatial SP connects from the unit region Rmc through the opening OP to the hole H_ST_LWI of the WLHU region Rwlhu. Furthermore, the spatial SP connects from the hole H_ST_LWI to its corresponding contact hole H_WLC through the spatial SP of each layer.

[0176] Next, a barrier insulating film (e.g., an aluminum oxide film) is thinly formed on the inner wall of the space SP formed between the first insulating films 51b via holes H_REP, H_ST_LWI, and contact hole H_WLC. Further, a titanium nitride film (not shown) is formed inside the barrier insulating film, and a conductive material is further embedded inside it. The conductive material may be, for example, tungsten or molybdenum. Thus, an electrode film 51a is formed between adjacent first insulating films 51b in the Z direction. The first laminate 51_1 and the third laminate 51_3 become a laminate containing multiple first insulating films 51b and multiple electrode films 51a. The second laminate 51_2 is also a laminate containing multiple first insulating films 51b and multiple second insulating films 51c. Thus, in the first laminate 51_1 and the third laminate 51_3, the second insulating film 51c is replaced with the electrode film 51a (replacement process).

[0177] Next, the material of the electrode film 51a formed on the inner wall of the hole H_REP, hole H_ST_LWI and contact hole H_WLC is etched by wet etching to remove the short circuit path between adjacent electrode films 51a in the Z direction.

[0178] Next, a sacrificial film SAC3 (e.g., polysilicon or carbon) is filled into holes H_REP, H_ST_LWI, and contact hole H_WLC. Then, after removing the top portion of the sacrificial film SAC3 using CMP or RIE etching, an interlayer insulating film 58 is deposited on the surface. Next, the interlayer insulating film 58 on holes H_REP and H_ST_LWI is removed using photolithography, and the sacrificial film SAC3 within holes H_REP and H_ST_LWI is selectively removed using wet etching or ashing. At this point, the sacrificial film SAC3 remains within the contact hole H_WLC. Next, spacers 26 (e.g., silicon oxide) are formed on the inner walls of holes H_REP and H_ST_LWI. Then, a conductive material is further embedded inside the spacers 26. Thus, a... Figure 32 The structure shown.

[0179] Then, multiple wiring layers (not shown) are formed, as per reference. Figures 3-6 The semiconductor memory device of the second embodiment is completed by following the described processes.

[0180] According to the second embodiment, slits ST_CELL, ST_LWI, ST_WLC, and ST_WLC2 are formed in the arrangement direction of holes H_ST_CELL, H_ST_LWI, H_ST_WLC, and H_ST_WLC2. Therefore, in the WLHU region Rwlhu, the area where the second insulating film 51c is replaced by the electrode film 51a is limited, making it difficult for the first insulating film 51b to bend during the replacement process. Therefore, it is not necessary to provide support pillars in the WLHU region Rwlhu. That is, the second embodiment achieves the same effects as the first embodiment.

[0181] According to the second embodiment, the hole H_ST_CELL used to form the slit ST_CELL is provided separately from the hole H_REP used in the replacement process. Therefore, the slit ST_CELL can be formed not only in the cell region Rmc, but also extended to form in the WLHU region Rwlhu. As a result, the first insulating film 51b becomes more difficult to bend during the replacement process.

[0182] According to the second embodiment, in the WLHU region Rwlhu, a slit ST_WLC2 is provided between adjacent word line contacts WLC along the X direction. Thus, during the replacement process, the first insulating film 51b becomes more resistant to bending, and the second insulating film 51c etched through each contact hole H_WLC is restricted, thereby suppressing short circuits between adjacent word line contacts WLC.

[0183] Additionally, one opening (OP) and one slot (ST_LWI) are configured for one block (BLK). However, multiple openings (OP) and multiple slots (ST_LWI) can also be configured for one block (BLK). In this case, word line contacts (WLCs) can also be configured around each slot (ST_LWI).

[0184] (Third Implementation)

[0185] Figure 40 This is a top view showing an example configuration of a semiconductor memory device according to the third embodiment. Figure 41 It is along Figure 40 A cross-sectional view of line A41-A41. Figure 42 It is along Figure 40 A cross-sectional view of line B42-B42. Figure 40 It shows Figure 41 and 42 The plane at the horizontal level indicated by the dashed line.

[0186] In the third embodiment, in the WLHU region Rwlhu, the second laminate 51_2 is processed into a stepped shape. For example, as... Figure 40As shown, the second stack 51_2 has steps STP1 to STP8. Steps STP1 to STP8 descend sequentially in the -Z direction. Above steps STP1 to STP8 of the second stack 51_2, as... Figure 41 and Figure 42 As shown, an interlayer insulating film 57 is provided. Multiple word line contacts WLCs penetrate the interlayer insulating film 57 disposed on the second laminate 51_2 along the Z direction, up to the depth of their respective corresponding electrode films 51a. Furthermore, each of the multiple word line contacts WLCs corresponds to steps STP1 to STP8, and is electrically connected to the multiple electrode films 51a located directly below steps STP1 to STP8 via the connecting layer 27. Therefore, the multiple word line contacts WLCs extend to different depths within the interlayer insulating film 57.

[0187] The second laminate 51_2 is processed into a stepped shape in both the X and Y directions. Therefore, the second laminate 51_2 descends in stages in the X direction according to steps STP1, STP3, STP5, and STP7, and also descends in stages according to steps STP2, STP4, STP6, and STP8. Further, the second laminate 51_2 descends in the Y direction according to steps STP1 and STP2, steps STP3 and STP4, steps STP5 and STP6, and steps STP7 and STP8.

[0188] The slit ST_LWI includes a plurality of holes H_ST_LWI extending through the third laminate 51_3 in the Z direction and arranged in the X direction. The slit ST_LWI is formed by filling the spaces between adjacent first insulating films 51b in the Z direction with a conductive material, such as tungsten, via the plurality of holes H_ST_LWI. Therefore, the slit ST_LWI is formed such that adjacent holes H_ST_LWI in the X direction are connected by a conductive material. Thus, the slit ST_LWI extends along the X direction where the plurality of holes H_ST_LWI are arranged, electrically connecting the electrode film 51a of the first laminate 51_1 to the word line contact WLC. The electrode film 51a of the slit ST_LWI functions as a path connecting to the word line contact WLC via the opening OP. That is, the slit ST_LWI (the electrode film 51a of the third laminate 51_3) can function in the same way as in the second embodiment. Furthermore, the third laminate 51_3 can be formed using holes H_ST_LWI in the same way as in the second embodiment.

[0189] Multiple word line contacts (WLCs) are connected to a connection layer 27 disposed at their respective bottoms, and are electrically connected to the electrode film 51a of their respective third laminates 51_3 via the connection layer 27. The configuration and formation method of the word line contacts (WLCs) and the connection layer 27 can be the same as those in the second embodiment. However, although the hole H_ST_LWI is provided through the third laminate 51_3 below the interlayer insulating film 57, it is not provided within the interlayer insulating film 57. On the other hand, the word line contacts (WLCs) penetrate the interlayer insulating film 57 and are provided up to the depth of the connection layer 27, but are not formed inside the second laminate 51_2.

[0190] For example, word line contact WLCa Figure 41 and Figure 42 As shown, the interlayer insulating film 57 is formed up to the connecting layer 27 corresponding to the step STP5. The connecting layer 27 corresponding to the word line contact WLCa is connected to the electrode film 51a (i.e., the word line WL) which is set at the same height. Thus, the word line contact WLCa can control the voltage of its corresponding word line WL.

[0191] Figure 41 The word line contact WLCb extends through the interlayer insulating film 57, reaching the connection layer 27 corresponding to the step STP6, which is one level below the word line contact WLCa. The connection layer 27 corresponding to the word line contact WLCb is connected to the electrode film 51a, which is disposed at the same height. Thus, the word line contact WLCb can control the voltage of its corresponding word line WL.

[0192] Figure 42 The word line contact WLCc extends through the interlayer insulating film 57 to the connecting layer 27, which corresponds to the step STP7 one level below the word line contact WLCb. The connecting layer 27 corresponding to the word line contact WLCc is connected to the electrode film 51a, which is disposed at the same height. Thus, the word line contact WLCc can control the voltage of its corresponding word line WL.

[0193] The same applies to the other steps STP1 to STP4 and STP8; the word line contact WLC is electrically connected to its corresponding word line WL. Thus, multiple word line contacts WLC can control the voltage of their respective word lines WL.

[0194] The difference between the third embodiment and the second embodiment is that, in the WLHU region Rwlhu, the second laminate 51_2 is processed into a stepped shape, and an interlayer insulating film 57 is disposed thereon. However, the configuration of the third embodiment roughly corresponds to that of the second embodiment. Therefore, the third embodiment does not require support pillars in the WLHU region Rwlhu, and can achieve the same effect as the second embodiment. In addition, the manufacturing method of the third embodiment can be understood by referring to the manufacturing method of the second embodiment. Therefore, the description of the manufacturing method of the third embodiment is omitted here.

[0195] Additionally, one opening (OP) and one slot (ST_LWI) are configured for one block (BLK). However, multiple openings (OP) and multiple slots (ST_LWI) can also be configured for one block (BLK). In this case, word line contacts (WLCs) can also be configured around each slot (ST_LWI).

[0196] (Fourth Implementation)

[0197] Figure 43 and Figure 44 This is a top view showing an example configuration of a semiconductor memory device according to the fourth embodiment. Figure 44 Showing will Figure 43 It is a magnified plane that constitutes part of the composition. Figure 45 It is along Figure 44 A cross-sectional view of line A45-A45. Figure 46 It is along Figure 44 A cross-sectional view of line B46-B46. Figure 44 It shows Figure 45 and 46 The plane at the horizontal level indicated by the dashed line.

[0198] like Figure 43 As shown, in the fourth embodiment, the WLHU region Rwlhu is located between multiple adjacent cell regions Rmc in the X direction and is shared by their storage cell array 11.

[0199] In the fourth embodiment, the WLHU region Rwlhu includes a stepped section STP and a bridging section BRG. The stepped section STP is a second laminate 51_2 that is processed into a stepped shape, descending from the center of the WLHU region Rwlhu towards the unit regions Rmc on both sides. The bridging section BRG is not processed into a stepped shape and remains until the top layer, serving as a second laminate 51_2 that connects multiple adjacent unit regions Rmc.

[0200] In the fourth embodiment, the word line contact WLC is connected to the slit ST_LWI provided in the bridging section BRG via a slit ST_LWI provided in the stepped section STP. The slit ST_LWI is also provided in the bridging section BRG, branching in the ±X direction and connecting to a plurality of adjacent memory cell arrays 11. The slit ST_LWI includes an aperture H_ST_LWI and a third laminate 51_3 provided around it. The word line contact WLC is electrically connected to the electrode film 51a (word line WL) of the cell region Rmc via the electrode film 51a of the third laminate 51_3.

[0201] For example, such as Figure 44 As shown, the second stack 51_2 has steps STP1 to STP6. Steps STP1 to STP6 descend sequentially in the -Z direction. Above steps STP1 to STP6 of the second stack 51_2, as... Figure 45 and Figure 46 As shown, an interlayer insulating film 57 is provided. Multiple word line contacts WLCs penetrate the interlayer insulating film 57 disposed on the second laminate 51_2 along the Z direction, up to the depth of their respective corresponding electrode films 51a. Furthermore, each of the multiple word line contacts WLCs corresponds to steps STP1 to STP6, and is electrically connected to the multiple electrode films 51a located directly below steps STP1 to STP6 via the connecting layer 27. Therefore, the multiple word line contacts WLCs extend to different depths within the interlayer insulating film 57.

[0202] The second laminate 51_2 is processed into a stepped shape in both the X and Y directions. Therefore, the second laminate 51_2 descends in stages in the X direction according to steps STP1, STP3, and STP5, and in stages according to steps STP2, STP4, and STP6. Further, the second laminate 51_2 descends in the Y direction according to steps STP1 and STP2, steps STP3 and STP4, and steps STP5 and STP6.

[0203] The slit ST_LWI has the same configuration as in the third embodiment. The slit ST_LWI extends along the X direction where a plurality of holes H_ST_LWI are arranged, electrically connecting the electrode film 51a of the first laminate 51_1 to the word line contact WLC. The electrode film 51a of the slit ST_LWI functions as a path connecting to the word line contact WLC via the opening OP.

[0204] In the fourth embodiment, the slit ST_LWI is provided throughout the second stack 51_2 of the center of the stepped portion STP, the WLHU region Rwlhu, and the second stack 51_2 of the bridging portion BRG. Furthermore, the slit ST_LWI branches in the bridging portion BRG toward multiple adjacent cell regions Rmc in the X direction, and connects to the first stack 51_1 of both at the opening OP of the multiple cell regions Rmc. Thus, the word line contact WLC is electrically connected to the corresponding word line WL in each of the multiple adjacent cell regions Rmc.

[0205] Multiple word line contacts (WLCs) are connected to a connection layer 27 disposed at their respective bottoms, and are electrically connected to the electrode film 51a of their respective third laminates 51_3 via the connection layer 27. The configuration and formation method of the word line contacts (WLCs) and the connection layer 27 can be the same as those in the second embodiment. However, although the hole H_ST_LWI is provided through the third laminate 51_3 below the interlayer insulating film 57, it is not provided in the interlayer insulating film 57. On the other hand, the word line contacts (WLCs) penetrate the interlayer insulating film 57 and are provided up to the depth of the connection layer 27, but are not formed inside the second laminate 51_2.

[0206] For example, word line contact WLCa Figure 45 and Figure 46 As shown, the interlayer insulating film 57 is formed up to the connecting layer 27 corresponding to the step STP3. The connecting layer 27 corresponding to the word line contact WLCa is connected to the electrode film 51a (i.e., the word line WL) which is set at the same height. Thus, the word line contact WLCa can control the voltage of its corresponding word line WL.

[0207] Figure 45 The word line contact WLCb extends through the interlayer insulating film 57, reaching the connecting layer 27 corresponding to the step STP4, which is one level below the word line contact WLCa. The connecting layer 27 corresponding to the word line contact WLCb is connected to the electrode film 51a, which is disposed at the same height. Thus, the word line contact WLCb can control the voltage of its corresponding word line WL.

[0208] Figure 46 The word line contact WLCc extends through the interlayer insulating film 57 to the connecting layer 27, which corresponds to the step STP5, one level below the word line contact WLCb. The connecting layer 27 corresponding to the word line contact WLCc is connected to the electrode film 51a, which is disposed at the same height. Thus, the word line contact WLCc can control the voltage of its corresponding word line WL.

[0209] Similarly, for the other step arrays STP1, STP2, and STP6, the word line contacts WLC are electrically connected to their respective word lines WL. That is, multiple connection layers 27 electrically connect the multiple word line contacts WLC to the multiple electrode films 51a in the adjacent memory cell array 11. Thus, the multiple word line contacts WLC can each control the voltage of their respective word lines WL.

[0210] The fourth embodiment differs from the third embodiment in the configuration of the WLHU region Rwlhu, the structure of the stepped section STP, and the structure of the bridging section BRG. Therefore, the difference between the fourth and third embodiments lies in the path of the slit ST_LWI that electrically connects the word line contact WLC and the word line WL. However, the other configurations of the fourth embodiment correspond to those of the third embodiment. Therefore, the fourth embodiment does not require a support column in the WLHU region Rwlhu, achieving the same effect as the second embodiment. Furthermore, similar to the third embodiment, the manufacturing method of the fourth embodiment can be understood by referring to the manufacturing method of the second embodiment. Therefore, the description of the manufacturing method of the fourth embodiment is omitted here.

[0211] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0212] [Explanation of reference numerals in the attached figures]

[0213] 11-cell array

[0214] BLK Block

[0215] MC storage unit

[0216] DMC Dummy column

[0217] WL lettering

[0218] Rwlhu, WLHU area

[0219] Rmc unit region

[0220] 51_1 First layer of stacked body

[0221] 51_2 Second layer stack

[0222] 51_3 Third layer stack

[0223] ST_WLC, ST_LWI, ST_CELL slit

[0224] WLC word line contact

[0225] 26 spacers

[0226] 27 Connection Layer

[0227] 51a electrode film

[0228] 51b, 51c First insulating film and second insulating film

[0229] 57 and 58 interlayer insulating film

Claims

1. A semiconductor memory device comprising: A first laminate, wherein an electrode film and a first insulating film are alternately laminated in a first direction; A second laminate is disposed adjacent to the first laminate, wherein the first insulating film and the second insulating film are alternately laminated in the first direction; A third laminate extends from the end of the first laminate in a second direction in a first plane orthogonal to the first direction, wherein the electrode film and the first insulating film are alternately laminated in the first direction. The first columnar body includes a semiconductor layer disposed through the first stacked body along the first direction, and forms a plurality of memory cells with the plurality of electrode films as gate electrodes at the intersection portions where they intersect with the plurality of electrode films. Multiple contacts extend along the first direction within the second laminate or within a third insulating film disposed above the second laminate, up to the respective depths of the multiple electrode films of the third laminate; as well as Multiple connection layers electrically connect the multiple contacts to the multiple electrode films corresponding to each of the multiple contacts.

2. The semiconductor memory device according to claim 1, wherein, It also has multiple first slits that penetrate the first laminate along the first direction and extend in the second direction to divide the first laminate into multiple blocks.

3. The semiconductor memory device according to claim 2, wherein, It also has a second slit that penetrates the first or second laminate in the first direction between the first laminate and the second laminate, extends discontinuously in the first surface in a third direction orthogonal to the second direction, and has an opening that connects a portion of the plurality of blocks to the third laminate.

4. The semiconductor memory device according to claim 3, wherein, It also has a third slit that extends in the third stack along the second direction and penetrates the third stack along the first direction.

5. The semiconductor memory device according to claim 1, wherein, The plurality of electrode films of the first laminate are electrically connected to the plurality of electrode films of the third laminate. In the first and third stacks, the plurality of electrode films adjacent in the first direction are electrically separated by the first insulating film.

6. The semiconductor memory device according to claim 1, wherein, The plurality of first insulating films in the first laminate and the third laminate respectively correspond to the plurality of first insulating films in the second laminate. The plurality of electrode films of the first laminate and the third laminate correspond to the plurality of second insulating films of the second laminate, respectively.

7. The semiconductor memory device according to claim 1, wherein, One of the plurality of contacts is electrically connected to the corresponding electrode film via one of the connection layers.

8. The semiconductor memory device according to claim 2, wherein, The first slit includes a plurality of first holes that penetrate the plurality of first insulating films of the first laminate along the first direction and are arranged in the second direction.

9. A method for manufacturing a semiconductor memory device, comprising the following processes: A laminate is formed by alternately stacking a first insulating film and a second insulating film in a first direction. A second slit hole is formed between a first region of the laminate and a second region of the laminate disposed adjacent to the first region. Furthermore, a plurality of contact holes are formed in the second region of the laminate up to the depth of each of the plurality of second insulating films. The second slit hole, while separating the first region from the second region, has an opening that connects a portion of the first region to the second region. A plurality of first slit holes and a plurality of third slit holes are formed. The plurality of first slit holes penetrate the first region of the laminate along the first direction and extend along the second direction in a first plane orthogonal to the first direction. The plurality of third slit holes penetrate the second region of the laminate along the first direction and extend along the second direction. By removing a portion of the second insulating film located on the bottom surface of each of the plurality of contact holes through the plurality of contact holes, and removing a portion of the plurality of second insulating film in the second region through the plurality of third slit holes, the plurality of contact holes are made to communicate with the plurality of third slit holes. The plurality of second insulating films in the first region are removed through the plurality of first slit holes, and the plurality of first slit holes are connected to the plurality of third slit holes through the opening. An electrode film is formed by removing the second insulating film through the plurality of contact holes, the plurality of first slit holes and the plurality of third slit holes, and embedding conductive material in the space formed between the first insulating films.

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