Capacitor, integrated passive device and glass interposer

Abstract

This invention discloses a capacitor, an integrated passive device, and a glass interposer, comprising: a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked on a substrate; the dielectric layer includes: a first sub-dielectric layer and a second sub-dielectric layer alternately arranged along the arrangement direction of the first electrode layer and the second electrode layer, wherein the number of first sub-dielectric layers is greater than the number of second sub-dielectric layers; the dielectric constant of the first sub-dielectric layer is less than the dielectric constant of the second sub-dielectric layer. Thus, by setting the alternating first and second sub-dielectric layers, the stress accumulated inside the dielectric layer due to the high dielectric constant of the second dielectric layer can be reduced, thereby reducing leakage current in the capacitor, increasing the breakdown voltage of the dielectric layer in the capacitor, and further improving the stability of the capacitor under complex operating conditions such as high voltage and high frequency, reducing the risk of capacitor failure due to dielectric layer breakdown, and improving the reliability of the capacitor.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and more particularly to a capacitor, an integrated passive device, and a glass interposer. Background Technology

[0002] In modern integrated circuit technology, various passive components, such as inductors, capacitors, and resistors, can be integrated into a relatively small space, greatly improving the integration and performance of circuits. These components are widely used in numerous fields, including radio frequency circuits and mixed-signal circuits. Among these, capacitors have gradually become the mainstream capacitor type due to their advantages such as low parasitic capacitance between the capacitor and the silicon substrate, minimal performance dependence on frequency and temperature, and compatibility with existing integrated circuit processes. Furthermore, as electronic products move towards miniaturization and higher frequencies, the capacitance density of capacitors is also increasing, which places higher demands on their reliability.

[0003] Therefore, how to improve the reliability of capacitors has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0004] This invention provides a capacitor, an integrated passive device, and a glass interposer to improve the reliability of the capacitor.

[0005] In a first aspect, embodiments of the present invention provide a capacitor, comprising: a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked on a substrate; The dielectric layer includes: a first sub-dielectric layer and a second sub-dielectric layer arranged alternately along the arrangement direction of the first electrode layer and the second electrode layer, wherein the number of the first sub-dielectric layers is greater than the number of the second sub-dielectric layers; The dielectric constant of the first sub-dielectric layer is less than that of the second sub-dielectric layer.

[0006] In some embodiments, the orthographic projection of the dielectric layer over the first electrode layer covers the sidewall of the first electrode layer.

[0007] In some embodiments, the ratio between the thickness of the second sub-dielectric layer and the thickness of the first sub-dielectric layer is greater than or equal to 4 and less than or equal to 10.

[0008] In some embodiments, the dielectric constant of the second sub-dielectric layer is greater than 10.

[0009] In some embodiments, the capacitor further includes an interface smoothing layer located between at least one of the first electrode layer and the second electrode layer and the dielectric layer, the interface smoothing layer being used to eliminate grain boundaries and spikes on the surface of the first electrode layer and / or the second electrode layer facing the dielectric layer.

[0010] In some embodiments, the thickness of the interface smoothing layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.

[0011] In some embodiments, the material of the interface smoothing layer is at least one of TiN, TaN, Ta, and TaTiN.

[0012] In some embodiments, the capacitor further includes: a field plate structure, wherein the field plate structure is located in the same film layer as the second electrode layer, and the orthographic projection of the field plate structure onto the dielectric layer covers the sidewall of the dielectric layer.

[0013] In some embodiments, the second electrode layer includes an electrode portion and an extension portion extending from the edge of the electrode portion, wherein the orthographic projection of the electrode portion onto the first electrode layer coincides with the first electrode layer; the extension portion is reused as the field plate structure.

[0014] Secondly, embodiments of the present invention provide an integrated passive device, including: a substrate, and a capacitor disposed on the substrate as described in the first aspect above.

[0015] Thirdly, embodiments of the present invention provide a glass interlayer, comprising: a glass substrate, and a capacitor as described in the first aspect above disposed on the glass substrate.

[0016] The beneficial effects of this invention are as follows: This invention provides a capacitor, an integrated passive device, and a glass interposer, comprising: a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked on a substrate; the dielectric layer includes: a first sub-dielectric layer and a second sub-dielectric layer alternately arranged along the arrangement direction of the first electrode layer and the second electrode layer, wherein the number of first sub-dielectric layers is greater than the number of second sub-dielectric layers; the dielectric constant of the first sub-dielectric layer is less than the dielectric constant of the second sub-dielectric layer. Thus, by setting the alternating first and second sub-dielectric layers, the stress accumulated inside the dielectric layer due to the high dielectric constant of the second dielectric layer can be reduced, thereby reducing leakage current in the capacitor, increasing the breakdown voltage of the dielectric layer in the capacitor, and further improving the stability of the capacitor under complex operating conditions such as high voltage and high frequency, reducing the risk of capacitor failure due to dielectric layer breakdown, and improving the reliability of the capacitor. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of a capacitor provided in an embodiment of the present invention; Figure 2 This is a cross-sectional view of another capacitor provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the film layer dimensions of a capacitor provided in an embodiment of the present invention; Figure 4 This is a cross-sectional view of an integrated passive device provided in an embodiment of the present invention; Figure 5 This is a cross-sectional view of a glass interlayer provided in an embodiment of the present invention. Detailed Implementation

[0018] The following detailed description, with reference to the accompanying drawings, provides a specific embodiment of a capacitor, an integrated passive device, and a glass interposer provided by the present invention. It should be noted that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0019] This invention provides a capacitor, such as... Figure 1 As shown, it includes: a first electrode layer 200, a dielectric layer 300, and a second electrode layer 400 sequentially stacked on a substrate 100. The dielectric layer 300 includes: a first sub-dielectric layer 310 and a second sub-dielectric layer 320 arranged alternately along the arrangement direction of the first electrode layer 200 and the second electrode layer 400, wherein the number of the first sub-dielectric layers 310 is greater than the number of the second sub-dielectric layers 320. The dielectric constant of the first sub-dielectric layer 310 is less than that of the second sub-dielectric layer 320.

[0020] In this way, by setting alternating first and second sub-dielectric layers, the stress accumulated inside the dielectric layer caused by setting a second dielectric layer with a high dielectric constant can be reduced, thereby reducing the leakage current problem of the capacitor, increasing the breakdown voltage of the dielectric layer in the capacitor, and thus improving the stability of the capacitor under complex working conditions such as high voltage and high frequency, reducing the risk of capacitor failure due to dielectric layer breakdown, and improving the reliability of the capacitor.

[0021] In addition, when the first sub-dielectric layer and the second sub-dielectric layer are arranged alternately, and the number of the first sub-dielectric layer is greater than the number of the second sub-dielectric layer, the film layer in the dielectric layer that is closest to the electrode layer (including the first electrode layer and the second electrode layer) is the first sub-dielectric layer. This can avoid direct contact between the second sub-dielectric layer with high dielectric constant and the electrode layer, reduce interface defects when the second sub-dielectric layer contacts the electrode layer, thereby reducing the risk of capacitor breakdown and further improving the reliability of the capacitor.

[0022] It should be understood that the dielectric layer is not limited to, for example, Figure 1The three-layer structure shown can also be a five-layer, seven-layer, nine-layer, or more-layer structure. For example, when the dielectric layer is a five-layer structure, the layers stacked in the dielectric layer are, in order: first sub-dielectric layer, second sub-dielectric layer, first sub-dielectric layer, second sub-dielectric layer, and first sub-dielectric layer. The number of layers in the dielectric layer is not specifically limited here.

[0023] In some embodiments, such as Figure 2 As shown, the orthographic projection of the dielectric layer 300 onto the first electrode layer 200 covers the sidewalls of the first electrode layer 200. Thus, by providing a dielectric layer 300 covering the sidewalls of the first electrode layer 200, the concentration of electric field lines at the edge of the first electrode layer 200 can be reduced, thereby optimizing the electric field of the capacitor, increasing the breakdown voltage of the capacitor, and improving the reliability of the capacitor.

[0024] In some embodiments, the ratio between the thickness of the second sub-dielectric layer and the thickness of the first sub-dielectric layer is greater than or equal to 4 and less than or equal to 10. This avoids a low dielectric constant due to an excessively small proportion of the second sub-dielectric layer thickness, thus achieving a higher capacitance density. It also avoids excessive internal stress in the dielectric layer due to an excessively large proportion of the second sub-dielectric layer thickness, thereby increasing the breakdown voltage of the dielectric layer in the capacitor, reducing the risk of capacitor failure due to dielectric layer breakdown, and improving the reliability of the capacitor.

[0025] Furthermore, for multiple first dielectric layers, the thickness of each first dielectric layer can be set to be the same, thereby reducing the manufacturing complexity of the capacitor. At least some of the first dielectric layers can have different thicknesses, allowing the thickness of each first dielectric layer to be set according to actual performance requirements, thus improving the design flexibility of the dielectric layers. Similarly, for multiple second dielectric layers, the thickness of each second dielectric layer can be set to be the same, thereby reducing the manufacturing complexity of the capacitor. At least some of the second dielectric layers can have different thicknesses, allowing the thickness of each second dielectric layer to be set according to actual performance requirements, thus improving the design flexibility of the dielectric layers.

[0026] In some embodiments, the dielectric constant of the second sub-dielectric layer is greater than 10, meaning the second sub-dielectric layer is a high-k dielectric layer. The material of the second sub-dielectric layer includes, but is not limited to, materials with high dielectric constants such as hafnium dioxide and zirconium dioxide. Thus, by employing a second sub-dielectric layer with a higher dielectric constant, the capacitance density of the capacitor can be increased, thereby achieving higher capacitance within the same capacitor size. This meets the requirements of integrated circuits for higher integration density and broadens the application scenarios of capacitors.

[0027] It should be understood that the first sub-dielectric layer can be made of a material with a low dielectric constant, such as silicon oxide or aluminum oxide, thereby improving the interfacial compatibility between the dielectric layer and the electrode layer and reducing the stress inside the dielectric layer.

[0028] In some embodiments, such as Figure 2 As shown, the capacitor further includes: an interface smoothing layer 500 located between at least one of the first electrode layer 200 and the second electrode layer 400 and the dielectric layer 300, the interface smoothing layer 500 being used to eliminate grain boundaries and spikes on the surfaces of the first electrode layer 200 and / or the second electrode layer 400 facing the dielectric layer 300. Figure 2 The diagram shows an interface smoothing layer 500 between the first electrode layer 200 and the dielectric layer 300, and also between the second electrode layer 400 and the dielectric layer 300. Alternatively, the interface smoothing layer 500 can be provided only between the first electrode layer 200 and the dielectric layer 300. Figure 2 (not shown in the image), or an interface smoothing layer 500 may be provided only between the second electrode layer 400 and the dielectric layer 300. Figure 2 (Not shown in the image).

[0029] Thus, by setting an interface smoothing layer between the dielectric layer and the electrode layers (including the first and second electrode layers), the interface smoothing layer eliminates grain boundaries and spikes on the surface of the electrode layer facing the dielectric layer, improves the uniformity of the electric field distribution on the surface of the electrode layer facing the dielectric layer, reduces the risk of local breakdown of the capacitor, and further improves the stability and reliability of the capacitor. Moreover, the interface smoothing layer can also improve the interfacial compatibility between the dielectric layer and the electrode layer. By blocking interdiffusion and chemical reactions between the electrode layer and the dielectric layer, it maintains the originality and stability of the dielectric layer, reduces defects at the interface between the electrode layer and the dielectric layer caused by chemical reactions or lattice mismatch, increases the Q value of the capacitor, reduces the leakage current at the interface between the electrode layer and the dielectric layer, and further improves the performance of the capacitor.

[0030] In some embodiments, the thickness of the interface smoothing layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers. This avoids the situation where the interface smoothing layer is too thin, preventing it from failing to eliminate grain boundaries and spikes on the electrode layer's surface facing the dielectric layer, thus reducing the risk of localized capacitor breakdown and improving the capacitor's stability and reliability. It also avoids the situation where the interface smoothing layer is too thin, preventing it from blocking interdiffusion and chemical reactions between the electrode layer and the dielectric layer, thereby increasing the capacitor's Q value, reducing leakage current at the interface between the electrode layer and the dielectric layer, and further improving the capacitor's performance. Furthermore, it avoids the situation where the interface smoothing layer is too thick, resulting in an excessively large overall capacitor thickness, reducing the capacitor's size, which is beneficial for the miniaturization of electronic devices and broadens the application scenarios of the capacitor.

[0031] In some embodiments, the material of the interface smoothing layer includes, but is not limited to, at least one of TiN, TaN, Ta, and TaTiN. Of course, the interface smoothing layer may also be selected from other materials capable of eliminating grain boundaries and spikes on the surface of the electrode layer facing the dielectric layer, and no specific limitation is made here.

[0032] In some embodiments, the first electrode layer and the second electrode layer may be made of aluminum doped with a small amount of copper, and the thickness may be greater than or equal to 100 nanometers and less than or equal to 3 micrometers. Of course, the first electrode layer and the second electrode layer may also be made of other materials as described by those skilled in the art, such as titanium, platinum, etc., and no specific limitation is made here.

[0033] In some embodiments, the capacitor further includes a field plate structure, which is located in the same film layer as the second electrode layer, and the orthographic projection of the field plate structure onto the dielectric layer covers the sidewalls of the dielectric layer. Thus, by incorporating a field plate structure in the capacitor, the electric field distribution at the capacitor edge can be optimized, thereby preventing excessive concentration of electric field lines, increasing the capacitor's breakdown voltage, and consequently improving the capacitor's reliability. Furthermore, by incorporating the field plate structure, the encapsulation effect of the dielectric layer can be improved, preventing moisture and contaminant intrusion caused by potential damage or defects on the dielectric layer sidewalls, further enhancing the capacitor's reliability.

[0034] In some embodiments, such as Figure 2 As shown, the second electrode layer 400 includes an electrode portion 410 and an epitaxial portion 420 extending from the edge of the electrode portion 410. The orthographic projection of the electrode portion 410 onto the first electrode layer 200 coincides with the first electrode layer 200. The epitaxial portion 420 is reused as a field plate structure.

[0035] Thus, by fabricating an epitaxial portion and using it as the field plate structure, the manufacturing process of capacitors can be simplified and manufacturing costs reduced.

[0036] In some embodiments, such as Figure 3As shown in the figure, when the positive projection of the dielectric layer 300 on the first electrode layer 200 covers the sidewall of the first electrode layer 200, and a part of the second electrode layer 400 is reused as a field plate structure, the first electrode layer 200, the dielectric layer 300, and the second electrode layer in the capacitor show a sequentially covering structure, and the capacitor can satisfy the following dimensional relationships: d10 < d20 < d30, d21 ≥ d20, d31 ≥ d30, d33 ≥ d32, where d10 is the size of the sidewall of the first electrode layer 200, d20 is the size of the part of the dielectric layer 300 that covers the sidewall of the first electrode layer 200 (which can be called the first inclined part), d30 is the size of the part of the second electrode layer 400 that covers the first sidewall of the first electrode layer 200 (which can be called the second inclined part), d21 is the length of the part of the dielectric layer 300 where the first inclined part extends towards the edge of the capacitor, and the second electrode layer 400 includes, in sequence from the second inclined part towards the edge of the capacitor: a first parallel part with a length of d31, a third inclined part d31 with a length of d32, and a second parallel part with a length of d33.

[0037] In this way, by controlling the sizes of each film layer, the coverage effect of the dielectric layer on the first electrode layer can be improved, the electric field improvement effect of the long plate structure can be enhanced, and thus the reliability of the capacitor can be further improved.

[0038] In addition to the structure described above, as Figure 1 shown, the capacitor further includes a packaging layer 600. The material of the packaging layer 600 can be, but is not limited to, common packaging materials in the art such as polyimide, etc. In this way, the packaging of the capacitor can be achieved, the erosion of external water vapor can be reduced, and the reliability of the capacitor can be improved.

[0039] As Figure 1 shown, the capacitor further includes a lead-out electrode 700. Figure 1 Only the lead-out electrode 700 of the second electrode layer 400 is shown in the figure, and the lead-out electrode 700 of the first electrode layer 200 is not shown. In this way, the input of an external electrical signal can be achieved, and the connection with other electronic devices can be realized.

[0040] Based on the same inventive concept, an embodiment of the present invention further provides an integrated passive device. The implementation principle of this integrated passive device is similar to that of the aforementioned capacitor. The specific implementation manner of this integrated passive device can refer to the embodiment of the aforementioned capacitor, and the repeated parts will not be elaborated here.

[0041] Specifically, an integrated passive device provided by an embodiment of the present invention, as Figure 4 shown, includes: a substrate 40, and a capacitor 41 as described above provided on the substrate 40. In addition, as Figure 4 shown, the integrated passive device further includes a multi-layer packaging layer 600, an inductor 42, and multiple pins 43.

[0042] The number of capacitors 42 can be set according to actual needs and is not limited to... Figure 5 As shown in the diagram, the number of inductors 42 can also be set according to actual needs and is not limited to one. Figure 5 The specific number of the package layer 600 and pins 43 shown in the figure is not specifically limited here.

[0043] Thus, by employing the capacitor described above, the series resistance caused by surface scattering and skin effect of the electrode layer can be reduced by setting an interface smoothing layer. Furthermore, the use of a high-dielectric-constant second dielectric layer and a low-dielectric-constant first dielectric layer, arranged in an alternating pattern, allows for a thicker dielectric layer, thereby reducing leakage current loss and improving the high-frequency Q value of the capacitor, thus enhancing the performance of the integrated passive device. In addition, the low-dielectric-constant first dielectric layer can suppress leakage current growth and mitigate the negative temperature coefficient of the high-dielectric-constant second dielectric layer, making the overall capacitance temperature coefficient of the capacitor close to zero. This, in turn, improves the capacitor's breakdown voltage and time-dependent dielectric breakdown lifetime, further enhancing the performance of the integrated passive device.

[0044] Based on the same inventive concept, this invention also provides a glass interlayer. The implementation principle of the glass interlayer is similar to that of the aforementioned capacitor. The specific implementation method of the glass interlayer can be found in the embodiments of the aforementioned capacitor, and the repeated parts will not be described again.

[0045] Specifically, an embodiment of the present invention provides a glass interlayer, such as... Figure 5 As shown, it includes: a glass substrate 50, and a capacitor 41 disposed on the glass substrate 50 as described above. Additionally, as... Figure 5 As shown, the glass interposer may also include multiple wiring layers 700, inductors 42, and multiple pins 43.

[0046] The number of capacitors 42 can be set according to actual needs and is not limited to... Figure 5 The two shown, the number of inductors 42 can also be set according to actual needs, and is not limited to... Figure 5 The specific number of trace layers 700 and pins 43 shown in the diagram is not specifically limited here.

[0047] In this way, capacitors can be directly integrated near the chip through the glass interposer, with a small loop inductance and a low equivalent series inductance, which is beneficial for applications in high-frequency scenarios. In addition, within the glass interposer, capacitors can be placed at any position on the entire glass substrate, allowing for flexible and distributed design and layout of the capacitor array according to the chip's power consumption distribution. This enables the achievement of an optimal power supply network topology and improves the reliability of the glass interposer.

[0048] Of course, other structures known to those skilled in the art may also be provided in the glass interlayer, such as thermal management structures, passivation layers, protective layers, etc., which are not specifically limited here.

[0049] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A capacitor, characterized in that, include: A first electrode layer, a dielectric layer, and a second electrode layer are sequentially stacked on a substrate; The dielectric layer includes: a first sub-dielectric layer and a second sub-dielectric layer arranged alternately along the arrangement direction of the first electrode layer and the second electrode layer, wherein the number of the first sub-dielectric layers is greater than the number of the second sub-dielectric layers; The dielectric constant of the first sub-dielectric layer is less than that of the second sub-dielectric layer.

2. The capacitor as claimed in claim 1, characterized in that, The orthographic projection of the dielectric layer over the first electrode layer covers the sidewall of the first electrode layer.

3. The capacitor as claimed in claim 1, characterized in that, The ratio between the thickness of the second sub-dielectric layer and the thickness of the first sub-dielectric layer is greater than or equal to 4 and less than or equal to 10.

4. The capacitor as claimed in claim 1, characterized in that, The dielectric constant of the second sub-dielectric layer is greater than 10.

5. The capacitor as claimed in claim 1, characterized in that, The capacitor further includes an interface smoothing layer located between at least one of the first electrode layer and the second electrode layer and the dielectric layer, the interface smoothing layer being used to eliminate grain boundaries and spikes on the surface of the first electrode layer and / or the second electrode layer facing the dielectric layer.

6. The capacitor as claimed in claim 5, characterized in that, The thickness of the interface smoothing layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.

7. The capacitor as claimed in claim 5, characterized in that, The material of the interface smoothing layer is at least one of TiN, TaN, Ta, and TaTiN.

8. The capacitor as claimed in claim 1, characterized in that, The capacitor further includes a field plate structure, wherein the field plate structure and the second electrode layer are located in the same film layer, and the orthographic projection of the field plate structure onto the dielectric layer covers the sidewall of the dielectric layer.

9. The capacitor as claimed in claim 8, characterized in that, The second electrode layer includes an electrode portion and an extension portion extending from the edge of the electrode portion, wherein the orthographic projection of the electrode portion onto the first electrode layer coincides with the first electrode layer; The extension portion is reused as the field plate structure.

10. An integrated passive device, characterized in that, include: A substrate, and a capacitor disposed on the substrate as described in any one of claims 1-9.

11. A glass interlayer, characterized in that, include: A glass substrate, and a capacitor as described in any one of claims 1-9 disposed on the glass substrate.

Images