A semiconductor device and a method of fabricating the same

Abstract

This invention relates to the field of semiconductor technology, and particularly to a semiconductor device and its fabrication method. The semiconductor device includes multiple fins, multiple spacer regions, a first dielectric layer, a second dielectric layer, and a gate layer; the multiple fins and multiple spacer regions are arranged alternately along a first direction; the fins extend along a second direction perpendicular to the first direction; the first dielectric layer covers the sidewalls of the spacer regions and the fins; a portion of the spacer regions is also filled with a second dielectric layer; the second dielectric layer is located in a first groove formed by the first dielectric layer, and the top of the second dielectric layer is higher than the top of the first dielectric layer; the second dielectric layer is made of a different material than the first dielectric layer; the gate layer spans across the multiple fins and the multiple second dielectric layers along the first direction. The semiconductor device provided by this application can effectively balance the stress of the gate layer on the fins, thereby preventing fin bending.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of integrated circuit technology, in addition to higher requirements for the electrical performance of electronic components (such as transistors) in integrated circuits, there is also a pursuit of smaller chip area. This has promoted the development of FinField-Effect Transistor (FinFET) technology. Compared with traditional transistors, FinFET is a three-dimensional structure in which the contact surface between the active region and the gate changes from a planar structure.

[0003] In the development of fin field-effect transistor technology, especially with the advancement and evolution of technology nodes, the fin pitch and gate pitch are getting smaller and smaller. This makes it impossible for the existing fin field-effect transistor structure to meet the electrical performance requirements of narrow fin pitch and narrow gate pitch. For example, due to the small fin pitch and fin width, the polysilicon material on the fin is prone to stress asymmetry, resulting in problems such as fin bending and fin stacking, which in turn causes circuit failure. Summary of the Invention

[0004] To address the aforementioned technical problems, this application discloses a semiconductor device comprising multiple fins, multiple spacer regions, a first dielectric layer, a second dielectric layer, and a gate layer.

[0005] The plurality of fins and the plurality of spacer regions are arranged alternately along a first direction; the fins extend along a second direction perpendicular to the first direction.

[0006] The first dielectric layer covers the spacer region and the sidewalls of the fin;

[0007] The spacer region is further filled with a second dielectric layer; the second dielectric layer is located in a first groove formed by the first dielectric layer, and the top of the second dielectric layer is higher than the top of the first dielectric layer; the second dielectric layer is made of a different material than the first dielectric layer.

[0008] The gate layer spans across the plurality of fins and the plurality of second dielectric layers along the first direction.

[0009] In one exemplary embodiment, the width of the second dielectric layer is on the same order of magnitude as the width of the fin;

[0010] The stress on the fins is balanced by adjusting the thickness and / or material of the first and second dielectric layers.

[0011] In an exemplary embodiment, the spacing region includes at least a first spacing region and a second spacing region; the first spacing region is filled with the first dielectric layer; the second spacing region is filled with both the first dielectric layer and the second dielectric layer; and the width of the second spacing region is greater than the width of the first spacing region.

[0012] In one exemplary embodiment, a third dielectric layer and a fourth dielectric layer are also included;

[0013] The third dielectric layer is located in the second groove formed by the second dielectric layer, and the fourth dielectric layer covers the third dielectric layer;

[0014] The material of the fourth dielectric layer is the same as that of the second dielectric layer.

[0015] In one exemplary embodiment, the material of the third dielectric layer includes silicon oxide;

[0016] The material of the fourth dielectric layer includes an inorganic material with a low dielectric constant; the inorganic material with a low dielectric constant includes nitride-like materials or SixOyNz, where x, y, and z are all non-negative numbers;

[0017] The material of the first dielectric layer includes silicon oxide;

[0018] The material of the second dielectric layer includes the inorganic material with the low dielectric constant.

[0019] In one exemplary embodiment, the top of the first dielectric layer is in contact with the bottom of the gate layer;

[0020] The top of the third dielectric layer is higher than the top of the first dielectric layer and lower than the top of the fin;

[0021] There is a first height difference between the top of the fourth dielectric layer and the top of the fin.

[0022] In an exemplary embodiment, the spacing region further includes a third spacing region; the third spacing region is filled with the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer, and the width of the third spacing region is greater than the width of the second spacing region.

[0023] In one exemplary embodiment, the top of the first dielectric layer is lower than the top of the fin;

[0024] There is a second height difference between the top of the second dielectric layer and the top of the fin.

[0025] In an exemplary embodiment, a partition layer is provided on the second dielectric layer in the second spacer region; the partition layer penetrates the gate layer along a third direction; the third direction is the height direction of the fin.

[0026] This application also discloses a method for fabricating a semiconductor device, comprising:

[0027] A semiconductor structure is provided; the semiconductor structure includes a plurality of fins, a plurality of spacer regions, and a first dielectric layer; the plurality of fins and the plurality of spacer regions are arranged alternately along a first direction; the fins extend along a second direction perpendicular to the first direction; the first dielectric layer covers the sidewalls of the spacer regions and the fins;

[0028] A second dielectric layer is formed on the first dielectric layer; the second dielectric layer is made of a different material than the first dielectric layer.

[0029] The region near the top of the fin in the first dielectric layer is removed, and the second dielectric layer located at the top of the fin is removed, so that a portion of the spacer region is still filled with the second dielectric layer; the second dielectric layer is located in the first groove formed by the first dielectric layer, and the top of the second dielectric layer is higher than the top of the first dielectric layer;

[0030] A gate layer is prepared; the gate layer extends across the plurality of fins and the plurality of second dielectric layers along the first direction.

[0031] In one exemplary embodiment, the provision of a semiconductor structure includes:

[0032] Provides a substrate structure with multiple fins on top;

[0033] Form the first dielectric layer;

[0034] Remove the fins in the third-party upward preset area; the third-party direction is the height direction of the fins, so that the first dielectric layer filled in part of the interval area forms the first groove.

[0035] In an exemplary embodiment, before removing the region of the first dielectric layer near the top of the fin, the method further includes:

[0036] A third dielectric layer is formed in the second groove formed by the second dielectric layer;

[0037] A fourth dielectric layer is formed; the fourth dielectric layer covers the third dielectric layer.

[0038] In an exemplary embodiment, removing the region of the first dielectric layer near the top of the fin and removing the second dielectric layer located at the top of the fin includes:

[0039] The second dielectric layer is etched back to remove the second dielectric layer located on top of the fin;

[0040] The semiconductor substrate is planarized to remove the first dielectric layer located on top of the fin;

[0041] Remove the first dielectric layer near the top of the fin so that the top of the first dielectric layer is lower than the top of the fin.

[0042] In one exemplary embodiment, the fabrication of the gate layer includes:

[0043] A gate material layer is formed on top of the semiconductor structure;

[0044] Remove material from a predetermined position of the gate material layer to form a segmented region penetrating the gate material layer on the second dielectric layer corresponding to the predetermined position, and obtain a functional gate structure;

[0045] A segmentation layer is formed to fill the segmented region, thereby obtaining the gate layer.

[0046] In another aspect, this application also discloses an integrated circuit that includes the aforementioned semiconductor device.

[0047] In another aspect, this application also discloses a chip that includes the aforementioned integrated circuit.

[0048] As described above, the semiconductor device provided in this application includes multiple fins, multiple spacer regions, a first dielectric layer, a second dielectric layer, and a gate layer. The multiple fins and multiple spacer regions are arranged alternately along a first direction. The fins extend along a second direction perpendicular to the first direction. The first dielectric layer covers the sidewalls of the spacer regions and the fins. A portion of the spacer regions is also filled with the second dielectric layer. The second dielectric layer is located in a first groove formed by the first dielectric layer, and the top of the second dielectric layer is higher than the top of the first dielectric layer. The second dielectric layer is made of a different material than the first dielectric layer. The gate layer spans across the multiple fins and the multiple second dielectric layers along the first direction. By providing the second dielectric layer on the first dielectric layer, the stress on the fins caused by the gate layer can be balanced, thereby alleviating fin bending. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figures 1-9 This is a schematic diagram illustrating a process for fabricating an existing semiconductor device, as exemplarily.

[0051] Figure 10 A cross-sectional view of an exemplary first type of semiconductor device;

[0052] Figure 11 A cross-sectional view of an exemplary second type of semiconductor device;

[0053] Figure 12 A cross-sectional view of an exemplary second type of semiconductor device;

[0054] Figure 13 This is a schematic diagram illustrating an exemplary process for fabricating a semiconductor device;

[0055] Figures 14-23 This is a schematic diagram illustrating a process for fabricating a semiconductor device.

[0056] The following is supplementary explanation of the attached figures:

[0057] 1-Fin; 2-Spacer region; 201-First spacer region; 202-Second spacer region; 203-Third spacer region; 3-First dielectric layer; 4-Second dielectric layer; 5-Gate layer; 501-Functional gate structure; 502-Segmentation layer; 6-First trench; 7-Third dielectric layer; 8-Fourth dielectric layer; 9-Second trench; 10-Substrate structure; 11-Segmentation region; 12-Fill layer; 13-Barrier layer; 14-Fifth dielectric layer. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0059] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0060] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0061] As FinFET technology advances, fin spacing and gate spacing become increasingly smaller, which can lead to various problems such as fin merging, fin width loss, fin bending and stacking, and gate dicing residue. Fin merging, in particular, refers to the phenomenon where, as chip area shrinks, fin spacing and width become smaller. During fin processing, the surface tension of the processing solution causes adjacent fins to approach and merge. This phenomenon is typically more severe the smaller the fin spacing and width. Therefore, in FinFET device fabrication, the aforementioned fin merging problem is highly likely to occur during the wet etching process for removing vertical fins.

[0062] The fin width loss is mainly due to flame chemical vapor deposition (FCVD) during FinFET device fabrication. As is well known, FCVD is widely used as a shallow trench isolation (STI) material in FinFET technology due to its excellent gap-filling capability. However, a significant drawback of the FCVD process is the large fin width loss during FCVD vapor annealing, which poses a significant challenge to controlling the fin width.

[0063] Fin bending and stacking are mainly caused by uneven stress on the fins due to the deposition of gate polycrystalline material. This is because the fin width is getting smaller and smaller. These slender fins will cause stress when the gate polycrystalline material is deposited in the future. However, in order to save chip area, the chip layout design requires uneven fin spacing and uneven fin space, which will lead to asymmetric stress on the fins, specifically manifested as problems such as fin bending and fin stacking failure.

[0064] Gate dicing residue refers to the situation where, as the width of the gate dicing becomes smaller (resulting in a larger aspect ratio), the area to be diced cannot be completely removed using existing dicing processes, leaving residue. This is because as the aspect ratio increases, different materials (such as gate material and STI) need to be etched, increasing the difficulty of etching removal. Regardless of the specific issue, all of these will ultimately lead to circuit malfunction and yield loss in semiconductor devices.

[0065] To better illustrate the technical effects of this application, a brief description of existing FinFET devices and their fabrication processes is provided below. For details, please refer to [link / reference needed]. Figures 1 to 9 The diagram illustrates an exemplary structural schematic of a conventional semiconductor device fabrication process. The fabrication process of conventional FinFET devices mainly includes the following steps: 1) providing a... Figure 1 The substrate structure 10 shown is provided with a plurality of fins 1 and a plurality of spacer regions 2 arranged alternately along a first direction (e.g., the x-direction). Specifically, the widths of the plurality of spacer regions 2 are different. This is mainly because with the current demand for miniaturization of chip area, it is necessary to arrange the distribution of various electronic devices more rationally, so that the fins 1 of the designed FinFET device have uneven fin spacing. 2) A filling layer 12 and a barrier layer 13 are sequentially formed on the substrate structure 10, wherein the filling layer 12 is used to fill the spacer regions 2 between the plurality of fins 1, and the barrier layer 13 is located on the filling layer 12. Subsequently, the barrier layer 13 is patterned to form an etching window, resulting in the following: Figure 2The structure shown involves etching fin 1 based on the etching window to remove the fin 1 corresponding to the etching window, forming a structure as shown. Figure 3 The structure shown is then obtained by removing the filler layer 12 and the barrier layer 13. Figure 4 The structure shown will further increase the non-uniformity of fin 1 distribution. 3) A first dielectric layer 3 is formed on the surface of fin 1, resulting in the structure shown. Figure 5 The structure shown specifically involves the first dielectric layer 3, which can be an oxide layer formed using an atomic layer deposition (ALD) process. 4) Next, shallow trench isolation is formed using a flame chemical vapor deposition process to create a fifth dielectric layer 14 within the fin spacing. The material of this fifth dielectric layer 14 can be the same as that of the first dielectric layer 3. The surface of the fifth dielectric layer 14 is then polished to achieve a relatively smooth surface for the entire device, resulting in the desired appearance. Figure 6 The structure shown. Specifically, the surface of the fifth dielectric layer 14 can be treated by chemical mechanical polishing. 5) Remove the fifth dielectric layer 14 and the first dielectric layer 3 within a predetermined depth range to expose the fin 1 at a predetermined height, resulting in the structure shown. Figure 7 The structure shown is as follows. 6) A gate oxide layer and a gate polysilicon layer are formed sequentially to form gate layer 5. Then, the polysilicon layer is planarized to obtain the structure shown. Figure 8 The structure shown is illustrated. The planarization process here includes at least five planarization treatments: oxide layer deposition, oxide layer planarization, oxide layer etch-back / gate polysilicon layer, chemical mechanical polishing of the gate polysilicon layer, and spot etching of the planarized gate polysilicon layer. Afterwards, source and drain regions are formed. 7) Subsequently, a step of dicing the gate polysilicon layer is performed to form a dicing region 11 in the gate polysilicon layer, and a dicing layer 502 is filled in the dicing region 11 to obtain the structure shown. Figure 9 The structure shown is such that the partition layer 502 divides the gate layer 5 into multiple isolated functional gate structures 501.

[0066] The existing FinFET devices described above have at least the following problems. Specifically, during the removal of the filler layer 12 and the barrier layer 13 in step 2), the narrow fins 1 and the narrow fin spacing are prone to fin coalescence due to surface tension in the solution. Furthermore, in step 4), the flame chemical vapor deposition process causes significant fin width loss due to oxidation. Based on steps 1)-6) and the appendix... Figure 1-8It can be seen that the width of the spacing region 2 between fins 1 is inconsistent, especially the spacing region 2 on both sides of fin 1 is asymmetrical. This causes uneven stress on fin 1 after the gate polysilicon layer is deposited, which in turn leads to fin bending and stacking problems. During the cutting of the gate polysilicon layer in step 7) above, since the material of the area to be cut includes not only polysilicon but also an oxide layer, and the cutting depth-to-width ratio is large, this can easily lead to cutting residue problems.

[0067] To address at least one of the problems (such as fin bending) present in existing semiconductor devices, please refer to [link / reference needed]. Figure 10 This application provides a semiconductor device comprising a plurality of fins 1, a plurality of spacer regions 2, a first dielectric layer 3, a second dielectric layer 4, and a gate layer 5; the plurality of fins 1 and the plurality of spacer regions 2 are arranged alternately along a first direction; the fins 1 extend along a second direction perpendicular to the first direction; the first dielectric layer 3 covers the sidewalls of the spacer regions 2 and the fins 1; a portion of the spacer regions 2 is further filled with the second dielectric layer 4; the second dielectric layer 4 is located in a first groove 6 formed by the first dielectric layer 3, and the top of the second dielectric layer 4 is higher than the top of the first dielectric layer 3; the second dielectric layer 4 is made of a different material than the first dielectric layer 3; the gate layer 5 spans across the plurality of fins 1 and the plurality of second dielectric layers 4 along the first direction.

[0068] Based on the second dielectric layer 4 disposed in the first groove 6 of the first dielectric layer 3, the stress of the gate layer 5 on the fins 1 on both sides of the second dielectric layer 4 can be balanced, thereby avoiding fin bending and fin stacking.

[0069] For example, semiconductor devices may be included in microprocessors, memory, and / or other integrated circuit devices. In some embodiments, the semiconductor device may be a portion of an IC chip, a system-on-a-chip (SOC), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Optionally, Figure 10-12 All of these are simplified semiconductor device structures for ease of understanding. In reality, other additional components can be added to the semiconductor device, or other components described in the text can be replaced. All of these structures fall within the inventive concept of this application.

[0070] For example, the top of the first dielectric layer 3 is lower than the top of the fin 1; the top of the second dielectric layer 4 has a second height difference with the top of the fin 1. This second height difference is specifically formed based on the molding process. In actual molding, due to limitations of molding equipment or processing conditions, the top of the second dielectric layer 4 and the top of the fin 1 cannot be completely flush. Of course, under ideal conditions, the top of the second dielectric layer 4 and the top of the fin 1 are flush. Optionally, the thickness of the first dielectric layer 3 is 20 to 200 angstroms. In an exemplary embodiment of the thickness of the first dielectric layer 3, the thickness can be 20 angstroms, 40 angstroms, 60 angstroms, 80 angstroms, 100 angstroms, 120 angstroms, 140 angstroms, 160 angstroms, 180 angstroms, or 200 angstroms. Optionally, the thickness of the second dielectric layer 4 is 10 to 500 angstroms. In an exemplary embodiment of the thickness of the second dielectric layer 4, the thickness of the second dielectric layer 4 can be 10 angstroms, 50 angstroms, 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, or 500 angstroms.

[0071] For example, the first direction in this article can specifically refer to the x direction, the second direction can specifically refer to the y direction, and the third direction can specifically refer to the z direction, which is the height direction of fin 1.

[0072] For example, the spacer region 2 includes at least a first spacer region 201 and a second spacer region 202; the first spacer region 201 is filled with a first dielectric layer 3; the second spacer region 202 is filled with the first dielectric layer 3 and the second dielectric layer 4. Specifically, the width of the second spacer region 202 is greater than the width of the first spacer region 201. Since the first spacer region 201 is narrower, it is completely filled when the first dielectric layer 3 is formed. At this time, the second spacer region 202 is wider, and the first dielectric layer 3 filled in it will form a first groove 6. Subsequently, when the second dielectric layer 4 is formed, the second dielectric layer 4 will fill the first groove 6. In this application, the spacer region 2 filled with dielectric layers can also be called a shallow trench structure (STI).

[0073] For example, in a plurality of fins 1, the width of the gap region 2 between any two adjacent pairs of fins 1 is different from the width of the gap region 2 between any pair of fins 1 in the two pairs of fins 1. In other words, the gap regions 2 between the plurality of fins 1 are not uniformly distributed, so as to improve the integration of the device or chip and reduce its size.

[0074] For example, the material of the first dielectric layer 3 includes an oxide, specifically silicon oxide, and the material of the second dielectric layer 4 can be an inorganic material with a low dielectric constant, such as a nitride-like compound or SixOyNz, where x, y, and z are all non-negative numbers. The K value of the inorganic material with a low dielectric constant is less than the K value of silicon oxide, and it can also be other suitable materials. Since the second dielectric layer 4 plays the role of balancing the stress on the fin 1, in order to further improve the effect of relieving the stress on the fin 1, the material properties (such as physical properties) of the second dielectric layer 4 can be comparable to those of the fin 1. Especially under certain specific conditions, such as when the width of the second dielectric layer 4 (i.e., the length along the first direction) is equal to the width of the adjacent fin 1, it is equivalent to adding a "fin 1" (actually formed as a part of the second dielectric layer 4) between the two fins 1, so that the width of the spacing region 2 between the three fins 1 is approximately equal, making the stress of the gate layer 5 on both sides of the fin 1 approximately balanced, thus avoiding fin bending. Specifically, with Figure 10 Taking the structure shown as an example, the semiconductor device includes four fins 1 arranged at intervals along a first direction. For ease of description, the four fins 1 arranged from left to right can be referred to as the first fin, the second fin, the third fin, and the fourth fin. The interval 2 between the first fin and the second fin is the first interval 201, that is, only the first dielectric layer 3 is filled between these two fins. The interval 2 between the second fin and the third fin is the second interval 202, that is, the first dielectric layer 3 and the second dielectric layer 4 are filled between these two fins; the interval 2 between the third fin and the fourth fin is the first interval 201. For the second fin, the interval 2 on both sides is the first interval 201 and the second interval 202, respectively. Since the widths of these two interval 2 are different, the stress generated by the gate layer 5 (polysilicon material) on it can easily cause it to bend. However, in this example, by setting the second dielectric layer 4, the second dielectric layer 4 is equivalent to adding a "fin" between the second fin and the third fin, thereby dispersing the stress of the gate layer 5 and avoiding bending of the second fin and the third fin.

[0075] In an exemplary embodiment, the width of the second dielectric layer 4 is on the same order of magnitude as the width of the fin 1. In fact, the width of the second dielectric layer 4 here refers to the width of the second dielectric layer 4 located in the first groove 6, which is equivalent to the width of the first groove 6. Therefore, it can also be said that the width of the first groove 6 is on the same order of magnitude as the width of the fin 1. For example, when the width of the fin 1 is 5 nanometers, the width of the second dielectric layer 4 can be 4 nanometers, 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, or 10 nanometers, that is, any value within the range of 4 to 10 nanometers. Specifically, the width of the second dielectric layer 4 in the first groove 6 is determined by both the width of the fin 1 and the thickness of the first dielectric layer 3. Based on the width of the fin 1, the thickness of the first dielectric layer 3 can be adjusted so that the first dielectric layer 3 in the second spacer region 202 can form the first groove 6, and the width of the first groove 6 can meet the required design requirements. Of course, depending on the material type of the second dielectric layer 4, the width of the second dielectric layer 4 in the first groove 6 can also be different. In some embodiments, the stress on the fin 1 is balanced by adjusting the thicknesses of the first dielectric layer 3 and the second dielectric layer 4. In other embodiments, the stress on the fin 1 is balanced by adjusting the materials of the first dielectric layer 3 and the second dielectric layer 4. In still other embodiments, the stress on the fin 1 is balanced by adjusting both the thickness and material of the first dielectric layer 3 and the second dielectric layer 4.

[0076] For example, substrate structure 10 may include a supporting substrate and one or more material layers (also referred to as semiconductor layers) located on the supporting substrate, and multiple fins 1 may be formed subsequently by patterning the semiconductor layers. Specifically, the semiconductor layers may include any suitable semiconductor material, such as silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. Depending on the design requirements of the semiconductor device, the semiconductor layers may include the same or different materials, etch rates, component atomic percentages, component weight percentages, thicknesses, and / or configurations. In some embodiments, the semiconductor layers include alternating material layers, such as semiconductor layers composed of a first material and a second material. For example, the semiconductor layers alternate between silicon layers and silicon-germanium layers (e.g., Si / SiGe / Si from bottom to top). In some embodiments, the semiconductor layers include semiconductor layers of the same material but with alternating component atomic percentages, such as semiconductor layers with a first atomic percentage of component and semiconductor layers with a second atomic percentage of component. Optionally, the supporting substrate and / or one or more material layers may comprise another elemental semiconductor, such as germanium; compound semiconductors, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and / or cadmium telluride; alloy semiconductors, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAs, etc., and may also be other group III-V materials, or other group II-V materials, or combinations thereof. Optionally, the substrate structure 10 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. No limitations are imposed herein.

[0077] For example, please refer to Figure 11 The aforementioned semiconductor device may further include a third dielectric layer 7 and a fourth dielectric layer 8; the third dielectric layer 7 is located in the second groove 9 formed by the second dielectric layer 4, and the fourth dielectric layer 8 covers the third dielectric layer 7. Specifically, the third dielectric layer 7 is located in the lower part of the second groove 9; the fourth dielectric layer 8 is located on the third dielectric layer 7 and in the upper part of the second groove 9. Since the third dielectric layer 7 can form a structure with a relatively flat top surface, the surface on which the fourth dielectric layer 8 is subsequently formed is also relatively flat, to meet the requirements of subsequent molding and processing. Of course, as described above, the first groove 6 formed by the first dielectric layer 3 may also be filled only with the second dielectric layer 4.

[0078] For example, the material of the third dielectric layer 7 includes silicon oxide; the material of the fourth dielectric layer 8 includes an inorganic material with a low dielectric constant, and may also include other suitable materials; the inorganic material with a low dielectric constant includes nitride-like materials or SixOyNz, and may also include carbon-doped silicon dioxide, silicate glass, etc., where x, y, and z are all non-negative numbers. Optionally, the material of the fourth dielectric layer 8 is the same as the material of the second dielectric layer 4, so that the dielectric layer filled in the spacer region 2 can form a whole, unaffected by atomic diffusion, and can better balance the stress on the fin 1.

[0079] For example, please continue reading Figure 11 The top of the first dielectric layer 3 is in contact with the bottom of the gate layer 5. The second dielectric layer 4, the third dielectric layer 7, and the fourth dielectric layer 8 are all located in the first groove 6 formed by the first dielectric layer 3, and the third dielectric layer 7 is located in the second groove 9 formed by the second dielectric layer 4. The top of the second dielectric layer 4 is higher than the top of the first dielectric layer 3, so the top of the second groove 9 formed by the second dielectric layer 4 is higher than the top of the first dielectric layer 3. The top of the third dielectric layer 7 located in the second groove 9 is higher than the top of the first dielectric layer 3 and lower than the top of the fin 1. There is a first height difference between the top of the fourth dielectric layer 8 located in the second groove 9 and the top of the fin 1. The first height difference is specifically formed based on the process. In the actual molding process, due to the limitations of molding equipment or processing conditions, the top of the fourth dielectric layer 8 and the top of the fin 1 cannot be completely flush. Of course, under ideal conditions, the top of the fourth dielectric layer 8 and the top of the fin 1 are flush.

[0080] For example, please refer to Figure 12The spacing region 2 may further include a third spacing region 203; the second spacing region 202 is filled with the first dielectric layer 3 and the second dielectric layer 4; the third spacing region 203 is filled with the first dielectric layer 3, the second dielectric layer 4, the third dielectric layer 7 and the fourth dielectric layer 8, and the width of the third spacing region 203 is greater than the width of the second spacing region 202. Since the spacing regions 2 between the multiple fins 1 are not uniformly arranged, if the width of the spacing region 2 is narrow, it is filled only with the first dielectric layer 3, and is called the first spacing region 201; if the width of the spacing region 2 is slightly wider, it may be filled only with the first dielectric layer 3 and the second dielectric layer 4, and is called the second spacing region 202; if the width of the spacing region 2 is wider, it may be filled only with the first dielectric layer 3 and the second dielectric layer 4, or it may be filled with the first dielectric layer 3, the second dielectric layer 4, the third dielectric layer 7 and the fourth dielectric layer 8. In fact, the spacer region 2 in this application can be divided into two categories according to its function. One category is the first spacer region 201, which is only used for filling and is filled with only the first dielectric layer 3. The other category is the second spacer region 202 and the third spacer region 203, which are used to balance stress and are filled with at least the first dielectric layer 3 and the second dielectric layer 4. According to the design requirements, i.e. the uneven distribution of fins 1, the width of the spacer 2 between adjacent fins 1 is different, and it can be divided into three categories. As mentioned above, the spacer 2 with a narrower width range is called the first spacer 201, the spacer 2 with a medium width range is called the second spacer 202, and the spacer 2 with a wider range is called the third spacer 203. The first dielectric layer 3 filled in the second spacer 202 can form a first groove 6, which is filled with a dielectric layer of only one material. The first dielectric layer 3 filled in the third spacer 203 can form a first groove 6, which is filled with a dielectric layer of at least two materials. However, the top of the material structure filled in the first groove 6 in both the second spacer 202 and the third spacer 203 is higher than the top of the first dielectric layer 3.

[0081] For example, please refer to Figure 12 A segmentation layer 502 is provided on the second dielectric layer 4 in the second spacing region 202; the segmentation layer 502 penetrates the gate layer 5 along a third direction; the third direction is the height direction of the fin 1. Since the top of the second dielectric layer 4 is higher than the top of the first dielectric layer 3, and the part of the second dielectric layer 4 that is higher than the first dielectric layer 3 is located in the gate layer 5, the segmentation layer 502 is specifically formed by etching and segmenting the gate layer 5 and then filling it. Therefore, in the actual preparation process, only one material needs to be etched to form the segmentation region 11 for filling the segmentation layer 502, which has the characteristics of high etching precision and etching efficiency, and is not easy to form etching residue.

[0082] This application Figure 10-12 The illustrated semiconductor devices are simplified structures. In practice, multiple functional gate structures 501 in gate layer 5 are located on the channel regions of multiple fins 1. Each functional gate structure 501 includes an interface layer, a gate dielectric layer, one or more power function layers, and a metal fill layer (not shown). In some embodiments, the interface layer may include a dielectric material, such as a silicon oxide layer or silicon oxynitride. The gate dielectric layer is formed of a high-k dielectric material (dielectric constant greater than about 3.9), which may include HfO2, TiO2, HfZrO, Ta2O3, HSiO4, ZrO2, ZrSiO2, combinations thereof, or other suitable materials. The one or more power function layers may include an n-type power function layer and a p-type power function layer. Optionally, the n-type power function layer may be formed of aluminum, titanium aluminide, titanium aluminum carbide, tantalum silicon carbide, aluminum tantalum silicon carbide, tantalum silicon carbide, tantalum silicide, or hafnium carbide. Optionally, the p-type function layer can be formed of titanium nitride, silicon titanium nitride, tantalum nitride, tungsten carbonitride, or molybdenum. The metal filling layer can be formed of tungsten, ruthenium, cobalt, or copper. Because the gate dielectric layer is formed of a high-k dielectric material and metal is used in the functional gate structure 501, the functional gate structure 501 can also be called a high-k metal gate structure or a metal gate structure. Optionally, the semiconductor device may also include contact holes, metal wiring layers, etc., which will not be described in detail here.

[0083] The above is a brief description of the semiconductor device provided in this application. The fabrication process of this semiconductor device will be described below. Please refer to [link / reference]. Figure 13 The diagram illustrates an exemplary process for fabricating a semiconductor device. The method for fabricating this semiconductor device may include:

[0084] S1301: A semiconductor structure is provided; the semiconductor structure includes a plurality of fins, a plurality of spacer regions and a first dielectric layer; the plurality of fins and the plurality of spacer regions are arranged alternately along a first direction; the fins extend along a second direction perpendicular to the first direction; the first dielectric layer covers the sidewalls of the spacer regions and the fins.

[0085] In an exemplary embodiment, step S1301 may specifically include: providing a substrate structure 10 with a plurality of fins 1 on its top; forming the first dielectric layer 3; removing the fins 1 in a third-direction upward predetermined region; wherein the third-direction is the height direction of the fins 1, so that the first dielectric layer 3 filled in the partial spacing region 2 forms the first groove 6. Specifically, it may provide, as follows: Figure 1 The substrate structure 10 is shown, and then a first dielectric layer 3 is formed on the substrate structure 10 in a carpet-like manner to obtain the following: Figure 14The structure shown has a filling layer 12 and a barrier layer 13 sequentially formed on the first dielectric layer 3. The filling layer 12 fills the first groove 6 formed by the first dielectric layer 3, and the barrier layer 13 is located on the filling layer 12. The barrier layer 13 is subsequently patterned to form an etching window, resulting in the structure shown. Figure 15 The structure shown includes both the filling layer 12 and the material corresponding to the fin 1 in the area corresponding to the etching window. To improve etching accuracy, these can be etched separately, such as first etching away the filling layer 12 corresponding to the etching window, to obtain the structure shown. Figure 16 The structure shown is then removed, and the fin 1 corresponding to the etched window is removed to obtain the structure shown. Figure 17 The structure is shown. Afterwards, the filler layer 12 and the barrier layer 13 are removed, which further increases the non-uniformity of the fin distribution. Optionally, the barrier layer 13 can be photoresist or an inorganic mask material (such as silicon nitride). Optionally, the filler layer 12 can be a spin-coated organic carbon material SOC, thus improving the flatness of the photoresist directly coated on it. Compared with existing processes, since this application first forms the first dielectric layer 3 and then performs the etching to remove the fins 1, the first dielectric layer 3 can effectively protect the fins 1, avoiding fin coalescence caused by solution surface tension during the etching process. Optionally, the first dielectric layer 3 can be an oxide layer (such as a silicon oxide layer) formed based on atomic layer deposition (ALD), which provides excellent step coverage. The first dielectric layer 3 can also be formed using other processes, such as flame chemical vapor deposition (CVD).

[0086] In an exemplary embodiment, the method for forming multiple fins 1 described above may include: providing a substrate (specifically a silicon wafer), coating the substrate with photoresist, patterning the photoresist using a photolithography process, etching the substrate using an etching process, and then removing the residual photoresist to obtain the desired fins. Figure 1 The structure shown is illustrated. Optionally, the above etching process can be either wet etching or dry etching; there is no limitation, and the appropriate choice should be made based on the type of photoresist and the required etching precision. Of course, the etching mask can be not only the aforementioned photoresist but also a hard mask, such as silicon nitride. The method for forming the fin 1 may further include: providing a substrate (specifically, a silicon wafer), forming a mask material layer on the substrate using a deposition process, then patterning the mask material layer to form a mask, and subsequently etching the substrate to a predetermined depth using a dry etching process based on the mask to form a structure as shown. Figure 1The structure is shown. Optionally, the specific method for patterning the mask material layer can be to form a patterned hard mask using self-aligned dual imaging technology. For example, an auxiliary layer can be formed on the surface of the patterned mask material layer, followed by the formation of a gate-like structure. The width of this gate-like structure is equal to the width between the lines of the subsequently patterned hard mask. A silicon dioxide layer is deposited on the surface of the gate-like structure as a mask. The width of the hard mask can be controlled by controlling the thickness of the silicon dioxide layer. Then, a dry etching process is used to form the gate sidewall structure. Next, the auxiliary layer is removed, and the hard mask material layer is etched to remove the silicon dioxide layer, thus obtaining the patterned hard mask. Other dry etching methods can also be used, and are not limited here. Specifically, a photoresist layer can be coated on the hard mask material layer, followed by an exposure-development-wet etching process to obtain the patterned hard mask. Optionally, the structure or material of the substrate can also be composed of multiple semiconductor layers as described above. Further details are omitted here.

[0087] The aforementioned interval 2 includes at least a second interval 202 and a first interval 201. The first interval 201 may be filled only with a first dielectric layer 3. The first dielectric layer 3 filled in the second interval 202 can form a first groove 6, and the width of the first groove 6 is on the same order of magnitude as the width of the fin 1.

[0088] In an exemplary embodiment, the material of the first dielectric layer 3 includes an oxide, specifically silicon oxide. Optionally, the thickness of the first dielectric layer 3 is 20 to 200 angstroms. In an exemplary embodiment of the thickness of the first dielectric layer 3, the thickness of the first dielectric layer 3 can be 20 angstroms, 40 angstroms, 60 angstroms, 80 angstroms, 100 angstroms, 120 angstroms, 140 angstroms, 160 angstroms, 180 angstroms, or 200 angstroms. Optionally, to facilitate the fabrication of the second dielectric layer 4 in subsequent steps and improve its formation effect, the thickness of the first dielectric layer 3 is at least greater than half the width of the narrowest spacing region 2. The thickness of the first dielectric layer 3 can be determined by the width of the spacer region 2 and the width of the fin 1. Assuming the minimum width of the spacer region 2 is W1, then the thickness D1 of the first dielectric layer 3 must be at least greater than W1 / 2. When there is a spacer region 2 with a width greater than W1, and the width of this spacer region 2 is W2, then the width W3 of the first groove 6 formed by the first dielectric layer 3 in this spacer region 2 is W2 - 2 * D1. W3 and the width of the fin 1 need to be on the same order of magnitude. Otherwise, the thickness of the first dielectric layer 3 needs to be adjusted. Specifically, either the thickness of the first dielectric layer 3 can be increased so that it can fill the aforementioned spacer region 2 with a width of W3, or the thickness of the first dielectric layer 3 can be decreased so that the width of the first groove 6 formed by the first dielectric layer 3 can meet the requirement that it is on the same order of magnitude as the width of the fin 1. Thus, when the second dielectric layer 4 is filled into the first groove 6 in the subsequent step, it can balance the uneven stress of the gate layer 5 on the fin 1.

[0089] S1303: A second dielectric layer is formed on the first dielectric layer; the second dielectric layer is made of a different material than the first dielectric layer.

[0090] In an exemplary embodiment, the material of the second dielectric layer 4 can be an inorganic material with a low dielectric constant, such as a nitride-like material or SixOyNz, where x, y, and z are all non-negative numbers. The K value of the inorganic material with a low dielectric constant is less than the K value of silicon oxide. It can also be other suitable materials. The second dielectric layer 4 can be formed by physical vapor deposition, such as sputtering, or by chemical vapor deposition, such as plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), sub-atmospheric chemical vapor deposition (SACVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or other types of chemical vapor deposition. There are no limitations on this method. Optionally, the thickness of the second dielectric layer 4 is 10 to 500 angstroms. In an exemplary embodiment of the thickness of the second dielectric layer 4, the thickness can be 10 angstroms, 50 angstroms, 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, or 500 angstroms. Specifically, based on the above description of the thickness of the first dielectric layer 3, the second dielectric layer 4 is mainly used to fill the first groove 6. The width of the second dielectric layer 4 in the first groove 6 (or the width of the first groove 6) is on the same order of magnitude as the width of the fin 1. Therefore, the specific thickness of the second dielectric layer 4 is determined by both the width of the fin 1 and the thickness of the first dielectric layer 3. Of course, this can also be related to the materials of the first dielectric layer 3 and the second dielectric layer 4.

[0091] In another exemplary embodiment, when a wider gap region 2 exists, such as the gap region 2 formed by removing multiple fins 1 (e.g., 4 fins 1) in step S1301 above, in order to shorten the time for forming the second dielectric layer 4, improve the fabrication efficiency, and increase the flatness of the dielectric layer surface, after forming the second dielectric layer 4, i.e., before step S1305 below, the method further includes: forming a third dielectric layer 7 in the second groove 9 formed by the second dielectric layer 4, to obtain... Figure 19 The structure shown is then formed; next, a fourth dielectric layer 8 is formed in a carpet-like manner, resulting in the structure shown. Figure 20 The structure shown can be followed by etching back the fourth dielectric layer 8 to obtain the following result: Figure 21In the structure shown, the fourth dielectric layer 8 is located in the second groove 9, and the fourth dielectric layer 8 covers the third dielectric layer 7. Optionally, the third dielectric layer 7 can be formed using an FCVD process, resulting in a flat surface for the formed third dielectric layer 7. Optionally, the material of the third dielectric layer 7 includes silicon oxide; the material of the fourth dielectric layer 8 includes an inorganic material with a low dielectric constant; the inorganic material with a low dielectric constant includes nitride-like materials or SixOyNz, where x, y, and z are all non-negative numbers, and the fourth dielectric layer 8 can also be other suitable materials. Optionally, the material of the fourth dielectric layer 8 is the same as the material of the second dielectric layer 4. Optionally, the top of the third dielectric layer 7 filling the second groove 9 is lower than the top of the fin 1. Specifically, the height of the third dielectric layer 7 in the second groove 9 is less than or equal to 3 / 4 of the height of the fin 1, so that the remaining space of the second groove 9 can be filled with the fourth dielectric layer 8 to improve its stress balancing effect on the fin 1.

[0092] S1305: Remove the region of the first dielectric layer near the top of the fin, and remove the second dielectric layer located at the top of the fin, so that a portion of the spacer region is still filled with the second dielectric layer; the second dielectric layer is located in the first groove formed by the first dielectric layer, and the top of the second dielectric layer is higher than the top of the first dielectric layer.

[0093] In an exemplary embodiment, when the spacer region 2 is filled with at most two materials, namely the first dielectric layer 3 and the second dielectric layer 4, step S1305 may specifically include: performing an etch-back process on the second dielectric layer 4 to remove the second dielectric layer 4 located on top of the fin 1; performing a planarization process on the semiconductor substrate to remove the first dielectric layer 3 located on top of the fin 1; and removing the first dielectric layer 3 near the top of the fin 1 so that the top of the first dielectric layer 3 is lower than the top of the fin 1.

[0094] In another exemplary embodiment, when the spacer region 2 is filled with at most the first dielectric layer 3, the second dielectric layer 4, the third dielectric layer 7, and the fourth dielectric layer 8, step S1305 may specifically include: performing an etch-back process on the fourth dielectric layer 8 to obtain the following... Figure 21 In the structure shown, the top of the fourth dielectric layer 8 is lower than the top of the first dielectric layer 3. Then, a chemical mechanical polishing process can be used to planarize the material in the spacer region 2 and remove the first dielectric layer 3 located on top of the fin 1, resulting in the structure shown. Figure 22 The structure shown has an insulating layer (such as a silicon nitride layer) on top of fin 1, which can serve as a stop layer for chemical mechanical polishing. Next, the insulating layer and part of the first dielectric layer 3 are removed, such that the top of the first dielectric layer 3 is lower than the top of the fin 1, resulting in the structure shown. Figure 23 The structure shown.

[0095] S1307: Prepare a gate layer; the gate layer spans across the plurality of fins and the plurality of second dielectric layers along the first direction.

[0096] In an exemplary embodiment, step S1307 includes at least: forming a gate material layer on top of the semiconductor structure; removing material from a predetermined location of the gate material layer to form a segmentation region 11 penetrating the gate material layer on the second dielectric layer 4 corresponding to the predetermined location, and obtaining a functional gate structure 501; forming a segmentation layer 502 to fill the segmentation region 11, and obtaining the gate layer 5. Specifically, after forming the gate material layer on the semiconductor structure, photoresist can be formed on the gate material layer, and then patterned to form an etching window. Based on the etching window, the gate material layer is etched to form the segmentation region 11, which can be located on the second dielectric layer 4 in the second spacer region 202. Since the portion of the second dielectric layer 4 above the first dielectric layer 3 is located in the gate layer 5, only one material needs to be etched to form the segmentation region 11 for filling the segmentation layer 502, which has the characteristics of high etching precision and etching efficiency, and is less prone to forming etching residue. Subsequently, the segmentation layer 502 can be deposited to fill the segmentation region 11. Optionally, to improve photolithography accuracy, an anti-reflective layer or a coating (such as a SOC) for planarizing the top surface of the gate material layer may be formed between the gate material layer and the photoresist.

[0097] It should be noted that the main processes related to the concept of this invention in the fabrication of semiconductor devices described above actually omit some common steps, such as ion doping of the channel region of fin 1 before step S1307 to adjust the threshold voltage of the active region.

[0098] In the fabrication process of the specific gate layer 5 or functional gate structure 501, after ion doping of the channel region of fin 1, the process also includes depositing a gate dielectric layer (which can be one or more dielectric materials, specifically silicon oxide, silicon nitride, high-k dielectric materials, etc.), depositing a gate electrode layer (the gate electrode layer can specifically include a polysilicon layer and a hard mask on it, and can also include some metal layers), patterning the gate electrode layer, drain ion implantation (for n-channel FinFET devices, the drain ion implantation ion type can be n-type ions, such as arsenic ions, phosphorus ions or antimony ions; for p-channel FinFET devices, the drain ion implantation ion type can be p-type ions, such as boron ions, boron fluoride ions or indium ions), and annealing, etc., thereby forming the functional gate structure 501.

[0099] For example, the functional gate structure 501 can be formed using a gate-before process or a gate-after process. In embodiments using a high-k dielectric layer and a metal gate (HK / MG), a gate-after method is employed to form the gate electrode. In the gate-after process, a dummy gate can be formed, which is then removed in a later operation after a high-temperature annealing operation, and the high-k dielectric layer and metal gate (HK / MG) are formed.

[0100] For example, after forming the functional gate structure 501, one or more epitaxial processes can be used to form the source and drain, so that Si components, SiC components, SiGe components, SiP components, SiCP components, or III-V semiconductor materials on Si EPI (epitaxy layer), or other suitable components are formed on the fin 1. Epitaxial processes include CVD deposition methods (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes.

[0101] For example, source / drain electrodes can also be formed in the regions corresponding to the source / drain electrodes. The electrodes can be formed from suitable conductive materials, such as copper, tungsten, nickel, and titanium.

[0102] For example, after the functional gate structure 501 is fabricated, the fabrication of contact holes, metal wiring layers, etc. may also be included.

[0103] In the semiconductor device fabrication method provided by this application, the formation sequence of the first dielectric layer 3 is adjusted to precede the step of removing part of the fin 1, thereby effectively protecting the fin 1 and preventing fin merging. After removing part of the fin 1, a second dielectric layer 4 (such as a low dielectric constant material) is formed. The combination of the first dielectric layer 3 and the second dielectric layer 4 not only protects the fin 1, preventing subsequent FCVD processes from consuming the fin 1 and reducing the width of the fin 1, but also balances the stress on the fin 1, avoiding fin bending problems. Subsequently, a third dielectric layer 7 and a fourth dielectric layer can be deposited as needed to further balance the stress on the fin 1 (this is mainly because when depositing polysilicon material, the space formed by the polysilicon material entering the dielectric material within the aforementioned fin 1, the second spacer region 202, and the third spacer region 203 is more uniform, and the stress on the fin 1 is relaxed and more symmetrical, which greatly improves fin bending and stacking failure problems). Moreover, the second dielectric layer 4 pre-cuts the gate layer 5, thereby reducing the gate's cut depth-to-width ratio, avoiding cut residue, and improving cutting efficiency. By employing the aforementioned deposition sequence of the first dielectric layer 3, the second dielectric layer 4, the third dielectric layer 7, and the fourth dielectric layer 8, the surface morphology of the subsequently deposited gate polysilicon material layer can be made flatter, simplifying the planarization process (existing technologies involve at least 5 steps, while this application only requires 2 steps, as detailed above). Furthermore, by using the second dielectric layer 4 as an isolation and protective layer, bridging between the source and drain can be effectively avoided.

[0104] This application also discloses an integrated circuit comprising the aforementioned semiconductor device. Specifically, the integrated circuit includes one or more semiconductor devices, such as N-type FinFET devices and P-type FinFET devices. The semiconductor device includes multiple fins 1, multiple spacer regions 2, a first dielectric layer 3, a second dielectric layer 4, and a gate layer 5. The multiple fins 1 and multiple spacer regions 2 are arranged alternately along a first direction. The fins 1 extend along a second direction perpendicular to the first direction. The first dielectric layer 3 covers the sidewalls of the spacer regions 2 and the fins 1. A portion of the spacer regions 2 is also filled with the second dielectric layer 4. The second dielectric layer 4 is located in a first groove 6 formed by the first dielectric layer 3, and the top of the second dielectric layer 4 is higher than the top of the first dielectric layer 3. The second dielectric layer 4 is made of a different material than the first dielectric layer 3. The gate layer 5 spans across the multiple fins 1 and the multiple second dielectric layers 4 along the first direction. The second dielectric layer 4 disposed on the first dielectric layer 3 can balance the stress on the fins 1 caused by the gate layer 5, thereby alleviating fin bending.

[0105] This application also discloses a chip comprising the aforementioned integrated circuit. This chip can be applied to a microprocessor or memory. The integrated circuit included in the chip comprises at least one of the aforementioned semiconductor devices, which includes multiple fins 1, multiple spacer regions 2, a first dielectric layer 3, a second dielectric layer 4, and a gate layer 5. The multiple fins 1 and the multiple spacer regions 2 are arranged alternately along a first direction; the fins 1 extend along a second direction perpendicular to the first direction; the first dielectric layer 3 covers the sidewalls of the spacer regions 2 and the fins 1; a portion of the spacer regions 2 is further filled with the second dielectric layer 4; the second dielectric layer 4 is located in a first groove 6 formed by the first dielectric layer 3, and the top of the second dielectric layer 4 is higher than the top of the first dielectric layer 3; the second dielectric layer 4 is made of a different material than the first dielectric layer 3; the gate layer 5 spans across the multiple fins 1 and the multiple second dielectric layers 4 along the first direction. The second dielectric layer 4 disposed on the first dielectric layer 3 can balance the stress on the fins caused by the gate layer 5, thereby alleviating fin bending.

[0106] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized by, It includes multiple fins, multiple spacer regions, a first dielectric layer, a second dielectric layer, and a gate layer; The plurality of fins and the plurality of spacer regions are arranged alternately along a first direction; the fins extend along a second direction perpendicular to the first direction. The first dielectric layer covers the spacer region and the sidewalls of the fin; The spacer region is further filled with a second dielectric layer; the second dielectric layer is located in a first groove formed by the first dielectric layer, and the top of the second dielectric layer is higher than the top of the first dielectric layer; the second dielectric layer is made of a different material than the first dielectric layer. The gate layer spans across the plurality of fins and the plurality of second dielectric layers along the first direction.

2. The semiconductor device according to claim 1, wherein The width of the second dielectric layer is on the same order of magnitude as the width of the fin; The stress on the fins is balanced by adjusting the thickness and / or material of the first and second dielectric layers.

3. The semiconductor device according to claim 1, characterized in that, The spacer region includes at least a first spacer region and a second spacer region; the first spacer region is filled with the first dielectric layer; the second spacer region is filled with both the first dielectric layer and the second dielectric layer; the width of the second spacer region is greater than the width of the first spacer region.

4. The semiconductor device according to any one of claims 1-3, characterized in that, It also includes a third dielectric layer and a fourth dielectric layer; The third dielectric layer is located in the second groove formed by the second dielectric layer, and the fourth dielectric layer covers the third dielectric layer; The material of the fourth dielectric layer is the same as that of the second dielectric layer.

5. The semiconductor device according to claim 4, characterized in that, The material of the third dielectric layer includes silicon oxide; The material of the fourth dielectric layer includes an inorganic material with a low dielectric constant; the inorganic material with a low dielectric constant includes nitride-like materials or Si xOyNz, where x, y, and z are all non-negative numbers; The material of the first dielectric layer includes silicon oxide; The material of the second dielectric layer includes the inorganic material with the low dielectric constant.

6. The semiconductor device according to claim 4, characterized in that, The top of the first dielectric layer is in contact with the bottom of the gate layer; The top of the third dielectric layer is higher than the top of the first dielectric layer and lower than the top of the fin; There is a first height difference between the top of the fourth dielectric layer and the top of the fin.

7. The semiconductor device according to claim 4, characterized in that, The spacer region further includes a third spacer region; the third spacer region is filled with the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer.

8. The semiconductor device according to any one of claims 1-5, characterized in that, The top of the first dielectric layer is lower than the top of the fin; There is a second height difference between the top of the second dielectric layer and the top of the fin.

9. The semiconductor device according to claim 8, characterized in that, A partition layer is provided on the second dielectric layer in the second spacer region; the partition layer penetrates the gate layer along a third direction; the third direction is the height direction of the fin.

10. A method for fabricating a semiconductor device, characterized in that, include: Provide a semiconductor structure; The semiconductor structure includes multiple fins, multiple spacer regions, and a first dielectric layer; The plurality of fins and the plurality of spacer regions are arranged alternately along a first direction; the fins extend along a second direction perpendicular to the first direction; the first dielectric layer covers the spacer regions and the sidewalls of the fins; A second dielectric layer is formed on the first dielectric layer; the second dielectric layer is made of a different material than the first dielectric layer. The region near the top of the fin in the first dielectric layer is removed, and the second dielectric layer located at the top of the fin is removed, so that a portion of the spacer region is still filled with the second dielectric layer; the second dielectric layer is located in the first groove formed by the first dielectric layer, and the top of the second dielectric layer is higher than the top of the first dielectric layer; A gate layer is prepared; the gate layer extends across the plurality of fins and the plurality of second dielectric layers along the first direction.

11. The preparation method according to claim 10, characterized in that, The provision of a semiconductor structure includes: A substrate structure with multiple fins on the top is provided; Form the first dielectric layer; Remove the fin in the third-party upward preset area; the third-party direction is the height direction of the fin, so that the first dielectric layer filled in part of the interval area forms the first groove.

12. The preparation method according to claim 10, characterized in that, Before removing the region of the first dielectric layer near the top of the fin, the method further includes: A third dielectric layer is formed in the second groove formed by the second dielectric layer; A fourth dielectric layer is formed; the fourth dielectric layer covers the third dielectric layer.

13. The preparation method according to claim 10, characterized in that, The removal of the region of the first dielectric layer near the top of the fin, and the removal of the second dielectric layer located at the top of the fin, includes: The second dielectric layer is etched back to remove the second dielectric layer located on top of the fin; The semiconductor substrate is planarized to remove the first dielectric layer located on top of the fin; Remove the first dielectric layer near the top of the fin so that the top of the first dielectric layer is lower than the top of the fin.

14. The preparation method according to claim 10, characterized in that, The fabrication of the gate layer includes: A gate material layer is formed on top of the semiconductor structure; Remove material from a predetermined position of the gate material layer to form a segmented region penetrating the gate material layer on the second dielectric layer corresponding to the predetermined position, and obtain a functional gate structure; A segmentation layer is formed to fill the segmented region, thereby obtaining the gate layer.

15. An integrated circuit, characterized in that, Includes the semiconductor device as described in any one of claims 1-9.

16. A chip, characterized in that, Including the integrated circuit as described in claim 15.

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