Split gate trench metal oxide semiconductor field effect transistor and method of fabrication

Abstract

This invention discloses a split-gate trench metal-oxide-semiconductor field-effect transistor and its fabrication method, belonging to the field of semiconductor technology. The transistor includes: a drain metal, a drift region, a current spread region, a body region, a trench, a split-gate structure, a gate metal, a source region, and a source metal. The trench has a sawtooth or wavy structure in the horizontal direction, sequentially penetrating the body region, the current spread region, and extending into the drift region. The split-gate structure includes a first source polysilicon, a second source polysilicon, and a gate polysilicon. Trench openings in the source region are etched to the second source polysilicon, electrically connecting the source metal to the second source polysilicon. This invention, through its sawtooth trench design, increases the process window of the source contact hole, reduces the requirements for photolithography precision, lowers the on-state voltage drop, increases the contact area between the contact hole and the second source polysilicon, and shortens the reverse recovery time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a split-gate trench metal-oxide-semiconductor field-effect transistor and its fabrication method. Background Technology

[0002] In power electronic systems, power semiconductor devices play an increasingly important role in handling high voltage, high current, high frequency signals, and high power management. Compared to traditional vertical double-diffused MOSFETs (VDMOS), split-gate trench MOSFETs (SGT MOSFETs) achieve a better balance between on-resistance and breakdown voltage and are more suitable for high-frequency switching circuits. In inductive load applications such as inverters and boost converters, the source-drain parasitic body diodes of SGT MOSFETs are used for freewheeling. Due to the bipolar characteristics of the parasitic body diodes, minority carriers are injected into the drift region during forward conduction, and excess carriers need to be extracted during turn-off, resulting in poor reverse recovery performance and thus additional power loss.

[0003] Over the past few decades, the industry has proposed a series of methods to solve the above problems. For example, anti-parallel external diodes are one of the most commonly used methods, however, this introduces additional parasitic capacitance and inductance into the circuit. In addition, existing solutions also optimize the reverse recovery characteristics of the device by introducing a built-in channel diode (BCD) structure on the front side of the SGT MOSFET. However, this structure also has certain drawbacks: (1) the spacing between the source polysilicon and the gate polysilicon on the device surface is small, which results in extremely high process precision requirements for opening the source polysilicon contact hole (CT), making it difficult to achieve large-area mass production; (2) this structure sacrifices some channel density, which leads to a certain increase in the on-resistance of the device, which in turn increases the on-voltage drop during forward conduction and increases the conduction loss of the device. Summary of the Invention

[0004] The purpose of this invention is to overcome the problems of the prior art and provide a split-gate trench metal-oxide-semiconductor field-effect transistor and its fabrication method.

[0005] The objective of this invention is achieved through the following technical solution: a split-gate trench metal-oxide-semiconductor field-effect transistor, comprising: Drain metal; The drift region located on the drain metal; The current extension region located above the drift region; The volume region located above the current extension region; The trenches sequentially penetrate the body region, the current extension region, and extend into the drift region, exhibiting a sawtooth or wavy structure in the horizontal direction. The split gate structure located in the trench includes a first source polysilicon located at the bottom of the trench, a second source polysilicon located in the upper part of the trench, and a gate polysilicon located in the upper part of the trench, wherein a first isolation layer is provided between the second source polysilicon and the gate polysilicon. The source region, located in the body region, has a sawtooth or wavy structure, and the trenches in the source region are provided with contact holes that extend to the second source polysilicon. The source metal is electrically connected to the second source polysilicon via a contact hole; The gate metal is electrically connected to the gate polysilicon.

[0006] In one example, the trench adopts a periodic sawtooth or wavy structure, with the sawtooth or wavy structures on the left and right sides arranged in a complementary and intersecting pattern.

[0007] In one example, the serrated structure includes any one or more of the following: trapezoidal, elliptical, triangular, or rectangular.

[0008] In one example, the size and spacing of the serrated structure are integer multiples of the groove width.

[0009] In one example, a second isolation layer is provided between the first source polysilicon and the drift region and current extension region.

[0010] In one example, a third isolation layer is provided between the first source polysilicon and the second source polysilicon and the gate polysilicon.

[0011] In one example, a fourth isolation layer is provided between the second source polysilicon and the current extension region, and a fifth isolation layer is provided between the gate polysilicon and the current extension region.

[0012] In one example, a shielding oxide layer is provided on the trench and source region.

[0013] It should be further noted that the technical features corresponding to the above-mentioned device examples can be combined or substituted to form new technical solutions.

[0014] This invention also includes a method for fabricating a split-gate trench metal-oxide-semiconductor field-effect transistor, the method comprising the following steps: A drift region, a current spreading region above the drift region, and a bulk region above the current spreading region are sequentially formed on a semiconductor substrate. In the drift region, current expansion region and body region, grooves with a sawtooth or wavy structure in the horizontal direction are formed by photolithography and etching. The grooves sequentially penetrate the body region, the current expansion region and extend into the drift region. A split gate structure is fabricated in a trench, including a first source polysilicon located at the bottom of the trench, a second source polysilicon located in the upper part of the trench, and a gate polysilicon located in the upper part of the trench, wherein a first isolation layer is provided between the second source polysilicon and the gate polysilicon. The source region is formed within the body region, and the source region is formed with the trench in a sawtooth or wavy shape; Contact holes extending to the second source electrode polycrystalline silicon are opened in the trench of the source region; A metal is deposited on top of the device to form the source metal, and is electrically connected to the second source polysilicon through a contact hole; A gate metal is formed, which is electrically connected to the gate polysilicon through a layout design. Drain metal is formed on the back side of the drift region.

[0015] In one example, the split gate structure is fabricated within the trench, including: A second initial isolation layer is deposited on the inner sidewall of the trench; A first polysilicon layer is deposited within the isolation layer of the trench; The first polysilicon layer and the second initial isolation layer are etched back to obtain the first source polysilicon and the second isolation layer located at the bottom of the trench. A third initial isolation layer is deposited in the trench and etched to obtain a third isolation layer located above the first source polysilicon and the second isolation layer. A fourth initial isolation layer is deposited in the upper part of the trench to obtain a fourth intermediate isolation layer located on the inner sidewall of the upper part of the trench. A second polysilicon layer is deposited between the fourth intermediate isolation layer on the two inner sidewalls of the upper part of the trench; The second polysilicon layer is etched back to obtain the second source polysilicon located in the upper part of the trench, and the fourth intermediate isolation layer is selectively etched to obtain the fourth isolation layer located between the second source polysilicon and the current extension region. First and fifth initial isolation layers are generated in the upper part of the trench, and the first and fifth initial isolation layers are selectively etched to obtain the fifth isolation layer located between the gate polysilicon and the current extension region, and the first isolation layer between the second source polysilicon and the gate polysilicon. A third polysilicon layer is deposited between the first and fifth isolation layers to obtain the gate polysilicon.

[0016] Compared with the prior art, the beneficial effects of the present invention are: 1. The trench adopts a wavy or sawtooth structure, which increases the exposure area of ​​the polysilicon of the second source electrode. It has a larger process window when etching the metal hole of the source level on the front side, which reduces the alignment accuracy requirements when etching the contact hole in the trench of the source region. The device does not require high-precision photolithography equipment in production, resulting in low manufacturing cost and enabling large-area mass production.

[0017] 2. The channel area of ​​the wavy or sawtooth trench is significantly increased compared to BCD-SGT, which effectively improves the channel density and reduces the on-state voltage drop of the device during forward conduction. This makes the on-state voltage drop of the device much lower than that of the traditional BCD-SGT, greatly reducing the power loss of the device.

[0018] 3. The sawtooth-shaped trench increases the contact area between the contact hole and the second source polysilicon, reduces the resistance of the carrier extraction path during reverse recovery, accelerates the extraction speed of excess carriers in the drift region, and shortens the reverse recovery time.

[0019] 4. Compared to traditional SGT MOSFET devices, only one additional mask is needed, and the trench, source region and contact hole patterns need to be modified to fabricate the device. No additional patterns are required, resulting in low manufacturing cost and easy compatibility with existing processes. Attached Figure Description

[0020] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The accompanying drawings are provided to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to denote the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0021] Figure 1 This is a schematic diagram of a device structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the device structure AA according to an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the device structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the grooved plate pattern provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the source region graphic appearance provided in an embodiment of the present invention; Figure 6 This is a top view schematic diagram of the device structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the trench structure in the drift region provided in an embodiment of the method of the present invention; Figure 8This is a schematic diagram of the device structure prepared by steps S31-S32 according to an embodiment of the method of the present invention; Figure 9 This is a schematic diagram of the device structure obtained by steps S33-S34 in an embodiment of the method of the present invention; Figure 10 This is a schematic diagram of the device structure prepared by steps S35-S36 in an embodiment of the method of the present invention; Figure 11 This is a schematic diagram of the device structure obtained by step S37 in an embodiment of the method of the present invention; Figure 12 This is a schematic diagram of the device structure prepared by steps S38-S39 in an embodiment of the method of the present invention.

[0022] In the diagram: 1-Drain metal; 2-Drift region; 3-Trench; 4-Second isolation layer; 5-Current spread region; 6-Third isolation layer; 7-Bulk region; 8-Fifth isolation layer; 9-Source region; 10-Shielding oxide layer; 11-Contact hole; 12-Gate polysilicon; 13-Fourth isolation layer; 14-Second source polysilicon; 15-First source polysilicon; 16-First isolation layer; 17-Second initial isolation layer; 18-First polysilicon layer; 19-Fourth intermediate isolation layer; 20-Second polysilicon layer; 21-Source metal. Detailed Implementation

[0023] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0025] In one embodiment, such as Figures 1-3 As shown, a split-gate trench metal-oxide-semiconductor field-effect transistor includes: The drain metal 1, located on the back of the device, is formed by a combination of one or more metal materials selected from aluminum, copper, titanium, and tungsten, and is specifically prepared by physical vapor deposition or chemical vapor deposition processes.

[0026] Drift region 2, located above the drain metal, is of the first conductivity type. In this embodiment, it is distributed on the N-type epitaxial layer with a doping concentration of 1×10⁻⁶. 12 cm -3 Up to 1×10 14 cm -3Between these elements, the doping element is phosphorus.

[0027] The current extension region 5 is located above the drift region. In this embodiment, it is an N-type CS storage layer with a higher doping concentration than the drift region.

[0028] Body region 7, located above the current extension region, is the second conductivity type, such as P-type.

[0029] Trench 3 extends downwards from the surface of the body region, successively penetrating the body region, the current extension region, and extending into the drift region. The trench depth is set according to the device's withstand voltage, typically between 1 μm and 10 μm. In this invention, the trench has a sawtooth or wavy structure in the horizontal direction, which is formed by photolithography. The sawtooth or wavy structure of the trench in this invention increases the surface area of ​​the trench sidewalls, providing a larger process window for subsequent contact hole formation, while also increasing the trench width.

[0030] The split-gate structure, located within a trench, includes a first source polysilicon 15 at the bottom of the trench, a second source polysilicon 14 in the upper middle part of the trench, and a gate polysilicon 12 in the upper middle part of the trench. A first isolation layer 16 is provided between the second source polysilicon and the gate polysilicon, and a gate metal is provided above the gate polysilicon. The second source polysilicon serves as a dummy gate for the built-in channel diode, inducing a unipolar conductive channel during reverse conduction to replace the bipolar parasitic diode for freewheeling.

[0031] Source region 9, located in the body region, is of the first conductivity type and has a higher doping concentration than the drift region. In this embodiment, the source region is a highly doped N-type source region with a doping concentration of approximately 1 × 10⁻⁶. 19 cm -3 Furthermore, the trench in the source region has a contact hole 11 extending to the second source polysilicon at the serrated edge.

[0032] The source metal 21 is electrically connected to the second source polysilicon via a contact hole, forming electrical conductivity. The source metal is formed by combining one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, and is prepared by physical vapor deposition or chemical vapor deposition processes.

[0033] The gate metal, electrically connected to the gate polysilicon, is formed using one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, and can be prepared by physical vapor deposition or chemical vapor deposition processes. It should be noted that in this embodiment, the gate metal is laid out on the edge region of the SGT MOSFET device and electrically connected to the gate polysilicon via metal interconnects.

[0034] This embodiment increases the channel width and contact hole process window by designing the trench as a sawtooth or wavy structure. At the same time, it allows the source metal to be directly electrically connected to the second source polysilicon. This significantly reduces the requirements for the precision of the photolithography equipment while reducing the forward conduction voltage drop and shortening the reverse recovery time, enabling the device to be mass-produced on a large scale.

[0035] In one embodiment, such as Figure 4 As shown, the trenches employ a periodic sawtooth or wavy structure, with the sawtooth or wavy structures on the left and right sides arranged in a complementary, intersecting pattern. This complementary, intersecting arrangement of the sawtooth or wavy structures further increases the trench's surface area, thereby enlarging the process window for subsequent contact holes and reducing the high-precision requirements of contact hole etching. Figure 5 As shown, due to the sawtooth or wavy structure of the trench, the source regions located on both sides of the trench also exhibit a sawtooth or wavy distribution. Furthermore, contact holes are formed at the sawtooth sections of the trench in the source region. These contact holes extend downwards to the surface of the second source polysilicon, allowing the source metal to form an ohmic contact with the second source polysilicon through these contact holes. A schematic diagram of the source region, contact holes, and trench is shown below. Figure 6 As shown.

[0036] In one embodiment, the serrated structure includes any one or more of trapezoidal, elliptical, triangular, or rectangular shapes. Triangular teeth can maximize the channel area, and different serrated structures can be defined by photolithography patterns.

[0037] In one embodiment, the size and spacing of the serrated structure are integer multiples of the groove width, for example, the serration width is 1-2 times the groove width, and the serration spacing is 1 to 3 times the groove width.

[0038] In one embodiment, such as Figure 1 As shown, a second isolation layer 4 is provided between the first source polysilicon and the drift region and current extension region. Specifically, it is a field oxide layer, which is made of silicon dioxide material and formed by wet oxygen oxidation plus high-density plasma deposition process. Its thickness is set according to the device withstand voltage, and is generally between 0.04 μm and 1 μm. It is used to achieve electrical isolation between the first source polysilicon and the drift region.

[0039] In one embodiment, such as Figure 1 As shown, a third isolation layer 6 is provided between the first source polysilicon and the second source polysilicon and gate polysilicon. Specifically, the intermediate isolation oxide layer is made of silicon dioxide and formed by deposition. The thickness of the intermediate isolation oxide layer is generally between 0.2 μm and 0.8 μm, and is determined according to the device breakdown voltage, trench size and capacitor design requirements. It is used to achieve electrical isolation between the first source polysilicon and the upper second source polysilicon and gate polysilicon.

[0040] In one embodiment, such as Figure 1 As shown, a fourth isolation layer 13 is provided between the second source polysilicon and the current extension region, and a fifth isolation layer 8 is provided between the gate polysilicon and the current extension region. The fourth isolation layer is a source oxide layer, formed using a dry oxidation process, with a thickness typically between 20 nm and 50 nm; the fifth isolation layer is a gate oxide layer, formed using a dry oxidation process, with a thickness typically between 50 nm and 100 nm. It should be noted that the first isolation layer and the fifth isolation layer (gate oxide layer) are fabricated simultaneously, using the same material (oxide layers), differing only in their location; the first isolation layer is located between the second source polysilicon and the gate polysilicon.

[0041] In one embodiment, a shielding oxide layer 10 is provided on the trench and source region. The shielding oxide layer is made of silicon dioxide and is formed by deposition or thermal oxidation processes.

[0042] This invention also includes a method for fabricating a split-gate trench metal-oxide-semiconductor field-effect transistor, the method comprising the following steps: S1: A drift region, a current spreading region above the drift region, and a body region above the current spreading region are sequentially formed on the semiconductor substrate.

[0043] In step S1, the drift region is an N-type epitaxial layer with a doping concentration of 1×10⁻⁶. 12 cm -3 Up to 1×10 14 cm -3 Between these regions, the doping element is phosphorus; the current extension region is formed by ion implantation, with a doping concentration higher than that of the drift region; the bulk region is a P-type base region, formed by boron ion implantation and annealing.

[0044] S2: In the drift region, current expansion region and body region, grooves with a sawtooth or wavy structure in the horizontal direction are formed by photolithography and etching. The grooves successively penetrate the body region, the current expansion region and extend into the drift region.

[0045] In step S2, the trench depth is set according to the device withstand voltage, generally between 1 μm and 10 μm. The sawtooth or wavy structure is achieved by photolithographic pattern definition, including any one or more of trapezoidal, elliptical, triangular or rectangular shapes. The tooth size and spacing are generally integer multiples of the trench width, and the sawtooth structures on the left and right sides are arranged in a complementary and staggered manner.

[0046] S3: A split gate structure is fabricated in the trench, including a first source polysilicon located at the bottom of the trench, a second source polysilicon located in the upper part of the trench, and a gate polysilicon located in the upper part of the trench, wherein a first isolation layer is provided between the second source polysilicon and the gate polysilicon.

[0047] In step S3, the second source polysilicon serves as the pseudo-gate of the built-in channel diode. When reverse-biased, it induces a unipolar conductive channel to replace the bipolar parasitic diode for freewheeling.

[0048] S4: A source region is formed within the body region, and the source region is formed in a sawtooth or wavy shape along with the groove.

[0049] In step S4, the source region is formed through high-dose arsenic ion implantation and annealing, with a doping concentration of approximately 1 × 10⁻⁶. 19 cm -3 The platform area located on both sides of the trench.

[0050] S5: A contact hole extending to the second source polysilicon is opened in the trench of the source region; In step S5, the contact hole extends to the second source polysilicon, providing a channel for the subsequent connection between the source metal and the second source polysilicon.

[0051] S6: Deposit metal on top of the device to form source metal, and electrically connect it to the second source polysilicon through a contact hole; In step S6, the source metal is formed by combining one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, and is prepared by physical vapor deposition or chemical vapor deposition processes.

[0052] S7: Form gate metal, which is electrically connected to the gate polysilicon through layout design; In step S7, the gate metal is formed using one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, and can be prepared by physical vapor deposition or chemical vapor deposition processes. It should be noted that in this embodiment, the gate metal is laid out on the edge region of the device and electrically connected to the gate polysilicon via metal interconnects.

[0053] S8: Drain metal is formed on the back side of the drift region.

[0054] In step S8, the drain metal is formed by a combination of one or more metal materials selected from aluminum, copper, titanium, titanium nitride, and tungsten, and can be formed by a back-side thinning process.

[0055] In one embodiment, fabricating a split gate structure within a trench includes: S31: As Figure 8 As shown, a second initial isolation layer 17 is deposited on the inner sidewall of the trench.

[0056] In particular, trenches 3 are formed in the N-type drift region 2 through photolithography and etching processes. Figure 7As shown, the trench depth is set according to the device withstand voltage, and is generally between 1µm and 10µm. Further, the second initial isolation layer is a field oxide layer, which is made of silicon dioxide material and formed by wet oxygen oxidation plus high-density plasma deposition process. Its thickness is set according to the device withstand voltage, and is generally between 0.04µm and 1µm, and is used to achieve electrical isolation between the first source polysilicon and the drift region.

[0057] S32: As Figure 8 As shown, a first polysilicon layer 18 is deposited within the second initial isolation layer 17 of the trench.

[0058] The first polycrystalline silicon layer is an N-type doped polycrystalline silicon layer, formed by low-pressure chemical vapor deposition, with phosphorus as the dopant element.

[0059] S33: As Figure 9 As shown, the first polysilicon layer and the second initial isolation layer are etched back to obtain the first source polysilicon 15 and the second isolation layer 4 located at the bottom of the trench.

[0060] The etch-back process employs anisotropic dry etching, which leaves the first polysilicon layer and the second isolation layer only at the bottom of the trench, forming the first source polysilicon and the field oxide layer that surrounds its bottom and sides.

[0061] S34: As Figure 9 As shown, a third initial isolation layer is deposited in the trench, and the third initial isolation layer is etched to obtain a third isolation layer 6 located above the first source polysilicon and the second isolation layer.

[0062] The third isolation layer is an intermediate isolation oxide layer, made of silicon dioxide and formed by deposition. Its thickness is generally between 0.2 μm and 0.8 μm, depending on the device's voltage rating, trench size, and capacitor design requirements. It is used to achieve electrical isolation between the first source polysilicon and the upper second source polysilicon and gate polysilicon.

[0063] S35: As Figure 10 As shown, a fourth initial isolation layer is deposited in the upper part of the trench to obtain a fourth intermediate isolation layer 19 located on the inner sidewall of the upper part of the trench.

[0064] The fourth intermediate isolation layer is a precursor to the source oxide layer. It is formed by dry oxidation process and its thickness is controlled between 20 nm and 50 nm. It is used to form the isolation layer of the second source polysilicon sidewall.

[0065] S36: As Figure 10 As shown, a second polysilicon layer 20 is deposited between the fourth intermediate isolation layer on the two inner sidewalls of the upper part of the trench.

[0066] The second polycrystalline silicon layer is an N-type doped polycrystalline silicon layer, formed by low-pressure chemical vapor deposition, with phosphorus as the dopant element.

[0067] S37: As Figure 11 As shown, the second polysilicon layer is etched back to obtain the second source polysilicon 14 located in the upper part of the trench, and the fourth intermediate isolation layer is selectively etched to obtain the fourth isolation layer 13 located between the second source polysilicon and the current extension region.

[0068] In this process, after etching back, the second source polysilicon fills one side of the upper part of the trench, while a space is reserved on the other side for forming the gate polysilicon. That is, the second source polysilicon and the gate polysilicon are arranged in parallel. The fourth isolation layer is a source oxide layer with a thickness of 20 nm to 50 nm.

[0069] S38: As Figure 12 As shown, a first and a fifth initial isolation layer are formed in the upper part of the trench, and the first and the fifth initial isolation layers are selectively etched to obtain a fifth isolation layer 8 located between the gate polysilicon and the current extension region, and a first isolation layer 16 between the second source polysilicon and the gate polysilicon.

[0070] The fifth isolation layer is a gate oxide layer, formed using a dry oxidation process, with a thickness typically between 50 nm and 100 nm, used to form the MOSFET channel during forward conduction. The first isolation layer is the isolation layer between the gate polysilicon and the second source polysilicon, also made of silicon dioxide, and is fabricated simultaneously with the fifth isolation layer, differing only in its position design.

[0071] S39: As Figure 12 As shown, a third polysilicon layer is deposited between the first isolation layer and the fifth isolation layer to obtain the gate polysilicon 12.

[0072] The third polysilicon layer is an N-type doped polysilicon layer, formed by low-pressure chemical vapor deposition, which fills the upper part of the trench to form a gate polysilicon structure.

[0073] This embodiment uses multiple deposition, etch-back, and selective etching processes to form a first source polysilicon, a second source polysilicon, and a gate polysilicon within the trench, while simultaneously achieving electrical connection between the second source polysilicon and the source metal. The process is simple and the device has high reliability.

[0074] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A split-gate trench metal-oxide-semiconductor field-effect transistor, characterized in that, include: Drain metal; The drift region located on the drain metal; The current extension region located above the drift region; The volume region located above the current extension region; The trenches sequentially penetrate the body region, the current extension region, and extend into the drift region, exhibiting a sawtooth or wavy structure in the horizontal direction. The split gate structure located in the trench includes a first source polysilicon located at the bottom of the trench, a second source polysilicon located in the upper part of the trench, and a gate polysilicon located in the upper part of the trench, wherein a first isolation layer is provided between the second source polysilicon and the gate polysilicon. The source region, located in the body region, has a sawtooth or wavy structure, and the trenches in the source region are provided with contact holes that extend to the second source polysilicon. The source metal is electrically connected to the second source polysilicon via a contact hole; The gate metal is electrically connected to the gate polysilicon.

2. The split-gate trench metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The groove adopts a periodic sawtooth or wave-like structure, with the sawtooth or wave-like structures on the left and right sides arranged in a complementary and intersecting pattern.

3. The split-gate trench metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The serrated structure includes any one or more of the following: trapezoidal, elliptical, triangular, or rectangular.

4. The split-gate trench metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The dimensions and spacing of the serrated structure are integer multiples of the groove width.

5. The split gate trench metal oxide semiconductor field effect transistor of claim 1, wherein, A second isolation layer is provided between the first source polysilicon and the drift region and the current extension region.

6. The split-gate trench metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, A third isolation layer is provided between the first source polysilicon, the second source polysilicon, and the gate polysilicon.

7. The split-gate trench metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, A fourth isolation layer is provided between the second source polysilicon and the current extension region, and a fifth isolation layer is provided between the gate polysilicon and the current extension region.

8. The split gate trench metal oxide semiconductor field effect transistor of claim 1, wherein, The trench and source area are provided with a shielding oxide layer.

9. A method of fabricating a split-gate trench MOSFET, comprising: Includes the following steps: A drift region, a current spreading region above the drift region, and a bulk region above the current spreading region are sequentially formed on a semiconductor substrate. In the drift region, current expansion region and body region, grooves with a sawtooth or wavy structure in the horizontal direction are formed by photolithography and etching. The grooves sequentially penetrate the body region, the current expansion region and extend into the drift region. A split gate structure is fabricated in a trench, including a first source polysilicon located at the bottom of the trench, a second source polysilicon located in the upper part of the trench, and a gate polysilicon located in the upper part of the trench, wherein a first isolation layer is provided between the second source polysilicon and the gate polysilicon. The source region is formed within the body region, and the source region is formed with the trench in a sawtooth or wavy shape; Contact holes extending to the second source electrode polycrystalline silicon are opened in the trench of the source region; A metal is deposited on top of the device to form the source metal, and is electrically connected to the second source polysilicon through a contact hole; A gate metal is formed, which is electrically connected to the gate polysilicon through a layout design. Drain metal is formed on the back side of the drift region.

10. The method for fabricating a split-gate trench metal-oxide-semiconductor field-effect transistor according to claim 9, characterized in that, Fabricating a split gate structure within a trench includes: A second initial isolation layer is deposited on the inner sidewall of the trench; A first polysilicon layer is deposited within the isolation layer of the trench; The first polysilicon layer and the second initial isolation layer are etched back to obtain the first source polysilicon and the second isolation layer located at the bottom of the trench. A third initial isolation layer is deposited in the trench and etched to obtain a third isolation layer located above the first source polysilicon and the second isolation layer. A fourth initial isolation layer is deposited in the upper part of the trench to obtain a fourth intermediate isolation layer located on the inner sidewall of the upper part of the trench. A second polysilicon layer is deposited between the fourth intermediate isolation layer on the two inner sidewalls of the upper part of the trench; The second polysilicon layer is etched back to obtain the second source polysilicon located in the upper part of the trench, and the fourth intermediate isolation layer is selectively etched to obtain the fourth isolation layer located between the second source polysilicon and the current extension region. First and fifth initial isolation layers are generated in the upper part of the trench, and the first and fifth initial isolation layers are selectively etched to obtain the fifth isolation layer located between the gate polysilicon and the current extension region, and the first isolation layer between the second source polysilicon and the gate polysilicon. A third polysilicon layer is deposited between the first and fifth isolation layers to obtain the gate polysilicon.

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