A solvent-processed pn polarity reversible field effect transistor and a preparation method thereof

Abstract

This invention proposes a solvent-treated PN polarity reversible field-effect transistor and its fabrication method, aiming to solve the problems of uncontrollable and irreversible doping in two-dimensional semiconductor devices and poor compatibility with standard processes. The transistor comprises a p-type silicon gate, a silicon dioxide dielectric layer, a few-layer indium selenide channel, and gold source / drain electrodes. Initially n-type, it transforms to p-type after immersion in acetone solution, and can be restored to n-type by vacuum or inert atmosphere annealing, achieving completely reversible polarity switching. The fabrication method encompasses channel stripping and transfer, electrode evaporation, acetone treatment, and annealing, requiring no external doping and compatible with existing micro / nano fabrication processes. By controlling the acetone treatment time and annealing conditions, the carrier type can be precisely controlled, and the device maintains good stability during multiple cycles.

Description

Technical Field

[0001] This invention relates to the field of two-dimensional semiconductor devices and their doping control technology, and in particular to a solvent-treated PN polarity reversible field-effect transistor and its fabrication method. Background Technology

[0002] In the post-Moore's Law era, as the feature size of integrated circuits continues to approach physical limits, traditional silicon-based field-effect transistors (FETs) face increasingly severe challenges in terms of power consumption, short-channel effect suppression, and mobility. Against this backdrop, two-dimensional (2D) semiconductor materials, due to their intrinsic advantages such as atomic-level thickness, tunable bandgap structure, and absence of dangling bonds, are considered ideal channel candidates for constructing next-generation high-performance, low-power electronic devices. Compared to bulk silicon, FETs based on 2D materials exhibit higher carrier mobility, lower static power consumption, and superior gate control capabilities, providing a new technological path for extending Moore's Law. However, 2D materials still face a fundamental obstacle in practical integrated applications: it is difficult to achieve stable and controllable p-type and n-type doping through traditional ion implantation methods, which severely restricts the construction of key circuit architectures such as complementary metal-oxide-semiconductor (CMOS) semiconductors.

[0003] To overcome these challenges, existing technologies primarily rely on unconventional doping strategies such as chemical modification, surface adsorption, or oxidation-induced doping. While these methods have achieved some degree of control over the carrier type in two-dimensional channels, they generally suffer from several inherent drawbacks. Specifically, chemical modification typically involves the introduction of strong oxidants or reducers, which can easily form uncontrollable side reaction products on the material surface, resulting in poor doping uniformity. Surface adsorption, although it can be performed at low temperatures, is highly dependent on the ambient atmosphere, lacks stability, and is difficult to achieve precise atomic-scale positioning. Oxidation-induced doping often requires high-temperature treatment, which may not only damage the lattice integrity of two-dimensional materials but also introduce deep-level defects, degrading the electrical performance of the device. More importantly, most of these doping methods are essentially irreversible processes, unable to support dynamic switching of conduction polarity during device operation, thus limiting their application potential in emerging fields such as reconfigurable logic and neuromorphic computing.

[0004] It is worth noting that photolithography is widely used for electrode patterning and channel definition in the large-scale fabrication of two-dimensional (2D) devices. In the crucial step of this process—photoresist removal—acetone is commonly used as a standard developing and removing solvent. For a long time, acetone has been considered merely an inert cleaning medium, and its potential impact on 2D semiconductor channels has not been fully considered. However, recent studies have shown that acetone molecules can undergo weak chemical interactions with the surface of certain 2D materials (such as indium selenide), or induce interfacial dipole changes through residual solvent molecules, thereby unintentionally altering the initial carrier type of the channel. This phenomenon may be mitigated through process fine-tuning in small-batch laboratory fabrication, but in large-scale manufacturing scenarios aimed at production line compatibility, it constitutes a hidden and systematic source of process disturbance: even slight fluctuations in acetone treatment conditions within the same batch of devices can lead to inconsistencies in polarity, ultimately causing circuit malfunctions.

[0005] Therefore, how to transform the influence of conventional process solvents such as acetone on the polarity of two-dimensional semiconductor channels from an uncontrollable process disturbance into a programmable, reversible, and atomically precise doping method, and ensure its seamless integration with large-scale photolithography processes, has become a key challenge and an urgent technical problem for those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to propose a solvent-treated PN polarity reversible field-effect transistor and its fabrication method, aiming to solve the problem of insufficient polarity stability of existing two-dimensional semiconductor devices in large-scale integration processes due to uncontrollable and irreversible doping and poor compatibility with standard micro-nano fabrication processes.

[0007] To achieve the above-mentioned objectives, this invention utilizes the interfacial chemical interaction of acetone solution on indium selenide channel materials, combined with subsequent vacuum or inert atmosphere annealing processes, to construct a field-effect transistor structure and its fabrication path that enables atomically precise, low-damage, and fully reversible switching between n-type and p-type.

[0008] This invention proposes a solvent-treated PN polarity reversible field-effect transistor, comprising a gate electrode, a dielectric layer, a channel layer, and source / drain electrodes. The gate electrode is a p-type heavily doped silicon substrate, the dielectric layer is a silicon dioxide thin film covering the surface of the gate electrode, the channel layer is composed of a few-layer indium selenide with a thickness of 5 to 80 nm, and the source / drain electrodes are formed of gold metal with a thickness of 40 to 50 nm and located at both ends of the channel layer. The transistor initially exhibits n-type conductivity, transforms to a p-type conductivity state after immersion in acetone solution, and then recovers to an n-type conductivity state after vacuum or inert atmosphere annealing, achieving completely reversible control of the carrier type.

[0009] Furthermore, the acetone solution treatment temperature is 20-60 ℃, and the soaking time is 1-10 hours.

[0010] Furthermore, the annealing process is carried out under vacuum or inert atmosphere, with an annealing temperature of 500 to 550 K and a holding time of 30 to 150 minutes.

[0011] Furthermore, the transverse dimension of the channel layer is not less than 20 μm, and the edges are complete and the morphology is uniform.

[0012] This invention proposes a method for fabricating a field-effect transistor, characterized by comprising the following steps: S1: Provide a p-type heavily doped silicon substrate with a 300±10nm thick silicon dioxide layer on the surface, and perform ultrasonic cleaning and drying; S2: A few-layer indium selenide sheet with a thickness of 5 to 80 nm is obtained by mechanical peeling and transferred to the surface of the substrate by polydimethylsiloxane; S3: Using mask thermal evaporation to deposit metallic gold, source and drain electrodes with a thickness of 40 to 50 nm are formed at both ends of the indium selenide channel; S4: Immerse the entire component obtained in S3 in an acetone solution and treat it at 20 to 60°C for 1 to 10 hours to transform it from n-type to p-type; S5: Place the acetone-treated device in a vacuum or inert atmosphere and anneal it at 500 to 550 K for 30 to 150 minutes to restore it to the n-type.

[0013] Furthermore, in S1, the p-type heavily doped silicon substrate is cut into 0.5-2cm square substrates along the cleavage direction.

[0014] Furthermore, in S2, indium selenide flakes are transferred to the surface of polydimethylsiloxane after being repeatedly adhered and peeled off 2 to 3 times with blue film tape. Flakes with a length greater than 20 μm, intact edges and no cracks are selected under an optical microscope for use as channel materials.

[0015] Furthermore, in S3, the thermal evaporation coating is performed in a cavity with a vacuum level of 2×10⁻⁶. -4 Up to 4×10 -4 The deposition was carried out under Pa conditions, with gold deposition rates ranging from 0.1 to 0.5 nm / s.

[0016] Furthermore, in S4, the acetone solution is analytical grade acetone, and the entire component is completely immersed in the solution during the processing.

[0017] Compared with the prior art, the advantages of this invention are as follows: by transforming the acetone treatment step, which is traditionally regarded as a source of process disturbance, into a controllable doping method, this invention establishes for the first time a polarity dynamic control paradigm based on solvent-two-dimensional material interface engineering. This not only solves the doping bottleneck of two-dimensional semiconductors in complementary circuit construction, but also provides a basic device platform with both process compatibility and functional flexibility for future new electronic systems such as reconfigurable logic and neuromorphic computing. Attached Figure Description

[0018] Figure 1 This is a schematic cross-sectional view of the field-effect transistor fabricated by the field-effect transistor fabrication method in this embodiment of the invention. Figure 2 The images show the initial transfer characteristic curves of the field-effect transistor in this embodiment of the invention before acetone treatment and the transfer characteristic curves after acetone solution treatment for 5 h and 10 h. Figure 3 The transfer characteristic curve of the field-effect transistor in this embodiment of the invention is shown after being treated with acetone solution for 10 h and then vacuum annealed at 550K for 2 h. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be further described below.

[0020] See Figure 1 The reversible polarity-controlled field-effect transistor of this invention comprises a gate electrode 4, a dielectric layer 3, a channel layer 2, and source / drain electrodes 1. The gate electrode 4 is a p-type heavily doped silicon substrate with a resistivity controlled within the range of 0.001 to 0.01 Ω·cm. The dielectric layer 3 is a silicon dioxide thin film thermally oxidized on the surface of the gate electrode, with a thickness of 300 ± 10 nm. The channel layer is composed of a few layers of indium selenide, with a thickness ranging from 5 to 80 nm and a lateral dimension not less than 20 μm. The source / drain electrodes 1 are gold metal electrodes formed by thermal evaporation deposition, with a thickness of 40 to 50 nm, located at both ends of the channel layer 2 and forming ohmic or near-ohmic contacts with it. This device initially exhibits n-type conductivity, transforms to a p-type conductivity state after treatment with acetone solution, and can be restored to the original n-type state after vacuum or inert atmosphere annealing, thus achieving completely reversible control of the carrier type.

[0021] The fabrication process of the field-effect transistor of the present invention includes the following five consecutive and interrelated process stages: channel layer fabrication, channel transfer and substrate preparation, source / drain electrode fabrication, acetone solution treatment, and annealing. Each stage contains several precisely controlled sub-steps, which together constitute a complete process path compatible with standard micro / nano fabrication flows.

[0022] The specific preparation process is as follows: S1: Channel layer preparation: A p-type heavily doped silicon substrate with a 300±10 nm thick silicon dioxide layer on its surface was selected and cut into 1×1 cm square substrates along the cleavage plane. The substrates were ultrasonically cleaned with acetone, anhydrous ethanol and deionized water for 10 min in sequence to remove organic residues and particulate contamination, and then dried in an oven.

[0023] S2: Few-layer indium selenide sheets were obtained by mechanical exfoliation. Indium selenide blocks were taken and repeatedly peeled off three times with blue adhesive tape to obtain few-layer sheets. These sheets were transferred onto pre-cut PDMS, and under a microscope, sheets with a thickness less than 80 nm and a length greater than 20 μm were selected as channel layers.

[0024] Performing Channel Transfer and Substrate Preparation: Turn on the optical microscope on the transfer platform, adjust the light source brightness to 40-60%, and place the cleaned and dried silicon wafer on the vacuum adsorption stage of the transfer platform. Turn on the mechanical pump to fix the substrate. First, use a low-magnification microscope to align with the silicon wafer surface and perform preliminary focusing to ensure accurate substrate positioning. Then, mount the PDMS / glass slide carrying the target indium selenide sheet in the transfer platform fixture, ensuring the adhesion surface is facing down. Slowly adjust the Z-axis height to gradually bring the indium selenide sheet closer to the substrate surface. During this process, accurately locate the target indium selenide nanosheet through the microscope's field of view and move it to the center of the field of view. Once the target nanosheet is positioned, continue to gradually lower the Z-axis at a rate of 0.1-0.3 μm / step, allowing the indium selenide sheet to gradually exhibit a complete coverage effect under the microscope and form a tight bond with the substrate surface. To avoid wrinkles or breakage of the sheet, the descent process should be kept smooth until complete adhesion. After adhesion, immediately and slowly raise the Z-axis in the opposite direction at the same rate to separate the PDMS from the silicon wafer surface until they are completely detached. At this stage, uniform operation must be ensured to prevent the material from being pulled or shifted during separation. Finally, the coarse / fine focus knob is readjusted to focus on the silicon substrate surface. When a distinct blue area is observed under the microscope, it can be confirmed that the indium selenide nanosheets have been successfully transferred to the silicon / silicon dioxide substrate surface, maintaining their intact morphology and good adhesion. If necessary, a short-term annealing at a low temperature (60-80 °C) can be performed to further eliminate residual stress and enhance adhesion.

[0025] Simultaneously, high-temperature adhesive tape is evenly applied around the copper mesh mask, extending slightly beyond the mask boundary to enhance fixation during the pressing process. The substrate with completed indium selenide transfer is fixed on the vacuum adsorption stage of the transfer platform, and the indium selenide channel region is quickly located under a low-power microscope; then, the microscope is switched to high-power for further precise confirmation of the channel position. Next, the copper mesh mask with the applied high-temperature adhesive tape is mounted on a glass slide carrying double-sided adhesive and placed into the fixture of the transfer platform. The X, Y, and Z axis heights are adjusted using a three-axis precision displacement stage to gradually align the mask mesh region with the channel region. During this process, reference lines or marks can be drawn using microscope imaging software to improve alignment accuracy. Once the mask and channel are fully aligned within the microscope's field of view, the Z axis is slowly pressed down, allowing the mask to gradually contact and evenly cover the substrate surface. At this point, the edges of the high-temperature adhesive tape adhere tightly to the substrate, effectively fixing the mask and preventing displacement or lifting during subsequent metal deposition. If necessary, slight mechanical pressure can be applied after the mask comes into contact with the substrate to ensure that the mask and the substrate surface are in close contact, thereby obtaining an electrode pattern with clear boundaries and complete morphology.

[0026] S3: Source / drain electrode fabrication; Place the aligned sample from step C1, along with the fixed substrate, onto the sample holder of the thermal evaporation coating instrument and secure it with high-temperature tape. Place 2-3 high-purity gold particles (purity ≥99.99%) into the tungsten boat of the evaporation source, ensuring uniform distribution and good contact between the gold particles and the tungsten boat. Close the chamber and turn on the mechanical pump to evacuate. When the vacuum level reaches approximately 2.3 Pa or less, start the molecular pump to further evacuate until the vacuum level in the chamber stabilizes at 2 × 10⁻⁶ Pa. -4 ——4×10 -4 Within the Pa range, the evaporation current was gradually increased to slowly heat and melt the gold particles in the tungsten boat. During the deposition process, the deposition rate and thickness were monitored in real time using a quartz crystal film thickness monitor, and the deposition rate was controlled at 0.1-0.5 nm / s to ensure the uniformity and density of the film. Once the film thickness reached 40-50 nm, the current was reduced until the evaporation power supply was completely shut off. After deposition, the sample was cooled under vacuum for 5-10 minutes. After the sample temperature decreased, nitrogen or air was slowly introduced to atmospheric pressure, and the sample was removed. At this point, gold electrodes with a thickness of 40-50 nm were formed at both ends of the indium selenide channel, constructing a source-drain electrode pair. Electrical performance testing showed that the transistor prepared in this stage exhibited stable n-type characteristics, and the transfer curve showed a significant gate control effect.

[0027] S4: The prepared transistors were completely immersed in an acetone solution for 5 h and 10 h, respectively, while the treatment temperature was maintained at room temperature. As the acetone treatment time increased, the channel polarity gradually changed: after 5 h of immersion, obvious bipolar characteristics were observed, while after 10 h of immersion, it transformed into a stable p-type.

[0028] S5: Place the p-type transistor obtained in step 6 in a tube furnace and anneal it at 550K for 2 hours under vacuum. After annealing, the polarity of the indium selenide channel changes from p-type to n-type, completing one full reversible switching process.

[0029] The electrical tests on the above devices were performed using a Janis ST-500 vacuum probe station and a Keithley 4200-SCS semiconductor parameter analyzer. The results are as follows: Figure 2 The images show the initial transfer characteristic curves of the field-effect transistor in this embodiment of the invention before acetone treatment and the transfer characteristic curves after acetone solution treatment for 5 h and 10 h. Figure 3 The transistor, which was converted to p-type after 10 h of acetone treatment, was restored to n-type after vacuum annealing at 550 K for 2 h.

[0030] contrast Figure 2 and Figure 3 As can be seen, the field-effect transistor of the present invention can achieve stable and reversible polarity switching between n-type and p-type, and maintain good electrical performance and device stability during the polarity conversion process, which proves the superiority and feasibility of the method of the present invention in polarity control.

[0031] In summary, this invention constructs a PN polarity reversible field-effect transistor based on interface dipole engineering by systematically integrating solvent treatment and thermal annealing processes. Its fabrication method is simple to operate, has a clearly defined parameter window, is highly compatible with existing production lines, and maintains excellent electrical performance through multiple cycles. This technology not only solves the core challenge of polarity control in two-dimensional semiconductors but also provides a novel device implementation path for reconfigurable electronics, dynamic logic gates, and neuromorphic computing hardware. All process steps have been experimentally verified, and the technical details are fully disclosed, sufficient to support those skilled in the art to reproduce all the technical effects of this invention without inventive effort.

[0032] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A solvent-treated PN polarity reversible field-effect transistor, characterized in that, The transistor comprises a gate electrode, a dielectric layer, a channel layer, and source / drain electrodes. The gate electrode is a p-type heavily doped silicon substrate, the dielectric layer is a silicon dioxide thin film covering the surface of the gate electrode, the channel layer is composed of a few-layer indium selenide with a thickness of 5 to 80 nm, and the source / drain electrodes are formed of gold metal with a thickness of 40 to 50 nm and located at both ends of the channel layer. The transistor initially exhibits n-type conductivity, transforms to a p-type conductivity state after immersion in acetone solution, and then recovers to an n-type conductivity state after vacuum or inert atmosphere annealing, thus achieving completely reversible control of the carrier type.

2. The solvent-treated PN polarity reversible field-effect transistor according to claim 1, characterized in that, The acetone solution treatment temperature is 20-60 ℃, and the soaking time is 1-10 hours.

3. The solvent-treated PN polarity reversible field-effect transistor according to claim 1, characterized in that, The annealing process is carried out under vacuum or inert atmosphere, at an annealing temperature of 500 to 550 K, and for a holding time of 30 to 150 minutes.

4. The solvent-treated PN polarity reversible field-effect transistor according to claim 1, characterized in that, The transverse dimension of the channel layer is not less than 20 μm, and the edges are complete and the morphology is uniform.

5. A method for fabricating a field-effect transistor as described in any one of claims 1 to 4, characterized in that, Includes the following steps: S1: Provide a p-type heavily doped silicon substrate with a 300±10nm thick silicon dioxide layer on the surface, and perform ultrasonic cleaning and drying; S2: A few-layer indium selenide sheet with a thickness of 5 to 80 nm is obtained by mechanical peeling and transferred to the surface of the substrate by polydimethylsiloxane; S3: Using mask thermal evaporation to deposit metallic gold, source and drain electrodes with a thickness of 40 to 50 nm are formed at both ends of the indium selenide channel; S4: Immerse the entire component obtained in S3 in an acetone solution and treat it at 20 to 60°C for 1 to 10 hours to transform it from n-type to p-type; S5: Place the acetone-treated device in a vacuum or inert atmosphere and anneal it at 500 to 550 K for 30 to 150 minutes to restore it to the n-type.

6. The preparation method according to claim 5, characterized in that: In S1, the p-type heavily doped silicon substrate is cut into 0.5-2cm square substrates along the cleavage direction.

7. The preparation method according to claim 5, characterized in that: In S2, indium selenide flakes are transferred to the surface of polydimethylsiloxane after being repeatedly adhered and peeled off 2 to 3 times with blue film tape. Flakes with a length greater than 20 μm, intact edges and no cracks are selected under an optical microscope for use as channel materials.

8. The preparation method according to claim 5, characterized in that: In S3, the thermal evaporation coating is performed in a cavity with a vacuum level of 2×10⁻⁶. -4 Up to 4×10 -4 The deposition was carried out under Pa conditions, with gold deposition rates ranging from 0.1 to 0.5 nm / s.

9. The preparation method according to claim 5, characterized in that: In S4, the acetone solution is analytical grade acetone, and the entire component is completely immersed in the solution during the process.

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