Semiconductor device and method of forming

Abstract

This invention provides a semiconductor device and its formation method, comprising: providing a substrate, the substrate including opposing front and back sides; forming a CMOS device on a portion of the front side of the substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located on both sides of the gate within the substrate; forming a silicide barrier oxide layer on the front side of the substrate, the silicide barrier oxide layer simultaneously covering the CMOS device; forming a first nitride layer on the back side of the substrate, and simultaneously forming a second nitride layer on the silicide barrier oxide layer; sequentially removing a portion of the second nitride layer and a portion of the silicide barrier oxide layer, retaining the silicide barrier oxide layer and the second nitride layer on the gate and source / drain regions. The nitride layer formed by this invention restricts charge flow in the bottom region of the CMOS device, suppressing discharge phenomena caused by the potential difference between the front and back sides of the substrate. This reduces charge accumulation, thereby reducing threshold voltage drift and improving threshold voltage uniformity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming it. Background Technology

[0002] In semiconductor manufacturing processes, the growth of interlayer films typically employs plasma-enhanced chemical vapor deposition (PECVD). During the film formation process, when high-energy particles collide with the interlayer surface, charge accumulation may occur on the film surface, resulting in localized charge distribution. This localized charge accumulation leads to an increase in localized electric field strength, affecting the electron movement and electromagnetic properties of semiconductor devices; this is known as the charge accumulation problem.

[0003] As device feature sizes shrink, they become highly susceptible to charge accumulation effects during semiconductor manufacturing. For example, the threshold voltage (VT) of CMOS devices may drift and the uniformity of the threshold voltage may deteriorate, leading to device performance degradation or even a decrease in reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for forming it, which can reduce charge accumulation, thereby reducing threshold voltage drift, improving threshold voltage uniformity, and ultimately improving the reliability of device performance.

[0005] To achieve the above objectives, the present invention provides a method for forming a semiconductor device, comprising:

[0006] A substrate is provided, the substrate comprising opposing front and back sides;

[0007] A CMOS device is formed on the front side of a portion of a substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located on both sides of the gate within the substrate;

[0008] A silicide barrier oxide layer is formed on the front side of the substrate, and the silicide barrier oxide layer simultaneously covers the CMOS device;

[0009] A first nitride layer is formed on the back side of the substrate, and a second nitride layer is formed on the silicide barrier oxide layer;

[0010] Part of the second nitride layer and part of the silicide barrier oxide layer are removed sequentially, while the silicide barrier oxide layer and the second nitride layer on the gate and source / drain regions are retained.

[0011] Optionally, in the method for forming the semiconductor device, both the first nitride layer and the second nitride layer comprise Si3N4.

[0012] Optionally, in the method for forming the semiconductor device, the silicide barrier oxide layer comprises silicon dioxide.

[0013] Optionally, in the method for forming the semiconductor device, sequentially removing a portion of the second nitride layer and a portion of the silicide barrier oxide layer, while retaining the silicide barrier oxide layer and the second nitride layer on the gate and source / drain regions, includes:

[0014] A patterned photoresist layer is formed on the second nitride layer, and the patterned photoresist layer covers the second nitride layer on the gate and source / drain regions;

[0015] Sequentially remove the portion of the second nitride layer and the portion of the silicide barrier oxide layer that are not covered by the patterned photoresist layer, while retaining the silicide barrier oxide layer and the second nitride layer on the gate and source / drain regions;

[0016] Remove the patterned photoresist layer.

[0017] The present invention also provides a semiconductor device, comprising:

[0018] A substrate, the substrate comprising opposing front and back sides;

[0019] A CMOS device located on the front side of a portion of a substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located in the substrate on both sides of the gate;

[0020] Silicide barrier oxide layers located on the gate and source / drain regions;

[0021] A first nitride layer located on the back side of the substrate;

[0022] A second nitride layer located on the silicide barrier oxide layer.

[0023] The present invention also provides a method for forming a semiconductor device, comprising:

[0024] A substrate is provided, the substrate comprising opposing front and back sides;

[0025] A CMOS device is formed on the front side of a portion of a substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located on both sides of the gate within the substrate;

[0026] A silicide barrier oxide layer is formed on the front side of the substrate, and the silicide barrier oxide layer simultaneously covers the CMOS device;

[0027] A first nitride layer is formed on the back side of the substrate, and a second nitride layer is formed on the silicide barrier oxide layer;

[0028] Remove the second nitride layer to expose the silicide barrier oxide layer;

[0029] Part of the silicide barrier oxide layer is removed, while the silicide barrier oxide layer on the gate and source / drain regions is retained.

[0030] Optionally, in the method for forming the semiconductor device, both the first nitride layer and the second nitride layer comprise Si3N4.

[0031] Optionally, in the method for forming the semiconductor device, the silicide barrier oxide layer comprises silicon dioxide.

[0032] Optionally, in the method for forming the semiconductor device, removing part of the silicide barrier oxide layer while retaining the silicide barrier oxide layer on the gate and source / drain regions includes:

[0033] A patterned photoresist layer is formed on the silicide barrier oxide layer, and the patterned photoresist layer covers the silicide barrier oxide layer on the gate and source / drain regions;

[0034] Remove the portion of the silicide barrier oxide layer that is not covered by the patterned photoresist layer, while retaining the silicide barrier oxide layer on the gate and source / drain regions;

[0035] Remove the patterned photoresist layer.

[0036] The present invention also provides a semiconductor device, comprising:

[0037] A substrate, the substrate comprising opposing front and back sides;

[0038] A CMOS device located on the front side of a portion of a substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located in the substrate on both sides of the gate;

[0039] Silicide barrier oxide layers located on the gate and source / drain regions;

[0040] A first nitride layer located on the back side of the substrate.

[0041] In the semiconductor device and its formation method provided by this invention, a nitride layer is formed on the back side of the substrate. The nitride layer has good insulation properties, which restricts the flow of charge in the bottom region of the CMOS device, thereby suppressing the discharge phenomenon caused by the potential difference between the front and back sides of the substrate (silicon wafer). This reduces charge accumulation, thereby reducing threshold voltage drift, improving threshold voltage uniformity, and ultimately improving the reliability of device performance. Attached Figure Description

[0042] Figure 1 This is a flowchart of a method for forming a semiconductor device according to Embodiment 1 of the present invention;

[0043] Figures 2 to 4 This is a schematic diagram illustrating the formation process of the semiconductor device according to Embodiment 1 of the present invention;

[0044] Figure 5This is a flowchart of the method for forming a semiconductor device according to Embodiment 2 of the present invention;

[0045] Figures 6 to 9 This is a schematic diagram illustrating the formation process of the semiconductor device according to Embodiment 2 of the present invention;

[0046] In the figure: 101-substrate, 102-gate oxide, 103-gate, 104-sidewall, 105-source region, 106-drain region, 107-silicide barrier oxide, 108-first nitride layer, 109-second nitride layer, 110-shallow trench isolation structure, 201-substrate, 202-gate oxide, 203-gate, 204-sidewall, 205-source region, 206-drain region, 207-silicide barrier oxide, 208-first nitride layer, 209-second nitride layer, 210-shallow trench isolation structure. Detailed Implementation

[0047] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0048] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0049] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0050] Example 1

[0051] Please refer to Figure 1 Embodiment 1 of the present invention provides a method for forming a semiconductor device, comprising:

[0052] S11: Provides a substrate, which includes opposing front and back sides;

[0053] S12: A CMOS device is formed on the front side of a portion of the substrate. The CMOS device includes a gate located on the front side of the substrate and source / drain regions located on both sides of the gate within the substrate.

[0054] S13: A silicide barrier oxide layer is formed on the front side of the substrate, which simultaneously covers the CMOS device;

[0055] S14: A first nitride layer is formed on the back side of the substrate, and a second nitride layer is formed on the silicide barrier oxide layer.

[0056] S15: Sequentially remove part of the second nitride layer and part of the silicide barrier oxide layer, while retaining the silicide barrier oxide layer and the second nitride layer on the gate and source / drain regions.

[0057] Please refer to Figure 4 The semiconductor device formed includes: a substrate 101, which includes a front side and a back side; a CMOS device located on a portion of the front side of the substrate 101, the CMOS device including a gate 103 located on the front side of the substrate and source / drain regions (source region 105 and drain region 106) located on both sides of the gate 103 within the substrate; a silicide barrier oxide layer 107 located on the gate 103 and the source / drain regions; a first nitride layer 108 located on the back side of the substrate 101; and a second nitride layer 109 located on the silicide barrier oxide layer 107. Preferably, multiple CMOS devices can be formed on the front side of the substrate 101, separated from each other by a shallow trench isolation structure 110 within the substrate. The shallow trench isolation structure 110 can also divide the substrate 101 into N-wells and P-wells, on which CMOS devices are formed respectively.

[0058] The specific method is as follows:

[0059] Please refer to Figure 2 First, a substrate 101 is provided, on which a gate oxide layer 102 and a gate 103 are sequentially formed. Sidewalls 104 are formed on the substrate 101 on both sides of the gate 103. Source regions 105 and drain regions 106 are formed in the substrate 101 on both sides of the gate 103.

[0060] Next, please refer to Figure 3 A silicide barrier oxide layer 107 is formed on the entire front side of the substrate 101, and the silicide barrier oxide layer 107 simultaneously covers the CMOS device. A first nitride layer 108 and a second nitride layer 109 are simultaneously formed on the back side of the substrate 101 by a furnace tube growing method.

[0061] Please refer to Figure 4A patterned photoresist layer is formed on the second nitride layer 109, covering the second nitride layer on the gate and source / drain regions. The portion of the second nitride layer 109 not covered by the patterned photoresist layer and a portion of the silicide barrier oxide layer 107 are sequentially removed, leaving the silicide barrier oxide layer 107 and the second nitride layer 109 on the gate 103 and the source / drain regions. The patterned photoresist layer is then removed. Finally, the silicide barrier oxide layer 107 and the second nitride layer 109 on the gate 103, source region 105, and drain region 106 remain.

[0062] Example 2

[0063] Please refer to Figure 5 Embodiment 2 of the present invention provides a method for forming a semiconductor device, comprising:

[0064] S21: Provide a substrate, the substrate including opposing front and back sides;

[0065] S22: A CMOS device is formed on the front side of a portion of the substrate. The CMOS device includes a gate located on the front side of the substrate and source / drain regions located on both sides of the gate within the substrate.

[0066] S23: A silicide barrier oxide layer (SAB oxide layer) is formed on the front side of the substrate, and the silicide barrier oxide layer also covers the CMOS device;

[0067] S24: A first nitride layer is formed on the back side of the substrate, and a second nitride layer is formed on the silicide barrier oxide layer.

[0068] S25: Remove the second nitride layer to expose the silicide barrier oxide layer;

[0069] S26: Remove part of the silicide barrier oxide layer, while retaining the silicide barrier oxide layer on the gate and source / drain regions.

[0070] Please refer to Figure 9 The formed semiconductor device includes: a substrate 201, which includes a front side and a back side; a CMOS device located on a portion of the front side of the substrate 201, the CMOS device including a gate 203 located on the front side of the substrate 201 and source / drain regions (source region 205 and drain region 206) located on both sides of the gate 203 within the substrate; a silicide barrier oxide layer 207 located on the gate 203 and the source / drain regions; and a first nitride layer 208 located on the back side of the substrate 201. Preferably, multiple CMOS devices can be formed on the front side of the substrate 201, separated from each other by a shallow trench isolation structure 210 within the substrate. The shallow trench isolation structure 210 can also divide the substrate 201 into N-wells and P-wells, on which CMOS devices are formed respectively.

[0071] The specific method is as follows:

[0072] Please refer to Figure 6 First, a substrate 201 is provided, on which a gate oxide layer 202 and a gate 203 are sequentially formed. Sidewalls 204 are formed on the substrate 201 on both sides of the gate 203. Source regions 205 and drain regions 206 are formed in the substrate 201 on both sides of the gate 203.

[0073] Next, please refer to Figure 7 A silicide barrier oxide layer 207 is formed entirely on the front side of substrate 201, and the silicide barrier oxide layer 207 simultaneously covers the CMOS device. Please refer to... Figure 8 A first nitride layer 208 is formed on the back side of the substrate 201 and a second nitride layer 209 is formed on the silicide barrier oxide layer 207 by means of furnace tube growth.

[0074] Next, please refer to Figure 9 The second nitride layer 209 is removed to expose the silicide barrier oxide layer 207. A patterned photoresist layer is formed on the silicide barrier oxide layer 207, covering the silicide barrier oxide layer 207 on the gate 203, source region 205, and drain region 206. A portion of the silicide barrier oxide layer 207 not covered by the patterned photoresist layer is removed, leaving the silicide barrier oxide layer 207 on the gate 203 and the source / drain regions. The patterned photoresist layer is then removed. Finally, the silicide barrier oxide layer 207 on the gate 203, source region 205, and drain region 206 remains.

[0075] In summary, in the semiconductor device and formation method provided in the embodiments of the present invention, a nitride layer is formed on the back side of the substrate. The nitride layer has good insulation properties, which restricts the flow of charge in the bottom region of the CMOS device, thereby suppressing the discharge phenomenon caused by the potential difference between the front and back sides of the substrate (silicon wafer). This reduces charge accumulation, thereby reducing threshold voltage drift, improving threshold voltage uniformity, and ultimately improving the reliability of device performance.

[0076] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising opposing front and back sides; A CMOS device is formed on the front side of a portion of a substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located on both sides of the gate within the substrate; A silicide barrier oxide layer is formed on the front side of the substrate, and the silicide barrier oxide layer simultaneously covers the CMOS device; A first nitride layer is formed on the back side of the substrate, and a second nitride layer is formed on the silicide barrier oxide layer; Part of the second nitride layer and part of the silicide barrier oxide layer are removed sequentially, while the silicide barrier oxide layer and the second nitride layer on the gate and source / drain regions are retained.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, Both the first nitrided layer and the second nitrided layer comprise Si3N4.

3. The method for forming a semiconductor device as described in claim 1, characterized in that, The silicide barrier oxide layer includes silicon dioxide.

4. The method for forming a semiconductor device as described in claim 1, characterized in that, The process involves sequentially removing a portion of the second nitride layer and a portion of the silicide barrier oxide layer, while retaining the silicide barrier oxide layer and the second nitride layer on the gate and source / drain regions. A patterned photoresist layer is formed on the second nitride layer, and the patterned photoresist layer covers the second nitride layer on the gate and source / drain regions; Sequentially remove the portion of the second nitride layer and the portion of the silicide barrier oxide layer that are not covered by the patterned photoresist layer, while retaining the silicide barrier oxide layer and the second nitride layer on the gate and source / drain regions; Remove the patterned photoresist layer.

5. A semiconductor device formed using the semiconductor device formation method according to any one of claims 1 to 4, characterized in that, include: A substrate, the substrate comprising opposing front and back sides; A CMOS device located on the front side of a portion of a substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located in the substrate on both sides of the gate; Silicide barrier oxide layers located on the gate and source / drain regions; A first nitride layer located on the back side of the substrate; A second nitride layer located on the silicide barrier oxide layer.

6. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising opposing front and back sides; A CMOS device is formed on the front side of a portion of a substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located on both sides of the gate within the substrate; A silicide barrier oxide layer is formed on the front side of the substrate, and the silicide barrier oxide layer simultaneously covers the CMOS device; A first nitride layer is formed on the back side of the substrate, and a second nitride layer is formed on the silicide barrier oxide layer; Remove the second nitride layer to expose the silicide barrier oxide layer; Part of the silicide barrier oxide layer is removed, while the silicide barrier oxide layer on the gate and source / drain regions is retained.

7. The method for forming a semiconductor device as described in claim 6, characterized in that, Both the first nitrided layer and the second nitrided layer comprise Si3N4.

8. The method for forming a semiconductor device as described in claim 6, characterized in that, The silicide barrier oxide layer includes: Silicon dioxide.

9. The method for forming a semiconductor device as described in claim 6, characterized in that, Removing part of the silicide barrier oxide layer while retaining the silicide barrier oxide layer on the gate and source / drain regions includes: A patterned photoresist layer is formed on the silicide barrier oxide layer, and the patterned photoresist layer covers the silicide barrier oxide layer on the gate and source / drain regions; Remove the portion of the silicide barrier oxide layer that is not covered by the patterned photoresist layer, while retaining the silicide barrier oxide layer on the gate and source / drain regions; Remove the patterned photoresist layer.

10. A semiconductor device formed using the semiconductor device formation method according to any one of claims 6 to 9, characterized in that, include: A substrate, the substrate comprising opposing front and back sides; A CMOS device located on the front side of a portion of a substrate, the CMOS device including a gate located on the front side of the substrate and source / drain regions located in the substrate on both sides of the gate; Silicide barrier oxide layers located on the gate and source / drain regions; A first nitride layer located on the back side of the substrate.

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