Display device

Abstract

A display device includes: a display panel including a display area having a plurality of sub-pixels and a non-display area at the periphery of the display area; a storage capacitor and a first transistor in each of the plurality of sub-pixels; a data line configured to be adjacent to the gate electrode of the first transistor; and a shielding capacitor configured to overlap with the data line, wherein a first width of the shielding capacitor is greater than a second width of the gate electrode of the first transistor.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0196991, filed on December 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, and more specifically to a display device including a shielding capacitor. Background Technology

[0003] Recently, various flat panel display devices with excellent characteristics such as thin profile, light weight and low power consumption have been developed, such as liquid crystal display (LCD) devices, organic light-emitting diode (OLED) display devices and field emission display (FED) devices, and they have been applied in various fields.

[0004] Among various flat panel display devices, organic light-emitting diode (OLED) display devices are light-emitting devices that do not include backlight units used in non-light-emitting devices such as liquid crystal displays (LCDs). As a result, OLED display devices have advantages in terms of viewing angle, contrast ratio, and power consumption, making them suitable for a wide range of applications.

[0005] OLED display devices include pixel circuitry in each sub-pixel, and the pixel circuitry includes storage capacitors for driving light-emitting diodes. In OLED display devices, the voltage of the gate electrode of the driving transistor varies due to the coupling between the gate electrode of the driving transistor and the data line, causing degradation such as vertical crosstalk. Summary of the Invention

[0006] Therefore, this disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0007] More specifically, this disclosure provides a display device in which voltage variations at the gate electrode of the driving transistor are minimized and degradations such as vertical crosstalk are prevented by forming a shielding capacitor between a data line and a shielding pattern below the data line corresponding to the gate electrode of the driving transistor.

[0008] Furthermore, this disclosure provides a display device in which the coupling between the gate electrode of the driving transistor and the data line is minimized and degradation such as vertical crosstalk is prevented by forming a shielding pattern below the data line with a width greater than the width of the gate electrode of the driving transistor.

[0009] Additional features and advantages of this disclosure will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of this disclosure. These and other advantages of this disclosure will be realized and attained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0010] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel including a display area having a plurality of subpixels and a non-display area at the periphery of the display area; a storage capacitor and a first transistor in each of the plurality of subpixels; a data line configured to be adjacent to the gate electrode of the first transistor; and a shielding capacitor configured to overlap with the data line, wherein a first width of the shielding capacitor is greater than a second width of the gate electrode of the first transistor.

[0011] It should be understood that the foregoing general description and the following detailed description are interpretive and intended to provide further interpretation of the claimed disclosure. Attached Figure Description

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0013] In the attached diagram: Figure 1 This is a view showing a display device according to a first embodiment of the present disclosure; Figure 2 This is a circuit diagram showing a sub-pixel of a display device according to a first embodiment of the present disclosure; Figure 3 This is a plan view showing the first sub-pixel, the second sub-pixel, and the third sub-pixel of a display device according to a first embodiment of the present disclosure; Figure 4 It is along Figure 3 A cross-sectional view taken from line IV-IV'; Figure 5 This is a plan view showing the first sub-pixel, the second sub-pixel, and the third sub-pixel of a display device according to a second embodiment of the present disclosure; Figure 6 It is along Figure 5 A cross-sectional view taken from line VI-VI'; Figure 7 This is a circuit diagram showing the sub-pixels of a display device according to a third embodiment of the present disclosure; Figure 8This is a plan view showing the first sub-pixel, the second sub-pixel, and the third sub-pixel of a display device according to a third embodiment of the present disclosure; and Figure 9 It is along Figure 8 The cross-sectional view taken from line IX-IX'. Detailed Implementation

[0014] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following exemplary aspects described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary aspects are provided to make this disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0015] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe various exemplary aspects of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. Unless otherwise stated, the same reference numerals denote the same elements throughout the specification.

[0016] In the following description, where a detailed description of a known function or configuration may unnecessarily obscure a feature or aspect of this disclosure, a detailed description of such a known function or configuration may be omitted, or a brief description may be provided.

[0017] When using terms such as “including,” “having,” or “comprising,” one or more additional elements may be added, unless a term such as “only” is used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context explicitly indicates otherwise.

[0018] When interpreting components, even if no explicit description of the error or tolerance range is provided, the component will be interpreted as including such error or tolerance range.

[0019] When describing positional relationships, such as when using terms like "above," "on top," "below," "over," "beside," or "adjacent" to describe the positional relationship between two parts, one or more other parts may be located between these two parts, unless more restrictive terms such as "closely," "directly," or "tightly" are used. For example, when one element or layer is placed on top of another element or layer, a third layer or element may be inserted between them.

[0020] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to refer to various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0021] The term "at least one" should be understood to include all combinations of one or more of the related elements. For example, the term "at least one of the first element, the second element, and the third element" can include all combinations of two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0022] The term "display device" can include display devices in the narrow sense, such as liquid crystal modules (LCMs), organic light-emitting diode (OLED) modules, and quantum dot (QD) modules. A display device includes a display panel and driving units for driving the display panel. Furthermore, the term "display device" can include complete products (or end products) having LCMs, OLED modules, and QD modules, such as notebook computers, televisions, computer monitors, equipment display devices (including automotive display devices or display devices for equipment other than vehicles), and assemblies of electronic equipment or assemblies (or complete sets of equipment), such as smartphones or tablet computers.

[0023] Therefore, the display devices disclosed herein may include application products or complete sets of end-user devices (including LCM, OLED modules and QD modules), as well as display devices in the narrow sense, such as LCM, OLED modules and QD modules.

[0024] Depending on the context, LCM, OLED, and QD modules having display panels and driving units can be described as "display devices," and electronic devices comprising complete products including LCM, OLED, and QD modules can be described as "assemblies." For example, a display device in a narrow sense may include a liquid crystal display panel, organic light-emitting diodes and quantum dots, and a source printed circuit board (PCB) for a control unit to drive the display panel, and an assembly may also include an assembly PCB electrically connected to an assembly control unit for controlling the entire assembly.

[0025] The display panel disclosed herein can include all types of display panels, such as liquid crystal display panels, organic light-emitting diode (OLED) display panels, quantum dot display panels, and electroluminescent display panels. The display panel disclosed herein is not limited to a specific display panel having a curved frame with a flexible substrate for an OLED display panel and a lower backplate support. The shape or size of the display panel of the display device disclosed herein is not limited thereto.

[0026] For example, when the display panel is an organic light-emitting diode (OLED) display panel, the display panel may include multiple gate lines, multiple data lines, and sub-pixels in the intersection regions of the multiple gate lines and multiple data lines. The display panel may include an array (the array having thin-film transistors with elements for selectively applying voltage to each sub-pixel), an emitter layer on the array, and an encapsulation substrate or encapsulation portion covering the emitter layer. The encapsulation portion can protect the thin-film transistors and emitter layer from external impacts and can prevent or at least reduce the penetration of moisture or oxygen into the emitter layer. Furthermore, the emitter layer on the array may include an inorganic light-emitting layer, such as a nanoscale material layer or quantum dots.

[0027] The thin-film transistors disclosed herein may include one of oxide thin-film transistors, amorphous silicon thin-film transistors, and low-temperature polycrystalline silicon thin-film transistors.

[0028] Features of the various embodiments of this disclosure may be combined or integrated with each other, either partially or entirely. As will be fully appreciated by those skilled in the art, they may be technically associated and operable in various ways. These aspects may be implemented independently of each other or in combination with each other.

[0029] In the following, a display device according to various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, wherein the influence on the oxide semiconductor layer of the thin-film transistor in the driving element portion is reduced by shielding light emitted and transmitted from the sub-pixels and / or light input from the outside.

[0030] Figure 1 This is a view illustrating a display device according to a first embodiment of the present disclosure. While the display device may be an organic light-emitting diode (OLED) display device, it is not limited thereto. For example, the display device may be a quantum dot display device, a micro light-emitting diode (LED) display device, or a miniature light-emitting diode (LED) display device.

[0031] exist Figure 1 In the first embodiment of the present disclosure, the display device 110 includes a timing control unit 120 (e.g., a circuit), a data driving unit 122 (e.g., a circuit), a first gate driving unit 124 (e.g., a circuit), a second gate driving unit 126 (e.g., a circuit), and a display panel 128.

[0032] The timing control unit 120 uses the image signal IS and multiple timing signals to generate image data RGB, data control signal DCS, and gate control signal GCS. The multiple timing signals include a data enable signal DE, a horizontal synchronization signal HSY, a vertical synchronization signal VSY, and a clock signal CLK sent from an external system such as a graphics card or a television system.

[0033] The timing control unit 120 sends the image data RGB and the data control signal DCS to the data driving unit 122, and sends the gate control signal GCS to the first gate driving unit 124 and the second gate driving unit 126.

[0034] Data drive unit 122 uses image data RGB and data control signal DCS sent from timing control unit 120 to generate data signal (data voltage) Vda. Figure 2 The data signal Vda is applied to the data line DL of the display panel 128.

[0035] The first gate driving unit 124 and the second gate driving unit 126 use the gate control signal GCS sent from the timing control unit 120 to generate gate signals (gate voltages) Sc1, Sc2 and Em. Figure 2 The gate signals Sc1, Sc2 and Em are applied to the gate line GL of the display panel 128.

[0036] The first gate driving unit 124 and the second gate driving unit 126 may have a gate in panel (GIP) type to be formed in the non-display area NDA of the substrate of the display panel 128 having gate lines GL, data lines DL and pixels P.

[0037] Despite Figure 1 In the first embodiment, the first gate driving unit 124 and the second gate driving unit 126 are disposed in two sides of the display panel 128. However, in another embodiment, only one gate driving unit may be disposed, wherein the gate driving unit may be disposed in one side of the display panel 128.

[0038] Display panel 128 includes a display area DA at its center and a non-display area NDA surrounding the display area DA. Display panel 128 uses gate signals Sc1, Sc2, and Em, as well as a data signal Vda, to display images. To display images, display panel 128 includes multiple pixels P, multiple gate lines GL, and multiple data lines DL in the display area DA.

[0039] Each of the plurality of pixels P includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. A gate line GL and a data line DL intersect each other to define the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 is connected to the gate line GL and the data line DL.

[0040] For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can correspond to red, green, and blue, respectively.

[0041] Despite Figure 1 In a first embodiment, a pixel P exemplarily includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, in another embodiment, a pixel P may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel (not shown) corresponding to red, green, blue, and white, respectively.

[0042] When the display device 110 is an organic light-emitting diode (OLED) display device, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include multiple transistors, such as ( Figure 2 The switching transistor T6 and ( Figure 2 The driving transistor T1, Figure 2 Storage capacitor Cs, ( Figure 2 The shielding capacitor Cb and ( Figure 2 (The light-emitting diode De)

[0043] Figure 2 This is a circuit diagram illustrating a sub-pixel of a display device according to a first embodiment of the present disclosure.

[0044] exist Figure 2 In the first embodiment of the present disclosure, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the display panel 128 of the display device 110 includes a first transistor T1 to a sixth transistor T6, a storage capacitor Cs, a shielding capacitor Cb, and a light-emitting diode De.

[0045] Although each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 is in Figure 2 In the first embodiment, a 6T1C structure (with six transistors and a capacitor) is used, but in another embodiment, a sub-pixel may have one of a 3T1C structure (with three transistors and a capacitor), a 7T1C structure (with seven transistors and a capacitor), or an 8T1C structure (with eight transistors and a capacitor).

[0046] Despite Figure 2 In the first embodiment, the first transistor T1 to the sixth transistor T6 have positive types (i.e., p-type transistors), but in another embodiment, at least one of the first transistor T1 to the sixth transistor T6 may have negative types (i.e., n-type transistors).

[0047] At least one of the first transistors T1 to the sixth transistor T6 may be an oxide semiconductor thin film transistor, and the other transistors among the first transistors T1 to the sixth transistor T6 may be low-temperature polycrystalline silicon thin film transistors.

[0048] The first transistor T1, acting as the driving transistor, switches according to the voltage of the first node N1. The gate electrode of the first transistor T1 is connected to the first node N1, the source electrode of the first transistor T1 is connected to the high-level signal (high-level voltage) Vdd, and the drain electrode of the first transistor T1 is connected to the second node N2.

[0049] Despite Figure 2 In a first embodiment, the first transistor T1 exemplarily has a dual-gate type comprising two gate electrodes and two channel regions separated from each other in a plan view, but in another embodiment, the first transistor T1 may have a single-gate type comprising one gate electrode and one channel region.

[0050] The second transistor T2, which acts as the emitter transistor, is switched according to the emitter signal Em. The gate electrode of the second transistor T2 is connected to the emitter signal Em, the source electrode of the second transistor T2 is connected to the second node N2, and the drain electrode of the second transistor T2 is connected to the fourth node N4.

[0051] The third transistor T3, which acts as a sensing transistor, is switched according to the scan signal Sc2. The gate electrode of the third transistor T3 is connected to the scan signal Sc2, the source electrode of the third transistor T3 is connected to the second node N2, and the drain electrode of the third transistor T3 is connected to the first node N1.

[0052] Despite Figure 2 In the first embodiment, the third transistor T3 exemplarily has a dual-gate type comprising two gate electrodes and two channel regions separated from each other in a plan view, but the third transistor T3 may have a single-gate type comprising one gate electrode and one channel region.

[0053] The fourth transistor T4 is switched according to the scan signal Sc2. The gate electrode of the fourth transistor T4 is connected to the scan signal Sc2, the source electrode of the fourth transistor T4 is connected to the fourth node N4, and the drain electrode of the fourth transistor T4 is connected to the reference signal (reference voltage) Vrf.

[0054] The fifth transistor T5 is switched according to the emit signal Em. The gate electrode of the fifth transistor T5 is connected to the emit signal Em, the source electrode of the fifth transistor T5 is connected to the third node N3, and the drain electrode of the fifth transistor T5 is connected to the reference signal Vrf.

[0055] The sixth transistor T6, acting as a switching transistor, is switched according to the scan signal Sc1. The gate electrode of the sixth transistor T6 is connected to the scan signal Sc1, the source electrode of the sixth transistor T6 is connected to the third node N3, and the drain electrode of the sixth transistor T6 is connected to the data signal Vda.

[0056] The storage capacitor Cs stores the data signal Vda and the threshold voltage (Vth) of the first transistor T1. The first capacitor electrode of the storage capacitor Cs is connected to the first node N1, and the second capacitor electrode of the storage capacitor Cs is connected to the third node N3.

[0057] The shielding capacitor Cb reduces the coupling between the data line DL and the first node N1. The first capacitor electrode of the shielding capacitor Cb is connected to the high-level signal Vdd, and the second capacitor electrode of the shielding capacitor Cb is connected to the data signal Vda.

[0058] The light-emitting diode De is connected between the fourth node N4 and the low-level signal (low-level voltage) Vss, and emits light with a brightness proportional to the current of the first transistor T1. The anode of the light-emitting diode De is connected to the fourth node N4, and the cathode of the light-emitting diode De is connected to the low-level signal Vss.

[0059] The gate electrode of the first transistor T1, the first capacitor electrode of the storage capacitor Cs, and the drain electrode of the third transistor T3 constitute the first node N1, and the drain electrode of the first transistor T1, the source electrode of the second transistor T2, and the source electrode of the third transistor T3 constitute the second node N2. The second capacitor electrode of the storage capacitor Cs, the source electrode of the fifth transistor T5, and the source electrode of the sixth transistor T6 constitute the third node N3, and the drain electrode of the second transistor T2, the source electrode of the fourth transistor T4, and the anode of the light-emitting diode De constitute the fourth node N4.

[0060] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the display device 110 according to the first embodiment of the present disclosure is driven by an initialization time period, a sampling time period, a holding time period, and an emission time period.

[0061] During the initialization period, transistors T2, T3, T4, and T5 are turned on due to the low-voltage scan signal Sc2 and the transmit signal Em, and transistor T6 is turned off due to the high-voltage scan signal Sc1. Since the reference signal Vrf is applied to nodes N1, N2, N3, and N4, transistor T1 is turned off, and the first and second capacitor electrodes of the storage capacitor Cs, the gate electrode of the first transistor T1, and the anode of the light-emitting diode De are initialized by the reference signal Vrf.

[0062] During the sampling period, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned on due to the low logic voltage scan signals Sc1 and Sc2, and the second transistor T2 and the fifth transistor T5 are turned off due to the high logic voltage emitt signal Em. Since the data signal Vda is applied to the third node N3 and the reference signal Vrf is applied to the fourth node N4, the first transistor T1 is turned on, and the second capacitor electrode of the storage capacitor Cs has the data signal Vda. As a result, the first capacitor electrode of the storage capacitor Cs has a high-level signal Vdd and a threshold voltage Vth (Vdd + Vth). Therefore, the threshold voltage Vth is stored in the storage capacitor Cs, and the anode of the light-emitting diode De is held at the reference signal Vrf.

[0063] During the hold period, due to the high logic voltages of the scan signals Sc1 and Sc2 and the transmit signal Em, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. As a result, the second capacitor electrode of the storage capacitor Cs remains at the data signal Vda, and the first capacitor electrode of the storage capacitor Cs remains at the sum of the high-level signal Vdd and the threshold voltage Vth (Vdd + Vth). Therefore, the threshold voltage Vth remains stored in the storage capacitor Cs, and the anode of the light-emitting diode De remains at the reference signal Vrf.

[0064] During the transmission period, transistors T2 and T5 are turned on due to the low logic voltage transmit signal Em, and transistors T3, T4, and T6 are turned off due to the high logic voltage scan signals Sc1 and Sc2. As a result, the reference signal Vrf is applied to the third node N3, and the voltage of the first node N1 becomes the sum of the values ​​(Vdd + Vth) and (Vrf - Vda) (Vdd + Vth + Vrf - Vda), where the value (Vdd + Vth) is obtained by adding the threshold voltage (Vth) to the high-level signal Vdd, and the value (Vrf - Vda) is obtained by subtracting the data signal Vda from the reference signal Vrf. Therefore, current flows through the first transistor T1, wherein the current is proportional to the square of the value obtained by subtracting the threshold voltage (Vth) from the gate-source voltage (Vgs=(Vdd+Vth+Vrf-Vda)-Vdd=Vth+Vrf-Vda), and the light-emitting diode De emits light with a brightness corresponding to the current flowing through the first transistor T1.

[0065] The planar and cross-sectional structures of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the display device 110 will be described with reference to the accompanying drawings.

[0066] Figure 3 This is a plan view illustrating the first sub-pixel, second sub-pixel, and third sub-pixel of a display device according to a first embodiment of the present disclosure, and Figure 4 It is along Figure 3 The cross-sectional view taken from line IV-IV'.

[0067] exist Figure 3 In the first embodiment of the display device 110 according to the present disclosure, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes a gate line GL, a data line DL, a reference line RL, and a power line PL. The gate line GL for transmitting the scan signal Sc2, the gate line GL for transmitting the transmit signal Em, the gate line GL for transmitting the scan signal Sc2, and the gate line GL for transmitting the scan signal Sc1 are arranged sequentially along the horizontal direction. The data line DL for transmitting the data signal Vda, the reference line RL for transmitting the reference signal Vrf, and the power line PL for transmitting the high-level signal Vdd are arranged sequentially along the vertical direction.

[0068] The first transistor T1 is connected to the power supply line PL for transmitting a high-level signal, and the second transistor T2 is connected to the gate line GL for transmitting the transmit signal Em. The third transistor T3 is connected to the gate line GL for transmitting the scan signal Sc2, and the fourth transistor T4 is connected to the gate line GL for transmitting the scan signal Sc2 and the reference line RL for transmitting the reference signal Vrf. The fifth transistor T5 is connected to the gate line GL for transmitting the transmit signal Em and the reference line RL for transmitting the reference signal Vrf, and the sixth transistor T6 is connected to the gate line GL for transmitting the scan signal Sc1 and the data line DL for transmitting the data signal Vda.

[0069] ( Figure 4 The metal pattern 144 is set in the first transistor T1. Figure 4 The gate electrode 140 of the first transistor T1 and the metal pattern 144 form a storage capacitor Cs.

[0070] From the first transistor T1 ( Figure 4 The source region of semiconductor layer 134 extends ( Figure 4 The shielding pattern 136 is disposed below the data line DL adjacent to the first transistor T1, and the shielding pattern 136 and the data line DL constitute the shielding capacitor Cb.

[0071] Because the shielding pattern 136 is positioned closer to the data line DL than the gate electrode 140 of the first transistor T1, most of the electric field lines of the data line DL will not reach the gate electrode 140 of the first transistor T1, but will instead reach the shielding pattern 136. As a result, the coupling (or parasitic capacitance) between the data line DL and the gate electrode 140 of the first transistor T1 (i.e., the first node N1) is reduced, the voltage variation of the gate electrode 140 of the first transistor T1 is minimized, and degradation such as vertical crosstalk is prevented.

[0072] Therefore, the shielding pattern 136 is formed to correspond to the entire end of the gate electrode 140 of the adjacent first transistor T1.

[0073] For example, the first width w1 of the shielding pattern 136 can be greater than the second width w2 of the gate electrode 140 of the first transistor T1.

[0074] exist Figure 4 In the process, a buffer layer 132 is disposed on the entire substrate 130, and a semiconductor layer 134 and a shielding pattern 136 are disposed on the buffer layer 132.

[0075] The buffer layer 132 prevents moisture or oxygen from penetrating from the outside. For example, the buffer layer 132 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0076] Semiconductor layer 134 includes a channel region at its central portion that is undoped, and source and drain regions at the two side portions of the channel region that are doped. For example, semiconductor layer 134 may include a polycrystalline semiconductor material, such as polycrystalline silicon, or an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0077] The shielding pattern 136 extends from the source region of the semiconductor layer 134 and is doped with impurities. For example, the shielding pattern 136 may include a polycrystalline semiconductor material, such as polycrystalline silicon, or an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0078] A gate insulating layer 138 is disposed over the entire substrate 130 on the semiconductor layer 134 and the shielding pattern 136, and a gate electrode 140 is disposed on the gate insulating layer 138 corresponding to the channel region of the semiconductor layer 134.

[0079] For example, the gate insulating layer 138 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0080] For example, the gate electrode 140 may have a single layer or multiple layers of metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0081] The semiconductor layer 134, the gate insulating layer 138, and the gate electrode 140 constitute the first transistor T1.

[0082] Despite Figure 3 and Figure 4 In a first embodiment, the first transistor T1 exemplarily has a dual-gate type comprising two gate electrodes and two channel regions separated from each other in a plan view, but in another embodiment, the first transistor T1 may have a single-gate type comprising one gate electrode and one channel region.

[0083] The first interlayer insulating layer 142 is disposed on the gate electrode 140 over the entire substrate 130, and the metal pattern 144 is disposed on the first interlayer insulating layer 142 corresponding to the gate electrode 140.

[0084] For example, the first interlayer insulating layer 142 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0085] For example, the metal pattern 144 may have a single layer or multiple layers of metal materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0086] The gate electrode 140, the first interlayer insulating layer 142, and the metal pattern 144 constitute the storage capacitor Cs, and the gate electrode 140 and the metal pattern 144 serve as the first capacitor electrode and the second capacitor electrode of the storage capacitor Cs, respectively.

[0087] The second interlayer insulating layer 146 is disposed on the metal pattern 144 over the entire substrate 130, and the source electrode 148, the drain electrode 150 and the data line DL are disposed on the second interlayer insulating layer 146.

[0088] For example, the second interlayer insulation layer 146 may have a single or multiple inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0089] The source electrode 148 and the drain electrode 150 are connected to the source region and the drain region of the semiconductor layer 134 through contact holes in the second interlayer insulating layer 146, the first interlayer insulating layer 142 and the gate insulating layer 138, respectively.

[0090] The data cable DL is set to overlap with shielding pattern 136.

[0091] For example, the source electrode 148, the drain electrode 150, and the data line DL can be made of single-layer or multi-layer metallic materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0092] The shielding pattern 136, the gate insulating layer 138, the first interlayer insulating layer 142, the second interlayer insulating layer 146 and the data line DL constitute the shielded capacitor Cb, and the shielding pattern 136 and the data line DL are respectively used as the first capacitor electrode and the second capacitor electrode of the shielded capacitor Cb.

[0093] The planarization layer 152 is disposed over the entire substrate 130 on the source electrode 148, the drain electrode 150 and the data line DL, and the first electrode 154 is disposed on the planarization layer 152.

[0094] For example, the planarization layer 152 may have a single or multiple layers of organic insulating material, such as photoacryl and benzocyclobutene (BCB).

[0095] The first electrode 154 can be connected to the drain region of the second transistor T2 or the source region of the fourth transistor T4 through the contact hole in the planarization layer 152.

[0096] For example, the first electrode 154 may be an anode and may have a single or multiple layers of transparent conductive material, such as indium tin oxide (ITO) and indium zinc oxide (IZO), or a single or multiple layers of opaque metallic material, such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) and their alloys.

[0097] The dam layer 156 is disposed on the first electrode 154, and the spacer 158 is disposed on the dam layer 156.

[0098] The embankment 156 covers the edge portion of the first electrode 154 and has an opening that exposes the central portion of the first electrode 154.

[0099] For example, the dam layer 156 may have a single or multiple layers of organic insulating materials, such as photopropylene materials and benzocyclobutene (BCB).

[0100] For example, spacer 158 may have a single layer or multiple layers of organic insulating material, such as photopropylene and benzocyclobutene (BCB).

[0101] The emitter layer 160 may be disposed on the first electrode 154 exposed through the opening of the dam layer 156, and the second electrode 162 may be disposed on the emitter layer 160 over the entire substrate 130.

[0102] The emitter layer 160 may include a hole auxiliary layer (e.g., a hole injection layer and a hole transport layer), an emitter material layer, and an electron auxiliary layer (e.g., an electron transport layer and an electron injection layer).

[0103] For example, the second electrode 162 can be a cathode and can have a single or multiple transparent conductive material, such as indium tin oxide (ITO) and indium zinc oxide (IZO), or a single or multiple semi-transparent material or opaque metallic material, such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), molybdenum (Mo), titanium (Ti) and their alloys.

[0104] The first electrode 154, the emitting layer 160, and the second electrode 162 constitute a light-emitting diode De.

[0105] Although not shown, an encapsulation layer may be disposed over the entire substrate 130 on the second electrode 162. For example, the encapsulation layer may include a first encapsulation layer and a third encapsulation layer having a single or multiple layers of inorganic insulating materials (such as silicon oxide (SiO2) and silicon nitride (SiNx)), and a second encapsulation layer located between the first and third encapsulation layers and including an organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin).

[0106] The touch layer used for sensing touch can be placed on the encapsulation layer.

[0107] In the display device 110 according to the first embodiment of the present disclosure, a shielding pattern 136 extending from the source region of the semiconductor layer 134 of the first transistor T1 is disposed below the data line DL adjacent to the gate electrode 140 of the first transistor T1 to form a shielding capacitor Cb having the shielding pattern 136 and the data line DL. As a result, the coupling (or parasitic capacitance) between the data line DL and the gate electrode 140 of the first transistor T1 (between the data line DL and the first node N1) is reduced, the voltage variation of the gate electrode 140 of the first transistor T1 is minimized, and degradation such as vertical crosstalk is prevented.

[0108] In another embodiment, the shielding pattern may be connected to the power cord.

[0109] Figure 5 This is a plan view illustrating the first sub-pixel, the second sub-pixel, and the third sub-pixel of a display device according to a second embodiment of the present disclosure, and Figure 6 It is along Figure 5 The cross-sectional view taken from line VI-VI'.

[0110] exist Figure 5 In the display device according to the second embodiment of the present disclosure, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes a gate line GL, a data line DL, a reference line RL, and a power line PL. The gate line GL for transmitting the scan signal Sc2, the gate line GL for transmitting the transmit signal Em, the gate line GL for transmitting the scan signal Sc2, and the gate line GL for transmitting the scan signal Sc1 are arranged sequentially along the horizontal direction. The data line DL for transmitting the data signal Vda, the reference line RL for transmitting the reference signal Vrf, and the power line PL for transmitting the high-level signal Vdd are arranged sequentially along the vertical direction.

[0111] The first transistor T1 is connected to the power supply line PL for transmitting a high-level signal, and the second transistor T2 is connected to the gate line GL for transmitting the transmit signal Em. The third transistor T3 is connected to the gate line GL for transmitting the scan signal Sc2, and the fourth transistor T4 is connected to the gate line GL for transmitting the scan signal Sc2 and the reference line RL for transmitting the reference signal Vrf. The fifth transistor T5 is connected to the gate line GL for transmitting the transmit signal Em and the reference line RL for transmitting the reference signal Vrf, and the sixth transistor T6 is connected to the gate line GL for transmitting the scan signal Sc1 and the data line DL for transmitting the data signal Vda.

[0112] ( Figure 6 The metal pattern 244 is set in the first transistor T1. Figure 6 The gate electrode 240 of the first transistor T1 and the metal pattern 244 form a storage capacitor Cs.

[0113] Connected to power cord PL ( Figure 6 The shielding pattern 236 is disposed below the data line DL adjacent to the first transistor T1, and the shielding pattern 236 and the data line DL constitute the shielding capacitor Cb.

[0114] Because the shielding pattern 236 is positioned closer to the data line DL than the gate electrode 240 of the first transistor T1, most of the electric field lines of the data line DL do not reach the gate electrode 240 of the first transistor T1, but instead reach the shielding pattern 236. As a result, the coupling (or parasitic capacitance) between the data line DL and the gate electrode 240 of the first transistor T1 (i.e., the first node N1) is reduced, the voltage variation of the gate electrode 240 of the first transistor T1 is minimized, and degradation such as vertical crosstalk is prevented.

[0115] Therefore, the shielding pattern 236 is formed to correspond to the entire end of the gate electrode 240 of the adjacent first transistor T1.

[0116] For example, the first width w1 of the shielding pattern 236 can be greater than the second width w2 of the gate electrode 240 of the first transistor T1.

[0117] exist Figure 6 In the process, a buffer layer 232 is disposed on the entire substrate 230, and a semiconductor layer 234 and a shielding pattern 236 are disposed on the buffer layer 232.

[0118] The buffer layer 232 prevents moisture or oxygen from penetrating from the outside. For example, the buffer layer 232 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0119] Semiconductor layer 234 includes a channel region at its central portion that is undoped, and source and drain regions at the two side portions of the channel region that are doped. For example, semiconductor layer 234 may include polycrystalline semiconductor materials, such as polycrystalline silicon, or oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0120] The shielding pattern 236 is separated from the semiconductor layer 234 and is doped with impurities. For example, the shielding pattern 236 may include a polycrystalline semiconductor material, such as polycrystalline silicon, or an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0121] A gate insulating layer 238 is disposed over the entire substrate 230 on the semiconductor layer 234 and the shielding pattern 236, and a gate electrode 240 is disposed on the gate insulating layer 238 corresponding to the channel region of the semiconductor layer 234.

[0122] For example, the gate insulating layer 238 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0123] For example, the gate electrode 240 may have a single layer or multiple layers of metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0124] The semiconductor layer 234, the gate insulating layer 238, and the gate electrode 240 constitute the first transistor T1.

[0125] Despite Figure 5 and Figure 6 In a second embodiment, the first transistor T1 exemplarily has a dual-gate type comprising two gate electrodes and two channel regions separated from each other in a plan view, but in another embodiment, the first transistor T1 may have a single-gate type comprising one gate electrode and one channel region.

[0126] The first interlayer insulating layer 242 is disposed on the gate electrode 240 over the entire substrate 230, and the metal pattern 244 is disposed on the first interlayer insulating layer 242 corresponding to the gate electrode 240.

[0127] For example, the first interlayer insulating layer 242 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0128] For example, the metal pattern 244 may have a single layer or multiple layers of metal materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0129] The gate electrode 240, the first interlayer insulating layer 242, and the metal pattern 244 constitute the storage capacitor Cs, and the gate electrode 240 and the metal pattern 244 serve as the first capacitor electrode and the second capacitor electrode of the storage capacitor Cs, respectively.

[0130] The second interlayer insulating layer 246 is disposed on the metal pattern 244 over the entire substrate 230, and the source electrode 248, drain electrode 250, data line DL and power line PL are disposed on the second interlayer insulating layer 246.

[0131] For example, the second interlayer insulation layer 246 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0132] The source electrode 248 and the drain electrode 250 are connected to the source region and the drain region of the semiconductor layer 234, respectively, through contact holes in the second interlayer insulating layer 246, the first interlayer insulating layer 242 and the gate insulating layer 238.

[0133] The data cable DL is set to overlap with the shielding pattern 236.

[0134] The power line PL is connected to the shielding pattern 236 through contact holes in the second interlayer insulation layer 246, the first interlayer insulation layer 242, and the gate insulation layer 238.

[0135] For example, the source electrode 248, drain electrode 250, data line DL, and power line PL can have single or multiple layers of metallic materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0136] The shielding pattern 236, the gate insulating layer 238, the first interlayer insulating layer 242, the second interlayer insulating layer 246 and the data line DL constitute the shielded capacitor Cb, and the shielding pattern 236 and the data line DL are respectively used as the first capacitor electrode and the second capacitor electrode of the shielded capacitor Cb.

[0137] The planarization layer 252 is disposed on the source electrode 248, drain electrode 250, data line DL and power line PL above the entire substrate 230, and the first electrode 254 is disposed on the planarization layer 252.

[0138] For example, the planarization layer 252 may have a single or multiple layers of organic insulating material, such as photopropylene materials and benzocyclobutene (BCB).

[0139] The first electrode 254 can be connected to the drain region of the second transistor T2 or the source region of the fourth transistor T4 through the contact hole in the planarization layer 252.

[0140] For example, the first electrode 254 can be an anode and can have a single or multiple layers of transparent conductive material, such as indium tin oxide (ITO) and indium zinc oxide (IZO), or a single or multiple layers of opaque metallic material, such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) and their alloys.

[0141] The dam layer 256 is disposed on the first electrode 254, and the spacer 258 is disposed on the dam layer 256.

[0142] The embankment 256 covers the edge portion of the first electrode 254 and has an opening that exposes the central portion of the first electrode 254.

[0143] For example, the dam layer 256 can have a single or multiple layers of organic insulating materials, such as photopropylene materials and benzocyclobutene (BCB).

[0144] For example, spacer 258 may have a single layer or multiple layers of organic insulating material, such as photopropylene materials and benzocyclobutene (BCB).

[0145] The emitter layer 260 may be disposed on the first electrode 254 exposed through the opening of the dam layer 256, and the second electrode 262 may be disposed on the emitter layer 260 over the entire substrate 230.

[0146] The emission layer 260 may include a hole auxiliary layer (e.g., a hole injection layer and a hole transport layer), an emission material layer, and an electron auxiliary layer (e.g., an electron transport layer and an electron injection layer).

[0147] For example, the second electrode 262 can be a cathode and can have a single or multiple layers of transparent conductive material, such as indium tin oxide (ITO) and indium zinc oxide (IZO), or a single or multiple layers of semi-transparent material or opaque metallic material, such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), molybdenum (Mo), titanium (Ti) and their alloys.

[0148] The first electrode 254, the emitting layer 260, and the second electrode 262 constitute a light-emitting diode De.

[0149] Although not shown, an encapsulation layer may be disposed over the entire substrate 230 on the second electrode 262. For example, the encapsulation layer may include a first encapsulation layer and a third encapsulation layer having a single or multiple layers of inorganic insulating materials (such as silicon oxide (SiO2) and silicon nitride (SiNx)), and a second encapsulation layer located between the first and third encapsulation layers and including an organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin).

[0150] The touch layer used for sensing touch can be placed on the encapsulation layer.

[0151] In the display device according to the second embodiment of this disclosure, a shielding pattern 236 connected to the power line PL is disposed below the data line DL adjacent to the gate electrode 240 of the first transistor T1 to form a shielded capacitor Cb having the shielding pattern 236 and the data line DL. As a result, the coupling (or parasitic capacitance) between the data line DL and the gate electrode 240 of the first transistor T1 (between the data line DL and the first node N1) is reduced, the voltage variation of the gate electrode 240 of the first transistor T1 is minimized, and degradation such as vertical crosstalk is prevented.

[0152] In another embodiment, the shielding pattern can extend from the drain region of the semiconductor layer.

[0153] Figure 7 This is a circuit diagram illustrating the sub-pixels of a display device according to a third embodiment of the present disclosure. Figure 8 This is a plan view showing the first sub-pixel, the second sub-pixel, and the third sub-pixel of a display device according to a third embodiment of the present disclosure, and Figure 9 It is along Figure 8 A cross-sectional view taken from line IX-IX'. Descriptions of portions identical to those in the first and second embodiments will be omitted.

[0154] exist Figure 7 In the third embodiment of the present disclosure, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the display device includes a first transistor T1 to a sixth transistor T6, a storage capacitor Cs, a shielding capacitor Cb, and a light-emitting diode De.

[0155] The first transistor T1, acting as the driving transistor, switches according to the voltage of the first node N1. The gate electrode of the first transistor T1 is connected to the first node N1, the source electrode of the first transistor T1 is connected to the high-level signal (high-level voltage) Vdd, and the drain electrode of the first transistor T1 is connected to the second node N2.

[0156] The second transistor T2, which acts as the emitter transistor, is switched according to the emitter signal Em. The gate electrode of the second transistor T2 is connected to the emitter signal Em, the source electrode of the second transistor T2 is connected to the second node N2, and the drain electrode of the second transistor T2 is connected to the fourth node N4.

[0157] The third transistor T3, which acts as a sensing transistor, is switched according to the scan signal Sc2. The gate electrode of the third transistor T3 is connected to the scan signal Sc2, the source electrode of the third transistor T3 is connected to the second node N2, and the drain electrode of the third transistor T3 is connected to the first node N1.

[0158] The fourth transistor T4 is switched according to the scan signal Sc2. The gate electrode of the fourth transistor T4 is connected to the scan signal Sc2, the source electrode of the fourth transistor T4 is connected to the fourth node N4, and the drain electrode of the fourth transistor T4 is connected to the reference signal (reference voltage) Vrf.

[0159] The fifth transistor T5 is switched according to the emit signal Em. The gate electrode of the fifth transistor T5 is connected to the emit signal Em, the source electrode of the fifth transistor T5 is connected to the third node N3, and the drain electrode of the fifth transistor T5 is connected to the reference signal Vrf.

[0160] The sixth transistor T6, acting as a switching transistor, is switched according to the scan signal Sc1. The gate electrode of the sixth transistor T6 is connected to the scan signal Sc1, the source electrode of the sixth transistor T6 is connected to the third node N3, and the drain electrode of the sixth transistor T6 is connected to the data signal Vda.

[0161] The storage capacitor Cs stores the data signal Vda and the threshold voltage (Vth) of the first transistor T1. The first capacitor electrode of the storage capacitor Cs is connected to the first node N1, and the second capacitor electrode of the storage capacitor Cs is connected to the third node N3.

[0162] The shielding capacitor Cb reduces the coupling between the data line DL and the first node N1. The first capacitor electrode of the shielding capacitor Cb is connected to the second node N2, and the second capacitor electrode of the shielding capacitor Cb is connected to the data signal Vda.

[0163] The light-emitting diode De is connected between the fourth node N4 and the low-level signal (low-level voltage) Vss, and emits light with a brightness proportional to the current of the first transistor T1. The anode of the light-emitting diode De is connected to the fourth node N4, and the cathode of the light-emitting diode De is connected to the low-level signal Vss.

[0164] The gate electrode of the first transistor T1, the first capacitor electrode of the storage capacitor Cs, and the drain electrode of the third transistor T3 constitute the first node N1, and the drain electrode of the first transistor T1, the source electrode of the second transistor T2, and the source electrode of the third transistor T3 constitute the second node N2. The second capacitor electrode of the storage capacitor Cs, the source electrode of the fifth transistor T5, and the source electrode of the sixth transistor T6 constitute the third node N3, and the drain electrode of the second transistor T2, the source electrode of the fourth transistor T4, and the anode of the light-emitting diode De constitute the fourth node N4.

[0165] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the display device according to the third embodiment of the present disclosure is driven by an initialization time period, a sampling time period, a holding time period, and an emission time period.

[0166] exist Figure 8 In the display device according to the third embodiment of the present disclosure, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes a gate line GL, a data line DL, a reference line RL, and a power line PL. The gate line GL for transmitting the scan signal Sc2, the gate line GL for transmitting the transmit signal Em, the gate line GL for transmitting the scan signal Sc2, and the gate line GL for transmitting the scan signal Sc1 are arranged sequentially along the horizontal direction. The data line DL for transmitting the data signal Vda, the reference line RL for transmitting the reference signal Vrf, and the power line PL for transmitting the high-level signal Vdd are arranged sequentially along the vertical direction.

[0167] The first transistor T1 is connected to the power supply line PL for transmitting a high-level signal, and the second transistor T2 is connected to the gate line GL for transmitting the transmit signal Em. The third transistor T3 is connected to the gate line GL for transmitting the scan signal Sc2, and the fourth transistor T4 is connected to the gate line GL for transmitting the scan signal Sc2 and the reference line RL for transmitting the reference signal Vrf. The fifth transistor T5 is connected to the gate line GL for transmitting the transmit signal Em and the reference line RL for transmitting the reference signal Vrf, and the sixth transistor T6 is connected to the gate line GL for transmitting the scan signal Sc1 and the data line DL for transmitting the data signal Vda.

[0168] ( Figure 9 The metal pattern 344 is set in the first transistor T1. Figure 9 The gate electrode 340 of the first transistor T1 and the metal pattern 344 form a storage capacitor Cs.

[0169] From the first transistor T1 ( Figure 9 The drain region of semiconductor layer 334 extends ( Figure 9The shielding pattern 336 is disposed below the data line DL adjacent to the first transistor T1, and the shielding pattern 336 and the data line DL constitute the shielding capacitor Cb.

[0170] Because the shielding pattern 336 is positioned closer to the data line DL than the gate electrode 340 of the first transistor T1, most of the electric field lines of the data line DL will not reach the gate electrode 340 of the first transistor T1, but will instead reach the shielding pattern 336. As a result, the coupling (or parasitic capacitance) between the data line DL and the gate electrode 340 of the first transistor T1 (i.e., the first node N1) is reduced, the voltage variation of the gate electrode 340 of the first transistor T1 is minimized, and degradation such as vertical crosstalk is prevented.

[0171] Therefore, the shielding pattern 336 is formed to correspond to the entire end of the gate electrode 340 of the adjacent first transistor T1.

[0172] For example, the first width w1 of the shielding pattern 336 can be greater than the second width w2 of the gate electrode 340 of the first transistor T1.

[0173] exist Figure 9 In the process, a buffer layer 332 is disposed on the entire substrate 330, and a semiconductor layer 334 and a shielding pattern 336 are disposed on the buffer layer 332.

[0174] The buffer layer 332 prevents moisture or oxygen from penetrating from the outside. For example, the buffer layer 332 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0175] Semiconductor layer 334 includes a channel region at its central portion that is undoped, and source and drain regions at the two side portions of the channel region that are doped. For example, semiconductor layer 334 may include a polycrystalline semiconductor material, such as polycrystalline silicon, or an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0176] The shielding pattern 336 extends from the drain region of the semiconductor layer 334 and is doped with impurities. For example, the shielding pattern 336 may include a polycrystalline semiconductor material, such as polycrystalline silicon, or an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0177] A gate insulating layer 338 is disposed over the semiconductor layer 334 and the shielding pattern 336 over the entire substrate 330, and a gate electrode 340 is disposed on the gate insulating layer 338 corresponding to the channel region of the semiconductor layer 334.

[0178] For example, the gate insulating layer 338 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0179] For example, the gate electrode 340 may have a single layer or multiple layers of metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0180] The semiconductor layer 334, the gate insulating layer 338, and the gate electrode 340 constitute the first transistor T1.

[0181] Despite Figure 8 and Figure 9 In a third embodiment, the first transistor T1 exemplarily has a dual-gate type comprising two gate electrodes and two channel regions separated from each other in a plan view, but in another embodiment, the first transistor T1 may have a single-gate type comprising one gate electrode and one channel region.

[0182] The first interlayer insulating layer 342 is disposed on the gate electrode 340 over the entire substrate 330, and the metal pattern 344 is disposed on the first interlayer insulating layer 342 corresponding to the gate electrode 340.

[0183] For example, the first interlayer insulating layer 342 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0184] For example, the metal pattern 344 can have a single layer or multiple layers of metal materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0185] The gate electrode 340, the first interlayer insulating layer 342, and the metal pattern 344 constitute the storage capacitor Cs, and the gate electrode 340 and the metal pattern 344 serve as the first capacitor electrode and the second capacitor electrode of the storage capacitor Cs, respectively.

[0186] The second interlayer insulating layer 346 is disposed on the metal pattern 344 over the entire substrate 330, and the source electrode 348, the drain electrode 350 and the data line DL are disposed on the second interlayer insulating layer 346.

[0187] For example, the second interlayer insulating layer 346 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0188] The source electrode 348 and the drain electrode 350 are connected to the source region and drain region of the semiconductor layer 334, respectively, through contact holes in the second interlayer insulating layer 346, the first interlayer insulating layer 342 and the gate insulating layer 338.

[0189] The data cable DL is set to overlap with shielding pattern 336.

[0190] For example, the source electrode 348, the drain electrode 350, and the data line DL can have single-layer or multi-layer metal materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0191] The shielding pattern 336, the gate insulating layer 338, the first interlayer insulating layer 342, the second interlayer insulating layer 346 and the data line DL constitute the shielded capacitor Cb, and the shielding pattern 336 and the data line DL are respectively used as the first capacitor electrode and the second capacitor electrode of the shielded capacitor Cb.

[0192] The planarization layer 352 is disposed over the entire substrate 330 on the source electrode 348, the drain electrode 350 and the data line DL, and the first electrode 354 is disposed on the planarization layer 352.

[0193] For example, the planarization layer 352 may have a single or multiple layers of organic insulating material, such as photopropylene materials and benzocyclobutene (BCB).

[0194] The first electrode 354 can be connected to the drain region of the second transistor T2 or the source region of the fourth transistor T4 through the contact hole in the planarization layer 352.

[0195] For example, the first electrode 354 can be an anode and can have a single layer or multiple layers of transparent conductive material, such as indium tin oxide (ITO) and indium zinc oxide (IZO), or an opaque metallic material, such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) and their alloys.

[0196] The dam layer 356 is disposed on the first electrode 354, and the spacer 358 is disposed on the dam layer 356.

[0197] The embankment 356 covers the edge portion of the first electrode 354 and has an opening that exposes the central portion of the first electrode 354.

[0198] For example, the dam layer 356 can have a single or multiple layers of organic insulating materials, such as photopropylene materials and benzocyclobutene (BCB).

[0199] For example, spacer 358 may have a single layer or multiple layers of organic insulating material, such as photopropylene materials and benzocyclobutene (BCB).

[0200] The emitter layer 360 may be disposed on the first electrode 354 exposed through the opening of the dam layer 356, and the second electrode 362 may be disposed on the emitter layer 360 over the entire substrate 330.

[0201] The emission layer 360 may include a hole auxiliary layer (e.g., a hole injection layer and a hole transport layer), an emission material layer, and an electron auxiliary layer (e.g., an electron transport layer and an electron injection layer).

[0202] For example, the second electrode 362 can be a cathode and can have a single or multiple layers of transparent conductive material, such as indium tin oxide (ITO) and indium zinc oxide (IZO), or a single or multiple layers of semi-transparent material or opaque metallic material, such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), molybdenum (Mo), titanium (Ti) and their alloys.

[0203] The first electrode 354, the emitting layer 360, and the second electrode 362 constitute a light-emitting diode De.

[0204] Although not shown, an encapsulation layer may be disposed over the entire substrate 330 on the second electrode 362. For example, the encapsulation layer may include a first encapsulation layer and a third encapsulation layer having a single or multiple layers of inorganic insulating materials (such as silicon oxide (SiO2) and silicon nitride (SiNx)), and a second encapsulation layer located between the first and third encapsulation layers and including an organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin).

[0205] The touch layer used for sensing touch can be placed on the encapsulation layer.

[0206] In the display device according to the third embodiment of this disclosure, a shielding pattern 336 extending from the drain region of the semiconductor layer 334 of the first transistor T1 is disposed below the data line DL adjacent to the gate electrode 340 of the first transistor T1 to form a shielding capacitor Cb having the shielding pattern 336 and the data line DL. As a result, the coupling (or parasitic capacitance) between the data line DL and the gate electrode 340 of the first transistor T1 (between the data line DL and the first node N1) is reduced, the voltage variation of the gate electrode 340 of the first transistor T1 is minimized, and degradation such as vertical crosstalk is prevented. Therefore, the display device is driven with relatively low power consumption.

[0207] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its scope. Therefore, this disclosure is intended to cover such modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: The display panel includes a display area having multiple sub-pixels and a non-display area around the periphery of the display area; A storage capacitor and a first transistor, wherein the storage capacitor and the first transistor are in each of the plurality of sub-pixels; A data line, wherein the data line is configured to be adjacent to the gate electrode of the first transistor; as well as A shielding capacitor, wherein the shielding capacitor is configured to overlap with the data line. The first width of the shielding capacitor is greater than the second width of the gate electrode of the first transistor.

2. The display device according to claim 1, wherein, The first transistor includes: A semiconductor layer on a substrate, comprising a channel region at its central portion and source and drain regions at portions on either side of the channel region; A gate insulating layer, the gate insulating layer being disposed on the semiconductor layer; and The gate electrode on the gate insulating layer corresponding to the semiconductor layer.

3. The display device according to claim 2, wherein, The shielding capacitor includes: The shielding pattern on the substrate; The gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer sequentially arranged on the shielding pattern; and The data lines on the second interlayer insulation layer that correspond to the shielding pattern.

4. The display device according to claim 3, wherein, The shielding pattern extends from the source region of the semiconductor layer of the first transistor.

5. The display device according to claim 3, wherein, The shielding pattern is separated from the semiconductor layer of the first transistor and transmits a high-level signal through contact holes in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.

6. The display device according to claim 3, wherein, The shielding pattern extends from the drain region of the semiconductor layer of the first transistor.

7. The display device according to claim 3, wherein, The storage capacitor includes: The gate electrode of the first transistor; The first interlayer insulating layer on the gate electrode of the first transistor; and Metal pattern on the first interlayer insulating layer.

8. The display device according to claim 1, further comprising: Multiple gate lines, which transmit a first scan signal, a second scan signal, and a transmit signal, are arranged sequentially in the display area along a horizontal direction; as well as Reference lines and power lines are arranged vertically in the display area.

9. The display device according to claim 1, wherein, The first transistor is a dual-gate type transistor, which includes two gate electrodes and two channel regions that are separated from each other.

10. The display device according to claim 9, wherein, The second width is the width of the two gate electrodes.

11. The display device according to claim 1, further comprising a light-emitting diode on the first transistor and the shielding capacitor.

12. The display device according to any one of claims 3 to 7, wherein, The shielding pattern is set to be closer to the data line than the gate electrode of the first transistor.

13. The display device according to claim 12, wherein, The shielding pattern contains impurities.

14. The display device according to claim 5, wherein, The shielding pattern is connected to the power cord.

15. The display device according to any one of claims 1 to 11, 13 and 14, wherein, The first transistor is configured as a driving transistor.

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