Semiconductor production method, apparatus, medium, and device

Abstract

This disclosure relates to a semiconductor manufacturing method, apparatus, medium, and equipment. The method includes: depositing a thin film on a wafer surface at a preset thin film depth and defining an etch region on the surface of the thin film; etching the etch region according to a target etch depth corresponding to the preset thin film depth; electroplating the etch region after etching; and grinding the etch region according to the target etch depth after electroplating to complete the semiconductor manufacturing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a semiconductor manufacturing method, apparatus, medium, and equipment. Background Technology

[0002] With the booming development of the semiconductor industry, the performance, integration, and functional complexity of chips are constantly improving, which places extremely stringent demands on semiconductor manufacturing processes. The semiconductor manufacturing process is a complex system composed of multiple closely related process steps, encompassing a series of key processes such as deposition, photolithography, etching, electroplating, and polishing. Through the coordinated operation of these processes, a precise chip structure composed of dielectric layers, metal layers, and semiconductor layers is ultimately constructed. Among these, the dielectric layer depth and metal layer depth are two core parameters that are particularly important in affecting the electrical and physical properties of the chip.

[0003] In existing technologies, the remaining quantity parameters obtained from the PAD (pad) frame are commonly used to adjust and control data transfer and process parameters between various steps in the semiconductor manufacturing process. For example, existing techniques typically use the remaining quantity parameters of the dielectric layer to control and adjust processes such as deposition, etching, and polishing. However, this control method has many drawbacks. Due to the complex relationship of mutual interference and influence between the two processes, it is impossible to precisely control the dielectric layer depth and metal layer depth of the semiconductor at the same time. As a result, the produced semiconductor products inevitably exhibit significant deviations in resistance variation, which will undoubtedly have a severely adverse impact on the overall performance and stability of the chip. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor manufacturing method, apparatus, medium, and device to address problems in the related art.

[0005] To achieve the above objectives, in a first aspect, this disclosure provides a semiconductor manufacturing method, the method comprising: A thin film is deposited on the wafer surface according to a preset thin film depth, and an etching area is defined on the surface of the thin film; The etching region is etched according to the target etching depth corresponding to the preset film depth; After the etching is completed, the etched area is electroplated. After the electroplating is completed, the etched area is ground according to the target etching depth to complete the production of the semiconductor.

[0006] Optionally, etching the etching area according to the target etching depth corresponding to the preset thin film depth includes: The target etching depth is determined based on the preset film depth and the preset perforation depth; The etching area is etched until the etching depth of the etched area reaches the target etching depth.

[0007] Optionally, the method further includes: Obtain the etching type of the etched area, where the etching type includes trench etching and through-hole etching; A first etching region and a second etching region are determined in the etching region, wherein the first etching region corresponds to the trench etching and the second etching region corresponds to the through-hole etching; The etching of the etched area until the etch depth of the etched area reaches the target etch depth includes: The first etched area is etched until the etch depth of the first etched area reaches the target etch depth; and The second etched area is etched until a perforation is formed in the second etched area.

[0008] Optionally, the step of electroplating the etched area after the etching is completed includes: After the etching is completed, the etched area is electroplated according to preset electroplating parameters.

[0009] Optionally, the step of grinding the etched area according to the target etch depth to complete the semiconductor production includes: The target grinding depth is determined based on the preset correspondence between the target etching depth and the grinding depth; The etched area is ground until the grinding depth of the etched area reaches the target grinding depth, thus confirming the completion of semiconductor production.

[0010] Optionally, the method further includes: After the grinding is completed, the actual coating depth is determined, which is the metal depth of the first etched area; If the actual coating depth is greater than the preset coating depth, the etched area is subjected to compensatory grinding control so that the actual coating depth reaches the preset coating depth.

[0011] Secondly, this disclosure also provides a semiconductor manufacturing apparatus, the apparatus comprising: The deposition module is configured to deposit a thin film on the wafer surface at a preset film depth and to define an etched area on the surface of the film. The etching module is configured to etch the etching area according to a target etching depth corresponding to the preset film depth; An electroplating module is configured to electroplat the etched area after the etching is completed; A polishing module is configured to polish the etched area according to the target etching depth after the electroplating is completed, so as to complete the production of the semiconductor.

[0012] Optionally, the etching module is configured to: The target etching depth is determined based on the preset film depth and the preset perforation depth; The etching area is etched until the etching depth of the etched area reaches the target etching depth.

[0013] Thirdly, this disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the semiconductor manufacturing method provided in the first aspect of this disclosure.

[0014] Fourthly, this disclosure also provides a semiconductor manufacturing apparatus, comprising: A memory on which computer programs are stored; A processor for executing the computer program in the memory to implement the semiconductor manufacturing method provided in the first aspect of this disclosure.

[0015] The above technical solution eliminates the reliance on the remaining parameters in the PAD frame, avoids mutual interference between processes in semiconductor manufacturing, and can accurately determine the target etching depth based on the preset thin film depth. This allows etching, electroplating, grinding, and other processes to run independently and precisely in sequence, effectively achieving precise control over the dielectric layer depth and metal layer depth. Consequently, it significantly reduces the resistance variation deviation of semiconductor products and significantly improves the overall performance and stability of the chip.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a semiconductor manufacturing process according to an exemplary embodiment.

[0018] Figure 2 This is a flowchart of a semiconductor manufacturing method according to an exemplary embodiment.

[0019] Figure 3 This is a schematic diagram of a semiconductor manufacturing process according to an exemplary embodiment.

[0020] Figure 4 This is a block diagram of a semiconductor manufacturing apparatus according to an exemplary embodiment.

[0021] Figure 5 This is a block diagram illustrating a semiconductor manufacturing apparatus according to an exemplary embodiment.

[0022] Figure 6 This is a block diagram illustrating a semiconductor manufacturing apparatus according to an exemplary embodiment. Detailed Implementation

[0023] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0024] In the relevant terminology of this application, "thickness" and "depth" have the same meaning, namely the height perpendicular to the plane of the semiconductor substrate (such as a wafer). For example, thin film thickness can also be described as thin film depth.

[0025] Before introducing the technical solutions provided in this disclosure, it is worth noting that in existing semiconductor manufacturing technologies, the "remaining quantity parameters" obtained from the PAD frame are typically used to adjust data transfer and process parameters at various stages of the semiconductor manufacturing process. (See [link to relevant documentation]). Figure 1 As shown, the following describes some processes in the existing semiconductor manufacturing process: Firstly, in the deposition process, the deposition parameters are controlled based on the "remaining film thickness" (i.e., real-time film depth) obtained from the PAD frame to generate a dielectric layer with an initial film depth. When the "remaining film thickness" reaches the initial film depth, the deposition is completed and the current "remaining film thickness" (which is the initial film depth at this time) is sent to the relevant equipment responsible for the etching and polishing processes.

[0026] Secondly, in the etching process, the etching amount is adjusted based on the "remaining film thickness" (represented here as the remaining etching amount) obtained from the PAD frame. The aim is to achieve a fixed Via (through-hole) depth, meaning the "remaining film thickness" reaches the target value. However, the "remaining film thickness" can only be obtained through the equipment used in the deposition process, thus the etching process is affected by the deposition process. For example, if the initial film depth is known to be 1000 nm, and the design requirement for the through-hole depth is 400 nm, the etching process needs to remove 600 nm of dielectric material by adjusting the etching parameters. However, in this process, since etching resources (such as the interaction time between the etchant and the material, the concentration of active particles, etc.) are mostly allocated to ensure precise control of the through-hole depth, this indirect method of controlling the etching depth makes it difficult to simultaneously achieve precise control of the trench depth.

[0027] Taking a semiconductor region with both through-hole and trench structures as an example, if the target depth of the trench is 500nm and the target depth of the through-hole is 400nm, the following situations may occur during the etching process to ensure that the through-hole depth accurately reaches the target depth: If the etching time is extended to meet the through-hole depth requirement, the trench may be over-etched, reaching an actual depth of 600nm, exceeding the design standard; on the other hand, if the etching time is controlled to avoid over-etching the trench, the through-hole depth may not reach the expected value of 400nm. Therefore, it is difficult to ensure that the through-hole depth is accurate while also meeting the design requirements during the etching process. This is one of the drawbacks of relying on the "residual amount parameter" as an indicator.

[0028] Thirdly (Grinding Process): In this process, the grinding amount is adjusted based on the "remaining film thickness" (represented here as grinding residue) and the via depth in the PAD frame, with the goal of achieving the preset grinding residue. For example, if the "remaining film thickness" after etching is 400nm, while the design requires a "remaining film thickness" of 300nm after grinding, then the grinding process needs to remove 100nm of dielectric layer material by adjusting the grinding parameters. However, in this process, it is impossible to control the coating depth, such as Cu THK (Copper Thickness). Since the grinding parameters are set to control the grinding amount of the dielectric layer, the copper film thickness may change significantly due to factors such as friction and chemical reactions during the grinding process. For example, the copper film thickness may be thinner than the designed target coating depth after grinding, or the copper film thickness may vary greatly in some etched areas due to uneven grinding, resulting in the inability to effectively control the copper film thickness on the entire chip.

[0029] The inability to simultaneously control trench depth and coating depth during etching and polishing directly leads to significant deviations in the semiconductor's resistance variation (Rs), thus affecting the chip's electrical performance. For interconnect structures within the chip, if the trench depth does not meet design requirements, it will alter the shape and size of the interconnect lines, affecting the effective cross-sectional area for current flow. For example, if the trench depth is too shallow, the cross-sectional area of ​​the interconnects formed by the subsequently electroplated metal (such as copper) will be smaller. According to the resistance formula R=ρ*(L / A), where ρ is the resistivity of the material, L is the length of the line, and A is the cross-sectional area, a smaller cross-sectional area will lead to an increase in resistance. Similarly, changes in the depth of the copper film will also have a significant impact on resistance. For example, if the copper film is thinner, it means that the conductive material of the interconnects is reduced, and the resistance will inevitably increase. Moreover, due to the inconsistent thickness of the copper film in different areas, the resistance of the interconnects at different locations within the chip will vary greatly, that is, the Rsvariation deviation will be large. Such large variations and inconsistencies in resistance will cause problems such as signal attenuation and delay during signal transmission, affecting the overall functionality and performance stability of the chip. For example, it may lead to an increase in the bit error rate and a deterioration in signal integrity when the chip processes high-frequency signals.

[0030] In summary, the current method of using the remaining parameters in the PAD frame as process data indicators cannot take into account factors such as trench depth and copper film thickness, which leads to problems such as large deviations in resistance and affects chip performance.

[0031] In view of this, in order to improve the manufacturing precision of semiconductors, thereby improving their electrical performance and physical stability, this disclosure provides a semiconductor manufacturing method, see [link to relevant documentation]. Figure 2 as well as Figure 3 As shown, the method includes the following steps: In step S201, a thin film is deposited on the wafer surface according to a preset thin film depth, and an etching area is determined on the surface of the thin film.

[0032] The film depth is used to characterize the thickness of the dielectric layer deposited on the wafer surface. The preset film depth is pre-calibrated based on at least one of the following: dielectric layer thickness, metal layer thickness, semiconductor layer thickness, semiconductor type, and semiconductor circuit structure, which correspond to the chip design and functional requirements.

[0033] In one embodiment, TF dep (Thin Film Deposition) can be performed by adjusting deposition parameters according to a preset film depth using CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition) to deposit a dielectric layer film, such as an oxide dielectric layer, on the wafer surface.

[0034] In one embodiment, to achieve a preset film depth, multiple deposition parameters need to be precisely controlled, including the reactive gas flow rate, reaction temperature, and deposition time. A higher reactive gas flow rate results in more substances participating in the reaction to form the film per unit time, leading to a faster film deposition rate. Different reaction temperatures correspond to different chemical reaction rates; excessively high or low temperatures will affect the film quality and deposition rate. Furthermore, if PECVD (Plasma Enhanced Chemical Vapor Deposition) technology is used during the deposition process, the deposition parameters also include the plasma power, which affects the activation level of the reactive gas and thus the film deposition.

[0035] For example, if the dielectric film to be generated is a silicon dioxide film, silane (SiH4) and oxygen (O2) are used as precursors. PECVD technology is employed to allow the precursors to undergo a chemical reaction under high temperature and plasma conditions, thereby generating a silicon dioxide film on the wafer surface. Through process exploration and repeated experiments, the deposition parameters corresponding to different preset film depths can be determined. For example, for a preset film depth of 500 nm, the corresponding silane flow rate is 100 standard cubic centimeters per minute, the oxygen flow rate is 200 standard cubic centimeters per minute, the reaction temperature is 400℃, the plasma power is 500 W, and the deposition time is 15 min.

[0036] In one implementation, see Figure 3 As shown, after deposition is complete, defining the etched area on the film surface involves the following steps: The first step is to coat the thin film surface with photoresist, a photoresist being a light-sensitive polymer material. This photoresist is uniformly coated onto the thin film surface using a spin coating method, forming a photoresist layer of uniform thickness, typically ranging from several hundred nanometers to several micrometers. For example, for positive photoresist, a photoresist layer with a thickness of approximately 800 nm can be obtained on the thin film by spin coating at a speed of 3000 revolutions per minute.

[0037] The second step (not shown) involves exposure using a lithography machine. The lithography machine projects a circuit pattern from a light source, such as ultraviolet, deep ultraviolet, or extreme ultraviolet light, onto a photoresist mask. The mask is a template with a circuit pattern used to define the etched areas.

[0038] The third step involves removing the photoresist from the exposed areas (for positive photoresist) or the unexposed areas (for negative photoresist) by developing the photoresist layer, forming a pattern on the photoresist layer that corresponds to the mask pattern, and defining these formed patterns as the etching areas.

[0039] The aforementioned thin film deposition and etching region determination steps lay the foundation for subsequent semiconductor manufacturing processes such as precise etching, electroplating, and polishing according to preset requirements.

[0040] In step S202, the etching area is etched according to the target etching depth corresponding to the preset film depth.

[0041] Among them, ET etch (Etching) includes wet etching and dry etching.

[0042] In one implementation, the correspondence between the preset film depth and the target etching depth can be pre-defined based on the electrical properties of different semiconductor structures. After determining the preset film depth, the corresponding target etching depth can be determined by looking up a table. For example, if the preset film depth is 1000 nm, and the target etching depth is determined to be 700 nm by looking up a table, then for films deposited at 1000 nm, the etching area can be etched according to the etching parameters corresponding to the etching depth of 700 nm. This achieves self-control of etching, eliminating the need to adjust the etching amount based on the remaining film amount in the PAD frame, reducing etching errors, and achieving precise control of the etching depth, thereby improving etching efficiency.

[0043] In step S203, after the etching is completed, the etched area is electroplated.

[0044] In one embodiment, the etched area can be electroplated according to preset electroplating parameters to achieve the target electroplating thickness. The preset electroplating parameters include at least one of electroplating type, electroplating solution concentration, current density, electroplating time, and electroplating solution temperature.

[0045] Taking Cu ECP (Copper Electrochemical Plating) as an example, the plating solution is copper sulfate (CuSO4) solution. An appropriate copper sulfate concentration ensures a sufficient supply of copper ions, allowing the plating process to proceed steadily. If the concentration is too low, insufficient copper ion supply will slow down the plating rate, or even prevent the target plating thickness from being achieved. If the concentration is too high, it may cause problems such as coarse crystal formation and decreased adhesion of the plating layer. For example, the concentration of the copper sulfate plating solution can be between 100 g / L and 200 g / L. Current density determines the plating rate and the quality of the plating layer. Too high a current density will cause the plating metal to deposit too quickly, easily producing defects such as dendrites and burning, and increasing the internal stress of the plating layer, which may lead to peeling. Too low a current density will result in a slow plating rate, reducing production efficiency. For example, in copper electroplating, the suitable current density range is typically between 1 A / dm² (amperes per square decimeter) and 3 A / dm². The current density is determined based on factors such as the area of ​​the electroplating region, the composition of the electroplating solution, and the temperature, to ensure a uniform and dense deposition of the electroplated layer. The electroplating time is determined based on the target plating thickness and the current density. For instance, according to Faraday's law, the thickness of the electroplated layer is directly proportional to the amount of electricity passed (the product of current density and time). The temperature of the electroplating solution can be controlled between 20 and 50°C to accelerate ion diffusion and thus speed up the electroplating reaction rate.

[0046] In step S204, after the electroplating is completed, the etched area is ground according to the target etching depth to complete the production of the semiconductor.

[0047] It is worth noting that grinding the etched area refers to smoothing the wafer surface using CMP (Chemical-Mechanical Polishing) technology in semiconductor manufacturing processes, so that the chip surface reaches a flat state.

[0048] In one embodiment, during the CMP process, an etchant first reacts chemically with the material on the wafer surface to soften or dissolve the thin film on the wafer surface, such as the dielectric layer film, making it easier to remove. Then, the wafer surface is mechanically ground by a grinding device to remove excess material.

[0049] The grinding parameters in the CMP process or the target coating depth after grinding have a pre-set correspondence with the target etching depth. Since the target etching depth corresponds with the preset thin film depth, the grinding parameters or the target coating depth also correspond with the preset thin film depth. In other words, in the semiconductor manufacturing process, as long as the preset thin film depth is set, the target etching depth in the etching process and the parameters in the grinding process can be obtained, so that the semiconductor has a dielectric layer depth and a metal film depth that conform to the electrical characteristics. The dielectric layer depth is used to characterize the thickness of the thin film between the wafer surface and the metal film layer. The dielectric layer depth is the difference between the preset thin film depth and the target etching depth. The metal film depth is used to characterize the thickness of the electroplated metal on the dielectric layer surface, i.e., the target coating depth.

[0050] In one embodiment, the preset thin film depth is set to 1000 nm. Based on experiments, the dielectric layer depth that meets the ideal electrical properties is 200 nm, and the metal layer depth is 300 nm. Therefore, the target etching depth can be set to 800 nm. The corresponding electroplating and polishing parameters are set according to the target etching depth so that the thickness of the metal coating on the dielectric layer surface reaches 300 nm after polishing. In the entire semiconductor manufacturing process, each process can be self-controlled and will not be affected by another process. For example, the etching process is not affected by the remaining amount of thin film (dielectric layer) in the deposition process, and etching is carried out according to fixed etching parameters. At the same time, the polishing process is not affected by the remaining amount of thin film in the deposition process, and polishing is carried out according to fixed polishing parameters. In other words, the etching and polishing processes completely eliminate the concern and dependence on the "remaining amount of thin film". This greatly improves the stability, reliability and repeatability of the entire semiconductor manufacturing process, effectively ensuring the consistency of semiconductor product quality and high-performance output, and providing a solid and reliable technical support and guarantee mechanism for the efficient and precise production of the semiconductor industry.

[0051] The above technical solution eliminates the reliance on the remaining parameters in the PAD frame, avoids mutual interference between processes in semiconductor manufacturing, and can accurately determine the target etching depth based on the preset thin film depth. This allows etching, electroplating, grinding and other processes to run independently and precisely in sequence, effectively achieving precise control over the dielectric layer depth and metal layer depth. As a result, it significantly reduces the resistance variation deviation of semiconductor products and significantly improves the overall performance and stability of the chip.

[0052] Optionally, step S202 above includes the following sub-steps: S202-1. Determine the target etching depth based on the preset film depth and the preset perforation depth.

[0053] It's worth noting that the preset film depth is set based on the thickness requirements of each functional layer and structural layer planned in the chip design. For example, in a multilayer metal interconnect structure, the preset film depth of the dielectric layer is determined according to the electrical isolation requirements between adjacent metal layers, signal transmission characteristics, and the overall physical layout of the chip. The preset via depth, on the other hand, is closely related to the subsequent interconnection requirements within the chip. For instance, to create vias or through-hole structures in the dielectric layer to connect different metal wiring layers, these vias need to reach a certain depth to ensure good electrical conductivity after subsequent electroplating of the fill metal. The preset via depth is determined based on factors such as the chip's multilayer interconnect architecture, signal transmission path planning, and the spacing between different layers.

[0054] For example, the target etching depth can be determined by the difference between the preset film depth and the preset perforation depth. For instance, if the preset film depth is 500nm and the preset perforation depth is 300nm, then the target etching depth is determined to be 200nm.

[0055] By combining the two key parameters mentioned above, the target etching depth can be accurately determined. The target etching depth is actually the specific depth value that needs to be etched down from the surface of the thin film during the etching process. It comprehensively considers the requirements of exposing the underlying structure for subsequent processes and meeting the requirements of the entire chip structure and function construction.

[0056] S202-2. Etch the etched area until the etch depth of the etched area reaches the target etch depth.

[0057] When etching the area, it is necessary to precisely control various etching parameters to ensure that the etching depth can accurately reach the target etching depth.

[0058] For wet etching, when using hydrofluoric acid (HF) solution to etch the silicon dioxide dielectric layer, parameters such as the concentration of the etchant, temperature, and etching time are crucial. For example, under a fixed concentration (e.g., 5% hydrofluoric acid solution) and temperature (e.g., 25°C), the etching rate of the etchant on silicon dioxide is approximately 10 nm per minute. To achieve the target etching depth of 200 nm calculated in the example above, the etching time needs to be precisely controlled to around 20 minutes.

[0059] For dry etching methods, such as Reaction Ion Etching (RIE), parameters such as RF power, gas flow rate, and chamber pressure affect the etching rate and effect. For example, when using fluorine-based gas for etching, with an RF power of 200W, a gas flow rate of 50 sccm (standard cubic centimeters per minute), and a chamber pressure of 10 mTorr, the tested etching rate on the target material is 30 nm per minute. To achieve a target etching depth of 200 nm, the etching time would be approximately 7 minutes.

[0060] Optionally, the semiconductor manufacturing method provided in this disclosure further includes: First, the etching type of the etched area is obtained, including trench etching and through-hole etching.

[0061] It's worth noting that trench etching is typically used to construct the channel structure of transistors or some isolation structures within a chip. Its purpose is to form elongated trenches of a certain length, width, and depth on a thin film to achieve specific electrical functions, such as restricting the direction of current flow or isolating different active regions. Through-hole etching, on the other hand, is mainly used to create through-holes in thin films such as dielectric layers to connect different conductive layers, facilitating subsequent metal filling processes such as electroplating to achieve electrical connections between the multiple layers within the chip.

[0062] By obtaining the etching type information of the etched area, subsequent etching strategies can be formulated in a targeted manner to ensure that each area can be etched accurately according to the design requirements, thereby ensuring the functional integrity and performance stability of the entire chip.

[0063] Then, a first etched region and a second etched region are determined in the etched region, wherein the first etched region corresponds to the trench etching and the second etched region corresponds to the through-hole etching.

[0064] It is worth noting that in some semiconductors, a large number of trenches may be needed to construct the trenches for each transistor and to isolate different transistor groups. These areas requiring trenches are designated as the first etching region. In the multilayer metal interconnect, in order to achieve vertical connections between different metal wiring layers, the area on the dielectric layer corresponding to the planned via locations is defined as the second etching region for via etching.

[0065] In one embodiment, the first etched region and the second etched region may overlap, i.e., the second etched region is located within the first etched region.

[0066] Optionally, the above sub-step S202-2 includes: First, the first etched area is etched until the etch depth of the first etched area reaches the target etch depth.

[0067] It is worth noting that when performing trench etching on the first etching area, the etching parameters need to be adjusted according to the specific design requirements of the trench, such as the trench length, width, depth, and the requirements for the roughness and perpendicularity of the trench sidewalls. However, the etching parameters will not be affected by the amount of film remaining.

[0068] Second, the second etched area is etched until a perforation is formed in the second etched area.

[0069] In one embodiment, during the etching of the second etching area, it is determined in real time whether a through-hole has been successfully formed. On one hand, this can be achieved through electrical detection methods, such as applying a small electrical signal to both ends of the second etching area. Once the through-hole is formed, the circuit will conduct, and the change in current can be detected to determine if the through-hole is complete. On the other hand, the second etching area can be directly observed using equipment such as an optical microscope or a scanning electron microscope to check whether a complete through-hole structure has appeared, and whether its size, shape, and boundary with the surrounding area meet the design requirements. Once it is confirmed that the through-hole has been formed, it indicates that the etching operation of the second etching area has achieved its intended purpose, preparing for subsequent processes such as electroplating and filling with metal.

[0070] By performing precise etching operations on the first and second etching areas respectively, the requirements of different functional areas of the chip for trench and via structures can be met, ensuring the smooth progress of the entire semiconductor manufacturing process and that the final chip meets design standards in terms of electrical performance and physical structure, thereby improving the yield and performance of the chip.

[0071] Optionally, step S203 above can be performed in the following manner: After the etching is completed, the etched area is electroplated according to preset electroplating parameters.

[0072] In one implementation, the preset electroplating parameters are related to the structural characteristics corresponding to the chip design. For example, if the interconnect lines in a certain area of ​​the chip need to carry a large current, a thicker and higher quality metal plating layer is required to ensure low resistance and good conductivity. For the preset electroplating parameters, a relatively high current density and a long electroplating time need to be set to achieve sufficient metal deposition to meet the conductivity requirements.

[0073] They are the same. For the same structural feature area in the same semiconductor or chip, the preset electroplating parameters are also related to the shape, size and material properties of the etched area. The larger the shape or size of the etched area, the greater the electroplating amount produced by the preset electroplating parameters, so as to ensure that the depth of the electroplated film layer produced by electroplating in etched areas of different sizes is the same.

[0074] For example, if the etched area is a trench or via structure with a high aspect ratio, electroplating must ensure that the metal fills the depth uniformly to avoid voids or incomplete filling. For preset electroplating parameters, a relatively stable current density and electroplating solution composition need to be selected. Furthermore, different substrate materials (wafers or thin films) of the etched area result in differences in their adhesion to the electroplated metal and surface activity. For instance, when the substrate is a silicon dioxide dielectric layer, its adsorption capacity for electroplated metal is weaker than that of a metal substrate. Pretreatment methods such as surface activation are required, and targeted adjustments to the electroplating parameters are necessary, such as appropriately reducing the initial current density and extending the electroplating induction period, to allow the metal to better initiate deposition on its surface and form a continuous and robust electroplated layer.

[0075] In one embodiment, the preset electroplating parameters are related to the size of the etched area. The electroplating parameters are adjusted according to the different sizes of the etched area so that the thickness of the metal coating after electroplating is fixed. In this way, the subsequent grinding process can be made more accurate, so as to achieve precise control of the thickness of the metal film.

[0076] Optionally, step S204 above includes the following steps: First, the target grinding depth is determined based on the preset correspondence between the target etching depth and the grinding depth.

[0077] It is worth noting that in the semiconductor manufacturing process, the pre-defined correspondence between the target etching depth and the polishing depth is a crucial step in ensuring that the final semiconductor product achieves the expected structure and performance. This correspondence is set based on the specific design requirements of the chip, the characteristics of each layer of materials, and the consistency of the entire process flow. From a chip design perspective, different functional areas (such as transistor areas and metal interconnect areas) have their own precise requirements for structural dimensions. For example, in transistor manufacturing, structures such as gate trenches formed by etching have specific etching depths. Subsequent polishing operations must ensure that while removing excess material, the final channel length and other key dimensions meet the designed electrical performance specifications. For metal interconnect areas, the etching depth of vias or trenches etched for electroplating filler metal is closely related to the remaining metal layer thickness and dielectric layer thickness after subsequent polishing. These must all meet functional requirements such as signal transmission and electrical isolation.

[0078] For example, in manufacturing a chip with a multilayer metal interconnect structure, the etching process for a dielectric layer involves etching vias for metal filling. The target etching depth is set at 600 nm, determined based on factors such as the spacing between adjacent metal layers and the electrical performance requirements of the vias. After etching, based on a pre-defined correspondence derived from extensive process experiments and experience, it is known that for this type of dielectric layer and the subsequent polishing process (including specific polishing equipment, polishing fluid, polishing pads, etc.), for every 100 nm of dielectric layer etched, approximately 30 nm of dielectric layer thickness must be retained after polishing to ensure good electrical isolation and structural stability. Therefore, according to this correspondence, the target polishing depth can be calculated as (600 - (600 ÷ 100) × 30) = 420 nm. This means that 420 nm of thickness needs to be removed from the etched dielectric layer through polishing, leaving a remaining dielectric layer thickness of 180 nm, which meets the subsequent chip functional and structural requirements.

[0079] Second, the etched area is ground until the grinding depth of the etched area reaches the target grinding depth, thus confirming the completion of semiconductor production.

[0080] In one embodiment, at least one of the grinding parameters, namely grinding pressure, grinding time, grinding flow rate and grinding speed, is adjusted according to the target grinding depth to make the grinding process stable and achieve the expected grinding effect, and to avoid under-grinding or over-grinding.

[0081] Optionally, the semiconductor manufacturing method provided in this disclosure further includes: After grinding is completed, the actual coating depth is determined, which is the metal depth of the first etched area.

[0082] For example, the vertical distance from the surface to the substrate of the polished film can be measured using equipment such as an optical interferometer and a scanning electron microscope. This distance value is determined as the actual film depth. Then, the actual coating depth is determined based on the difference between the actual film depth and the preset perforation depth.

[0083] In one embodiment, the actual coating depth can also be measured by at least one of the following methods: weighing method (calculating the actual coating depth based on the relationship between the density of the coating metal, the coating area, and the mass), profilometry method (measuring using a stylus profilometer or optical profilometer), XRF (X-ray Fluorescence Spectrometer), and elliptic polarization method.

[0084] When the actual coating depth is greater than the preset coating depth, the etched area is subjected to compensatory grinding control so that the actual coating depth reaches the preset coating depth.

[0085] In one implementation, after grinding is completed, the surface flatness and metal film depth of the etched area need to be tested. If they do not meet the process requirements, compensation grinding control is required, such as performing grinding again.

[0086] For example, if the actual coating depth is 50nm greater than the preset coating depth, based on previous grinding rate tests of the metal film material (such as copper film) under the current grinding conditions, assuming that 100nm of metal film can be ground away every 10 minutes, the required compensation grinding time can be roughly estimated to be 5 minutes. At the same time, the grinding pressure should be adjusted appropriately, and the pressure should be reduced appropriately to avoid over-grinding and damage to the underlying structure, for example, from the conventional 200g / cm². 2 Adjust to 150g / cm 2 The grinding fluid flow rate and grinding speed are adjusted accordingly to achieve a precise and stable compensation grinding process.

[0087] During the compensation grinding process, it is also necessary to monitor the grinding status in real time. This can be achieved through various means, such as using optical measurement technology (e.g., using a laser interferometer to monitor changes in the metal film thickness in real time) and electrical measurement methods (indirectly determining the film thickness by measuring relevant electrical parameters). Once it is found that the metal film thickness is close to the preset coating depth, the grinding parameters can be further fine-tuned (e.g., further reducing the grinding pressure, reducing the grinding speed, etc.) to ensure that the actual metal depth can accurately reach the preset coating depth.

[0088] The main function of compensation grinding control is to precisely adjust the thickness of the metal film layer to meet chip design requirements. By removing excess metal material, the electrical performance of structures such as metal interconnects can be optimized, ensuring signal transmission quality and reducing problems such as excessive resistance and signal delay that may result from an excessively thick metal film layer. Simultaneously, precise control of the metal film layer thickness also helps maintain the stability and compatibility of the entire chip structure. For example, in subsequent packaging processes, an appropriate metal film layer thickness ensures good connection and space adaptation between the chip and the packaging material; in multilayer chips, maintaining an appropriate thickness relationship with adjacent dielectric layers and other metal layers ensures electrical isolation, heat dissipation, and the integrity of the overall physical structure, thereby improving chip yield and lifespan, enabling it to function stably and reliably in various electronic devices.

[0089] This supplementary step further improves the quality control aspects of semiconductor manufacturing methods, enhances the ability to control key parameters of the final semiconductor product, and ensures high-quality and high-performance chip manufacturing output.

[0090] This disclosure also provides a semiconductor manufacturing apparatus, see [link to relevant documentation] Figure 4 As shown, the semiconductor manufacturing apparatus 500 includes a deposition module 501, an etching module 502, an electroplating module 503, and a polishing module 504.

[0091] Deposition module 501 is configured to deposit a thin film on the wafer surface according to a preset thin film depth and to define an etched area on the surface of the thin film. Etching module 502 is configured to etch the etching area according to a target etching depth corresponding to the preset film depth; Electroplating module 503 is configured to electroplat the etched area after the etching is completed; The polishing module 504 is configured to polish the etched area according to the target etching depth after the electroplating is completed, so as to complete the production of the semiconductor.

[0092] Optionally, the etching module 502 is configured to: The target etching depth is determined based on the preset film depth and the preset perforation depth; The etching area is etched until the etching depth of the etched area reaches the target etching depth.

[0093] Optionally, the etching module 502 is configured to: Obtain the etching type of the etched area, where the etching type includes trench etching and through-hole etching; A first etching region and a second etching region are determined in the etching region, wherein the first etching region corresponds to the trench etching and the second etching region corresponds to the through-hole etching; The first etched area is etched until the etch depth of the first etched area reaches the target etch depth; and The second etched area is etched until a perforation is formed in the second etched area.

[0094] Optionally, the electroplating module 503 is configured as follows: After the etching is completed, the etched area is electroplated according to preset electroplating parameters.

[0095] Optionally, the grinding module 504 is configured as follows: The target grinding depth is determined based on the preset correspondence between the target etching depth and the grinding depth; The etched area is ground until the grinding depth of the etched area reaches the target grinding depth, thus confirming the completion of semiconductor production.

[0096] Optionally, the grinding module 504 is configured as follows: After the grinding is completed, the actual coating depth is determined, which is the metal depth of the first etched area; If the actual coating depth is greater than the preset coating depth, the etched area is subjected to compensatory grinding control so that the actual coating depth reaches the preset coating depth.

[0097] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0098] This disclosure also provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the semiconductor manufacturing method provided in this disclosure.

[0099] This disclosure also provides a semiconductor manufacturing apparatus, including: A memory on which computer programs are stored; A processor is configured to execute the computer program in the memory to implement the semiconductor manufacturing method provided in this disclosure.

[0100] Figure 5 This is a block diagram illustrating a semiconductor manufacturing apparatus 800 according to an exemplary embodiment. Figure 5 As shown, the semiconductor manufacturing apparatus 800 may include a processor 801 and a memory 802. The semiconductor manufacturing apparatus 800 may also include one or more of a multimedia component 803, an input / output (I / O) interface 804, and a communication component 805.

[0101] The processor 801 controls the overall operation of the semiconductor manufacturing equipment 800 to complete all or part of the steps in the semiconductor manufacturing method described above. The memory 802 stores various types of data to support the operation of the semiconductor manufacturing equipment 800. This data may include, for example, instructions for any application or method operating on the semiconductor manufacturing equipment 800, and application-related data such as contact data, sent and received messages, images, audio, video, etc. The memory 802 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. Multimedia component 803 may include a screen and an audio component. The screen may be, for example, a touchscreen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory 802 or transmitted via communication component 805. The audio component also includes at least one speaker for outputting audio signals. I / O interface 804 provides an interface between processor 801 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual or physical buttons. Communication component 805 is used for wired or wireless communication between the semiconductor manufacturing equipment 800 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, NB-IoT, eMTC, or other 5G technologies, or combinations thereof, is not limited here. Therefore, the corresponding communication component 805 may include: a Wi-Fi module, a Bluetooth module, an NFC module, etc.

[0102] In an exemplary embodiment, the semiconductor manufacturing equipment 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the semiconductor manufacturing method described above.

[0103] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, which, when executed by a processor, implement the steps of the semiconductor manufacturing method described above. For example, the computer-readable storage medium may be the memory 802 including program instructions described above, which may be executed by the processor 801 of the semiconductor manufacturing apparatus 800 to complete the semiconductor manufacturing method described above.

[0104] Figure 6 This is a block diagram illustrating a semiconductor manufacturing apparatus 1900 according to an exemplary embodiment. For example, the semiconductor manufacturing apparatus 1900 may be provided as a server. (Refer to...) Figure 6 The semiconductor manufacturing apparatus 1900 includes processors 1922, which may be one or more, and a memory 1932 for storing computer programs executable by the processors 1922. The computer programs stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processors 1922 may be configured to execute the computer program to perform the semiconductor manufacturing method described above.

[0105] Additionally, the semiconductor manufacturing equipment 1900 may also include a power supply component 1926 and a communication component 1950. The power supply component 1926 can be configured to perform power management of the semiconductor manufacturing equipment 1900, and the communication component 1950 can be configured to enable communication of the semiconductor manufacturing equipment 1900, such as wired or wireless communication. Furthermore, the semiconductor manufacturing equipment 1900 may also include an input / output (I / O) interface 1958. The semiconductor manufacturing equipment 1900 can operate on an operating system stored in memory 1932.

[0106] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, which, when executed by a processor, implement the steps of the semiconductor manufacturing method described above. For example, the non-transitory computer-readable storage medium may be the memory 1932 including program instructions described above, which may be executed by the processor 1922 of the semiconductor manufacturing apparatus 1900 to complete the semiconductor manufacturing method described above.

[0107] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0108] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0109] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor manufacturing method, characterized in that, The method includes: A thin film is deposited on the wafer surface according to a preset thin film depth, and an etching area is defined on the surface of the thin film; The etching region is etched according to the target etching depth corresponding to the preset film depth; After the etching is completed, the etched area is electroplated. After the electroplating is completed, the etched area is ground according to the target etching depth to complete the production of the semiconductor.

2. The method according to claim 1, characterized in that, The step of etching the etching area according to the target etching depth corresponding to the preset thin film depth includes: The target etching depth is determined based on the preset film depth and the preset perforation depth; The etching area is etched until the etching depth of the etched area reaches the target etching depth.

3. The method according to claim 2, characterized in that, The method further includes: Obtain the etching type of the etched area, where the etching type includes trench etching and through-hole etching; A first etching region and a second etching region are determined in the etching region, wherein the first etching region corresponds to the trench etching and the second etching region corresponds to the through-hole etching; The etching of the etched area until the etch depth of the etched area reaches the target etch depth includes: The first etched area is etched until the etch depth of the first etched area reaches the target etch depth; and The second etched area is etched until a perforation is formed in the second etched area.

4. The method according to claim 1, characterized in that, The step of electroplating the etched area after etching is completed includes: After the etching is completed, the etched area is electroplated according to preset electroplating parameters.

5. The method according to claim 1, characterized in that, The step of grinding the etched area according to the target etch depth to complete the semiconductor production includes: The target grinding depth is determined based on the preset correspondence between the target etching depth and the grinding depth; The etched area is ground until the grinding depth of the etched area reaches the target grinding depth, thus confirming the completion of semiconductor production.

6. The method according to claim 3, characterized in that, The method further includes: After the grinding is completed, the actual coating depth is determined, which is the metal depth of the first etched area; If the actual coating depth is greater than the preset coating depth, the etched area is subjected to compensatory grinding control so that the actual coating depth reaches the preset coating depth.

7. A semiconductor manufacturing apparatus, characterized in that, The device includes: The deposition module is configured to deposit a thin film on the wafer surface at a preset film depth and to define an etched area on the surface of the film. The etching module is configured to etch the etching area according to a target etching depth corresponding to the preset film depth; An electroplating module is configured to electroplat the etched area after the etching is completed; A polishing module is configured to polish the etched area according to the target etching depth after the electroplating is completed, so as to complete the production of the semiconductor.

8. The apparatus according to claim 7, characterized in that, The etching module is configured to: The target etching depth is determined based on the preset film depth and the preset perforation depth; The etching area is etched until the etching depth of the etched area reaches the target etching depth.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method described in any one of claims 1-6.

10. A semiconductor manufacturing apparatus, characterized in that, include: A memory on which computer programs are stored; A processor for executing the computer program in the memory to implement the steps of the method according to any one of claims 1-6.

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