Patterning method and patterning system for semiconductor processes

Abstract

This application discloses a patterning method and a patterning system for semiconductor processes. A patterning method for semiconductor processes includes the following steps: (1) forming a differential pattern on a target region using a double-layer photoresist photolithography process, the target region comprising a substrate target layer, a first hard mask layer, a mandrel layer, and a second hard mask layer; (2) using the differential pattern as a mask, etching the second hard mask layer and the mandrel layer to form a mandrel in the mandrel layer; (3) depositing a spacer layer on the target region where the mandrel is formed; (4) etching the horizontal portion of the spacer layer, retaining the vertical portion of the spacer layer near the sidewalls of the mandrel; (5) removing the mandrel, retaining the vertical portion of the spacer layer; and (6) using the vertical portion of the spacer layer as a mask, etching the first hard mask layer and the substrate target layer to form a fin structure of a fin field-effect transistor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor microstructure fabrication technology, and more specifically to a patterning method and patterning system for semiconductor processes. Background Technology

[0002] The rapid development of integrated circuits relies on the development of related manufacturing processes—photolithography technology, which is the highest precision processing technology achievable to date.

[0003] In principle, photolithography refers to the technique of transferring a pattern from a photomask to a substrate using a photoresist (also known as a photoresist film) under illumination. The main process is as follows: First, ultraviolet light passes through the photomask and irradiates the surface of the substrate coated with a thin film of photoresist, causing a chemical reaction in the exposed areas of the photoresist. Then, development technology dissolves and removes the photoresist in the exposed or unexposed areas, allowing the pattern on the photomask to be copied onto the photoresist film. Finally, etching or deposition techniques are used to transfer the pattern onto the substrate. Photoresists can be mainly divided into positive and negative photoresists. Positive photoresists have the following characteristics: their exposed areas undergo a photochemical reaction and dissolve in the developer, while the unexposed areas are insoluble in the developer. Negative photoresists have the following characteristics: their exposed areas are insoluble in the developer due to cross-linking curing or a photochemical reaction, while the unexposed areas are soluble in the developer.

[0004] Photolithography technology is mainly divided into optical lithography based on the exposure source. Common light sources include ultraviolet (UV), deep ultraviolet (DUV), extreme ultraviolet (EUV) light sources, and particle beam lithography. Common particle beam lithography mainly includes X-ray, electron beam, and ion beam lithography.

[0005] Typically, in optical lithography, UV lithography can only achieve a pattern resolution of about one micrometer. While DUV and EUV lithography can achieve higher resolutions, they are expensive. In addition, in particle beam lithography, electron beam lithography and focused ion beam lithography can also improve the resolution to some extent, but they require time-consuming and multi-cycle writing processes, which greatly reduces work efficiency. Summary of the Invention

[0006] It should be understood that the above general description and the following detailed description of the invention are exemplary and illustrative, and are intended to provide further explanation of the invention as described in the claims.

[0007] According to a first aspect of the present invention, a patterning method for semiconductor processes is provided, wherein the method comprises the following steps: (1) forming a differential pattern on a target region using a double-layer photoresist photolithography process, the target region comprising a substrate target layer, a first hard mask layer, a mandrel layer, and a second hard mask layer; (2) etching the second hard mask layer and the mandrel layer using the differential pattern as a mask to form a mandrel in the mandrel layer; (3) depositing a spacer layer on the target region where the mandrel is formed; (4) etching a horizontal portion of the spacer layer while retaining a vertical portion of the spacer layer near the sidewall of the mandrel; (5) removing the mandrel while retaining the vertical portion of the spacer layer; and (6) etching the first hard mask layer and the substrate target layer using the vertical portion of the spacer layer as a mask to form a fin structure of a fin field-effect transistor.

[0008] Further, step (2) includes: using the differential pattern as a mask, etching the second hard mask layer to form a second hard mask pattern; trimming the second hard mask pattern to form a trimmed second hard mask pattern; using the trimmed second hard mask pattern as a mask, etching the mandrel layer to form a mandrel.

[0009] Furthermore, step (5) also includes cutting a portion of the vertical portion of the spacer layer.

[0010] According to a second aspect of the present invention, a patterning method for semiconductor processes is provided, wherein the method comprises the following steps: (1) forming a differential pattern on a target region using a double-layer photoresist photolithography process, the target region comprising a fin structure and a polysilicon layer and a hard mask layer located on the fin structure; (2) etching the hard mask layer using the differential pattern as a mask to form a hard mask pattern; (3) removing the edge portion of the hard mask pattern using a photolithography and etching process to form a mask for a pseudo-gate structure; and (4) etching the polysilicon layer using the mask for the pseudo-gate structure to form a pseudo-gate structure of a fin field-effect transistor.

[0011] Furthermore, step (2) also includes trimming the hard mask pattern.

[0012] According to a third aspect of the present invention, a patterning method for semiconductor processes is provided, wherein the method comprises the following steps: (1) forming a differential pattern on a target region using a double-layer photoresist photolithography process, the target region being composed of a substrate target layer and a hard mask layer located on the substrate target layer; (2) etching the hard mask layer using the differential pattern as a mask to form a hard mask pattern; and (3) etching the substrate target layer using the hard mask pattern as a mask to form a fin structure of a fin field-effect transistor.

[0013] Furthermore, step (2) also includes trimming the hard mask pattern.

[0014] Further, forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (A1) forming a negative photoresist layer on the target area using negative photoresist, and forming a positive photoresist layer on the negative photoresist layer using positive photoresist; (A2) patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern area and a negative pattern area on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern area is larger than the negative pattern area; (A3) developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist in the positive pattern area; (A4) developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

[0015] Further, forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (B1) forming a positive photoresist layer on the target area using positive photoresist, and forming a negative photoresist layer on the positive photoresist layer using negative photoresist; (B2) patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern area and a negative pattern area on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern area is larger than the negative pattern area; (B3) developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist outside the negative pattern area; (B4) developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist at the edge of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

[0016] Further, forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (C1) forming a negative photoresist layer on the target area using negative photoresist, forming a spacer layer on the negative photoresist layer, and forming a positive photoresist layer on the spacer layer using positive photoresist; (C2) patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern area and a negative pattern area on the positive photoresist layer and the negative photoresist layer respectively, wherein the positive pattern area is larger than the negative pattern area; (C3) developing the positive photoresist layer with a positive photoresist developer to remove... (C4) Develop the spacer layer with a spacer developer, or etch the spacer layer using the pattern of the developed positive resist layer as an etch resist mask, so that the pattern of the spacer layer is consistent with the pattern of the developed positive resist layer; (C5) Develop the negative resist layer with a negative resist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

[0017] Further, forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (D1) forming a positive photoresist layer on the target area using a positive photoresist, forming a spacer layer on the positive photoresist layer, and forming a negative photoresist layer on the spacer layer using a negative photoresist; (D2) patterning the negative photoresist layer and the positive photoresist layer to form a positive pattern area and a negative pattern area on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern area is larger than the negative pattern area; (D3) developing the negative photoresist layer with a negative photoresist developer to remove... (D4) The negative photoresist outside the negative pattern area; (D5) The spacer layer is developed with a spacer developer, or the spacer layer is etched using the pattern of the developed negative photoresist layer as an etch resist mask, so that the pattern of the spacer layer is consistent with the pattern of the developed negative photoresist layer; (D6) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist at the edge of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

[0018] Further, patterning the negative resist layer and the positive resist layer to form positive and negative pattern areas on the positive and negative resist layers respectively includes: exposing the positive and negative resist layers under an exposure source using a photomask carrying a template pattern or by focused direct writing, thereby forming positive and negative pattern areas on the positive and negative resist layers respectively.

[0019] According to a fourth aspect of the present invention, a patterning system for semiconductor processes is provided, comprising a differential pattern forming section, a mandrel forming section, a spacer layer deposition section, a spacer layer etching section, a mandrel removal section, and a fin structure forming section, the patterning system being configured to perform the following steps: (1) using the differential pattern forming section, forming a differential pattern on a target region using a double-layer photoresist photolithography process, the target region comprising a substrate target layer, a first hard mask layer, a mandrel layer, and a second hard mask layer; (2) using the mandrel forming section, using the differential pattern as a mask, etching the second hard mask layer and the mandrel layer. (3) Using the spacer layer deposition section, depositing a spacer layer on the target region where the spacer layer is formed; (4) Using the spacer layer etching section, etching the horizontal portion of the spacer layer while retaining the vertical portion of the spacer layer near the sidewall of the spacer layer; (5) Using the spacer removal section, removing the spacer layer while retaining the vertical portion of the spacer layer; and (6) Using the fin structure forming section, using the vertical portion of the spacer layer as a mask, etching the first hard mask layer and the substrate target layer to form the fin structure of the fin field-effect transistor.

[0020] According to a fifth aspect of the present invention, a patterning system for semiconductor processes is provided, comprising a differential pattern forming section, a hard mask pattern forming section, a mask forming section, and a dummy gate structure forming section, the patterning system being configured to perform the following steps: (1) using the differential pattern forming section, forming a differential pattern on a target region using a double-layer photoresist photolithography process, the target region comprising a fin structure and a polysilicon layer and a hard mask layer located on the fin structure; (2) using the hard mask pattern forming section, etching the hard mask layer using the differential pattern as a mask to form a hard mask pattern; (3) using the mask forming section, removing the edge portion of the hard mask pattern using a photolithography and etching process to form a mask for a dummy gate structure; and (4) using the dummy gate structure forming section, etching the polysilicon layer using the mask for the dummy gate structure to form a dummy gate structure for a fin field-effect transistor.

[0021] According to a sixth aspect of the present invention, a patterning system for semiconductor processes is provided, comprising a differential pattern forming section, a hard mask pattern forming section, and a fin structure forming section, the patterning system being configured to perform the following steps: (1) using the differential pattern forming section to form a differential pattern on a target region using a double-layer photoresist photolithography process, the target region being composed of a substrate target layer and a hard mask layer located on the substrate target layer; (2) using the hard mask pattern forming section to etch the hard mask layer using the differential pattern as a mask to form a hard mask pattern; and (3) using the fin structure forming section to etch the substrate target layer using the hard mask pattern as a mask to form a fin structure of a fin field-effect transistor. Attached Figure Description

[0022] The accompanying drawings are included to provide a further understanding of the invention; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the invention and, together with this specification, serve to explain the principles of the invention. In the drawings:

[0023] Figure 1 This is a schematic diagram of the SAQP process in the prior art.

[0024] Figures 2A-2B This is a schematic flowchart illustrating a patterning method for manufacturing fin structures for semiconductor processes using a double-layer photoresist photolithography process combined with SADP process, according to an embodiment of the present disclosure.

[0025] Figures 3A-3D This is a schematic flowchart illustrating the formation of a differential pattern on a target area using a double-layer photoresist photolithography process according to an embodiment of the present disclosure.

[0026] Figure 4 This is a schematic diagram of the process for forming a pseudo-gate structure using the SADP process in the prior art.

[0027] Figure 5 This is a schematic flowchart illustrating a patterning method for manufacturing a pseudo-gate structure for a semiconductor process according to an embodiment of the present disclosure.

[0028] Figure 6 This is a schematic flowchart illustrating a patterning method for manufacturing fin structures for semiconductor processes using a double-layer photoresist photolithography process combined with an etching process, according to an embodiment of the present disclosure. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solution of the present invention, providing detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0030] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure. It should be understood that spatial relative terms are intended to include different orientations of the device used or operated in addition to those shown in the figure. For example, if the device in the figure were flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features.

[0031] Unless otherwise specified, the terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms should be understood to have the meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formalized manner, unless explicitly stated otherwise herein.

[0032] In the semiconductor field, FinFET (Fin Field-Effect Transistor) is a novel type of complementary metal-oxide-semiconductor transistor. In nanoscale FinFET manufacturing, the challenge lies in forming the shape of the fins. The fin size is approximately 0.67 times the minimum gate length. For 22nm process technology, the fin width is 14.67nm, which is far smaller than the smallest size achievable by even the most precise immersion lithography machines. Therefore, fabricating higher-density fin structures has become a key challenge in manufacturing higher-density FinFETs.

[0033] In the formation of FinFETs at 7nm and below, existing solutions typically use SAQP (Self-Aligned Quadruple Patterning) technology to form high-density fin structures by quadrupling the number of lines.

[0034] Figure 1This is a schematic diagram of the SAQP process in the prior art. First, in step 1A, a first hard mask layer 120, a first spindle layer 130, a second hard mask layer 140, a second spindle layer 150, a SOC (Spin-On Carbon) layer 160, and an anti-reflective coating 170 are sequentially coated on the substrate material 110. Photoresist is then patterned on the anti-reflective coating 170 to form a first pattern 182. Next, in step 2A, using the first pattern 182 as a mask, the anti-reflective coating 170, the SOC layer 160, and the second spindle layer 150 are etched to form the second spindle 152. Then, in step 3A, a spacer layer 190 is deposited on the second spindle 152. In step 4A, the horizontal portion of the spacer layer 190 is etched, retaining the vertical portion 192 of the spacer layer 190 near the sidewall of the second spindle 152. In step 5A, the second spindle 152 is removed, retaining the vertical portion 192 of the spacer layer 190. Next, in step 6A, using the vertical portion 192 as a mask, the second hard mask layer 140 and the first mandrel layer 130 are etched to form the second hard mask pattern 142 and the first mandrel 132. In step 7A, the vertical portion 192 and the second hard mask pattern 142 are removed, while the first mandrel 132 is retained. Then, in step 8A, the deposition of the second spacer layer 194 is performed. Finally, in step 9A, the horizontal portion of the second spacer layer 194 is etched, the second vertical portion 196 of the second spacer layer 194 near the sidewall of the first mandrel 132 is retained, and the first mandrel 132 is removed to form a fin-structured mask. However, because the SAQP technology involves multiple thin film deposition and etching processes, especially the ALD (Atomic Layer Deposition) process involved in the deposition of the spacer layer, the cost is high, and the multiple etching steps require precise control, making the process relatively complex.

[0035] Therefore, this disclosure provides a patterning method for semiconductor processes used to fabricate fin structures.

[0036] <Double-layer photoresist lithography + SADP (Self-Aligned Double Patterning) process>

[0037] The patterning method for semiconductor processes disclosed herein includes the following steps:

[0038] (1) A differential pattern is formed on the target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer, a first hard mask layer, a mandrel layer, and a second hard mask layer.

[0039] (2) Using the difference pattern as a mask, the second hard mask layer and the mandrel layer are etched to form a mandrel in the mandrel layer;

[0040] (3) Deposit a spacer layer on the target region where the core is formed;

[0041] (4) Etch the horizontal portion of the spacer layer while retaining the vertical portion of the spacer layer near the sidewall of the mandrel;

[0042] (5) Remove the mandrel, retaining the vertical portion of the spacer layer; and

[0043] (6) Using the vertical portion of the spacer layer as a mask, the first hard mask layer and the substrate target layer are etched to form the fin structure of the fin field-effect transistor.

[0044] In some embodiments, step (2) includes:

[0045] Using the differential pattern as a mask, the second hard mask layer is etched to form the second hard mask pattern;

[0046] The second hard mask pattern is trimmed to form a trimmed second hard mask pattern;

[0047] Using the trimmed second hard mask pattern as a mask, the mandrel layer is etched to form the mandrel.

[0048] In some embodiments, step (5) further includes cutting a portion of the vertical portion of the spacer layer.

[0049] Figures 2A-2B This is a schematic flowchart illustrating a patterning method for manufacturing fin structures for semiconductor processes using a double-layer photoresist photolithography process combined with SADP process, according to an embodiment of the present disclosure.

[0050] <Double-layer photoresist photolithography process>

[0051] like Figure 2A As shown, in step 1B, a target region is prepared. The target region may be composed of a substrate target layer 210, a first hard mask layer 220, a mandrel layer 230, and a second hard mask layer 240. In some embodiments, the target region may further include a first coating layer 250 and a second coating layer 260 located on the second hard mask layer 240. Then, a differential pattern composed of a first photoresist layer 272 and a second photoresist layer 274 is formed on the target region using a double-layer photoresist photolithography process (corresponding to forming a differential pattern on the target region using a double-layer photoresist photolithography process, wherein the target region is composed of a substrate target layer, a first hard mask layer, a mandrel layer, and a second hard mask layer). Although a differential pattern composed of a first photoresist layer 272 and a second photoresist layer 274 is used as an example here, other differential patterns may be formed in other embodiments. See below. Figures 3A-3DA further description is given of the process of forming differential patterns using a double-layer photoresist lithography process.

[0052] As an example, the substrate target layer 210 may be a silicon layer, the first coating 250 may be a SOC layer, and the second coating 260 may be an anti-reflection coating, such as a silicon anti-reflection coating, but the present invention is not limited thereto. Alternatively, the target area may not include the above-mentioned first coating 250 and second coating 260, and is not limited to the above example.

[0053] <SADP process>

[0054] In step 2B, the target area is etched using the differential pattern as a mask until it stops at the first hard mask layer 2 to form a mandrel 232 in the mandrel layer 230 (corresponding to etching the second hard mask layer and the mandrel layer using the differential pattern as a mask to form a mandrel in the mandrel layer).

[0055] Optionally, in some embodiments, step 2B may include the following steps: In step 2B-1, the target area is etched using the differential pattern as a mask until it stops at the mandrel layer 230 to form a second hard mask pattern in the second hard mask layer 240 (corresponding to etching the second hard mask layer using the differential pattern as a mask to form a second hard mask pattern). Then, in step 2B-2, the second hard mask pattern 242 is trimmed to further reduce the size of the second hard mask pattern 242 (corresponding to trimming the second hard mask pattern to form a trimmed second hard mask pattern). Finally, in step 2B-3, the target area is etched using the trimmed second hard mask pattern 242 as a mask until it stops at the first hard mask layer 220 to form a mandrel 232 in the mandrel layer 230 (corresponding to etching the mandrel layer using the trimmed second hard mask pattern as a mask to form a mandrel).

[0056] In step 3B, an interlayer 280 is deposited on the mandrel 232 (corresponding to depositing an interlayer on the target area where the mandrel is formed). Regarding the method of depositing the interlayer, for example, ALD (atomic deposition) or the like can be used. The interlayer may be, for example, a metal oxide, silicon oxide, silicon metal oxide, metal nitride, silicon nitride, or silicon metal nitride, and the present invention is not particularly limited.

[0057] In step 4B, the horizontal portion of the spacer layer 280 is etched, while the vertical portion 282 of the spacer layer 280 near the sidewall of the mandrel 232 is retained (corresponding to etching the horizontal portion of the spacer layer while retaining the vertical portion of the spacer layer near the sidewall of the mandrel). For example, the horizontal portion of the spacer layer can be etched using a process such as dry etching (anisotropic etching). Then, the mandrel 232 is removed, while the vertical portion 282 of the spacer layer 280 is retained (corresponding to removing the mandrel while retaining the vertical portion of the spacer layer). For example, the mandrel can be etched using a process such as dry etching.

[0058] like Figure 2B As shown, in step 5B, using the vertical portion 282 of the spacer layer 280 as a mask, the first hard mask layer 220 and the substrate target layer 210 are etched to form the fin structure of the fin field-effect transistor (corresponding to using the vertical portion of the spacer layer as a mask to etch the first hard mask layer and the substrate target layer to form the fin structure of the fin field-effect transistor). As an example, a dry etching process can be used for etching.

[0059] Alternatively, in some embodiments, in step 5B', a portion of the vertical portion 282 of the spacer layer 280 is cut, retaining only the vertical portion 282 at the desired location (corresponding to cutting a portion of the vertical portion of the spacer layer). Then, in step 6B', using the remaining vertical portion 282 as a mask, the first hard mask layer 220 and the substrate target layer 210 are etched to form the fin structure of the fin field-effect transistor.

[0060] Figures 3A-3D This is a schematic flowchart illustrating the formation of a differential pattern on a target area using a double-layer photoresist photolithography process according to an embodiment of the present disclosure.

[0061]

[0062] Figure 3A This is a schematic diagram of a two-layer photoresist photolithography process, where the negative resist is applied first, followed by the positive resist. In the accompanying figures, identical or equivalent parts are labeled with the same symbols for explanation.

[0063] First, in step 1C, a layer of negative photoresist 340A (i.e., negative resist layer) is spin-coated onto the target area and dried. Then, a layer of positive photoresist 350A (i.e., positive resist layer) is spin-coated onto the negative photoresist 340A and dried (corresponding to forming a negative resist layer on the target area using negative photoresist and forming a positive resist layer on the negative resist layer using positive photoresist).

[0064] The target area is composed of a substrate target layer 310A and a substrate coating (first coating 320A and second coating 330A) located on the substrate target layer 310A. However, the present invention is not limited to this, and the first coating 320A and the second coating 330A may be omitted depending on the circumstances. Furthermore, as the first coating 320A, a hard mask SOC may be used, and as the second coating 330A, an anti-reflective coating SiARC may be used. However, the present invention is not limited to this.

[0065] Following step 1C, in step 2C, under an exposure source, two layers of photoresist 340A and 350A are exposed using a photomask carrying a template pattern or by focused direct writing (an example of photomask 360A is shown in the figure). After exposure, exposure patterns 342A and 352A (i.e., negative pattern area and positive pattern area) of different sizes are formed on the negative photoresist 340A and positive photoresist 350A, respectively, and then dried (corresponding to patterning the negative and positive photoresist layers, thereby forming positive and negative pattern areas on the positive and negative photoresist layers, respectively, wherein the positive pattern area is larger than the negative pattern area).

[0066] The exposure source includes ultraviolet light, deep ultraviolet light, extreme ultraviolet light, ion beam, electron beam, or X-rays. As an example, the wavelength of the exposure source can be 1-500 nm, and the drying temperature after exposure can be 30-300 °C. Further, the wavelength of the exposure source can be 350-400 nm, and the drying temperature after exposure can be 95-105 °C.

[0067] Focused direct writing includes ultraviolet light direct writing, deep ultraviolet light direct writing, extreme ultraviolet light direct writing, ion beam direct writing, electron beam direct writing, or X-ray direct writing. As an example, the feature linewidth or feature size of the template pattern can be 2 nm to 1000 μm. Further, the feature linewidth or feature size of the template pattern can be 2 nm to 1 μm.

[0068] After step 2C, in step 3C, the positive photoresist is developed with a positive photoresist developer (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist in the positive pattern area); then, in step 4C, the negative photoresist is controlled to develop with a negative photoresist developer, washing away only the edge portion of the exposure pattern 342A on the negative photoresist and exposing the target area, thereby converting the template pattern into a contour line pattern (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern). Therefore, the embodiments of this disclosure utilize positive and negative photoresists to produce different development results under the same illumination conditions. The positive photoresist exposure area is removed after development to form a groove of size CD1, while the negative photoresist exposure area is retained after development to form a protrusion of size CD2. By utilizing the difference between CD1 and CD2, a narrow groove with a size of (CD1-CD2) / 2 can be formed in a self-aligned manner, thus exceeding the original photolithography resolution and achieving pattern multiplication.

[0069] Then, returning to step 1B, the previously described method can be used to... Figure 3A The resulting differential pattern is used as a mask for etching, thereby forming a raised pattern on the coating of the target area (i.e., the mandrel in the SADP process).

[0070]

[0071] Figure 3B This is a schematic diagram of the double-layer photoresist photolithography process, which involves applying positive resist first and then negative resist.

[0072] The above description illustrates an example of using a double-layer photoresist lithography process, first applying negative resist then positive resist, to form bumps and thus double the line density; however, the present invention is not limited thereto. The present invention can also employ a double-layer photoresist lithography process, first applying positive resist then negative resist, to form the mandrel (bump pattern) used in subsequent SADP processes.

[0073] Figure 3B In the middle, the pattern of the photomask and Figure 3A The pattern of the mask is different, that is, the present invention does not have a particular limitation on the pattern of the mask.

[0074] First, in step 1D, a layer of positive photoresist 350B (i.e., positive photoresist layer) is spin-coated onto the target area and dried. Then, a layer of negative photoresist 340B (i.e., negative photoresist layer) that matches the positive photoresist 350B is spin-coated onto the positive photoresist 350B and dried (corresponding to forming a positive photoresist layer on the target area using positive photoresist and forming a negative photoresist layer on the positive photoresist layer using negative photoresist).

[0075] The target area is composed of a substrate target layer 310B and a substrate coating (first coating 320B and second coating 330B) located on the substrate target layer 310B. However, the present invention is not limited to this, and the first coating 320B and the second coating 330B may be omitted depending on the circumstances. Furthermore, as the first coating 320B, a hard mask SOC may be used, and as the second coating 330B, an anti-reflective coating SiARC may be used, but the present invention is not limited to this.

[0076] Following step 1D, in step 2D, under an exposure source, two layers of photoresist 340B and 350B are exposed using a photomask carrying a template pattern or by focused direct writing (an example of photomask 360B is shown in the figure). After exposure, exposure patterns 342B and 352B of different sizes (i.e., negative pattern area and positive pattern area) are formed on the negative photoresist 340B and positive photoresist 350B, respectively, and then dried (corresponding to patterning the negative and positive photoresist layers, thereby forming positive and negative pattern areas on the positive and negative photoresist layers, respectively, wherein the positive pattern area is larger than the negative pattern area).

[0077] Following step 2D, in step 3D, the negative photoresist is developed using a negative photoresist developer (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove the negative photoresist outside the negative pattern area); then, in step 4D, the positive photoresist is controlled to develop using a positive photoresist developer, washing away only the edge portion of the exposed pattern 352B on the positive photoresist and exposing the target area, thereby converting the template pattern into a contour line pattern (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist at the edge portion of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern). Therefore, the embodiments of this disclosure utilize positive and negative photoresists to produce different development results under the same illumination conditions. The negative photoresist exposure area is retained after development, forming a groove of size CD1. The positive photoresist exposure area is removed only at the edge after development, forming a protrusion of size CD2. By utilizing the difference between CD1 and CD2, a narrow groove can be formed in self-alignment with a size of (CD1-CD2) / 2. Therefore, it can exceed the original photolithography resolution and achieve pattern multiplication.

[0078] Then, returning to step 1B, the previously described method can be used to... Figure 3B The resulting differential pattern is used as a mask for etching, thereby forming a raised pattern on the coating of the target area (i.e., the mandrel in the SADP process).

[0079] <A two-layer photoresist lithography process consisting of a negative resist layer, a spacer layer, and a positive resist layer>

[0080] Figure 3C This is a schematic diagram of a two-layer photoresist photolithography process consisting of a negative resist layer, a spacer layer, and a positive resist layer.

[0081] The above description illustrates examples of using a double-layer photoresist lithography process with negative resist followed by positive resist, and a double-layer photoresist lithography process with positive resist followed by negative resist, to form bumps and thus double the line density. However, the present invention is not limited to these examples. The present invention can also use a double-layer photoresist lithography process with negative resist + spacer + positive resist to form the mandrel (bump pattern) used in the subsequent SADP process.

[0082] Figure 3C In the middle, the pattern of the photomask and Figure 3A The pattern of the mask is different, that is, the present invention does not have a particular limitation on the pattern of the mask.

[0083] First, in step 1E, a layer of negative photoresist 340C (i.e., negative resist layer) is spin-coated onto the target area and dried; then, a spacer film 370C is coated onto the negative photoresist 340C; then, a layer of positive photoresist 350C (i.e., positive resist layer) that matches the negative photoresist 340C is spin-coated onto the spacer film 370C and dried (corresponding to forming a negative resist layer on the target area using negative photoresist, forming a spacer layer on the negative resist layer, and forming a positive resist layer on the spacer layer using positive photoresist).

[0084] The target area is composed of a substrate target layer 310C and a substrate coating (first coating 320C and second coating 330C) located on the substrate target layer 310C. However, the present invention is not limited to this, and the first coating 320C and the second coating 330C may be omitted depending on the circumstances. Furthermore, as the first coating 320C, a hard mask SOC may be used, and as the second coating 330C, an anti-reflective coating SiARC may be used, but the present invention is not limited to this.

[0085] Following step 1E, under an exposure source, two layers of photoresist 340C and 350C are exposed using a photomask carrying a template pattern or by focused direct writing. After exposure, exposure patterns (i.e., negative pattern areas and positive pattern areas) of different sizes are formed on the negative photoresist 340C and the positive photoresist 350C, respectively, and then dried (corresponding to patterning the negative and positive photoresist layers, thereby forming positive and negative pattern areas on the positive and negative photoresist layers, respectively, wherein the positive pattern area is larger than the negative pattern area). This exposure process is similar to... Figure 3A Step 2C is similar, so repeated explanations are omitted here.

[0086] After exposure, in step 2E, the positive photoresist is developed using a positive photoresist developer (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist from the positive pattern area); then, in step 3E, the interlayer film is developed using a spacer film developer, or the interlayer film is etched using the pattern of the developed positive photoresist as an etch resist mask, so that the pattern of the interlayer film is consistent with the pattern of the developed positive photoresist (corresponding to developing the interlayer with an interlayer developer, or etching the interlayer using the pattern of the developed positive photoresist layer as an etch resist mask). Etching is performed to make the pattern of the spacer layer consistent with the pattern of the developed positive photoresist layer; then, in step 4E, the negative photoresist is controlled to develop with negative photoresist developer, washing away only the edge portion of the exposed pattern on the negative photoresist and exposing the target area, thereby converting the template pattern into a contour line pattern (corresponding to developing the negative photoresist layer with negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern).

[0087] By coating a separator film between two layers of photoresist, the dissolution of the two layers of photoresist during the coating process can be avoided or reduced.

[0088] Then, returning to step 1B, the previously described method can be used to... Figure 3C The resulting differential pattern is used as a mask for etching, thereby forming a raised pattern on the coating of the target area (i.e., the mandrel in the SADP process).

[0089] <A two-layer photoresist lithography process consisting of a positive resist layer, a spacer layer, and a negative resist layer>

[0090] Figure 3D This is a schematic diagram of a two-layer photoresist photolithography process consisting of a positive resist layer, a spacer layer, and a negative resist layer.

[0091] The above description illustrates examples of using a double-layer photoresist lithography process (negative resist followed by positive resist), a double-layer photoresist lithography process (positive resist followed by negative resist), and a double-layer photoresist lithography process (negative resist + spacer + positive resist) to form bumps and thus double the line density. However, the present invention is not limited to these methods. The present invention can also use a double-layer photoresist lithography process (positive resist + spacer + negative resist) to form the mandrel (bump pattern) used in subsequent SADP processes.

[0092] Figure 3D In the middle, the pattern of the photomask and Figure 3A The pattern of the mask is different, that is, the present invention does not have a particular limitation on the pattern of the mask.

[0093] First, in step 1F, a layer of positive photoresist 350D (i.e., positive resist layer) is spin-coated onto the target area and dried; then, a spacer film 370D is coated onto the positive photoresist 350D; then, a layer of negative photoresist 340D (i.e., negative resist layer) that matches the positive photoresist 350D is spin-coated onto the spacer film 370D and dried (corresponding to forming a positive resist layer on the target area using positive photoresist, forming a spacer layer on the positive resist layer, and forming a negative resist layer on the spacer layer using negative photoresist).

[0094] The target area is composed of a substrate target layer 310D and a substrate coating layer (first coating layer 320D and second coating layer 330D) located on the substrate target layer 310D. However, the present invention is not limited to this, and the first coating layer 320D and the second coating layer 330D may be omitted depending on the circumstances. Furthermore, a hard mask SOC may be used as the first coating layer 320D, and an anti-reflective coating SiARC may be used as the second coating layer 330D, but the present invention is not limited to this.

[0095] Following step 1F, under an exposure source, two layers of photoresist 340D and 350D are exposed using a photomask carrying a template pattern or by focused direct writing. After exposure, exposure patterns (i.e., negative pattern areas and positive pattern areas) of different sizes are formed on the negative photoresist 340D and the positive photoresist 350D, respectively, and then dried (corresponding to patterning the negative and positive photoresist layers, thereby forming positive and negative pattern areas on the positive and negative photoresist layers, respectively, wherein the positive pattern area is larger than the negative pattern area). This exposure process is similar to... Figure 3B Step 2D is similar, so repeated explanations are omitted here.

[0096] After exposure, in step 2F, the negative photoresist is developed using a negative photoresist developer (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist outside the negative pattern area); then, in step 3F, the interlayer film is developed using a spacer film developer, or the interlayer film is etched using the pattern of the developed negative photoresist as an etch resist mask, so that the pattern of the interlayer film is consistent with the pattern of the developed negative photoresist (corresponding to developing the interlayer with an interlayer developer, or etching the interlayer using the pattern of the developed negative photoresist layer as an etch resist mask). Etching is performed to make the pattern of the spacer layer consistent with the pattern of the developed negative photoresist layer; then, in step 4F, the positive photoresist is controlled to develop with positive photoresist developer, washing away only the edge portions of the exposed pattern on the positive photoresist and exposing the target area, thereby converting the template pattern into a contour line pattern (corresponding to developing the positive photoresist layer with positive photoresist developer to remove the positive photoresist at the edge portions of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern).

[0097] By coating a separator film between two layers of photoresist, the dissolution of the two layers of photoresist during the coating process can be avoided or reduced.

[0098] Then, returning to step 1B, the previously described method can be used to... Figure 3D The resulting differential pattern is used as a mask for etching, thereby forming a raised pattern on the coating of the target area (i.e., the mandrel in the SADP process).

[0099] Furthermore, in this invention, based on the double-layer photoresist photolithography process, it is not limited to performing a single SADP, but can also perform two or more SADPs (i.e., SAMP (Self-Aligned Multi Patterning), such as SAQP, SAOP (Self-Aligned Octuple Patterning), etc.) to achieve higher resolution.

[0100] Therefore, this disclosure organically combines a double-layer photoresist lithography process, which utilizes double-layer photoresist to achieve doubled line density, with the SADP process, thereby achieving a further increase in pattern density and a further reduction in pattern size. Specifically, by utilizing the different responses of positive and negative photoresists (positive and negative photoresists) to light sources and the different exposure energies obtained during exposure, and by leveraging the difference in pattern size after actual development using matched positive and negative photoresists, a contour line pattern based on the original mask pattern features is obtained. Since the linewidth of this contour line pattern is smaller than the linewidth of the original mask pattern features, a doubling of line density is achieved. Simultaneously with the doubling of line density, the groove size between lines is also doubled. Therefore, during the further transfer of the contour line pattern to the target area by combining an etching process targeting the target area, the etching process can further widen the groove size between lines, resulting in a narrower mandrel size formed by etching for the SADP process, enabling the formation of a higher-density fin structure for fin field-effect transistors.

[0101] Compared with the existing SAQP process, this disclosure reduces one SADP process while still being able to form a fin structure with the same dimensions as the SAQP technology. This means that the mandrel deposition process, the spacer layer deposition process using the ALD process, the spacer layer etch-back process, and the mandrel removal process are all eliminated. This greatly simplifies the process flow and saves costs, thereby enabling the formation of higher density FinFET structures with higher efficiency, lower cost, and simpler operation.

[0102]

[0103] Each step in the patterning method for semiconductor processes of the present invention can be implemented by each component in the patterning system for semiconductor processes.

[0104] This invention provides a patterning system for semiconductor processes, comprising a differential patterning section, a mandrel forming section, a spacer layer deposition section, a spacer layer etching section, a mandrel removal section, and a fin structure forming section. The patterning system is used to perform the following steps:

[0105] (1) Using a differential pattern forming unit, a differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer, a first hard mask layer, a mandrel layer, and a second hard mask layer.

[0106] (2) Using the mandrel forming part, the second hard mask layer and the mandrel layer are etched with the differential pattern as a mask to form a mandrel in the mandrel layer;

[0107] (3) Using the spacer layer deposition section, a spacer layer is deposited on the target area where the mandrel is formed;

[0108] (4) Using the spacer etching section, the horizontal portion of the spacer layer is etched, while the vertical portion of the spacer layer near the sidewall of the mandrel is retained;

[0109] (5) Using the mandrel removal section, remove the mandrel, retaining the vertical portion of the spacer layer; and

[0110] (6) Using the fin structure forming part, with the vertical portion of the spacer layer as a mask, the first hard mask layer and the substrate target layer are etched to form the fin structure of the fin field-effect transistor.

[0111] In the process of forming 7nm and below FinFETs, after forming the fin structure, a dummy gate structure needs to be fabricated on top of the fin structure in order to form the final gate structure. Existing solutions typically use the SADP process to form a high-density dummy gate structure by achieving line multiplication.

[0112] Figure 4 This is a schematic diagram of the process for forming a pseudo-gate structure using the SADP process in the prior art. First, in step 1G, a polysilicon layer 410, a hard mask layer 420, a mandrel layer 430, a SOC layer 440, and an anti-reflective coating 450 are sequentially coated on the fin structure. Photoresist is then patterned on the anti-reflective coating 450 to form a first pattern 462. Next, in step 2G, using the first pattern 462 as a mask, the anti-reflective coating 450, the SOC layer 440, and the mandrel layer 430 are etched to form the mandrel 432. Then, in step 3G, a spacer layer 470 is deposited on the mandrel 432. In step 4G, the horizontal portion of the spacer layer 470 is etched, retaining the vertical portion 472 of the spacer layer 470 near the sidewalls of the mandrel 432. In step 5G, the mandrel 432 is removed, retaining the vertical portion 472 of the spacer layer 470. Finally, in step 6G, the hard mask layer 420 and the polysilicon layer 410 are etched using the vertical portion 472 as a mask to form a pseudo-gate structure above the shallow trench isolation (STI) and fin structure. However, since SADP technology involves thin film deposition and etching processes, the ALD process is involved in the deposition of the spacer layer, resulting in high costs, and the multiple etching steps require precise control, making the process relatively complex.

[0113] Therefore, this disclosure provides a patterning method for semiconductor processes to fabricate pseudo-gate structures.

[0114] <Dual-layer photoresist photolithography process + etching process>

[0115] The patterning method for semiconductor processes disclosed herein includes the following steps:

[0116] (1) A differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a fin structure and a polysilicon layer and a hard mask layer located on the fin structure.

[0117] (2) Using the difference pattern as a mask, the hard mask layer is etched to form a hard mask pattern;

[0118] (3) Using photolithography and etching processes, the edge portions of the hard mask pattern are removed to form a mask with a pseudo-gate structure; and

[0119] (4) Using the mask of the pseudo-gate structure, the polysilicon layer is etched to form the pseudo-gate structure of the fin field-effect transistor.

[0120] In some embodiments, step (2) further includes trimming the hard mask pattern.

[0121] Figure 5 This is a schematic flowchart illustrating a patterning method for manufacturing a pseudo-gate structure for a semiconductor process according to an embodiment of the present disclosure.

[0122] <Double-layer photoresist photolithography process>

[0123] In step 1H, a target region is prepared. The target region may consist of a fin structure and a polysilicon layer 510 and a hard mask layer 520 located on the fin structure. In some embodiments, the target region may further include a first coating layer 530 and a second coating layer 540 located on the hard mask layer 520. Then, a differential pattern consisting of a first photoresist layer 552 and a second photoresist layer 554 is formed on the target region using a double-layer photoresist photolithography process (corresponding to the formation of a differential pattern on the target region using a double-layer photoresist photolithography process, wherein the target region consists of a fin structure and a polysilicon layer and a hard mask layer located on the fin structure). The left side of the figure is a cross-sectional view of the formed structure along the dashed line Y, and the right side of the figure is a cross-sectional view of the formed structure along the dashed line X. Although a differential pattern consisting of a first photoresist layer 552 and a second photoresist layer 554 is used as an example here, other differential patterns may be formed in other embodiments. (See above for reference.) Figures 3A-3D The process of forming differential patterns using a double-layer photoresist photolithography process is described in detail, so repeated explanations are omitted here.

[0124] As an example, the first coating 530 may be a SOC layer, and the second coating 540 may be an anti-reflective coating, such as a silicon anti-reflective coating, but the invention is not limited thereto. Alternatively, the target area may not include the first coating 530 and the second coating 540 described above, and is not limited to the above example.

[0125] <Etching Process>

[0126] In step 2H, the target area is etched using the differential pattern as a mask until it stops at the polysilicon layer 510, to form a hard mask pattern 522 in the hard mask layer 520 (corresponding to etching the hard mask layer using the differential pattern as a mask to form the hard mask pattern). The top of the figure is a top view of the formed structure.

[0127] Optionally, in some embodiments, the method may further include step 2H-2. After completing step 2H, in step 2H-2, the hard mask pattern 522 is trimmed to further reduce the size of the hard mask pattern 522 (corresponding to trimming the hard mask pattern).

[0128] In step 3H, a SOC layer, an anti-reflective coating, and photoresist are coated on the hard mask pattern 522. The photoresist is exposed and developed to form a photolithographic pattern. Then, the anti-reflective coating and the SOC layer are etched using the photolithographic pattern as a mask to transfer the pattern to the hard mask pattern 522, forming a mask 524 for a pseudo-gate structure. This step can remove the edge portions of the hard mask pattern 522 indicated by the dashed box, so that the pseudo-gate structure is ultimately formed only at the desired location in the polysilicon layer 510 (corresponding to removing the edge portions of the hard mask pattern to form the pseudo-gate structure using photolithography and etching processes).

[0129] In step 4H, the polysilicon layer 510 is etched using a mask 524 with a pseudo-gate structure to form a pseudo-gate structure for a fin field-effect transistor (corresponding to etching the polysilicon layer using the mask with the pseudo-gate structure to form a pseudo-gate structure for a fin field-effect transistor). For example, the polysilicon layer can be etched using processes such as dry etching.

[0130] Therefore, this disclosure organically combines a double-layer photoresist photolithography process to achieve a doubling of line density with an etching process, thereby further increasing the pattern density and further miniaturizing the pattern size. During the process of further transferring the contour-line pattern to the target area by combining an etching process targeting the target area, the etching process can further widen the groove size between the lines, making the mask pattern formed by the etching for the pseudo-gate structure even narrower, thus enabling the formation of a higher-density fin field-effect transistor pseudo-gate structure.

[0131] Compared with the existing SADP process, this disclosure reduces the steps of mandrel deposition, spacer deposition using ALD process, spacer etch-back process, and mandrel removal process while forming a pseudo-gate structure with the same dimensions as SADP technology. This greatly simplifies the process flow and saves costs, thereby enabling the formation of higher density FinFET structures with higher efficiency, lower cost, and simpler operation.

[0132] Patterning systems for semiconductor processes used to fabricate pseudo-gate structures.

[0133] Each step in the patterning method for semiconductor processes of the present invention can be implemented by each component in the patterning system for semiconductor processes.

[0134] This invention provides a patterning system for semiconductor processes, including a differential pattern forming section, a hard mask pattern forming section, a mask forming section, and a dummy gate structure forming section. The patterning system is used to perform the following steps:

[0135] (1) Using a differential pattern forming unit, a differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a fin structure and a polysilicon layer and a hard mask layer located on the fin structure.

[0136] (2) Using a hard mask pattern forming unit, the hard mask layer is etched to form a hard mask pattern using the differential pattern as a mask;

[0137] (3) Using a mask forming unit, photolithography and etching processes are employed to remove the edge portions of the hard mask pattern to form a mask with a pseudo-gate structure; and

[0138] (4) Using a pseudo-gate structure forming part, the polysilicon layer is etched using the mask of the pseudo-gate structure to form a pseudo-gate structure for a fin field-effect transistor.

[0139] In the formation of fin structures for FinFETs above 7nm, existing methods typically use SADP (Self-Device Processing) to form the fin structures. However, SADP has drawbacks such as high cost and complex process.

[0140] Therefore, this disclosure provides another patterning method for semiconductor processes, used to fabricate fin structures.

[0141] <Dual-layer photoresist photolithography process + etching process>

[0142] The patterning method for semiconductor processes disclosed herein includes the following steps:

[0143] (1) A differential pattern is formed on a target area using a double-layer photoresist photolithography process, wherein the target area is composed of a substrate target layer and a hard mask layer located on the substrate target layer;

[0144] (2) Using the difference pattern as a mask, the hard mask layer is etched to form a hard mask pattern; and

[0145] (3) Using the hard mask pattern as a mask, the substrate target layer is etched to form the fin structure of the fin field-effect transistor.

[0146] In some embodiments, step (2) further includes trimming the hard mask pattern.

[0147] Figure 6 This is a schematic flowchart illustrating a patterning method for manufacturing fin structures for semiconductor processes using a double-layer photoresist photolithography process combined with an etching process, according to an embodiment of the present disclosure.

[0148] <Double-layer photoresist photolithography process>

[0149] In step 1I, a target region is prepared. The target region may be composed of a substrate target layer 610 and a hard mask layer 620. In some embodiments, the target region may further include a first coating layer 630 and a second coating layer 640 located on the hard mask layer 620. Then, a differential pattern composed of a first photoresist layer 652 and a second photoresist layer 654 is formed on the target region using a double-layer photoresist photolithography process (corresponding to forming a differential pattern on the target region using a double-layer photoresist photolithography process, wherein the target region is composed of a substrate target layer and a hard mask layer located on the substrate target layer). Although a differential pattern composed of a first photoresist layer 652 and a second photoresist layer 654 is used as an example here, other differential patterns may be formed in other embodiments. (See above for reference.) Figures 3A-3D The process of forming differential patterns using a double-layer photoresist photolithography process is described in detail, so repeated explanations are omitted here.

[0150] As an example, the substrate target layer 610 may be a silicon layer, the first coating 630 may be a SOC layer, and the second coating 640 may be an anti-reflective coating, such as a silicon anti-reflective coating, but the present invention is not limited thereto. Alternatively, the target area may not include the first coating 630 and the second coating 640 described above, and is not limited to the above example.

[0151] <Etching Process>

[0152] In step 2I, the target area is etched using the differential pattern as a mask until it stops at the substrate target layer 610, so as to form a hard mask pattern 622 in the hard mask layer 620 (corresponding to etching the hard mask layer using the differential pattern as a mask to form a hard mask pattern).

[0153] Optionally, in some embodiments, the method may further include step 2I-2. After completing step 2I, in step 2I-2, the hard mask pattern 622 is trimmed to further reduce the size of the hard mask pattern 622 (corresponding to trimming the hard mask pattern).

[0154] In some embodiments, after step 2I, a portion of the hard mask pattern 622 may be cut off, retaining only the hard mask pattern 622 at the desired location.

[0155] In step 3I, the substrate target layer 610 is etched using the hard mask pattern 622 as a mask to form the fin structure of the fin field-effect transistor (corresponding to etching the substrate target layer using the hard mask pattern as a mask to form the fin structure of the fin field-effect transistor).

[0156] Therefore, this disclosure organically combines a double-layer photoresist photolithography process to achieve a doubling of line density with an etching process, thereby further increasing the pattern density and further miniaturizing the pattern size. During the process of further transferring the contour pattern to the target area by combining an etching process targeting the target area, the etching process can further widen the groove size between the lines, making the mask pattern formed by the etching for the fin structure even narrower, thus enabling the formation of a higher-density fin structure for fin field-effect transistors.

[0157] Compared with the existing SADP process, this disclosure reduces the steps of mandrel deposition, spacer deposition using ALD process, spacer etch-back process, and mandrel removal process while still being able to form fin structures with the same dimensions as SADP technology. This greatly simplifies the process flow and saves costs, thereby enabling the formation of higher density FinFET structures with higher efficiency, lower cost, and simpler operation.

[0158]

[0159] Each step in the patterning method for semiconductor processes of the present invention can be implemented by each component in the patterning system for semiconductor processes.

[0160] This invention provides a patterning system for semiconductor processes, including a differential patterning section, a hard mask patterning section, and a fin structure forming section. The patterning system is used to perform the following steps:

[0161] (1) Using a differential pattern forming unit, a differential pattern is formed on a target area using a double-layer photoresist photolithography process, wherein the target area is composed of a substrate target layer and a hard mask layer located on the substrate target layer;

[0162] (2) Using a hard mask pattern forming unit, with the differential pattern as a mask, the hard mask layer is etched to form a hard mask pattern; and

[0163] (3) Using the fin structure forming part, the hard mask pattern is used as a mask to etch the substrate target layer to form the fin structure of the fin field-effect transistor.

[0164] Furthermore, this disclosure provides a method for manufacturing a FinFET structure, which forms a fin structure using any of the above-described patterning methods for manufacturing fin structures in semiconductor processes, and forms a pseudo-gate structure on the fin structure using any of the above-described patterning methods for manufacturing pseudo-gate structures in semiconductor processes.

[0165] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular conditions or materials to the teachings of the various embodiments of the invention without departing from the scope of the invention. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of the invention, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A patterning method for semiconductor processes, characterized in that, The method includes the following steps: (1) A differential pattern is formed on the target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer, a first hard mask layer, a mandrel layer, and a second hard mask layer. (2) Using the difference pattern as a mask, the second hard mask layer and the mandrel layer are etched to form a mandrel in the mandrel layer; (3) Deposit a spacer layer on the target region where the core is formed; (4) Etch the horizontal portion of the spacer layer while retaining the vertical portion of the spacer layer near the sidewall of the mandrel; (5) Remove the mandrel, retaining the vertical portion of the spacer layer; and (6) Using the vertical portion of the spacer layer as a mask, the first hard mask layer and the substrate target layer are etched to form the fin structure of the fin field-effect transistor.

2. The patterning method for semiconductor processes according to claim 1, characterized in that, Step (2) includes: Using the differential pattern as a mask, the second hard mask layer is etched to form the second hard mask pattern; The second hard mask pattern is trimmed to form a trimmed second hard mask pattern; Using the trimmed second hard mask pattern as a mask, the mandrel layer is etched to form the mandrel.

3. The patterning method for semiconductor processes according to claim 1, characterized in that, Step (5) also includes: A portion of the vertical section of the spacer layer is cut.

4. A patterning method for semiconductor processes, characterized in that, The method includes the following steps: (1) A differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a fin structure and a polysilicon layer and a hard mask layer located on the fin structure. (2) Using the difference pattern as a mask, the hard mask layer is etched to form a hard mask pattern; (3) Using photolithography and etching processes, the edge portions of the hard mask pattern are removed to form a mask with a pseudo-gate structure; and (4) Using the mask of the pseudo-gate structure, the polysilicon layer is etched to form the pseudo-gate structure of the fin field-effect transistor.

5. The patterning method for semiconductor processes according to claim 4, characterized in that, Step (2) also includes: The hard mask pattern is trimmed.

6. A patterning method for semiconductor processes, characterized in that, The method includes the following steps: (1) A differential pattern is formed on a target area using a double-layer photoresist photolithography process, wherein the target area is composed of a substrate target layer and a hard mask layer located on the substrate target layer; (2) Using the difference pattern as a mask, the hard mask layer is etched to form a hard mask pattern; and (3) Using the hard mask pattern as a mask, the substrate target layer is etched to form the fin structure of the fin field-effect transistor.

7. The patterning method for semiconductor processes according to claim 6, characterized in that, Step (2) also includes: The hard mask pattern is trimmed.

8. The patterning method for semiconductor processes according to any one of claims 1 to 7, characterized in that, Forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (A1) A negative photoresist layer is formed on the target area using negative photoresist, and a positive photoresist layer is formed on the negative photoresist layer using positive photoresist; (A2) Pattern the negative adhesive layer and the positive adhesive layer to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; (A3) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist in the positive pattern area; (A4) The negative photoresist layer is developed with a negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

9. The patterning method for semiconductor processes according to any one of claims 1 to 7, characterized in that, Forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (B1) A positive photoresist layer is formed on the target area using a positive photoresist, and a negative photoresist layer is formed on the positive photoresist layer using a negative photoresist; (B2) The negative adhesive layer and the positive adhesive layer are patterned to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer, respectively, wherein the positive pattern area is larger than the negative pattern area; (B3) The negative photoresist layer is developed with a negative photoresist developer to remove negative photoresist outside the negative pattern area; (B4) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist at the edge of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

10. The patterning method for semiconductor processes according to any one of claims 1 to 7, characterized in that, Forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (C1) A negative photoresist layer is formed on the target area using negative photoresist, a spacer layer is formed on the negative photoresist layer, and a positive photoresist layer is formed on the spacer layer using positive photoresist. (C2) Pattern the negative adhesive layer and the positive adhesive layer to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; (C3) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist in the positive pattern area; (C4) Develop the separator with a separator developer, or etch the separator using the pattern of the developed positive resist layer as an etch mask, so that the pattern of the separator is consistent with the pattern of the developed positive resist layer. (C5) The negative photoresist layer is developed with a negative photoresist developer to remove the negative photoresist located near the negative pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

11. The patterning method for semiconductor processes according to any one of claims 1 to 7, characterized in that, Forming a differential pattern on a target area using a double-layer photoresist photolithography process includes the following steps: (D1) A positive photoresist layer is formed on the target area using a positive photoresist, a spacer layer is formed on the positive photoresist layer, and a negative photoresist layer is formed on the spacer layer using a negative photoresist. (D2) Pattern the negative adhesive layer and the positive adhesive layer to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; (D3) The negative photoresist layer is developed with a negative photoresist developer to remove negative photoresist outside the negative pattern area; (D4) Develop the separator with a separator developer, or etch the separator using the pattern of the developed negative adhesive layer as an anti-etching mask, so that the pattern of the separator is consistent with the pattern of the developed negative adhesive layer. (D5) The positive photoresist layer is developed with a positive photoresist developer to remove the positive photoresist at the edge of the positive pattern area, thereby providing an exposure area related to the size of the positive pattern area and the negative pattern area to expose the target area, and the remaining photoresist forms the differential pattern.

12. The patterning method for semiconductor processes according to any one of claims 8 to 11, characterized in that, Patterning the negative adhesive layer and the positive adhesive layer to form positive and negative patterned areas on the positive and negative adhesive layers respectively includes: Under exposure source, the positive resist layer and the negative resist layer are exposed using a photomask carrying a template pattern or by focused direct writing, thereby forming positive pattern areas and negative pattern areas on the positive resist layer and the negative resist layer, respectively.

13. A patterning system for semiconductor processes, comprising a differential patterning section, a mandrel forming section, a spacer layer deposition section, a spacer layer etching section, a mandrel removal section, and a fin structure forming section, wherein the patterning system is used to perform the following steps: (1) Using the differential pattern forming unit, a differential pattern is formed on the target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer, a first hard mask layer, a mandrel layer, and a second hard mask layer. (2) Using the mandrel forming part, with the differential pattern as a mask, the second hard mask layer and the mandrel layer are etched to form a mandrel in the mandrel layer; (3) Using the spacer layer deposition section, a spacer layer is deposited on the target region where the mandrel is formed; (4) Using the spacer etching section, the horizontal portion of the spacer layer is etched, while the vertical portion of the spacer layer near the sidewall of the mandrel is retained; (5) Using the mandrel removal section, remove the mandrel while retaining the vertical portion of the spacer layer; as well as (6) Using the fin structure forming part, with the vertical portion of the spacer layer as a mask, the first hard mask layer and the substrate target layer are etched to form the fin structure of the fin field-effect transistor.

14. A patterning system for semiconductor processes, comprising a differential patterning section, a hard mask patterning section, a mask forming section, and a dummy gate structure forming section, the patterning system being used to perform the following steps: (1) Using the differential pattern forming unit, a differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a fin structure and a polysilicon layer and a hard mask layer located on the fin structure. (2) Using the hard mask pattern forming unit, the hard mask layer is etched to form a hard mask pattern using the differential pattern as a mask; (3) Using the mask forming part, the edge portion of the hard mask pattern is removed by photolithography and etching processes to form a mask with a pseudo gate structure; as well as (4) Using the pseudo-gate structure forming part, the polysilicon layer is etched using the mask of the pseudo-gate structure to form the pseudo-gate structure of the fin field-effect transistor.

15. A patterning system for semiconductor processes, comprising a differential patterning section, a hard mask patterning section, and a fin structure forming section, the patterning system being used to perform the following steps: (1) Using the differential pattern forming unit, a differential pattern is formed on a target area using a double-layer photoresist photolithography process. The target area is composed of a substrate target layer and a hard mask layer located on the substrate target layer. (2) Using the hard mask pattern forming unit, the hard mask layer is etched to form a hard mask pattern using the differential pattern as a mask; as well as (3) Using the fin structure forming part, with the hard mask pattern as a mask, the substrate target layer is etched to form the fin structure of the fin field-effect transistor.

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