Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device is disclosed. The semiconductor device includes a first substrate having a plurality of components disposed thereon, and a plurality of chips disposed on the first substrate corresponding to the respective components. The method includes preparing a component comprising the first substrate and the plurality of chips disposed on the substrate; forming a first film having a flat top surface by applying a precursor to the component such that the amount of precursor applied to the chips is less than the amount of precursor applied to another portion; and dicing the component, wherein forming the first film includes contacting a cover plate with the precursor.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing semiconductor devices. Background Technology

[0002] A method for manufacturing a semiconductor device is known by arranging multiple chips on a substrate such as a semiconductor wafer and then dicing them. Japanese Patent Publication No. 2022-089275 describes a manufacturing method in which multiple chips arranged on a semiconductor wafer are embedded in an oxide film, and then a support substrate is provided thereon. Summary of the Invention

[0003] Japanese Patent Publication No. 2022-089275 does not detail the step of embedding multiple chips and the planarization step following the embedding step. This disclosure aims to provide a technique advantageous for manufacturing semiconductor devices in which multiple chips are arranged on a substrate.

[0004] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the semiconductor device including a first substrate and a plurality of chips, a plurality of components disposed on the first substrate, the plurality of chips being deployed on the first substrate to correspond to each component. The method includes: preparing a component including the first substrate and the plurality of chips deployed on the substrate; forming a first film having a flat top surface by applying a precursor to the component such that the amount of precursor applied to the chip is less than the amount of precursor applied to another portion; and dicing the component, wherein forming the first film includes contacting a cover plate with the precursor.

[0005] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the semiconductor device including a first substrate and a plurality of chips, a plurality of components disposed on the first substrate, the plurality of chips being deployed on the first substrate to correspond to each component. The method includes: preparing a component including the first substrate and the plurality of chips deployed on the first substrate; forming a first film having a flat top surface by applying a precursor to the component such that the amount of precursor applied to the chips is less than the amount of precursor applied to another portion; and dicing the component, wherein forming the first film includes curing the precursor while a second substrate is in contact with the precursor, and bonding the second substrate to the first film.

[0006] The features of this disclosure will become clear from the following description of embodiments with reference to the accompanying drawings. The following description of embodiments is by way of example. Attached Figure Description

[0007] Figure 1This is a schematic diagram illustrating the configuration of the planarization device.

[0008] Figure 2A , Figure 2B and Figure 2C This is a schematic diagram used to describe the flattening process.

[0009] Figure 3A and Figure 3B This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0010] Figure 4A , Figure 4B and Figure 4C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 5A , Figure 5B and Figure 5C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0012] Figure 6A and Figure 6B This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment.

[0013] Figure 7A , Figure 7B and Figure 7C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment.

[0014] Figure 8A and Figure 8B This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment.

[0015] Figure 9A , Figure 9B and Figure 9C This is a schematic diagram used to describe an application example of a semiconductor device according to a third embodiment. Detailed Implementation

[0016] The embodiments will now be described with reference to the accompanying drawings. These embodiments are not intended to limit the disclosure described in the claims. While the embodiments describe multiple features, not all features are essential to this disclosure, and multiple features can be freely combined. In the drawings, identical or similar components are indicated by the same reference numerals, and redundant descriptions may be omitted.

[0017] Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. In the following description, terms indicating specific directions and locations (e.g., "top," "bottom," "right," "left," and other terms including these) will be used as needed. These terms are used to facilitate understanding of the embodiments with reference to the accompanying drawings, and the technical scope of the present disclosure is not limited by the meaning of the terms.

[0018] As used herein, a plan view refers to a view in a direction perpendicular to the top surface of the semiconductor substrate. A cross-sectional view refers to a plane in a direction perpendicular to the top surface of the semiconductor substrate. If the top surface of the semiconductor substrate is microscopically rough, the plan view is defined with reference to the top surface of the semiconductor substrate as viewed macroscopically. The top surface of the semiconductor substrate should refer to the surface containing elements formed on the semiconductor substrate, such as transistor gates, or the surface containing connectors to contact plugs.

[0019] Unless otherwise explicitly defined, expressions such as "A or B", "at least one of A and B", "at least one of A and / or B", and "one or more of A and / or B" should include all possible combinations of the listed items. In other words, the above expressions are understood to disclose all of the following: including at least one A, including at least one B, and including both at least one A and at least one B. The same applies to combinations of three or more elements.

[0020] The term "substantially equal" will be described in this disclosure. Items designed to be equal may differ due to manufacturing variations. "Substantially equal" covers minor differences caused by manufacturing variations.

[0021] First Embodiment

[0022] Figure 1 This is a schematic diagram illustrating the configuration of the planarization apparatus 100 according to this embodiment. Directions are shown in the XYZ coordinate system, with the horizontal plane being the XY plane. The substrate 1, the object to be processed, is typically placed on a substrate stage 3, its surface parallel to the horizontal plane (XY plane). In the following description, mutually orthogonal directions in the plane along the surface of the substrate 1 will be represented as the X-axis and Y-axis, and directions perpendicular to the X-axis and Y-axis will be represented as the Z-axis. Directions parallel to the X-axis, Y-axis, and Z-axis of the XYZ coordinate system will be referred to as the X direction, Y direction, and Z direction, respectively. The directions of rotation about the X-axis, Y-axis, and Z-axis will be referred to as the θX direction, θY direction, and θZ direction, respectively. As described below, the substrate 1 is a component to which semiconductor processing can be applied. Examples include semiconductor wafers, semiconductor wafers with wiring structures, glass substrates with components, and metal substrates.

[0023] The underlying pattern on the substrate exhibits an uneven profile due to patterns formed in previous processes. In particular, with the recent trend towards multilayer structures in memory devices, the step height of some processed substrates has reached approximately 100 nm. Step differences caused by the smoothing of the entire substrate can be corrected using the focus-tracking function of the scanning exposure apparatus used in photolithography. In contrast, fine-pitch inhomogeneities falling within the exposure slit area of ​​the exposure apparatus may deviate from the depth of focus (DOF) of the exposure apparatus. Traditionally, techniques such as spin-coated carbon (SOC) and chemical mechanical polishing (CMP) for forming planarization layers or performing planarization processes have been used to smooth the underlying pattern of the substrate. However, conventional techniques suffer from insufficient planarization performance. For example, manufacturing processes have been evolving towards new technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm. A planarization layer sufficient for practical use at a previous generation node may not be practically usable at subsequent nodes. For example, surface irregularities in a planarization layer acceptable for a previous node may be unacceptable for subsequent nodes. Furthermore, CMP requires high processing costs and may only be applicable to a limited range of processes, while the unevenness of the lower layers tends to increase further in the future due to the multi-layer nature of the process.

[0024] To address this problem, a planarization apparatus using imprinting technology is being researched. The planarization apparatus partially or completely planarizes the substrate surface by bringing a flat surface of a component or a non-patterned component (planar template) into contact with an uncured composition pre-supplied to the substrate. The composition is then cured using the planar template and the composition in contact, and the planar template is separated from the cured composition.

[0025] This forms a planarization layer on the substrate. Unlike planarization methods that typically use a sacrificial SOC layer, this planarization apparatus is unaffected by the non-uniformity of the patterned surface of the substrate, and therefore is expected to improve planarization accuracy compared to existing methods.

[0026] Figure 1 The planarization apparatus 100 can be implemented by a molding apparatus that uses a plate (cover plate) 9 as a pressing member to mold the composition on the substrate 1. The planarization apparatus 100 cures the composition while the material on the substrate 1 and the substrate 9 are in contact with each other, and separates the plate 9 from the cured composition, thereby forming a planarization layer of material on the substrate 1.

[0027] Substrate 1 is a semiconductor, insulator, or metal substrate, and may have a circular shape such as a silicon wafer or a quartz wafer, or a rectangular shape such as the (mother) glass of a flat panel display (FPD). The material of substrate 1 may be a single-crystal silicon wafer, but this is not limiting. Examples of substrate materials may include silicon, germanium, diamond, silicon carbide, silicon germanium, gallium nitride, gallium arsenide, indium arsenide, cadmium telluride, and other elemental or compound semiconductors. Other examples of materials for substrate 1 may include inorganic insulators such as silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride. Other examples of materials for substrate 1 may include organic insulators such as polyimide, polyamide, and polycarbonate. Substrate 1 may be made of aluminum, titanium-tungsten alloy, aluminum-silicon alloy, or aluminum-copper-silicon alloy. In short, substrate 1 may be made of any one or more materials selected from the above-mentioned materials. At least one semiconductor, insulator, or metal film may be formed on the surface of substrate 1, and the film surface may be planar or patterned.

[0028] An adhesive layer can be formed on the substrate surface through surface treatments such as silane coupling treatment, silazane treatment, and organic thin film deposition, and the resulting substrate with improved adhesion to the composition can be used. The substrate 1 typically has a circular shape with a diameter of 300 mm, but is not limited to.

[0029] Considering the light irradiation process, plate 9 can be made of an optically transparent material. Examples of such materials include optically transparent inorganic materials such as glass and quartz, and optically transparent organic materials such as polymethyl methacrylate (PMMA) and polycarbonate resin. Plate 9 can be a rigid plate or a flexible film. The surface of plate 9 in contact with the composition is flat. Plate 9 can have a circular shape, but is not limited to, a diameter greater than 300 mm and less than 500 mm. A suitable thickness of plate 9 is, but is not limited to, greater than 0.25 mm and less than 2 mm. If the composition is not a photocurable material but a thermosetting material, plate 9 does not need to be transparent and can be made of any material having the above-described properties.

[0030] The composition is a precursor for at least a portion of curing to form a planarized film, and is a curable composition that can be cured by light or heat. A curable compound that can be cured by light or heat can be a light-curable composition that cures when exposed to light, a thermosetting composition that cures when heated, or a photothermal-curable composition that cures when exposed to both light and heat. Examples of light-curable compositions include ultraviolet (UV) curable liquids. Typically, monomers such as acrylates and methacrylates are used as UV curable liquids. The curable composition may be referred to as a moldable material. Hereinafter, moldable materials may be simply referred to as "materials".

[0031] like Figure 1As shown, the planarization apparatus 100 includes a substrate chuck 2, a substrate stage 3, a base plate 4, a support column 5, a top plate 6, a guide rod 7, a support column 8, a plate chuck 11, a head 12, and an alignment stage 13. The planarization apparatus 100 also includes a pressure adjustment unit 15, a supply unit 17, a substrate transfer unit 18, an alignment observation instrument 19, a light source 20, a stage drive unit 21, a plate transfer unit 22, a cleaning unit 23, an input unit 24, and a control unit 200. The substrate chuck 2 and the substrate stage 3 can hold and move the substrate 1. The plate chuck 11 and the head 12 can hold and move the plate 9.

[0032] The substrate 1 is carried from the outside into the planarization apparatus 100 by a substrate transfer unit 18 including a transfer hand, and held by a substrate chuck 2. A substrate stage 3 is supported by a base plate 4 and driven in the X and Y directions to position the substrate 1 held by the substrate chuck 2 at a predetermined position. A stage drive unit 21 includes, for example, a linear motor or cylinder, and drives the substrate stage 3 at least in the X and Y directions. The stage drive unit 21 may have the function of driving the substrate stage 3 in three or more axial directions (e.g., six axial directions). The stage drive unit 21 includes a rotation mechanism and can drive the substrate chuck 2 or the substrate stage 3 to rotate in the θZ direction.

[0033] The plate 9, serving as a pressing member, is carried from the outside into the planarization apparatus 100 by a plate transport unit 22 including a transport hand, and is held by a plate chuck 11. The plate 9 has, for example, a circular or rectangular shape, and has a first surface including a flat surface 10 that contacts the material placed on the substrate 1 and a second surface opposite the first surface. In this embodiment, the flat surface 10 has the same or larger dimensions as the substrate 1. The plate chuck 11 is supported by a head 12 and has the function of correcting the position of the plate 9 in the θZ direction (tilt about the Z-axis). Both the plate chuck 11 and the head 12 have openings that allow light (ultraviolet light) emitted from the light source 20 via a collimating lens to pass through. The plate chuck 11 serves as a holding unit for mechanically holding the plate 9. For example, the plate chuck 11 holds the plate 9 by attracting the second surface of the plate 9 with the second surface facing upwards. The head 12 mechanically holds the plate chuck 11. The plate chuck 11 and the head 12 constitute a forming unit 50 that performs the planarization film forming process. The head 12 includes a drive mechanism (not shown) for adjusting the distance between the substrate 1 and the plate 9 as the material on the plate 9 and the substrate 1 comes into contact with and separates from the material, and for moving the plate 9 in the Z direction. For example, the drive mechanism of the head 12 may include actuators such as linear motors, cylinders, and voice coil motors. A load cell for measuring the pressing force (imprint force) of the plate 9 on the material on the substrate 1 may be deployed on the plate chuck 11 or the head 12. The plate deformation mechanism (plate deformation unit) includes a sealing member 14 that seals the space region A formed by the internal space of the plate chuck 11 and the internal space surrounded by the plate 9 and the sealing member 14. The plate deformation mechanism also includes a pressure adjustment unit 15 located outside the plate chuck 11 and adjusting the pressure inside the space region A. The sealing member 14 is made of an optically transparent flat member such as quartz glass and includes a connection port (not shown) for connecting to the pressure adjustment unit 15 via a conduit 16. The pressure adjustment unit 15 can increase the amount of deformation of the plate 9 protruding towards the substrate 1 by increasing the pressure in the space region A. The pressure adjustment unit 15 can also reduce the deformation of the plate 9 protruding towards the substrate 1 by reducing the pressure in the space region A. A support column 5 for supporting the top plate 6 is deployed on the substrate 4. A guide rod 7 is suspended from the top plate 6, passes through the alignment stage 13, and is fixed to the head 12. The alignment stage 13 is suspended from the top plate 6 via the support column 8. The guide rod 7 passes through the alignment stage 13. A height measurement system (not shown), for example, for measuring the height (flatness) of the substrate 1 held by the substrate chuck 2 using an oblique incidence image displacement method, is deployed on the alignment stage 13.

[0034] The alignment observation instrument 19 includes an optical system and an imaging system for observing the reference marks provided on the substrate stage 3 and the alignment marks provided on the plate 9. If the plate 9 does not have alignment marks, the alignment observation instrument 19 can be omitted. The alignment observation instrument 19 is used for alignment purposes to measure the relative position between the reference marks on the substrate stage 3 and the alignment marks on the plate 9, and to correct for their positional deviations.

[0035] The supply unit 17 includes a dispenser comprising outlets (nozzles) for discharging uncured material into the substrate 1 and supplying (applying) material onto the substrate 1. The supply unit 17 employs, for example, piezoelectric jetting or micro-solenoid technology and can supply small volumes of material, such as approximately 1 pL, onto the substrate 1 during scan drive. The number of outlets in the supply unit 17 is not particularly limited and can be one (single nozzle) or multiple (e.g., 100 or more). Multiple nozzles can form a single-row or multi-row linear nozzle array. In particular, the dispenser, referred to as an inkjet head, can suitably apply liquid material to the substrate in the form of small droplets. Especially because the volume of the discharged droplets can be varied, a piezoelectric inkjet head including at least one piezoelectric discharge energy generator for each outlet is more suitable.

[0036] The cleaning unit 23 cleans the plate 9 while it is held on the plate chuck 11. When the plate 9 separates from the cured material on the substrate 1, the cleaning unit 23 removes the material adhering to the plate 9 or, in particular, the flat surface 10. For example, the cleaning unit 23 can wipe away the material adhering to the plate 9, or use UV irradiation, electrostatic elimination, wet cleaning, dry plasma cleaning, etc., to remove the material adhering to the plate 9.

[0037] The control unit 200 comprises a computer device including a central processing unit (CPU) and memory, and controls the entire planarization apparatus 100. The control unit 200 serves as a processing unit that comprehensively controls the components of the planarization apparatus 100 to perform planarization processing. As used herein, planarization processing refers to the process of planarizing material on substrate 1 by bringing the planar surface 10 of board 9 into contact with material so that the planar surface 10 conforms to the surface shape of substrate 1. Planarization processing is typically performed in batches, i.e., performed on each of multiple substrates included in the same batch.

[0038] Next, we will refer to Figure 2A , Figure 2B and Figure 2C Describe the planarization process. Initially, the supply unit 17 supplies material IM to the substrate 1 on which the underlying pattern 1a is formed. Figure 2A The diagram illustrates the state in which material IM is placed on substrate 1 before plate 9 makes contact. Next, as... Figure 2BAs shown, the material IM on the substrate 1 is brought into contact with the flat surface 10 of the plate 9. The plate 9 presses the material IM down, thereby spreading the material IM across the entire surface of the substrate 1. Figure 2B The illustration shows the entire flat surface 10 of plate 9 contacting the material IM on substrate 1, and the flat surface 10 of plate 9 conforming to the surface shape of substrate 1. Figure 2B In the state shown, the light source 20 then illuminates the material IM on the substrate 1 with light via the plate 9, thereby curing the material IM. The plate 9 is then separated from the cured material IM on the substrate 1. As a result, a layer (planarization layer) of material IM with a uniform thickness is formed on the entire surface of the substrate 1. Figure 2C The diagram illustrates the state in which a planarization layer of material IM is formed on substrate 1. In the following description, the contact (close contact) and separation between the planar surface 10 of plate 9 and the material IM on substrate 1 will be referred to as contact (close contact) and separation between plate 9 and the material IM on substrate 1, respectively. Furthermore, in the following text, the material IM in the state of being supplied to substrate 1 may be referred to as a precursor, and the cured material IM may be referred to as a film.

[0039] Next, a method for manufacturing articles (such as semiconductor devices, liquid crystal display devices, color filters, and microelectromechanical systems [MEMS]) using the planarization apparatus 100 will be described. This manufacturing method includes the steps of planarizing the composition by bringing a composition and a mold placed on a substrate (such as a wafer or glass substrate) into contact with each other using the planarization apparatus 100, curing the composition, and separating the composition and the mold. A planarization film is thus formed on the substrate. The substrate with the planarization film then undergoes a process such as patterning using a photolithography apparatus, and the treated substrate is processed in other conventional processing or fabrication steps to manufacture articles. Other conventional steps include etching, resist removal, dicing, bonding, and encapsulation. Using this manufacturing method, articles of higher quality than those produced to date can be manufactured.

[0040] A method for manufacturing a semiconductor device will now be described using a semiconductor device as a specific example of an article. A semiconductor device is, for example, a photoelectric conversion sensor. The method for manufacturing a semiconductor device according to this embodiment refers to... Figure 1 , Figure 2A , Figure 2B and Figure 2C The planarization method described is applied to a configuration that includes multiple chips arranged on a substrate.

[0041] Figure 3A and Figure 3B This is a schematic plan view used to describe a method for manufacturing a semiconductor device according to this embodiment. Figure 3A The illustration shows the steps for preparing a substrate 101 (first substrate) including component 102. Figure 3AThe diagram illustrates a planar layout of substrate 101. Substrate 101 has a circular shape, and a plurality of components 102 are arranged thereon. Substrate 101 may include a semiconductor wafer and wiring structures formed thereon. Substrate 101 is, for example, a semiconductor substrate comprising a silicon single-crystal substrate as its semiconductor wafer. Components 102 may, for example, be semiconductor elements comprising portions formed in the semiconductor wafer and portions formed by wiring structures. Substrate 101 and components 102 are formed by conventional semiconductor device manufacturing methods.

[0042] Figure 3B The illustration shows that the preparation chip 103 is further arranged in... Figure 3A The steps for configuring the components. In the following steps, the substrate 101 and the chip 103 can be collectively referred to as components. Figure 3B This is a diagram illustrating a planar layout of a substrate 101 on which chips 103 are arranged. This step can be achieved, for example, by bonding the conductor patterns of the substrate 101 and the chips 103 to each other. This embodiment demonstrates an example of deploying two chips 103 on each individual component 102. Chips 103 may include circuitry for operating components 102 and circuitry for processing signals output from components 102. The number of chips deployed on a single component 102 is not limited to two. Multiple chips 103 having the same function may be deployed on component 102. Multiple chips 103 having different functions may be deployed on component 102. Examples of chips 103 include semiconductor chips.

[0043] Next, the step of embedding the chip 103 arranged on the substrate 101 is performed. Figure 4A , Figure 4B and Figure 4C It is along Figure 3B A schematic cross-sectional view taken by line AB. The steps for embedding the chip 103 will be described. The substrate 101 has a first surface P1 and a second surface P2 opposite to the first surface P1. As used herein, the first surface P1 may be referred to as the top surface of the substrate 101, and the second surface P2 may be referred to as the bottom surface of the substrate 101.

[0044] Component 102 may include, for example, photoelectric conversion elements that convert light into electrical charge. Typically, each component 102 includes multiple photoelectric conversion elements arranged in a multi-row, multi-column array. The photoelectric conversion elements generate charge based on light incident from the second surface P2. A transfer transistor (not shown) transfers charge from the photoelectric conversion elements to a floating diffusion region (not shown). An output circuit including an amplifying transistor (not shown) outputs a signal based on the amount of charge transferred to the floating diffusion region to a column circuit (not shown). The column circuit is deployed, for example, on chip 103 and performs various types of processing, including analog-to-digital (AD) conversion processing for converting the input signal into a digital signal and processing for reducing noise components. Digital signals are sequentially read from the multiple column circuits. Therefore, a semiconductor device including photoelectric conversion elements can generate a signal based on light incident on the photoelectric conversion elements.

[0045] Figure 4A The illustration shows the steps of applying a liquid precursor 104 (the aforementioned material IM) to a substrate 101 on which a chip 103 is disposed. The precursor 104 is applied in a predetermined amount, such that less of the precursor 104 is applied to the chip 103 and more to other portions. The liquid precursor 104 may be an energy-curable resin precursor or a SOC precursor. Examples of energy-curable resin precursors may include photocurable compositions.

[0046] Uncured material IM is applied to a pre-formed chip 103 using an inkjet head equipped with a piezoelectric element serving as an ejection actuator. Specifically, the application process involves applying droplets to the chip 103 N times per unit area (N being a natural number) and applying droplets to other flat surfaces of the substrate 101 (among multiple chips 103) N times per unit area. The number of droplets to be applied can be determined based on the arrangement pattern of the chips 103. Specifically, droplets are applied by changing the relative position of the ejection port and the substrate 101 based on a drawing, where the number (or amount) of droplets to be applied to the substrate 101 and the application position within the first surface P1 are determined based on the arrangement pattern data on the chip 103. The application amount can be changed not only by altering the number of droplets in the liquid precursor 104 but also by changing the droplet size. Both are adjustable.

[0047] exist Figure 4B In this process, the flat surface 10 of plate 9 is pressed onto precursor 104, and the liquid is cured. This step improves the flatness of the chip 103. Precursor 104 can be cured by irradiating precursor 104 with light through plate 9. For example, an exposure apparatus can be used as a curing apparatus. ArF immersion exposure apparatus, ArF dry exposure apparatus, or KrF exposure apparatus can be used. The exposure amount can also be adjusted according to the arrangement pattern of chip 103.

[0048] like Figure 4C As shown, the plate 9 is then separated from the cured precursor 104. This planarization process forms a first film 105 with a highly flat top surface. Here, a portion of the first film 105 located above the chip 103 can be removed.

[0049] exist Figure 5A Then, the substrate 101 having the first film 105 is integrated with the support substrate 107 (second substrate). Specifically, an adhesive layer 106 is applied to the first film 105, and the support substrate 107 is adhered and bonded thereto. Alternatively, the materials of the portion of the first film 105 forming the bonding interface and the material of the portion of the support substrate 107 forming the bonding interface can be suitably selected to cause bonding (e.g., covalent bonding, etc.) between the materials at the bonding interface.

[0050] exist Figure 5B In this process, substrate 101 is thinned into substrate 108 (the third substrate). Thinning can be performed using techniques such as etching, mechanical polishing, and CMP. If substrate 101 is a silicon-on-insulator (SOI) substrate, thinning can be performed using water jetting. Such processing can reduce the thickness of the semiconductor layer of substrate 101, thereby achieving at least one effect, including miniaturization and improved heat dissipation.

[0051] like Figure 5C As shown, the entire component is then cut into the required number of pieces to complete the semiconductor device.

[0052] As described above, the method for manufacturing a semiconductor device according to this embodiment can provide technology that is advantageous for manufacturing a semiconductor device on which multiple chips are deployed on a substrate. In this embodiment, the flatness above the portions of the multiple chips 103 and between the multiple chips 103 is improved. Due to the improved flatness of the bonding interface between the first film 105 and the support substrate 107, the bonding strength between the support substrate 107 and the first film 105 is improved.

[0053] In this embodiment, when material IM is applied, the inkjet head is controlled such that fewer droplets are ejected onto chip 103 than droplets are ejected onto portions other than those on chip 103. However, this mode is not limiting. For example, material IM is applied such that droplets are uniformly applied onto chip 103 and portions other than those on chip 103. Then, a flat plate 9 is brought into contact with material IM. Even with such a method, the amount of material IM on chip 103 can be less than the amount of material IM on portions other than those on chip 103. Such techniques also encompass the step of applying precursor 104 such that the amount applied to chip 103 is less than the amount applied to other portions.

[0054] exist Figure 4B In the middle, it can be used Figure 5A The support plate 107 shown replaces plate 9. In this case, the liquid precursor 104 (material IM) can be a thermosetting composition. Figure 5B As shown, the substrate 101 is then thinned into substrate 108 (the third substrate). (As shown...) Figure 5C As shown, the entire component is then cut into the required number of pieces to complete the semiconductor device. This manufacturing method eliminates the step of separating the plate 9 from the cured precursor 104. Figure 4C The steps shown) and the step of applying adhesive layer 106 ( Figure 5A (Part of the steps shown).

[0055] <Second Embodiment>

[0056] A method for manufacturing a semiconductor device according to this embodiment will be described. Figure 6A and Figure 6B This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment. This embodiment differs from the first embodiment in that, in addition to chip 103, a chip having a different size than chip 103 is also deployed on component 102. Detailed descriptions of configurations and steps similar to those in the first embodiment will be omitted below.

[0057] Figure 6A and Figure 6B This is a schematic plan view used to describe a method for manufacturing a semiconductor device according to this embodiment. Figure 6A The illustration shows the steps for preparing a substrate 101 (first substrate) including component 102. Figure 6A This is a diagram showing the planar layout of the substrate 101.

[0058] Figure 6B The illustration shows that the preparation chip 103 and chip 201 are further arranged in... Figure 6A The steps for configuring the components. In the following steps, substrate 101, chip 103 and chip 201 can be collectively referred to as components. Figure 6B The diagram illustrates a planar layout of a substrate 101 on which chips 103 and 201 are arranged. This embodiment describes an example of deploying two chips 103 and one chip 201 with a different size from the chips 103 on each individual component 102. Chip 201 may include circuitry for operating component 102 and circuitry for processing signals output from component 102. Chip 201 is, for example, a semiconductor chip.

[0059] Figure 7A , Figure 7B and Figure 7C It is along Figure 6BA schematic cross-sectional view taken by line AB. The steps for embedding chips 103 and 201 will now be described. Chip 103 has a height H1 greater than the height H2 of chip 201. Chip 103 has a width W1 less than the width W2 of chip 201. The distance W3 between one chip in chip 103 and chip 201 is substantially the same as the distance between the other chip 103 and chip 201. Heights H1 and H2 can be, for example, approximately 1 μm to 30 μm. Widths W1 and W2 can be, for example, approximately 1 nm to 10 nm.

[0060] Figure 7A The illustration depicts the steps of applying a liquid precursor 104 (the aforementioned material IM) to a substrate 101 on which chips 103 and 201 are disposed. The precursor 104 is applied in a predetermined amount, such that the precursor 104 is applied to chip 103 in a first amount, to chip 201 in a second amount, and to other portions in a third amount. Examples of other portions include the region between chip 103 and chip 201. The first amount is less than the second amount, and the second amount is less than the third amount.

[0061] The liquid precursor 104 may be an energy-curable resin precursor or a SOC precursor. Examples of energy-curable resins may include photocurable compositions.

[0062] Uncured material IM is applied to pre-formed chips 103 and 201 using an inkjet head equipped with a piezoelectric element serving as an ejection actuator. Specifically, droplets are applied to chip 103 N times per unit area (N is a natural number) and to substrate 201 M times per unit area (M is a natural number greater than N). Furthermore, droplets are applied to other flat surfaces of substrate 101 (between chips 103 and 201) L times or more per unit area (L is a natural number greater than M). The number of droplets to be applied can be determined based on the arrangement pattern of chips 103 and 201. Droplets are applied by changing the relative position of the ejection port and substrate 101 based on a drawing. The number (or amount) of droplets to be applied to substrate 101 and the application position within the first surface P1 are determined based on the arrangement pattern data on chips 103 and 201. The application amount can be changed not only by altering the number of droplets in the liquid precursor 104 but also by changing the droplet size. Both can be adjusted.

[0063] exist Figure 7BIn this process, the flat surface 10 of plate 9 is pressed onto precursor 104, and the liquid is cured. This step improves the flatness of chips 103 and 201. Precursor 104 can be cured by irradiating precursor 104 with light through plate 9. For example, an exposure apparatus can be used as a curing apparatus. ArF immersion exposure apparatus, ArF dry exposure apparatus, or KrF exposure apparatus can be used. The exposure amount can be adjusted according to the arrangement pattern of chips 103 and 201.

[0064] like Figure 7C As shown, plate 9 is then separated from the cured precursor 104. This planarization process forms a first film 105 with a highly flat top surface. Here, a portion of the first film 105 located above chips 103 and 201 can be removed.

[0065] Next, in Figure 8A In this process, a substrate 101 having a first film 105 is integrated with a support substrate 107 (second substrate). Specifically, an adhesive layer 106 is applied to the first film 105, and the support substrate 107 is adhered and bonded thereto. Alternatively, the materials of the portion of the first film 105 forming the bonding interface and the material of the portion of the support substrate 107 forming the bonding interface can be suitably selected to result in bonding (e.g., covalent bonding, etc.) between the materials at the bonding interface.

[0066] exist Figure 8B In this process, substrate 101 is thinned into substrate 108 (the third substrate). Thinning can be performed using techniques such as etching, mechanical polishing, and CMP. If substrate 101 is an SOI substrate, thinning can be performed using water jetting. Such processing can reduce the thickness of the semiconductor layer of substrate 101, thereby achieving at least one effect including miniaturization and improved heat dissipation.

[0067] The entire component is then cut into the required number of pieces to complete the semiconductor device.

[0068] As described above, the method for manufacturing a semiconductor device according to this embodiment provides a technique advantageous for manufacturing a semiconductor device on which multiple chips are deployed on a substrate. In this embodiment, the flatness above the multiple chips 103, the chip 201, and the portion between the multiple chips 103 and 201 is improved. In other words, even if multiple chips with different heights and widths are deployed on component 102, a first film 105 with high flatness can be formed by adjusting the amount of precursor 104. Since the flatness of the bonding interface between the first film 105 and the support substrate 107 is improved, the bonding strength between the support substrate 107 and the first film 105 is improved.

[0069] The number of chips deployed on a single component 102, the width of the chips, the height of the chips, and the distance between chips are not limited to... Figure 6A and Figure 6B The amount of precursor 104 applied can be determined based on the number of chips, the width of the chips, the height of the chips, and the chip-to-chip distance. For example, distances W3 and W4 can be different. Even in such cases, a first film 105 with high flatness can be formed.

[0070] In this embodiment, when material IM is applied, the inkjet head is controlled to eject varying amounts of droplets onto chip 103, chip 201, and other portions. However, this mode is not limiting. For example, material IM is applied such that droplets are uniformly applied to chip 103, chip 201, and portions other than those on chips 103 and 201. The plate 9 is then brought into contact with material IM. Even with such a method, material IM can be applied to chip 103 in a first amount, to chip 201 in a second amount, and to portions other than chips 103 and 201 in a third amount. This technique also encompasses the step of applying precursor 104 such that the amount applied to chips 103 and 201 is less than the amount applied to other portions.

[0071] exist Figure 7B In the middle, it can be used Figure 8A The support plate 107 shown replaces plate 9. In this case, the liquid precursor 104 (material IM) can be a thermosetting composition. Figure 8B As shown, substrate 101 is then thinned to substrate 108 (the third substrate). The entire assembly is then cut into the required number of wafers to complete the semiconductor device. This manufacturing method eliminates the step of separating the plate 9 from the cured precursor 104. Figure 7C The steps shown) and the step of applying adhesive layer 106 ( Figure 8A (Part of the steps shown).

[0072] <Third Embodiment>

[0073] This embodiment describes an application example using a semiconductor device manufactured by the manufacturing method according to the first and second embodiments. The semiconductor device 910 is, for example, a photoelectric conversion sensor.

[0074] Figure 9AThis is a schematic diagram illustrating apparatus 9191 as an application example. Apparatus 9191 includes a semiconductor device 930. Semiconductor device 930 includes a semiconductor apparatus 910 and a package 920 housing the semiconductor apparatus 910. Semiconductor apparatus 910 can be manufactured by a manufacturing method according to other embodiments. Package 920 may include a base to which semiconductor apparatus 910 is fixed and a glass or other cover opposite semiconductor apparatus 910. Package 920 may also include engagement members such as bonding wires and bumps connecting terminals provided on the base and terminals provided on semiconductor apparatus 910.

[0075] Equipment 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is compatible with the semiconductor device 930. The optical device 940 is, for example, a lens, shutter, mirror, etc., and includes an optical system for guiding light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is a semiconductor device such as an application-specific integrated circuit (ASIC).

[0076] Processing device 960 processes signals output from semiconductor device 930. Processing device 960 is a semiconductor device used to construct an analog front-end (AFE) or digital front-end (DFE). Examples include CPUs and ASICs. Display device 970 is an electroluminescent (EL) display device or liquid crystal display device that displays information (images) obtained by semiconductor device 930. Storage device 980 is a magnetic device or semiconductor device that stores information (images) obtained by semiconductor device 930. Storage device 980 is volatile memory such as static random access memory (SRAM) and dynamic random access memory (DRAM), or non-volatile memory such as flash memory and hard disk drives.

[0077] Mechanical device 990 includes a movable unit or propulsion unit such as a motor or engine. Equipment 9191 displays signals output from semiconductor device 930 on display device 970, or transmits signals to an external location using a communication device (not shown) included in equipment 9191. For this purpose, in addition to the storage and computing circuitry included in semiconductor device 930, equipment 9191 may also include storage device 980 and processing device 960. Mechanical device 990 can be controlled based on signals output from semiconductor device 930.

[0078] Equipment 9191 is applicable to electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). Mechanical devices 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, mechanical devices 990 in the camera can move the semiconductor device 930 for image stabilization operations.

[0079] Equipment 9191 can be transportation equipment such as vehicles, ships, and aircraft. The mechanical device 990 within the transportation equipment can function as a mobile device. Equipment 9191 as transportation equipment is suitable for transporting semiconductor devices 930, or for using imaging functions to assist and / or automate operation (driving). A processing device 960 for assisting and / or automate operation (driving) can perform processing for operating the mechanical device 990 as a mobile device based on information obtained from the semiconductor device 930. Alternatively, equipment 9191 can be medical equipment such as endoscopes, measuring equipment such as distance sensors, analytical equipment such as electron microscopes, office equipment such as photocopiers, or industrial equipment such as robots.

[0080] According to the above embodiments, advantageous pixel characteristics can be obtained. Therefore, the value of the semiconductor device 930 can be increased. As used herein, increasing value includes at least one of the following: adding functionality, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing cost, miniaturization, and reducing weight.

[0081] Therefore, using the semiconductor device 930 according to this embodiment in equipment 9191 can also enhance the value of equipment 9191. For example, when the semiconductor device 930 is installed on transport equipment, excellent performance can be obtained when capturing images of the outside of the transport equipment or measuring the external environment. When manufacturing and selling transport equipment, it is beneficial to incorporate the semiconductor device 930 according to this embodiment into the transport equipment to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that uses information obtained by the semiconductor device to perform driving assistance and / or automatic driving.

[0082] Next, we will describe the moving body as another application example. Figure 9BAn example of a photoelectric conversion system associated with a vehicle-mounted camera is illustrated. The photoelectric conversion system 80 includes a semiconductor device 800. The semiconductor device 800 is, for example, a photoelectric conversion device (imaging device). The photoelectric conversion system 80 includes an image processing unit 801 and a disparity acquisition unit 802. The image processing unit 801 performs image processing on multiple image data acquired by the semiconductor device 800. The disparity acquisition unit 802 calculates the disparity (phase difference between disparity images) based on the multiple data acquired by the photoelectric conversion system 80.

[0083] Here, the photoelectric conversion system 80 may include an optical system (not shown) such as a lens, shutter, and mirror that guides light to the semiconductor device 800. The pixels of the semiconductor device 800 may include multiple photoelectric conversion units substantially conjugate to the pupil of the optical system. For example, a single microlens may be provided with multiple photoelectric conversion units substantially conjugate to the pupil. The multiple photoelectric conversion units receive light beams passing through different positions of the pupil of the optical system, thereby the semiconductor device 800 outputs image data corresponding to the light beams passing through the different positions. The parallax acquisition unit 802 can then use the output image data to calculate the parallax. The photoelectric conversion system 80 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines the probability of a collision based on the calculated distance. The parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition units that acquire distance information about an object. In other words, the distance information is information about parallax, defocus, distance to an object, etc. The collision determination unit 804 can use one of such distance information to determine the probability of a collision. Distance information can be acquired using time-of-flight (ToF). The distance information acquisition unit can be implemented using specially designed hardware or software modules. Field-programmable gate arrays (FPGAs), ASICs, and other similar devices can be used for implementation. Combinations of these can also be employed.

[0084] The photoelectric conversion system 80 is connected to the vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 80 is also connected to an electronic control unit (ECU) 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 80 is also connected to an alarm device 830, which issues an alert to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high probability of collision, the ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user through audible alarms, displaying warning messages on the screen of the car navigation system, vibrating the seat belt or steering wheel, etc.

[0085] In this embodiment, the photoelectric conversion system 80 captures images of the vehicle's surroundings, such as images of the front or rear. Figure 9C The illustration shows a photoelectric conversion system 80 capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends commands to the photoelectric conversion system 80 or a semiconductor device 800. This configuration can further improve the accuracy of distance measurement.

[0086] While examples of collision avoidance control have been described above, the photoelectric conversion system 80 is also applicable to autonomous driving control such as following another vehicle and maintaining lane position. Furthermore, the photoelectric conversion system 80 is not limited to vehicles such as automobiles, but can be applied to mobile bodies (mobile devices) such as ships, aircraft, and industrial robots. This mobile body includes one or both a drive force generating unit that generates the driving force primarily for the mobile drive body and a rotating body primarily for the mobile drive body. The drive force generating unit can be an engine, motor, etc. The rotating body can be a tire, wheel, ship propeller, thruster, etc. The photoelectric conversion system 80 is also not limited to mobile bodies and can be widely applied to equipment using object recognition, such as intelligent transportation systems (ITS).

[0087] The equipment according to this embodiment can be transportation equipment such as vehicles, ships, and aircraft. The mechanical devices within the transportation equipment can function as mobile devices. The equipment as transportation equipment is suitable for equipment transporting semiconductor devices or equipment using imaging functions to assist and / or automate operation (driving). The processing device for assisting and / or automate operation (driving) can perform processing for operating the mechanical devices as mobile devices based on information obtained from the semiconductor devices.

[0088] This embodiment has been described using a photoelectric conversion device as an example of a semiconductor device. However, other semiconductor devices can also be used. Both a photoelectric conversion device and other semiconductor devices can be used.

[0089] According to embodiments of this disclosure, techniques can be provided that facilitate methods for manufacturing semiconductor devices having multiple chips arranged on a substrate.

[0090] While this disclosure has been described with reference to embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. The scope of the following claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. A method for manufacturing a semiconductor device, the semiconductor device comprising a first substrate and a plurality of chips, a plurality of components disposed on the first substrate, the plurality of chips being deployed on the first substrate corresponding to each component, the method comprising: Prepare a component comprising the first substrate and the plurality of chips disposed on the substrate; A first film with a flat top surface is formed by applying a precursor to the component such that the amount of precursor applied to the chip is less than the amount of precursor applied to another part. as well as Cut the component. Forming the first membrane includes bringing the cover plate into contact with the precursor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein forming the first film comprises planarizing the top surface of the precursor and curing the precursor to have the planar top surface.

3. The method for manufacturing a semiconductor device according to claim 1, wherein forming the first film comprises curing the precursor while the cover plate is in contact with the precursor.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising bonding a second substrate to the first film after forming the first film.

5. The method for manufacturing a semiconductor device according to claim 1, further comprising bonding a second substrate to the first film and thinning the first substrate before cutting the component.

6. The method for manufacturing a semiconductor device according to claim 1, wherein forming the first film includes applying the precursor such that the amount of precursor applied to the chip is less than the amount of precursor applied to the portion between the chips.

7. The method for manufacturing a semiconductor device according to claim 1, wherein forming the first film includes applying the precursor such that the amount of precursor applied to the chip is less than the amount of precursor applied to a chip of the plurality of chips that is different from the chip.

8. The method for manufacturing a semiconductor device according to claim 1, wherein forming the first film includes applying the precursor such that the amount of precursor applied to the plurality of chips is less than the amount of precursor applied to another portion.

9. The method for manufacturing a semiconductor device according to claim 8, wherein forming the first film includes applying the precursor such that the amount of precursor applied to the plurality of chips is less than the amount of precursor applied to the portion between the plurality of chips.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, The plurality of components include photoelectric conversion elements, and The chip includes circuitry configured to process signals output from the photoelectric conversion element.

11. A method for manufacturing a semiconductor device, the semiconductor device comprising a first substrate and a plurality of chips, a plurality of components disposed on the first substrate, the plurality of chips being deployed on the first substrate corresponding to each component, the method comprising: Prepare a component comprising the first substrate and the plurality of chips disposed on the first substrate; A first film with a flat top surface is formed by applying a precursor to the component such that the amount of precursor applied to the chip is less than the amount of precursor applied to another part. as well as Cut the component. The formation of the first film includes curing the precursor while the second substrate is in contact with the precursor, and bonding the second substrate to the first film.

12. The method for manufacturing a semiconductor device according to claim 11, wherein forming the first film comprises planarizing the top surface of the precursor and curing the precursor to have the planar top surface.

13. The method for manufacturing a semiconductor device according to claim 11, further comprising bonding the second substrate to the first film after forming the first film.

14. The method for manufacturing a semiconductor device according to claim 11, further comprising bonding the second substrate to the first film and thinning the first substrate before cutting the component.

15. The method of manufacturing a semiconductor device according to claim 11, wherein forming the first film includes applying the precursor such that the amount of precursor applied to the chip is less than the amount of precursor applied to the portion between the plurality of chips.

16. The method for manufacturing a semiconductor device according to claim 11, wherein forming the first film includes applying the precursor such that the amount of precursor applied to the chip is less than the amount of precursor applied to a chip of the plurality of chips that is different from the chip.

17. The method of manufacturing a semiconductor device according to claim 11, wherein forming the first film includes applying the precursor such that the amount of precursor applied to the plurality of chips is less than the amount of precursor applied to another portion.

18. The method of manufacturing a semiconductor device according to claim 17, wherein forming the first film includes applying the precursor such that the amount of precursor applied to the plurality of chips is less than the amount of precursor applied to the portion between the plurality of chips.

19. The method for manufacturing a semiconductor device according to any one of claims 11 to 18, The plurality of components include photoelectric conversion elements, and The chip includes circuitry configured to process signals output from the photoelectric conversion element.

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