Buffer for streaming in quantum hub supercomputing

Abstract

The one or more systems, devices, computer program products, and / or computer-implemented methods described herein relate to buffers for streaming in quantum-centric supercomputing. The system may include a memory that stores computer-executable components. The system may also include a processor that executes the computer-executable components stored in the memory, wherein the computer-executable components may include a receiver component that can receive quantum input and a publication criterion associated with the quantum input from a source node. The computer-executable components may also include a computation component that can perform computations in the buffered environment based on the quantum input to generate results that satisfy the publication criterion.

Description

Technical Field

[0001] This disclosure relates to quantum computing, and more specifically to buffers for streaming in quantum-centric supercomputing. Background Technology

[0002] Quantum computing, in general, aims to perform computational and information processing functions using quantum mechanical phenomena. It contrasts with classical computing, which typically uses transistors to operate on binary values. That is, while classical computers operate on bit values ​​(which are either 0 or 1), quantum computers operate on qubits, which are a superposition of both 0 and 1. Multiple qubits can be entangled, and interference can be used. Quantum computing can involve large payloads, where payloads can represent data transferred between modules. Payloads requiring real-time decision-making should be streamed rather than batched. However, coordinating the streaming of large payloads across different use cases can be challenging.

[0003] The background description above is intended only to provide a contextual overview of quantum computing and quantum payloads and is not intended to be exhaustive. Summary of the Invention

[0004] The following overview is provided to offer a basic understanding of one or more embodiments described herein. This overview is not intended to identify key or essential elements, nor to define the scope of any particular embodiment or claim. Its sole purpose is to present concepts in a simplified form as an introduction to the more detailed description that follows. In one or more embodiments described herein, systems, computer-implemented methods, apparatuses, and / or computer program products that enable buffers for streaming in quantum-centric supercomputing are discussed.

[0005] According to one embodiment, a system is provided. The system may include a memory for storing computer-executable components. The system may also include a processor for executing the computer-executable components stored in the memory, wherein the computer-executable components may include a receiver component that can receive quantum input and a publication criterion associated with the quantum input from a source node. The computer-executable components may further include a computation component that can perform computations based on the quantum input in a buffered environment to generate results that satisfy the publication criterion. Embodiments of this system can provide numerous advantages, including efficient and rapid payload transfer between modules to allow streaming data for real-time decision-making in quantum-centric supercomputing.

[0006] In one or more embodiments of the aforementioned system, generating a result may include performing at least a first iteration of computation in a buffered environment to generate a first result. In one or more embodiments of the aforementioned system, an updating component may update the quantum input based on the first result to generate updated quantum input, such that performing computation in the buffered environment based on the updated quantum input can generate the result. In one aspect, if the result does not meet the publication criteria, the updating component may further update the updated quantum input based on the result. In one or more embodiments of the aforementioned system, an output component may publish an output to a receiver node based on the result, wherein the receiver node may be a quantum device or a classical device. In one or more embodiments of the aforementioned system, the source node may be a quantum device or a classical device. In one or more embodiments of the aforementioned system, generating a result based on publication criteria can improve the efficiency of the receiver node in performing computation. Embodiments of such a system can provide numerous advantages, including efficient and rapid payload transfer between modules to allow streaming data for real-time decision-making in quantum hub supercomputing; improved quantum processing unit (QPU) utilization by minimizing endpoint-to-quantum hardware compilation; and faster development of quantum computing products using a flexible and powerful quantum hub software framework.

[0007] According to various embodiments, the above system can be implemented as a computer-implemented method or as a computer program product. Attached Figure Description

[0008] One or more embodiments are described below in the detailed description section with reference to the following figures:

[0009] Figure 1 A block diagram of an exemplary non-limiting system that can provide a buffered environment for streaming payloads according to one or more embodiments described herein is shown.

[0010] Figure 2 A flowchart is shown illustrating an exemplary, non-limiting process for using a buffer to stream a payload according to one or more embodiments described herein.

[0011] Figure 3 A schematic diagram illustrates an exemplary, non-limiting implementation of a buffer environment interacting with classic source and classic receiver nodes according to one or more embodiments described herein.

[0012] Figure 4 Another flowchart illustrates an exemplary, non-limiting process for using a buffer to stream a payload according to one or more embodiments described herein.

[0013] Figure 5Another flowchart illustrates an exemplary non-limiting process for using a buffer to stream a payload according to one or more embodiments described herein.

[0014] Figure 6 Another flowchart illustrates an exemplary non-limiting process for using a buffer to stream a payload according to one or more embodiments described herein.

[0015] Figure 7 A flowchart is shown illustrating an exemplary non-limiting method that can provide a buffered environment for streaming payloads according to one or more embodiments described herein.

[0016] Figure 8 A block diagram is shown that illustrates an exemplary, non-limiting operating environment that may facilitate one or more embodiments described herein. Detailed Implementation

[0017] The following detailed description is merely illustrative and is not intended to limit the embodiments and / or applications or uses of the embodiments. Furthermore, there is no intention to be bound by any express or implied information presented in the foregoing Background or Summary of the Invention or Detailed Description sections.

[0018] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are used throughout the specification to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances.

[0019] The embodiments depicted in one or more of the accompanying drawings described herein are for illustrative purposes only, and therefore, the architecture of the embodiments is not limited to the systems, devices, and / or components described herein, nor is it limited to any particular order, connection, and / or coupling of the systems, devices, and / or components described herein. For example, in one or more embodiments, the non-limiting systems described herein, such as Figure 1 The non-limiting system 100 and its system shown may further include, in conjunction with the operating environment referred to herein (such as... Figure 8 The operating environment 800 shown is associated with and / or coupled to one or more computers and / or computing-based components described. For example, system 100 may be associated with the following references Figure 8 The described computing environment 800 is associated with features such as accessibility via the computing environment 800, allowing processing aspects to be distributed between the system 100 and the computing environment 800. In one or more of the described embodiments, a computer and / or computing-based components may be integrated into the implementation. Figure 1And / or one or more associated uses of the operations implemented by the systems, devices, components and / or computers shown and / or described in the other accompanying drawings described herein.

[0020] Quantum-centric supercomputing is the path to useful quantum computing. It can be defined as a modular computing architecture that enables scalability and combines communication and computation to increase computing power, while employing hybrid cloud middleware to seamlessly integrate quantum and classical workflows. One example of quantum-centric supercomputing could include circuit slicing to adapt larger quantum circuits to smaller quantum devices, where such slicing enables the collection and processing of tomographic results on the circuit fragments. Another example could include error mitigation methods with large classical overhead, where such mitigation enables the storage of device noise parameters, real-time (e.g., in flight) generation of mitigation circuits, and the collection and processing of the mitigation circuits' results to stream the expected value of the mitigation. In general, quantum-centric supercomputing can include classical computer networks connected to quantum computers and involves significantly complex timing, large amounts of data flowing between computing units, varying data sizes, different buffer times, etc. The data to be transferred between modules can be called payloads. In quantum-centric supercomputing, input circuits and output results, for example, can be payloads, with multiple payloads being transferred back and forth between modules and involving a large number of real-time decisions.

[0021] Payloads requiring real-time decision-making should be streamed rather than batch-processed. Streaming data can refer to performing computations on incoming data immediately, unlike batch processing, which involves collecting blocks of data and sending the collected data to a computer all at once for further computation and decision-making. Streaming payloads can be processed sequentially and incrementally on a record-by-record basis, or over a sliding time window, and can be used for various analyses, including correlation, aggregation, filtering, and sampling. The information derived from such analyses can provide companies with visibility into many aspects of their business and customer activities. In general, stream processing can involve processing within a rolling time window. For example, in the case of classical computing, stream processing can involve data in the form of single records or micro-batches, low latency, and simple analysis. Table 1 highlights the differences between stream processing and batch processing.

[0022] Table 1:

[0023]

[0024] While payloads requiring real-time decision-making should be streamed, coordinating the real-time streaming of large payloads across different use cases can be challenging. Existing solutions in this regard involve batch processing of data and do not provide a paradigm for handling diverse real-time payloads. Furthermore, existing hybrid quantum-classical computing workflows are application-specific and not generalizable within a streaming framework, and some existing methods do not allow low-level interactive access. For applications involving convergence criteria as parameters, some existing techniques allow specifying the number of samples to be acquired to achieve that criterion. However, this can be problematic because in some scenarios, the convergence criterion is significantly satisfied before the specified number of samples can be acquired, leading to oversampling without adding value to the given task, while in other scenarios, convergence is not achieved even after the specified number of samples are acquired. Therefore, efficient methods for streaming payloads based on quantum computing-specific inputs for real-time decision-making are desirable.

[0025] Various embodiments of this disclosure can be implemented to generate solutions to one or more of the problems described above. The embodiments described herein include systems, computer-implemented methods, and computer program products that can enable buffers for streaming payloads in quantum-centric supercomputing. For example, in various embodiments, the buffer can interact with a source node to receive input. In various embodiments, the source node can be a classical device or classical computer (e.g., a central processing unit (CPU)) or a quantum device or quantum computer (e.g., a QPU), and the input can be a quantum input comprising gates, circuit layers, circuits, circuit groups, bit string counts, probability distributions, expected values, etc. Inputs comprising gates, circuit layers, circuits, circuit groups, etc., can be received from classical devices, and inputs comprising bit string counts, probability distributions, expected values, etc., can be received from quantum devices.

[0026] In various embodiments, the buffer may also receive publication criteria associated with the corresponding input from classical or quantum devices. Publication criteria may include time window criteria, convergence criteria, sufficient compression criteria, or criteria for minimum or maximum memory size or dataset size, etc. In various embodiments, the buffer may store the input in memory, process the input in iterations, and compare the results of processing the input with the corresponding publication criteria. For example, the buffer may perform computations based on the input to generate a first result; if the first result does not meet the publication criteria, the buffer may update the input based on the first result, re-perform the computation using the first result to generate a second result, and so on. The buffer may perform computations until the publication criteria are met. In various embodiments, after generating a result that meets the publication criteria, the buffer may perform additional computations based on the result, and the buffer may publish the output of the additional computations to a receiver node. The receiver node may perform further processing of the output or perform actions based on the output received from the buffer. In various embodiments, the receiver node may also be a classical device or classical computer (e.g., CPU) or a quantum device or quantum computer (e.g., QPU). In various embodiments, the input may be received by the buffer and the output may be published by the buffer via cloud transmission.

[0027] In various embodiments, buffers can be implemented by streaming infrastructure to transmit data over a channel (topic) and a set of buffer instances. The method of implementing buffers on computational payloads can allow data to be processed in small packet sequences, which can allow buffers to implement streaming techniques such as back pressure, parallel processing, and unique quantum computing workloads such as transpilation, error mitigation, and expectation value computation. Buffer instances can be implemented in any programming language. The streaming infrastructure for the buffer can be a computing node comprising memory and a small computer. The buffer can store inputs in memory, and the buffer can employ a computer to perform computations on the stored inputs to process the inputs. In various embodiments, the memory can be classical memory and / or quantum memory, and the computer can be a classical computer (e.g., a CPU) and / or a quantum computer (e.g., a QPU). For example, because the input received by the buffer can contain quantum mechanical information that needs to be stored in quantum memory, the buffer can employ quantum memory in addition to classical memory. For example, the buffer can receive quantum states from a quantum computer, and the buffer can store the quantum states in quantum memory.

[0028] Therefore, a buffer can be a classical computing node, a quantum computing node, or both, or both. Since the computations performed by a buffer can involve the processing of a limited amount of information, a buffer can be a compact computing resource of the type required to perform a specific task based on acceptance and publication criteria. In other words, a buffer can be a small intermediary device between larger computing nodes. Other aspects of buffers will now be described in more detail with reference to the accompanying drawings.

[0029] Now go to Figure 1 This diagram illustrates an exemplary non-limiting system 100 that can provide a buffered environment for streaming payloads according to one or more embodiments described herein.

[0030] System 100 and / or components of System 100 can be employed to solve inherently highly technical problems (e.g., problems related to quantum supercomputing, buffers, streaming payloads, etc.) using hardware and / or software, problems that are not abstract and cannot be performed by humans as a set of thought activities. Furthermore, some of the processes performed can be executed by a dedicated computer for performing defined tasks related to buffers used for streaming payloads in quantum central supercomputing. System 100 and / or components of the system can be employed to address new problems arising from advancements in the technologies, computer architectures, etc., mentioned above. System 100 can provide technical improvements to quantum computing systems by enabling efficient and fast data transfer between computing nodes without overloading the network. For example, various embodiments herein can provide for streaming large payloads, where data can be transmitted bit by bit and real-time computation can be performed on the data, rather than transmitting data in large blocks (e.g., many gigabytes (GB)) and processing such payloads in batches.

[0031] System 100 can provide further improvements regarding sampling and accuracy. For example, by employing System 100, information can be sampled from a quantum computer fewer times, and the total amount of data to be transmitted can be smaller. Furthermore, by employing System 100, the number of samples to be acquired for the application can be pre-specified, ensuring that the results generated based on the specified number of samples are accurate, rather than guessing the sample size or post-hoc verification of the results' validity. For example, in a dynamically terminated adaptive zero-noise extrapolation application, batch processing could involve the user guessing the noise amplification factor, the extrapolation function, and the number of shots. Additionally, the user can submit a batch of noise-amplified circuits (up to many GB), receive a batch count for each circuit, estimate the zero-noise expectation using an error bar defined by the number of shots, and repeat the above steps if the results are inaccurate. Conversely, streaming data for the same application could involve the user defining the required level of accuracy and buffer window rate for the results and submitting a single target circuit (several megabytes (MB)). System 100 can then iteratively execute the streaming process between a cloud-hosted CPU and a QPU. During the buffering process, a batch of noise amplification circuits can be sent to the endpoints one by one. The zero-noise expected value can be returned to the CPU at the buffer window rate. The CPU can automatically select a new noise amplification factor, extrapolation function, and number of shots. The system 100 can repeat this process until the desired accuracy is achieved. Finally, the user can receive results with guaranteed accuracy.

[0032] The discussion temporarily turns to the processor 102, memory 104, and bus 106 of system 100. For example, in one or more embodiments, system 100 may include processor 102 (e.g., computer processing unit, microprocessor, classical processor, quantum processor, and / or similar processor). In one or more embodiments, components associated with system 100 as described herein (with or without reference to one or more figures of one or more embodiments) may include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that can be executed by processor 102 to enable the execution of one or more processes defined by such components and / or instructions.

[0033] In one or more embodiments, system 100 may include a computer-readable storage device (e.g., memory 104) operatively connected to processor 102. Memory 104 may store computer-executable instructions that, when executed by processor 102, cause processor 102 and / or one or more other components of system 100 (e.g., receiver component 108, computing component 110, update component 112, and / or output component 114) to perform one or more actions. In one or more embodiments, memory 104 may store computer-executable components (e.g., receiver component 108, computing component 110, update component 112, and / or output component 114).

[0034] System 100 and / or its components as described herein may be communicatively, electrically, operably, optically, and / or otherwise coupled to each other via bus 106. Bus 106 may include one or more of a memory bus, memory controller, peripheral bus, external bus, local bus, and / or another type of bus that may employ one or more bus architectures. One or more of these examples of bus 106 may be employed. In one or more embodiments, system 100 may be coupled (e.g., communicatively, electrically, operably, optically, and / or similarly) to one or more external systems (e.g., power generation systems not shown, one or more output targets, output target controllers, etc.), sources, and / or devices (e.g., classical computing devices, communication devices, etc.), for example, via a network. In one or more embodiments, one or more components of system 100 may reside in the cloud and / or may reside locally in a local computing environment (e.g., at one or more designated locations).

[0035] In addition to the processor 102 and / or memory 104 described above, system 100 may also include one or more computer and / or machine-readable, writable, and / or executable components and / or instructions that, when executed by processor 102, can enable the execution of one or more operations defined by such components and / or instructions. For example, system 100 may be a buffer that can enable streaming payloads for real-time decision-making in quantum-centric supercomputing. In various embodiments, receiver component 108 may receive quantum input 116 and publication standard 118 associated with quantum input 116 from a source node. In various embodiments, the source node may be a classical computer or a quantum computer, and quantum input 116 may include quantum gates, quantum circuit layers, quantum circuits, quantum circuit groups, bit string counts, probability distributions, or expected values, etc. Quantum input 116 including quantum gates, quantum circuit layers, quantum circuits, or quantum circuit groups, etc., may be received from classical devices, and quantum input 116 including bit string counts, probability distributions, or expected values, etc., may be received from quantum devices. In various embodiments, publication standard 118 may include time window criteria, convergence criteria, sufficient compression criteria, minimum or maximum memory criteria, or minimum or maximum dataset size criteria, etc. Publication standard 118 may be specific to quantum input 116.

[0036] In various embodiments, system 100 may store quantum input 116 in memory 104, and computation component 110 may perform computations in a buffered environment based on quantum input 116 to generate results that satisfy publication criterion 118. Generating results may include performing computations in the buffered environment for at least a first iteration to generate a first result. In various embodiments, updating component 112 may update quantum input 116 based on the first result to generate updated quantum input, such that performing computations in the buffered environment based on the updated quantum input can generate results that satisfy publication criterion 118. In one aspect, if the result does not satisfy publication criterion 118, updating component 112 may further update the updated quantum input based on the result.

[0037] More specifically, computation component 110 can perform computation in a buffered environment based on quantum input 116 to generate result 120, where result 120 may represent a result that satisfies publication criterion 118. For example, in various embodiments, generating result 120 may include performing computation in the buffered environment for at least a first iteration to generate a first result. In various embodiments, update component 112 may check whether the first result satisfies publication criterion 118. If the first result does not satisfy publication criterion 118, update component 112 may update quantum input 116 based on the first result to generate an updated quantum input. Then, computation component 110 may re-perform computation in the buffered environment based on the updated quantum input to generate a second result. In various embodiments, update component 112 may check whether the second result satisfies publication criterion 118. If the second result does not satisfy publication criterion 118, update component 112 may further update the updated quantum input based on the second result. Therefore, system 100 may iteratively perform computation until a usable result satisfying publication criterion 118 (e.g., result 120) can be generated.

[0038] In various embodiments, after generating result 120, computation component 110 can perform another computation based on result 120 to generate output, and output component 114 can publish the output to a receiver node that can perform further processing on the output or perform actions based on the output. In other words, system 100 can publish the output to the receiver node based on publication standard 118. In various embodiments, the receiver node can be a classical computer or a quantum computer. In various embodiments, quantum input 116 can be received by receiver component 108, and output can be published by output component 114 via cloud transmission. In various embodiments, generating result 120 based on publication standard 118 can increase the efficiency of computation performed by the receiver node. For example, in some scenarios, the receiver node can perform computation more promptly by utilizing output based on result 120 compared to using output not based on result 120, because output based on result 120 can include the exact information needed by the receiver node, and the receiver can begin computation immediately. For similar reasons, in some other scenarios, the receiver node can perform fewer computations because the receiver node can receive the exact information needed to generate further results.

[0039] In various embodiments, system 100 may be a buffer, which can be implemented via streaming infrastructure to transmit data over a channel (topic) and a set of implemented buffer instances. Thus, the buffer can provide a software framework that enables end-to-end protocols with several intermediate stages. For example, the buffer can receive quantum input 116 (e.g., quantum circuits, results from a sampling process, gates, runs (shots), expected values, quantum memory limitations, etc.) and generate result 120, which can be used for subsequent computations. The method implemented by the buffer on the computational payload (e.g., quantum input 116) can allow data to be processed in small packet sequences, which can allow the buffer to implement streaming techniques such as backpressure, parallel processing, etc., as well as unique quantum computing workloads such as translation, error mitigation, and expected value computation. Buffer instances can be implemented in any programming language. Algorithm 1 can be an algorithm of a software framework that can implement buffer instances.

[0040] Algorithm 1:

[0041] trait Type {

[0042] pub fn process(inputs: HashMap)

[0043] pub fn checkCriteria() -> Bool

[0044] pub fn release(sink: Channel)

[0045] }

[0046] pub struct Buffer<T: Type> {

[0047] source: Channel / / inputs channel

[0048] sink: Channel / / output channel

[0049] }

[0050] impl<T: Type> Buffer <t>{

[0051] [#listen(source)] / / stream handler listens to input channel

[0052] pub fn handle(inputs: HashMap) {

[0053] T.process(inputs); / / process input

[0054] if T.checkCriteria() { / / check release criterion

[0055] T.release(sink: Channel); / / release if criteria met to outchannel

[0056] }

[0057] }

[0058] }

[0059] Furthermore, the buffer can represent a computing node including memory 104 and processor 102. System 100 can store quantum input 116 in memory 104, and system 100 can employ processor 102 to perform computations based on quantum input 116. In various embodiments, memory 104 can represent classical memory (e.g., hard disk drive, etc.) and / or quantum memory, and processor 102 can represent a classical processor (e.g., CPU) and / or a quantum processor (e.g., QPU). For example, since quantum input 116 may include quantum mechanical information that needs to be stored in quantum memory, system 100 may require quantum memory to store quantum input 116. For example, system 100 may receive quantum states that may require quantum memory to store. Therefore, system 100 can be a classical computing node, a quantum computing node, or both, or a classical computing node and a quantum computing node. Since the computations performed by system 100 can involve the processing of a limited amount of information, system 100 can be a compact computing resource of the type required to perform a specific task based on a publishing standard. Therefore, system 100 can be a small intermediate device between larger nodes.

[0060] System 100 can be used for a variety of applications, some of which are listed in Table 2. As is apparent from Table 2 and as described elsewhere herein, the source node can be a classical computer or a quantum computer, the receiver node can be a classical computer or a quantum computer, and System 100 can include a classical computer, a quantum computer, or both, or both. For example, for state verification, System 100 could be a quantum computer that receives quantum information (such as quantum states) and generates outputs by performing computations that determine the fidelity of the quantum state to other quantum states of interest (e.g., a reference quantum state). System 100 can publish the outputs to receiver nodes, which can then feed the outputs to another quantum computer. Thus, System 100 can receive a single quantum state and generate an output for each quantum state, rather than, for example, receiving 100 quantum states, performing 100 computations to generate 100 outputs, and publishing all 100 outputs to the receiver nodes at once. Furthermore, the receiver nodes can determine the action to be performed based on the outputs per quantum state. A similar process can be applied. Figure 2 Other examples listed are explained in more detail with reference to the accompanying figures.

[0061] Table 2: Examples of applications of System 100 for real-time decision-making.

[0062]

[0063] System 100 can unlock new capabilities in quantum-centric supercomputing. For example, System 100 can provide efficient payload delivery even as quantum devices evolve from 100 qubits to 400 qubits, then to 1000 qubits, and finally to 100,000 qubits. Furthermore, System 100 can enable real-time decision-making in quantum computing, including dynamic termination, quantum error correction, and adaptive error mitigation. System 100 can also provide improved QPU utilization (U metric) by minimizing compilation to the quantum hardware endpoints and enabling faster development using a flexible and powerful quantum-centric software framework. Overall, System 100 can enable streaming data in quantum-centric supercomputing, where streaming data can offer advantages over batch processing of data.

[0064] Figure 2 A flowchart illustrating an exemplary, non-limiting process 200 using a buffer for streaming payloads according to one or more embodiments described herein is shown. References Figure 2 One or more embodiments described may be derived from Figure 1 One or more components are executed. For the sake of brevity, repeated descriptions of similar elements and / or processes used in various embodiments have been omitted.

[0065] In various embodiments, buffer 202 (e.g., system 100) can enable the streaming of payloads for real-time decision-making in quantum-centric supercomputing. For example, buffer 202 can interact with source node 208 to receive inputs and publishing criteria specific to those inputs. In various embodiments, source node 208 can be a classical computer 210 or a quantum computer 212, and the inputs can be quantum inputs, including quantum gates, quantum circuit layers, quantum circuits, quantum circuit groups, bit string counts, probability distributions, or expected values, etc. Quantum inputs including quantum gates, quantum circuit layers, quantum circuits, or quantum circuit groups, etc., can be received from classical computer 210, and quantum inputs including bit string counts, probability distributions, or expected values, etc., can be received from quantum computer 212. Buffer 202 can hold quantum inputs in memory associated with buffer 202 and publish inputs based on publishing criteria.

[0066] In various embodiments, the publication criteria may include time window criteria, convergence criteria, sufficient compression criteria, or minimum or maximum memory or dataset size criteria, etc. A corresponding publication criterion (e.g., publication criterion 118) may be specific to a particular quantum input (e.g., quantum input 116). In classical supercomputing, the publication criterion is typically a time window, where information can be collected by sensors and published at specified time intervals, such as every 100 microseconds (μs). In quantum supercomputing, convergence can also be an important publication criterion because quantum computers are probabilistic machines that can collect data over multiple runs, and the user can seek convergence after collecting data over a sufficient number of runs. Therefore, the various embodiments herein can be tailored to various publication criteria for quantum supercomputing. Another publication criterion in quantum supercomputing may be minimum / maximum memory or dataset size. In some applications, information may be collected until a specified number of data points are acquired, exceeding the specified number of data points, or a maximum number of data points are acquired. Therefore, the various embodiments herein can define general publication criteria that can be applied to different applications in quantum supercomputing.

[0067] In various embodiments, buffer 202 may store quantum inputs in memory and perform computations (e.g., using computing component 110) in a buffered environment based on the quantum inputs to generate a result (e.g., result 120) that satisfies publication criterion 118. For example, in various embodiments, buffer 202 may be a quantum computer that can perform at least a first iteration of quantum computation based on the quantum inputs to generate a first result. In various embodiments, buffer 202 may check (e.g., using update component 112) whether the first result satisfies a quantum input-specific publication criterion. If the first result does not satisfy the publication criterion, buffer 202 may update the quantum inputs based on the first result to generate updated quantum inputs. Thereafter, buffer 202 may re-execute (e.g., using computing component 110) the quantum computation in the buffered environment based on the updated quantum inputs to generate a second result. In various embodiments, buffer 202 may check (e.g., using update component 112) whether the second result satisfies the publication criterion. If the second result does not satisfy the publication criterion, buffer 202 may further update (e.g., using update component 112) the updated quantum inputs based on the second result. Therefore, buffer 202 can perform quantum computations in iterations until a result that meets the publication criteria can be generated.

[0068] In various embodiments, once a result is generated, buffer 202 can perform another computation based on the result (e.g., using computation component 110) to generate an output, and buffer 202 can publish the output (e.g., using output component 114) to receiver node 214, where receiver node 214 can perform further processing on the output or perform actions based on the output. In various embodiments, receiver node 214 can be a quantum computer 216 or a classical computer 218. In various embodiments, quantum input can be received by buffer 202 (e.g., via receiver component 108), and output can be published by buffer 202 (e.g., via output component 114) via transmission over a cloud network. In various embodiments, generating results based on publication criteria can improve the efficiency of performing computations for receiver node 214.

[0069] In summary, the following steps can be used to utilize buffer 202.

[0070] Step 1: Buffer 202 can be defined by input, release standard and output.

[0071] Step 2: Buffer 202 can accept input in memory.

[0072] Step 3: The buffer can handle the input.

[0073] Step 4: Buffer 202 can check the release standard.

[0074] Step 5: Buffer 202 can repeat steps 2-4 until the result that satisfies the release criteria is met.

[0075] Step 6: Buffer 202 can calculate the output based on the result.

[0076] Step 7: Buffer 202 can publish the output to receiver node 214.

[0077] As discussed in one or more embodiments, buffer 202 can be implemented via streaming infrastructure to transmit data over a channel (topic) and a set of implemented buffer instances. Therefore, buffer 202 can provide a software framework that enables end-to-end protocols with several intermediate stages. Furthermore, buffer 202 can represent a computing node including memory and a computer, allowing buffer 202 to store quantum inputs in memory and perform quantum input-based computations using a computer. The method implemented by buffer 202 on a computational payload (e.g., quantum input 116) can allow data to be processed in small packet sequences, which allows buffer 202 to implement streaming techniques such as backpressure, parallel processing, and unique quantum computing workloads such as translation, error mitigation, and expectation value computation. Buffer instances can be implemented in any programming language.

[0078] In various embodiments, the memory can be classical memory (e.g., hard disk drive, etc.) and / or quantum memory (e.g., memory 206), and the computer can be a classical computer and / or a quantum computer (e.g., CPU / QPU 204). For example, because the information received by buffer 202 from source node 208 may include quantum mechanical information, buffer 202 may require memory 206 to store quantum mechanical information. For example, buffer 202 may receive quantum states that may require quantum memory to store. Figure 2 In the diagram, memory 206 is shown as a diamond with embedded arrows and atoms, illustrating one way of describing a quantum memory. Arrows and atoms can represent defects in solid-state materials, and such materials are often attempted as quantum memories due to their ability to maintain quantum states. Therefore, buffer 202 can be a classical computing node, a quantum computing node, or both, or both. Since the computations performed by buffer 202 can involve processing a limited amount of information, buffer 202 can be a compact computing resource of the type required to perform a specific task based on acceptance and publication criteria. Therefore, buffer 202 can be a small intermediate device between larger nodes. Application examples of buffer 202 listed in Table 2 will now be described in more detail with reference to the following figures.

[0079] Figure 3 A schematic diagram illustrates an exemplary, non-limiting implementation 300 of a buffer environment interacting with classic source and classic receiver nodes according to one or more embodiments described herein. References Figure 3 One or more embodiments described may be derived from Figure 1 One or more components are executed. For the sake of brevity, repeated descriptions of similar elements and / or processes used in various embodiments have been omitted.

[0080] One application of quantum computing is the translation of quantum circuits, where the circuits can be manipulated based on topology matching the quantum hardware, reducing noise in the quantum circuits, and so on. Such quantum circuits are typically large-scale circuits. (Continue reading...) Figure 2 Instead of translating a large quantum circuit at a time, buffer 202 (e.g., system 100) can be used for on-the-fly translation of quantum circuits. For example, instead of feeding a large quantum circuit from source node 208 to buffer 202, the quantum circuit can be broken down into layers, and each layer of the quantum circuit can be an input from source node 208 to buffer 202 (e.g., quantum input 116). Buffer 202 can translate each layer of the quantum circuit in real time at a given instance, which can reduce the latency experienced when transferring quantum circuits (e.g., large payloads) back and forth between modules or computing nodes.

[0081] In this application, buffer 202 can accept (e.g., via receiver component 108) individual gates (i.e., individual quantum gates) as input, and the release criterion for buffer 202 can be defined as a sufficient number of gates to form a dense circuit layer (e.g., "sufficient gates to form a dense circuit layer"). Buffer 202 can process (e.g., using computing component 110) individual gates to form a circuit layer, and buffer 202 can check (e.g., using computing component 110) whether the aggregated circuit layer is dense before the released circuit layer is added to the translated quantum circuit. If the circuit layer is not dense enough to meet the release criterion, buffer 202 can continue to accept individual gates and process inputs to the circuit layer until the release criterion is met.

[0082] When the circuit layer is dense enough to meet the publishing criteria, buffer 202 can translate the circuit layer by adding parameterized Pauli gates for rotating and merging single-qubit gates (e.g., using computation component 110). For example, at 302, buffer 202 can process individual gates in the circuit layer in topological order, such as, for example, H gates (or Hadamard gates), Ry gates (which can perform single-qubit gates rotating by a certain amount θ around the Y-axis), X gates, or Pauli X gates (which can perform single-qubit gates rotating by π radians around the X-axis), etc., and at 304, buffer 202 can translate the circuit layer. After translating the circuit layer, buffer 202 can publish (e.g., using output component 114) the translated circuit layer on the fly. Reference Figure 1 The circuit layer published by buffer 202 can represent result 120, and the translated circuit layer can represent the output generated by buffer 202 based on result 120.

[0083] In this application, source node 208 can be classical computer 210, and receiver node 214 can be classical computer 218. While the applications discussed herein may involve classical-classical interactions, various embodiments enable classical-classical interactions (i.e., classical communication to classical communication interactions) by streaming payloads, rather than using batch processing as in the prior art. Furthermore, the embodiments discussed herein enable the application of this technology to the quantum realm.

[0084] Figure 4 Another flowchart illustrates an exemplary, non-limiting process 400 using a buffer for streaming payloads according to one or more embodiments described herein. References Figure 4 One or more embodiments described may be derived from Figure 1 One or more components are executed. For the sake of brevity, repeated descriptions of similar elements and / or processes used in the respective embodiments have been omitted.

[0085] In quantum computing, it is common to measure multiple Pauli operators (or Pauli observables) from quantum circuits, and Pauli observables can be measured in an efficient manner. (Continue to reference...) Figure 2 Buffer 202 (e.g., system 100) can be used for the estimation of complex operators. For example, buffer 202 can accept (e.g., via receiver component 108) Pauli observables from source node 208 and collect information from individual Pauli observables at a given time. After collecting the minimum required number of Pauli observables, buffer 202 can perform computations and publish the output of the computations to receiver node 214.

[0086] More specifically, buffer 202 can accept individual Pauli operators as inputs in memory and can define the release criteria of buffer 202 as N Pauli operators (e.g., "collect N Pauli operators"), where N represents a positive integer of the minimum number of Pauli operators required for a task. After receiving each Pauli operator, buffer 202 can perform calculations (e.g., using computing component 110) to count the number M of Pauli operators received as inputs, where M represents a positive integer of the number of Pauli operators counted by buffer 202. Additionally, buffer 202 can update (e.g., using update component 112) the value of M when receiving additional Pauli operators as inputs, and buffer 202 can check (e.g., using update component 112) whether the updated number M of Pauli operators exceeds the threshold number N of Pauli operators defined by the release criteria (i.e., if M > N).

[0087] If the value of M does not exceed the value of N, buffer 202 can continue to accept individual Pauli operators, count the number M of Pauli operators, and check whether the value of M exceeds the value of N. When the number M of Pauli operators exceeds the number N of Pauli operators, buffer 202 can perform additional calculations (e.g., using computing component 110) to determine the minimum number (e.g., O) of measurement rotation circuits for measuring M Pauli operators as efficiently as possible, and buffer 202 can release the number O of measurement rotation circuits to receiver node 214, where O represents a positive integer. Ideally, the number O of measurement rotation circuits can be less than the number M of Pauli operators.

[0088] In the present application, source node 208 can be a classical computer, and receiver node 214 can be a quantum computer. Receiver node 214 can execute O measurement rotation circuits and return the executed results to the quantum hardware. Refer to Figure 1 , for the number M of Pauli operators where M > N, it can represent result 120, and the number O of measurement rotation circuits can represent the output generated by buffer 202 based on result 120. A connectivity graph can be used to show that the number M of Pauli observables can be measured by buffer 202 using O measurement rotation circuits (O < M) (e.g., using computing component 110). The connectivity graph can show that different Pauli observables, such as XI, IX, XX, etc., can be measured using the same quantum circuit.

[0089] Figure 5 Another flowchart shows an exemplary non - restrictive process 500 for using a buffer for streaming payloads according to one or more embodiments described herein. Refer to Figure 5 One or more embodiments described may be derived from Figure 1 One or more components are executed. For the sake of brevity, repeated descriptions of similar elements and / or processes used in the respective embodiments have been omitted.

[0090] As discussed elsewhere in this article, convergence can be a crucial publication criterion in quantum supercomputing because quantum computers are probabilistic machines that can collect data across multiple runs and average the results of the collected data to generate a final answer. For example, a graph of the expected value (Y-axis) versus the number of runs (X-axis) can indicate that a quantum computer can be used to sample values ​​over time or multiple times, and that the sampled results can be expected to converge to a value with some fluctuation. See also... Figure 2 Buffer 202 (e.g., system 100) can be used for dynamic termination of expectation value estimation. For example, buffer 202 can accept (e.g., via receiver component 108) a bit string of the number of runs from source node 208 as input, and can define a publication criterion for buffer 202 (e.g., "expectation value should converge at 0.01") based on the expectation value that should converge at 0.01. After receiving the bit string as input, buffer 202 can store the bit string in memory, and buffer 202 can compute (e.g., using computation component 110) the expectation value based on all the bit strings in memory. For example, for each new bit string received as input, buffer 202 can compute the expectation value of all the bit strings in memory, and buffer 202 can update the expectation value generated during previous iterations. Additionally, buffer 202 can check (e.g., using update component 112) whether the bit string value has converged at 0.01 compared to the previous iteration. Algorithm 2 can be an example implementation of dynamic termination of expectation value computation.

[0091] Algorithm 2:

[0092] pub struct ExpValDynamicTerminationType {

[0093] lastIteration: Float,

[0094] threshold: Float = 0.01,

[0095] converged: Boolean = false

[0096] }

[0097] impl Type for ExpValDynamicTerminationType {

[0098] pub fn process(inputs: HashMap) {

[0099] expectationValue = inputs["expectationValue"];

[0100] if (lastIteration - expectationValue).abs() < self.threshold {

[0101] self.converged = true

[0102] }

[0103] self.lastIteration = expectationValue

[0104] }

[0105] pub fn checkCriteria() { self.converged}

[0106] pub fn release(sink: Channel) { self.sink.publish(self.lastIteration)}

[0107] }

[0108] pub type ExpValDynamicTerminationBuffer = Buffer <expvaldynamicterminationtype>;

[0109] buffer = ExpValDynamicTerminationBuffer(source, sink)

[0110] If the expected value does not converge according to the publication criteria, buffer 202 can continue to accept bit strings as input, compute the expected value from all bit strings in memory, and check beforehand whether the latest expected value is within the predefined tolerance range used for the publication / convergence criteria. If the expected value converges, buffer 202 can submit a new noise factor to the quantum backend, and buffer 202 can compute (e.g., using computation component 110) the converged expected value. That is, buffer 202 can adaptively determine the noise factor that should be measured for the expected value to achieve the goal of computed zero-noise expected value using the results of expected values ​​at different noise factors. Buffer 202 can then output the converged expected value to receiver node 214 (e.g., using output component 114), where the output can be received by the user.

[0111] In this application, the source node 208 can be a quantum computer, and the receiver node can be a classical computer. (See reference) Figure 1 The expected value calculated by buffer 202 can represent result 120, and the convergent expected value calculated by buffer 202 can represent the output generated by buffer 202 based on result 120.

[0112] Figure 6 Further flowcharts are shown of an exemplary non-limiting process 600 using a buffer for streaming payloads according to one or more embodiments described herein. References Figure 7 One or more embodiments described may be derived from Figure 1 One or more components are executed. For the sake of brevity, repeated descriptions of similar elements and / or processes used in the various embodiments have been omitted.

[0113] Continue to refer to Figure 2 Buffer 202 (e.g., system 100) can be used for state verification or quantum state verification. For example, buffer 202 can accept (e.g., via receiver component 108) a quantum state as input and store the quantum state in a quantum memory slot. In this application, the release criteria of buffer 202 can be defined by memory occupancy (e.g., "states A and B should be received in memory slots C and D"). Buffer 202 can accept quantum states as input, and buffer 202 can probe (e.g., using computing component 110) the quantum memory slots of memory 206 to determine the number of slots occupied by the quantum state. Additionally, buffer 202 can check (e.g., using update component 112) whether both memory slots are occupied.

[0114] If neither memory slot is occupied, buffer 202 can continue to accept quantum states, probing the quantum memory slots upon receiving each new quantum state and checking if the publication criteria are met. After both memory slots are occupied according to the publication criteria, buffer 202 can use a SWAP test to calculate (e.g., using computing component 110) the fidelity between states A and B. After calculating the fidelity, buffer 202 can publish the fidelity to receiver node 214 as needed. In this application, both source node 208 and receiver node 214 can be quantum computers. A SWAP test can be a method for calculating the fidelity between states A and B, and 'SWAP' can refer to the actual exchange of quantum states. When a controlled exchange is performed, the information that can be projected onto the zero-state qubit can be the fidelity. For example, in various embodiments, buffer 202 can calculate the fidelity between a first quantum state (e.g., Φ) and a second quantum state (e.g., ψ) by running quantum circuitry, and the information can be projected onto the zero-state qubit, where this information can represent the fidelity.

[0115] Figure 7 A flowchart is shown of an exemplary non-limiting method 700 that can provide a buffered environment for streaming payloads according to one or more embodiments described herein. References Figure 7 One or more embodiments described may be derived from Figure 1 One or more components are executed. For the sake of brevity, repeated descriptions of similar elements and / or processes used in the various embodiments have been omitted.

[0116] At 702, the non-limiting method 700 may include: receiving quantum input and a publication standard associated with the quantum input from the source node by a system operatively coupled to the processor (e.g., by receiver component 108).

[0117] At 704, the non-limiting method 700 may include: the system performing computation in a buffered environment based on quantum input (e.g., by computation component 110) to generate results that meet the publication criteria.

[0118] At 706, the non-limiting method 700 may include: updating the quantum input by the system based on a first result (e.g., by updating component 112) to generate an updated quantum input, such that performing computation based on the updated quantum input in a buffered environment can generate the result.

[0119] At 708, the non-restrictive method 700 may include: determining by the system (e.g., by the update component 112) whether the result meets the release criteria.

[0120] If so, at 710, the non-limiting method 700 may include: output generated by the system based on the result (e.g., by computing component 110), and output published by the system to the receiver node (e.g., by output component 114).

[0121] If not, at 712, the non-limiting method 700 may include: updating the component by the system based on the result (e.g., by updating component 112).

[0122] For the sake of simplicity, the computer-implemented and non-computer-implemented methods provided herein are depicted and / or described as a series of actions. It should be understood that the subject matter of the invention is not limited to the illustrated and / or described actions, nor to the order of the actions; for example, actions may occur in one or more sequences and / or may occur in parallel with other actions not described herein. Furthermore, not all actions shown can be used to implement the computer-implemented and non-computer-implemented methods according to the subject matter described herein. Additionally, the computer-implemented methods described below and throughout the specification can be stored on the article of manufacture to allow for the transfer and assignment of the computer-implemented methods to a computer. As used herein, the term article of manufacture is intended to cover a computer program accessible from any computer-readable device or storage medium.

[0123] The system and / or device have been (and / will be further) described herein with respect to the interaction between one or more components. Such a system and / or component may include specified components or sub-components therein, one or more specified components and / or sub-components, and / or additional components. Sub-components may be implemented as components communicatively coupled to other components, rather than being included within a parent component. One or more components and / or sub-components may be combined into a single component to provide aggregate functionality. For brevity, components may interact with other components not specifically described herein but known to those skilled in the art.

[0124] One or more embodiments described herein can employ hardware and / or software to solve highly technical problems that are not abstract and cannot be performed by humans as a set of mental activities. For example, even thousands of humans cannot efficiently, accurately, and / or effectively stream quantum information for real-time decision-making in quantum-centric supercomputing, a process that one or more embodiments described herein can enable. Furthermore, neither the human mind nor humans using pen and paper can, as described in one or more embodiments herein, base their work on results generated in a publishing-standard monitoring buffer environment.

[0125] In summary, the various embodiments described herein can provide a framework and protocol for transferring computation between quantum and classical computers. In some embodiments, the methods described herein can achieve a specific precision by increasing the number of times the quantum circuit is run, executed, or the number of operator measurements. This allows for automatic management of noise due to the inherent probabilistic nature of quantum computing without user input. Thus, the various embodiments described herein can control statistical noise through release criteria of convergence level. In other embodiments, the methods described herein can use efficient measurement bases to more effectively measure each measurement base to estimate the desired value within a specific precision. Overall, the various embodiments described herein can release quantum computing when release criteria are met. Depending on the application, release criteria can be specific precision, time window, convergence, size of memory or dataset, whether enough gates have been received to form a dense circuit layer, whether all desired values ​​of interest have been received, or whether certain quantum states have been stored, etc.

[0126] The embodiments discussed herein can provide numerous advantages for quantum computing systems, including efficient and rapid payload transfer between modules to allow streaming data for real-time decision-making in quantum-centric supercomputing, improved QPU utilization by minimizing compilation to endpoints of quantum hardware, and faster development of quantum computing products using a flexible and robust quantum-centric software framework. In the future, the embodiments of this disclosure can be extended to multiplexed inputs and / or outputs, as well as quantum memories and processing for quantum-to-quantum buffering. The data streams provided by the embodiments of this disclosure can also be explored in the future for secure protocols when communicating with external nodes, for adapting existing classical protocols to quantum data, and for communicating with higher levels of abstraction in the stack.

[0127] Figure 8 A block diagram of an exemplary non-limiting operating environment 800 that may facilitate one or more embodiments described herein is shown. Figure 8 The following discussion aims to provide suitable methods for implementation in Figure 1-7 A general description of the general operating environment 800 of one or more embodiments described herein.

[0128] Various aspects of this disclosure are described by narrative text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, in parallel, or in a manner that at least partially overlaps.

[0129] Computer Program Product Embodiment ("CPP Embodiment" or "CPP") is a term used in this disclosure to describe any group or number of storage media (also referred to as "media") that collectively comprise machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim, contained in one or more storage devices. A "storage device" is any tangible device capable of holding and storing instructions for use by a computer processor. Without limitation, a computer-readable storage medium can be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punch cards or pits / bumps formed on the main surface of a disc), or any suitable combination of the foregoing. As used in this disclosure, the term "computer-readable storage medium" should not be construed as storage in the form of transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, light pulses passing through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As those skilled in the art will understand, during normal operation of a storage device, such as during access, defragmentation, or garbage collection, data moves at some random points in time, but this does not make the storage device transient, because it is not transient when the data is stored.

[0130] The computing environment 800 includes examples of an environment for executing at least some computer code related to innovative methods, such as quantum input buffer code 845. In addition to block 845, the computing environment 800 also includes, for example, a computer 801, a wide area network (WAN) 802, an end-user device (EUD) 803, a remote server 804, a public cloud 805, and a private cloud 806. In this embodiment, the computer 801 includes a processor set 810 (including processing circuitry 820 and a cache 821), a communication structure 811, volatile memory 812, persistent storage device 813 (including an operating system 822 and the aforementioned block 845), a peripheral device set 814 (including a user interface (UI) device set 823, a storage device 824, and an Internet of Things (IoT) sensor set 825), and a network module 815. The remote server 804 includes a remote database 830. The public cloud 805 includes a gateway 840, a cloud orchestration module 841, a host physical machine set 842, a virtual machine set 843, and a container set 844.

[0131] Computer 801 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device that can be developed in the future to run programs, access networks, or query databases (such as remote database 830). As is well known in the art of computer technology, and depending on the technology, the performance of a computer-implemented method can be distributed among multiple computers and / or across multiple locations. On the other hand, in this introduction of computing environment 800, the focus is on a single computer, specifically computer 801, to keep the introduction as simple as possible. Computer 801 may reside in the cloud, even if it is not physically present in the cloud. Figure 8 The image shows the computer in the cloud. On the other hand, unless explicitly stated otherwise, computer 801 does not need to be located in the cloud.

[0132] Processor set 810 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 820 may be distributed across multiple packages, for example, multiple coordinated integrated circuit chips. Processing circuitry 820 may implement multiple processor threads and / or multiple processor cores. Cache 821 is located within the processor chip package and is typically used for memory that should be available for data or code that is quickly accessed by the threads or cores running on processor set 810. Cache memory is typically organized into multiple levels based on relative proximity to the processing circuitry. Alternatively, some or all of the cache of the processor set may be located "off-chip". In some computing environments, processor set 810 may be designed to work with qubits and perform quantum computing.

[0133] Computer-readable program instructions are typically loaded onto computer 801 to cause a series of operational steps to be performed by processor set 810 of computer 801, thereby implementing a computer-implemented method, such that the instructions executed instantiate the method specified in the flowcharts and / or descriptive passages of the computer-implemented method included in this document (collectively, the "innovative method"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 821 and other storage media discussed below. Processor set 810 accesses the program instructions and associated data to control and direct the execution of the innovative method. In computing environment 800, at least some of the instructions for executing the innovative method may be stored in block 845 of persistent storage device 813.

[0134] The communication structure 811 is a signal transmission path that allows the various components of the computer 801 to communicate with each other. Typically, this structure is made of switches and electrically conductive paths (such as switches and electrically conductive paths that form buses, bridges, physical input / output ports, etc.). Other types of signal communication paths, such as fiber optic communication paths and / or wireless communication paths, can be used.

[0135] Volatile memory 812 is any type of volatile memory now known or to be developed in the future. Examples include dynamically typed random access memory (RAM) or statically typed RAM. Typically, volatile memory is characterized by random access, but this is not necessary unless explicitly stated otherwise. In computer 801, volatile memory 812 is located in a single package and is located inside computer 801; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computer 801.

[0136] Persistent storage device 813 is any form of non-volatile storage for computers now known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained regardless of whether power is supplied to the computer 801 and / or directly to the persistent storage device 813. Persistent storage device 813 may be read-only memory (ROM), but typically at least a portion of the persistent storage device allows data to be written, deleted, and rewritten. Some familiar forms of persistent storage devices include hard disks and solid-state storage devices. Operating system 822 can take many forms, such as various known proprietary operating systems or operating systems of the open-source Portable Operating System Interface type employing a kernel. The code included in block 845 typically includes at least some computer code related to implementing innovative methods.

[0137] Peripheral device set 814 includes a collection of peripheral devices for computer 801. Data communication connections between peripheral devices and other components of computer 801 can be implemented in various ways, such as Bluetooth connections, near field communication (NFC) connections, connections made of cables (such as Universal Serial Bus (USB) type cables), plug-in type connections (e.g., secure digital (SD) cards), connections made over local area communication networks, and even connections made over wide area networks such as the Internet. In various embodiments, UI device set 823 may include components such as displays, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage device 824 is external memory, such as an external hard drive, or pluggable storage devices, such as SD cards. Storage device 824 can be persistent and / or volatile. In some embodiments, storage device 824 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 801 requires substantial storage (e.g., where computer 801 locally stores and manages a large database), such storage can be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 825 consists of sensors that can be used in IoT applications. For example, one sensor could be a thermometer, and another sensor could be a motion detector.

[0138] Network module 815 is a collection of computer software, hardware, and firmware that allows computer 801 to communicate with other computers via WAN 802. Network module 815 may include hardware (such as a modem or Wi-Fi transceiver), software for packetizing and / or depacketizing data for transmission over a communication network, and / or web browser software for communicating data via the Internet. In some embodiments, the network control and network forwarding functions of network module 815 are performed on the same physical hardware device. In other embodiments (e.g., embodiments using software-defined networking (SDN), the control and forwarding functions of network module 815 are performed on physically separate devices, such that the control functions manage multiple different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can typically be downloaded to computer 801 from an external computer or external storage device via a network adapter card or network interface included in network module 815.

[0139] A WAN (WAN) is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances using any currently known or future-developed technology. In some embodiments, a WAN can be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0140] End User Equipment (EUD) 803 is any computer system that can be used and controlled by an end user (e.g., an enterprise customer operating computer 801) and can take any of the forms discussed above regarding computer 801. EUD 803 typically receives helpful and useful data from the operation of computer 801. For example, assuming computer 801 is designed to provide recommendations to the end user, these recommendations would typically be communicated from computer 801's network module 815 via WAN 802 to EUD 803. Thus, EUD 803 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 803 can be a client device, such as a thin client, a thick client, a mainframe computer, a desktop computer, etc.

[0141] Remote server 804 is any computer system that can provide at least some data and / or functionality to computer 801. Remote server 804 can be controlled and used by the same entity operating computer 801. Remote server 804 represents a machine that collects and stores helpful and useful data for use by other computers, such as computer 801. For example, assuming computer 801 is designed and programmed to provide recommendations based on historical data, that historical data can be provided to computer 801 from a remote database 830 of remote server 804.

[0142] Public cloud 805 is any computer system that can be used by multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities (particularly data storage (cloud storage) and computing power) without direct active management by the user. Cloud computing typically leverages resource sharing to achieve consistency and economies of scale. Direct and active management of the computing resources of public cloud 805 is performed by the computer hardware and / or software of cloud orchestration module 841. The computing resources provided by public cloud 805 are typically implemented by virtual computing environments that run on individual computers constituting host physical machine set 842, which is the total number of physical computers in and / or available in public cloud 805. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 843 and / or containers from container set 844. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after VCE instantiation. Cloud orchestration module 841 manages the transfer and storage of images, deploys new VCE instantiations, and manages active VCE deployment instantiations. Gateway 840 is a collection of computer software, hardware, and firmware that allows public cloud 805 to communicate via WAN 802.

[0143] Now, some further explanation of Virtualized Computing Environments (VCEs) will be given. A VCE can be stored as an "image." New active instances of a VCE can be instantiated from an image. Two familiar types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows the existence of multiple isolated user-space instances (called containers). These isolated user-space instances typically behave like a real computer to the programs running on them. A computer program running on a regular operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running within a container can only use the contents of the container and the devices allocated to the container; this is a characteristic known as containerization.

[0144] Private cloud 806 is similar to public cloud 805, except that computing resources are available only to a single enterprise. While private cloud 806 is depicted as communicating with WAN 802, in other embodiments, private cloud can be completely disconnected from the internet and accessed only through a local / private network. Hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is brought together by standardized or proprietary technologies that enable coordination, management, and / or data / application portability across the multiple component clouds. In this embodiment, public cloud 805 and private cloud 806 are both part of a larger hybrid cloud.

[0145] The embodiments described herein may refer to any one or more systems, methods, apparatuses, and / or computer program products, with integration at any possible level of technical detail. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of one or more embodiments described herein. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, superconducting storage devices, and / or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile optical disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as perforated cards or protruding structures having instructions recorded thereon in recesses), and / or any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as temporary signals themselves, such as radio waves and / or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides and / or other transmission media (e.g., light pulses passing through fiber optic cables), and / or electrical signals transmitted through wires.

[0146] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, and / or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them for storage in a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of one or more embodiments described herein may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, and / or object code and / or source code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and / or procedural programming languages ​​such as the "C" programming language and / or similar programming languages. Computer-readable program instructions can be executed entirely on a computer, partially on a computer, as a standalone software package, partially on a computer and / or partially on a remote computer, or entirely on a remote computer and / or a server. In the latter case, the remote computer can be connected to the computer via any type of network, including local area networks (LANs) and / or wide area networks (WANs), and / or can be connected to an external computer (e.g., via the Internet provided by an Internet service provider). In one or more embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), and / or programmable logic arrays (PLAs) can be personalized with state information from the computer-readable program instructions to execute aspects of one or more embodiments described herein, thereby executing the computer-readable program instructions.

[0147] Aspects of one or more embodiments described herein are described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and / or computer program products according to one or more embodiments described herein. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, and / or other programmable data processing apparatus to produce a machine, such that the instructions, executable via the processor of the computer or other programmable data processing apparatus, can create means for implementing the functions / actions specified in the flowchart and / or block diagram blocks or frames. These computer-readable program instructions can also be stored in a computer-readable storage medium capable of directing a computer, programmable data processing apparatus, and / or other devices to function in a particular manner, such that a computer-readable storage medium having instructions stored therein can include an article of manufacture containing instructions that can implement aspects of the functions / actions specified in the flowchart and / or block diagram blocks or frames. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus and / or other equipment to cause a series of operations to be performed on the computer, other programmable apparatus and / or other equipment to produce a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus and / or other equipment implement the functions / actions specified in the flowchart and / or block diagram boxes or frames.

[0148] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and / or operation of possible implementations of systems, computer-implementable methods, and / or computer program products according to one or more embodiments described herein. In this regard, each block in a flowchart or block diagram may represent a portion of a module, segment, and / or instruction, which includes one or more executable instructions for implementing a specified logical function. In one or more alternative implementations, the functions indicated in the blocks may occur in a different order than that indicated in the figures. For example, two blocks shown consecutively may be executed substantially simultaneously, and / or blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block and / or combination of blocks illustrated in the block diagrams and / or flowcharts may be implemented by a system based on dedicated hardware capable of performing the specified functions and / or actions and / or executing one or more combinations of dedicated hardware and / or computer instructions.

[0149] While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and / or multiple computers, those skilled in the art will recognize that one or more embodiments described herein can also be implemented, at least in part, in parallel with one or more other program modules. Typically, program modules include routines, programs, components, and / or data structures that perform specific tasks and / or implement specific abstract data types. Furthermore, the computer-implemented methods described above can be implemented using other computer system configurations, including single-processor and / or multi-processor computer systems, small computing devices, mainframe computers, etc., as well as computers, handheld computing devices (e.g., PDAs, telephones), and / or microprocessor-based or programmable consumer and / or industrial electronic devices. The aspects shown can also be implemented in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. However, one or more aspects, if not all, of the embodiments described herein can be implemented on a standalone computer. In a distributed computing environment, program modules can reside in both local and remote memory storage devices.

[0150] As used herein, the terms "component," "system," "platform," and / or "interface" may refer to and / or include entities related to a computer or to an operating machine having one or more specific functions. Entities described herein may be hardware, a combination of hardware and software, software, or software being executed. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. For illustration, applications running on a server and servers themselves can both be components. One or more components may reside within a process and / or execution thread, and components may be located on a single computer and / or distributed across two or more computers. In another example, individual components may be executable from various computer-readable media on which various data structures are stored. Components may communicate via local and / or remote processes, such as according to signals having one or more data packets (e.g., data from one component interacting with a local system, another component in a distributed system, and / or data interacting with other systems via signals across a network such as the Internet). As another example, a component can be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by software and / or firmware applications executed by a processor. In this case, the processor can be located internally and / or externally to the device and can execute at least a portion of the software and / or firmware applications. As yet another example, a component can be a device without mechanical parts that provides specific functions through electronic parts, wherein the electronic parts can include a processor and / or other devices to execute software and / or firmware that at least partially endow the electronic parts with functionality. In one aspect, the component can simulate electronic parts via a virtual machine, for example, in a cloud computing system.

[0151] Furthermore, the term "or" is intended to mean an inclusive "or," not an exclusive "or." That is, unless otherwise stated or clear from the context, "X adopts A or B" is intended to mean any of the natural inclusive permutations. That is, if X adopts A; X adopts B; or X adopts both A and B, then in any of the foregoing instances, "X adopts A or B" is satisfied. Additionally, the articles "a" and "an" as used herein should generally be interpreted as meaning "one or more," unless otherwise stated or clearly indicated from the context to the singular form. The terms "example" and / or "exemplary" as used herein are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter described herein is not limited to such examples. Furthermore, any aspect or design described herein as "example" and / or "exemplary" does not necessarily imply preference or advantage over other aspects or designs, nor does it exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0152] As used herein, the term "processor" can refer to virtually any computing processing unit and / or device, including but not limited to: a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and / or a parallel platform with distributed shared memory. Furthermore, a processor can refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, and / or any combination thereof designed to perform the functions described herein. Additionally, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and / or gates, to optimize space utilization and / or enhance the performance of the associated device. A processor can be implemented as a combination of computing processing units.

[0153] In this document, terms such as "storage," "storage device," "data storage," "data storage apparatus," "database," and any other information storage component substantially related to the operation and function of a component are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. The memory and / or memory components described herein can be volatile or non-volatile memory, or may include both. By way of illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, and / or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may, for example, act as external cache memory. By way of illustration and not limitation, RAM can be available in a variety of forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and / or Rambus dynamic RAM (RDRAM). Furthermore, the memory components and / or computer-implemented methods of the systems described herein are intended to include, but are not limited to, these and / or any other suitable types of memory.

[0154] The above description includes only examples of systems and computer-implemented methods. It is certainly impossible to describe every conceivable combination of components and / or computer-implemented methods for the purpose of describing one or more embodiments; however, those skilled in the art will recognize that many further combinations and / or arrangements of one or more embodiments are possible. Furthermore, with regard to the use of the terms "comprising," "having," "possessing," etc., in the detailed description, claims, appendices, and / or drawings, these terms are intended to be inclusive in a manner similar to the interpretation of the term "comprising" when used as a transitional term in a claim.

[0155] The descriptions of various embodiments have been presented for illustrative purposes and are not intended to be exhaustive or to limit the embodiments to those described herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, and / or technical improvements relative to technologies found on the market, and / or to enable others skilled in the art to understand the embodiments described herein.< / expvaldynamicterminationtype> < / t>

Claims

1. A system comprising: Memory stores computer-executable components; as well as A processor that executes computer-executable components stored in memory, wherein the computer-executable components include: A receiver assembly that receives quantum input and a publication standard associated with the quantum input from a source node; as well as A computing component that performs computations in a buffered environment based on quantum input to generate results that meet publication standards.

2. The system according to claim 1, wherein, The generation of results includes performing at least the first iteration of computation in a buffered environment to generate the first result.

3. The system according to claim 2, further comprising: An updating component updates the quantum input based on the first result to generate an updated quantum input, such that computation is performed in a buffered environment based on the updated quantum input to generate the result.

4. The system according to claim 3, wherein, If the result does not meet the publication criteria, the updating component further updates the updated quantum input based on the result.

5. The system according to any one of the preceding claims further comprises: An output component that outputs the result to a receiver node, wherein the receiver node is a quantum device or a classical device.

6. The system according to any one of the preceding claims, wherein, The source node can be a quantum device or a classical device.

7. The system according to any one of the preceding claims, wherein, Generating the results based on the publishing standard improves the efficiency of the receiver node in performing computations.

8. A computer-implemented method, comprising: A system operatively coupled to the processor receives quantum input from the source node and a publication standard associated with the quantum input; as well as The system performs computations in a buffered environment based on quantum inputs to generate results that meet publication criteria.

9. The computer-implemented method according to claim 8, wherein, The generation of results includes performing at least the first iteration of computation in a buffered environment to generate the first result.

10. The computer-implemented method according to claim 9, further comprising: The system updates the quantum input based on the first result to generate an updated quantum input, such that computation is performed in a buffered environment based on the updated quantum input to generate the result.

11. The computer-implemented method according to claim 10, further comprising: If the result does not meet the publication criteria, the system updates the updated quantum input based on the result.

12. The computer-implemented method according to any one of claims 8 to 11 further comprises: The system outputs the result to a receiver node, which is either a quantum device or a classical device.

13. The computer-implemented method according to any one of claims 8 to 12, wherein the source node is a quantum device or a classical device.

14. The computer-implemented method according to any one of claims 8 to 13, wherein, Generating the results based on the publishing standard improves the efficiency of the receiver node in performing computations.

15. A computer program product for enabling a buffer for streaming in quantum-centric supercomputing, the computer program product comprising a computer-readable storage medium having program instructions implemented therewith, the program instructions being executable by a processor to cause the processor to: The processor receives the quantum input and the publication standard associated with the quantum input from the source node; and The processor performs computations in a buffered environment based on quantum inputs to generate results that meet publication criteria.

16. The computer program product according to claim 15, wherein, The generation of results includes performing at least the first iteration of computation in a buffered environment to generate the first result.

17. The computer program product according to claim 16, wherein, The program instructions can also be executed by a processor to cause the processor to: The processor updates the quantum input based on the first result to generate an updated quantum input, such that computation is performed in a buffered environment based on the updated quantum input to generate the result.

18. The computer program product according to claim 17, wherein, The program instructions can also be executed by a processor to cause the processor to: If the result does not meet the publication criteria, the processor updates the updated quantum input based on the result.

19. The computer program product according to any one of claims 15 to 18, wherein, The program instructions can also be executed by a processor to cause the processor to: The processor outputs the result to a receiver node, which is either a quantum device or a classical device.

20. The computer program product according to any one of claims 15 to 19, wherein the source node is a quantum device or a classical device.

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