Light emitting diode chip, preparation method thereof, display panel and display device

Abstract

Light-emitting diode (LED) chips, their fabrication methods, display panels, and display devices are disclosed. The LEDs include a substrate; a light-emitting unit disposed on the substrate, comprising an array of multiple light-emitting elements; each light-emitting element includes a first semiconductor layer, a quantum well material layer, and a second semiconductor layer stacked along a direction perpendicular to the plane of the substrate, the first semiconductor layer being disposed close to the substrate; a dielectric insulating layer disposed on the substrate, comprising multiple through-holes corresponding one-to-one with the light-emitting elements, the light-emitting elements being at least partially located within the through-holes; a first electrode disposed on the side of the light-emitting unit facing away from the substrate; and a bonding pad disposed on the side of the first electrode facing away from the substrate.

Description

Light-emitting diode chips and their fabrication methods, display panels, and display devices. Technical Field

[0001] This disclosure relates to the field of display device technology, and in particular to a light-emitting diode chip and its fabrication method, a display panel, and a display device. Background Technology

[0002] Conventional gallium nitride (GaN)-based LEDs (light-emitting diodes) typically employ an epitaxial InGaN / GaN multiple quantum well structure as the active layer on a c-plane sapphire substrate. Due to the significant lattice and thermal mismatch between the substrate and epitaxial materials, a strong polarization electric field exists within the quantum well structure grown on the c-plane. This causes spatial wavefunction separation between electrons and holes, leading to a decrease in internal quantum efficiency and thus limiting the luminous efficiency of GaN-based LEDs. Furthermore, total internal reflection at the GaN-air interface significantly restricts the light extraction efficiency of GaN-based LEDs.

[0003] Summary of the Invention

[0004] According to a first aspect of this disclosure, a light-emitting diode chip is provided, comprising:

[0005] Substrate;

[0006] A light-emitting unit is disposed on the substrate and includes a plurality of light-emitting elements arranged in an array; each light-emitting element includes a first semiconductor layer, a quantum well material layer and a second semiconductor layer stacked along a direction perpendicular to the plane of the substrate, wherein the first semiconductor layer is disposed close to the substrate;

[0007] A dielectric insulating layer is disposed on the substrate, including a plurality of through holes corresponding one-to-one with the light-emitting element, wherein the light-emitting element is at least partially located in the through holes;

[0008] The first electrode is disposed on the side of the light-emitting layer away from the substrate, corresponding one-to-one with the light-emitting unit, and the orthographic projection of the first electrode on the substrate coincides with the orthographic projection of the light-emitting unit on the substrate;

[0009] A bonding pad is disposed on the side of the first electrode away from the substrate, corresponding to the first electrode one by one, and the orthographic projection of the bonding pad on the substrate coincides with the orthographic projection of the first electrode on the substrate.

[0010] Optionally, the cross-sectional shape of the light-emitting body in a plane parallel to the substrate includes a circle, a square, or a polygon.

[0011] Optionally, the light emitter has a circular cross-sectional shape in the plane parallel to the substrate, and the diameter of the circular cross-section is greater than or equal to 300 nm and less than or equal to 1000 nm.

[0012] Optionally, the distance between two adjacent light emitters is greater than or equal to 300 nm and less than or equal to 1000 nm.

[0013] Optionally, the thickness of the light emitter is greater than or equal to 400 nm and less than or equal to 2000 nm.

[0014] Optionally, the dielectric insulating layer is doped with quantum dot material.

[0015] Optionally, the light-emitting diode chip further includes:

[0016] A reflective layer is disposed on the side of the light-emitting layer opposite to the substrate, and the orthographic projection of the reflective layer on the substrate does not overlap with the orthographic projection of the bonding pad on the substrate.

[0017] Optionally, the light-emitting diode chip further includes:

[0018] A buffer layer is disposed between the substrate and the light-emitting unit.

[0019] According to a second aspect of the present disclosure, a display panel is provided, including a back panel and a plurality of light-emitting diode chips as provided in the first aspect of the present disclosure disposed on the back panel;

[0020] The backplane is provided with a bonding layer, which includes a plurality of mating pads. The mating pads correspond one-to-one with the bonding pads of the light-emitting diode chip and are bonded to each other.

[0021] Optionally, the display panel further includes:

[0022] The second electrode is disposed on the side of the light-emitting unit of the LED chip that is away from the back plate.

[0023] According to a third aspect of this disclosure, a display device is provided, including a display panel as provided in the second aspect of this disclosure.

[0024] According to a fourth aspect of this disclosure, a method for fabricating a light-emitting diode chip is provided. In some embodiments, the fabrication method includes:

[0025] Provide substrate;

[0026] A light-emitting unit is formed on one side of the substrate. The light-emitting unit includes a plurality of light-emitting elements arranged in an array. The light-emitting element includes a first semiconductor layer, a quantum well material layer and a second semiconductor layer stacked along a direction perpendicular to the plane of the substrate. The first semiconductor layer is disposed close to the substrate.

[0027] A dielectric insulating layer is formed on one side of the substrate, the dielectric insulating layer including a plurality of through holes corresponding one-to-one with the light emitter, the light emitter being at least partially located in the through holes;

[0028] A first electrode is formed on the side of the light-emitting element that is away from the substrate;

[0029] A bonding pad is formed on the side of the first electrode away from the substrate to form an intermediate structure;

[0030] The intermediate structure is patterned to form multiple mutually separated and insulated light-emitting units. Each light-emitting unit includes at least two light emitters, and each light-emitting unit has a first electrode and a bonding pad.

[0031] In other embodiments, the preparation method includes:

[0032] A first semiconductor layer, a quantum well material layer, a second semiconductor layer, and a mask layer are sequentially formed on the substrate;

[0033] The mask layer is patterned, and the patterned mask layer is etched to expose a portion of the second semiconductor layer.

[0034] The second semiconductor layer, the quantum well material layer, and the first semiconductor layer are sequentially etched to form multiple light emitters;

[0035] In this process, the first semiconductor layer is partially etched to form a semiconductor thin film layer.

[0036] Optionally, the thickness of the mask layer is greater than or equal to 100 nm and less than or equal to 400 nm.

[0037] In some other embodiments, the preparation method includes:

[0038] A first semiconductor layer is formed on one side of the substrate;

[0039] A mask layer is formed on the side of the first semiconductor layer that is away from the substrate;

[0040] The mask layer is patterned to expose a portion of the first semiconductor layer;

[0041] A quantum well material layer and a second semiconductor layer are formed on the exposed first semiconductor layer to form a plurality of light emitters.

[0042] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 is a schematic diagram of a planar structure of a light-emitting diode chip according to an embodiment of the present disclosure;

[0045] Figure 2 is a schematic diagram of the planar structure of a single light-emitting unit in a light-emitting diode chip according to an embodiment of the present disclosure;

[0046] Figure 3 is a structural schematic diagram of section A-A' in Figure 1;

[0047] Figure 4 is a flowchart of the steps of a method for fabricating a light-emitting diode chip according to an embodiment of the present disclosure;

[0048] Figure 5 is a schematic diagram of the structure of a light-emitting diode chip according to an embodiment of the present disclosure, showing the fabrication of a first semiconductor layer, a quantum well material layer, a second semiconductor layer and a mask layer.

[0049] Figure 6 is a schematic diagram of the graphic structure of a light-emitting diode chip completing a mask layer according to an embodiment of the present disclosure;

[0050] Figure 7 is a schematic diagram of a light-emitting diode chip completing mask layer etching according to an embodiment of the present disclosure;

[0051] Figure 8 is a schematic diagram of a light-emitting diode chip after etching the first semiconductor layer, the quantum well material layer and the second semiconductor layer according to an embodiment of the present disclosure.

[0052] Figure 9 is a schematic diagram of a light-emitting diode chip completing mask layer removal according to an embodiment of the present disclosure;

[0053] Figure 10 is a schematic diagram of the structure of a light-emitting diode chip after completing the fabrication of the first semiconductor layer and mask layer according to an embodiment of the present disclosure;

[0054] Figure 11 is a schematic diagram of a light-emitting diode chip in an embodiment of the present disclosure, showing the completion of mask layer etching and exposure of the first semiconductor layer.

[0055] Figure 12 is a schematic diagram of the structure of a light-emitting diode chip that completes the growth of a quantum well material layer and a second semiconductor layer according to an embodiment of the present disclosure;

[0056] Figure 13 is a schematic diagram of a structure for filling a dielectric insulating layer in a light-emitting diode chip according to an embodiment of the present disclosure.

[0057] Figure 14 is a schematic diagram of a structure for etching the dielectric insulating layer of a light-emitting diode chip according to an embodiment of the present disclosure.

[0058] Figure 15 is a schematic diagram of the structure of a light-emitting diode chip completing the fabrication of the first electrode according to an embodiment of the present disclosure;

[0059] Figure 16 is a schematic diagram of the structure of a light-emitting diode chip according to an embodiment of the present disclosure, showing the fabrication of a first semiconductor layer, a quantum well material layer, a second semiconductor layer, a third electrode, and a mask layer.

[0060] Figure 17 is a schematic diagram of a light-emitting diode chip in an embodiment of the present disclosure, showing the completion of mask layer etching and exposure of part of the third electrode;

[0061] Figure 18 is a schematic diagram of a light-emitting diode chip according to an embodiment of the present disclosure, showing the etching of a first semiconductor layer, a quantum well material layer, a second semiconductor layer and a third electrode.

[0062] Figure 19 is a schematic diagram of a light-emitting diode chip in an embodiment of the present disclosure, in which a dielectric insulating layer is filled on the third electrode layer.

[0063] Figure 20 is a schematic diagram of a light-emitting diode chip according to an embodiment of the present disclosure, in which the dielectric insulating layer is etched on the third electrode layer and the third electrode is exposed.

[0064] Figure 21 is a schematic diagram of a common electrode fabrication structure of a light-emitting diode chip according to an embodiment of the present disclosure;

[0065] Figure 22 is a schematic diagram of the structure of a light-emitting diode chip completing the bonding pad fabrication according to an embodiment of the present disclosure;

[0066] Figure 23 is a schematic diagram of a light-emitting diode chip completing the patterning process and the fabrication of the reflective layer according to an embodiment of the present disclosure;

[0067] Figure 24 is a schematic diagram of the structure of another light-emitting diode chip according to an embodiment of the present disclosure;

[0068] Figure 25 is a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure. Specific Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0070] Referring to Figures 1 and 3, a light-emitting diode chip is provided according to an embodiment of the present disclosure. The light-emitting diode chip includes a substrate 10, a light-emitting unit 20, a dielectric insulating layer 30, a first electrode 40, and a bonding pad 80.

[0071] Specifically, the substrate 10 can be made of any one of sapphire, silicon, or silicon carbide (SiC). In this embodiment, the substrate 10 is made of sapphire. In some embodiments, a buffer layer is formed on the substrate 10 before the light-emitting layer 20 is fabricated. The buffer layer can be made of gallium nitride.

[0072] The light-emitting unit 20 is disposed on one side of the substrate 10. The light-emitting unit 20 can emit light. When applied to a display device, the display of image content can be achieved by utilizing the coordination between the light emitted by the light-emitting layer 20. It can be understood that the light-emitting diode chip includes a light-emitting area and a non-light-emitting area, wherein the orthogonal projection of the light-emitting unit 20 on the substrate 10 is located within the light-emitting area.

[0073] Referring to FIG1, in this embodiment of the present disclosure, the light-emitting unit 20 includes a plurality of light-emitting elements 22. The plurality of light-emitting elements 22 are arranged in an array on the substrate 10. The cross-sectional shape of the light-emitting elements 22 parallel to the plane of the substrate 10 can be any one of circular, square or polygonal. That is, the overall shape of the light-emitting elements 22 can be approximately any one of cylindrical, square prism or variable prism. This embodiment of the present disclosure does not limit this, and those skilled in the art can set it according to actual needs.

[0074] In this embodiment, the light emitter 22 has a circular cross-sectional shape parallel to the plane of the substrate 10, and the diameter of the circular cross-section is greater than or equal to 300 nm and less than or equal to 1000 nm. That is, the diameter of the light emitter 22 is greater than or equal to 300 nm and less than or equal to 1000 nm. Exemplarily, the diameter of the light emitter 22 can be 300 nm, 500 nm, 700 nm, 900 nm, 1000 nm, etc.

[0075] Referring to Figure 3, in this embodiment of the present disclosure, the thickness h of the light-emitting element 22 is greater than or equal to 400 nm and less than or equal to 2000 nm. The thickness h of the light-emitting element 22 can also be understood as the height of the light-emitting element 22, that is, the dimension of the light-emitting element 22 in the light-emitting direction of the light-emitting chip. Exemplarily, the thickness h of the light-emitting element 22 can be 400 nm, 800 nm, 1200 nm, 1600 nm, 2000 nm, etc.

[0076] Referring to FIG2, in this embodiment of the present disclosure, the distance a / b between two adjacent light emitters 22 is greater than or equal to 300 nm and less than or equal to 1000 nm. Exemplarily, the distance a / b between two adjacent light emitters 22 can be 300 nm, 500 nm, 700 nm, 900 nm, 1000 nm, etc. It is understood that the distance a between two adjacent light emitters 22 in the first direction and the distance b between two adjacent light emitters 22 in the second direction can be equal or unequal.

[0077] Referring to FIG3, in this embodiment, each light emitter 22 includes a first semiconductor layer 221, a quantum well material layer 222, and a second semiconductor layer 223 stacked in a direction perpendicular to the plane of the substrate 10, with the first semiconductor layer 221 disposed close to the substrate 10. The first semiconductor layer 221 can be made of n-type gallium nitride, and the second semiconductor layer 223 can be made of p-type gallium nitride. Therefore, after applying an electrical signal to each light emitter 22, each light emitter 22 can emit light.

[0078] Furthermore, in this embodiment, a semiconductor thin film layer 21 is formed between the light emitter 22 and the substrate 10. This semiconductor thin film layer 21 is used to realize the electrical connection between the multiple light emitters 22, that is, electrical signals can be transmitted to each light emitter 22 through the semiconductor thin film layer 21. The material of the semiconductor thin film layer 21 can be the same as the material of the first semiconductor layer 221 and formed in the same preparation step (in the accompanying drawings, the semiconductor thin film layer 21 and the first semiconductor layer 221 are shown separately to distinguish them).

[0079] Furthermore, referring to Figure 3, a dielectric insulating layer 30 is formed on one side of the substrate 10. The dielectric insulating layer 30 includes a plurality of vias (not shown in the figure) corresponding one-to-one with the light emitters 22, and the light emitters 22 are at least partially located in the corresponding vias to achieve insulation between the light emitters 22. The dielectric insulating layer 30 can cover the sidewalls of the light emitters 22, thereby passing off the sidewalls and reducing surface defects of the light emitters 22 caused by subsequent etching processes. The dielectric insulating layer 30 can be made of SOG (Silicon On Glass) material.

[0080] In some embodiments, quantum dot materials can be doped into the dielectric insulating layer 30 to achieve the conversion of blue light to red or green light, and ultimately realize full-color display of red, green, and blue light. The quantum dot materials can be selected from cadmium selenide (CdSe), zinc selenide (ZnSe), indium phosphide (InP), etc.

[0081] Referring to FIG3, a first electrode 40 is disposed on the side of the light-emitting layer 20 facing away from the substrate 10, and the first electrode 40 is connected to each light-emitting element 22. The first electrode 40 is mainly used to realize the connection between the light-emitting elements 22. The first electrode 40 can be a transparent electrode layer made of indium tin oxide (ITO), or a transparent electrode layer made of indium zinc oxide (IZO), or at least one of gold (Au), tin (Sn), silver (Ag), titanium (Ti), aluminum (Al), nickel (Ni), and copper (Cu). In the embodiments of this disclosure, multiple first electrodes 40 are provided, and each first electrode 40 corresponds to a light-emitting unit 20. At the same time, the orthographic projection of the first electrode 40 on the substrate 10 coincides with the orthographic projection of the corresponding light-emitting unit 20 on the substrate 10.

[0082] Referring to Figure 3, the bonding pad 80 is disposed on the side of the first electrode 40 facing away from the substrate 10. The bonding pad 80 can be made of MTD / Cu material and fabricated by sputtering, or of Au material and fabricated by vapor deposition. The thickness of the bonding pad 80 is greater than or equal to 1000 nm and less than or equal to 2000 nm. For example, the thickness of the bonding pad 80 can be 1000 nm, 1300 nm, 1500 nm, 1800 nm, 2000 nm, etc.

[0083] In this embodiment of the disclosure, multiple bonding pads 80 are provided, each bonding pad 80 corresponds to a first electrode 40, and the orthographic projection of the bonding pad 80 on the substrate 10 coincides with the orthographic projection of the corresponding first electrode 40 on the substrate 10.

[0084] Referring to Figure 3, the light-emitting diode chip also includes a reflective layer 90. The reflective layer 90 is disposed on the side of the light-emitting unit 20 facing away from the substrate 10, and the orthographic projection of the reflective layer 90 onto the substrate 10 does not overlap with the orthographic projection of the bonding pad 80 onto the substrate 10. That is, the reflective layer 90 covers the sidewalls of each light-emitting unit 20 and the area between the light-emitting units 20. The reflective layer 90 can be made of a high-reflectivity metal such as Ag or Al, and its thickness is greater than or equal to 90 nm and less than or equal to 100 nm; for example, the thickness of the reflective layer 90 can be 90 nm, 93 nm, 95 nm, 98 nm, 100 nm, etc.

[0085] The light-emitting diode chip provided in this embodiment can reduce the polarization electric field and improve the internal quantum efficiency of the quantum well by utilizing the light-emitting unit 20 with multiple light-emitting elements 22 arranged in an array. It can also overcome total internal reflection at the interface and enhance the light extraction efficiency, thereby improving the light-emitting effect of the light-emitting diode chip.

[0086] Figure 4 shows a flowchart of a method for fabricating a light-emitting diode (LED) chip. Referring to Figure 4, this disclosure provides a method for fabricating an LED chip, the method comprising:

[0087] Step 100: Provide substrate 10.

[0088] Specifically, substrate 10 can be a sapphire substrate.

[0089] Step 101: Form an array of multiple light emitters 22 on one side of the substrate 10.

[0090] Specifically, each light emitter 22 includes a first semiconductor layer 221, a quantum well material layer 222, and a second semiconductor layer 223 stacked in a direction perpendicular to the plane of the substrate 10, and the first semiconductor layer 221 is disposed close to the substrate 10, as shown in FIG9.

[0091] Meanwhile, in step 101, the preparation method includes:

[0092] Step 1011: A first semiconductor layer 221, a quantum well material layer 222, a second semiconductor layer 223 and a mask layer 23 are sequentially formed on the substrate 10.

[0093] Specifically, the material of the first semiconductor layer 221 can be n-type gallium nitride, and the material of the second semiconductor layer 223 can be p-type gallium nitride.

[0094] The mask layer 23 can be made of silicon dioxide. The mask layer 23 can be formed on the side of the second semiconductor layer 223 facing away from the substrate 10 using a chemical vapor deposition process, as shown in Figure 5. The thickness of the mask layer 23 is greater than or equal to 100 nm and less than or equal to 400 nm. For example, the thickness of the mask layer 23 can be 100 nm, 200 nm, 300 nm, 400 nm, etc.

[0095] Step 1012: Perform a patterning process on the mask layer 23 and etch the patterned mask layer 23 to expose a portion of the second semiconductor layer 223.

[0096] Specifically, a patterned protective adhesive is formed on the mask layer 23 by exposure development or nanoimprinting. Then, an F-based gas (e.g., CF4, SF6, CHF3) is used to etch the mask layer 23 to ensure that the mask layer 23 is completely etched. At this time, part of the second semiconductor layer 223 will be exposed, as shown in Figures 6 and 7.

[0097] Step 1013: The second semiconductor layer 223, the quantum well material layer 222 and the first semiconductor layer 221 are etched sequentially to form multiple light emitters 22.

[0098] Specifically, the second semiconductor layer 223, the quantum well material layer 222, and the first semiconductor layer 221 can be etched sequentially using gases such as Cl2 / BCl3, and the etching can penetrate the second semiconductor layer 223, the quantum well material layer 222, and the first semiconductor layer 221 in sequence, with an etching depth of about 300nm-1000nm (that is, the thickness of each light-emitting element 22), as shown in Figure 8.

[0099] It should be noted that the etching of the first semiconductor layer 221 is incomplete etching, so as to form a semiconductor thin film layer 21 between the light emitter 22 and the substrate 10. The semiconductor thin film layer 21 is used to realize the electrical connection between the multiple light emitters 22, that is, the electrical signal can be transmitted to each light emitter 22 through the semiconductor thin film layer 21.

[0100] Then, the etched multiple light emitters 22 are cleaned to remove the remaining mask layer 23, as shown in Figure 9.

[0101] In one embodiment, the light emitter 22 can also be formed in a bottom-up manner, and the preparation method includes:

[0102] Step 1014: Form a first semiconductor layer 221 on one side of the substrate 10.

[0103] Step 1015: Form a mask layer 23 on the side of the first semiconductor layer 221 away from the substrate 10.

[0104] Specifically, the mask layer 23 can be made of silicon dioxide, and it can be formed on the side of the substrate 21 away from the substrate 10 using a chemical vapor deposition process, as shown in Figure 10. The thickness of the mask layer 23 is greater than or equal to 100 nm and less than or equal to 400 nm. For example, the thickness of the mask layer 23 can be 100 nm, 200 nm, 300 nm, 400 nm, etc.

[0105] Step 1016: Perform a patterning process on the mask layer 23 to expose a portion of the first semiconductor layer 221.

[0106] Specifically, a patterned protective adhesive is formed on the mask layer 23 by exposure development or nanoimprinting, and then the mask layer 23 is etched using an F-based gas (e.g., CF4, SF6, CHF3) to ensure that the mask layer 23 is completely etched, as shown in Figure 11.

[0107] Step 1017: Form a quantum well material layer 222 and a second semiconductor layer 223 on the exposed first semiconductor layer 221 to form a plurality of light emitters 22.

[0108] Specifically, in forming the quantum well material layer 222 and the second semiconductor layer 223, since the quantum well material layer 222 and the second semiconductor layer 223 are grown only in places without the mask layer 23, multiple light emitters 22 can eventually be formed, and these light emitters 22 share the first semiconductor layer 221, as shown in Figure 12.

[0109] Step 102: Form a dielectric insulating layer 30 on one side of the substrate 10.

[0110] Specifically, the dielectric insulating layer 30 includes a plurality of through holes corresponding one-to-one with the light emitters 22, and the light emitters 22 are at least partially located in the corresponding through holes. The dielectric insulating layer 30 can be made of SOG material. As shown in Figures 13 and 14, after the dielectric insulating layer 30 is formed, it will cover the surface of the plurality of light emitters 22. Therefore, it is necessary to etch the dielectric insulating layer 30 on the surface so that the dielectric insulating layer 30 is located between the various light emitters 22.

[0111] After the dielectric insulating layer 30 is formed, defects in the light-emitting body 22 can be repaired. For example, repair can be carried out by high-temperature annealing, wet etching, sidewall passivation, etc. High-temperature annealing refers to annealing at a certain temperature (500-900℃) in an atmosphere such as N2 or NH3 to reduce internal dislocations and promote local element diffusion and recombination, thereby reducing internal defects. Wet etching refers to using alkaline KOH, TMAH, or acidic H3PO4 solutions to react with the sidewalls of the light-emitting body 22 to reduce the content of surface dangling bonds and oxides, thereby reducing defects. Alternatively, neutral solutions such as ammonium sulfide can be used to replace the surface and reduce the defect content. Sidewall passivation refers to protecting the sidewalls of the light-emitting body 22 with silicon oxide, silicon nitride, or aluminum oxide. Silicon oxide can be formed by atomic layer deposition, chemical vapor deposition, etc., or silicon oxide formed after curing organic passivating adhesive can be used as a passivation layer.

[0112] Step 103: Form a first electrode 40 on the side of the light emitter 22 away from the substrate 10.

[0113] Specifically, the first electrode 40 is connected to the light emitter 22. The first electrode 40 can be a transparent electrode layer made of indium tin oxide (ITO), or a transparent electrode layer made of indium zinc oxide (IZO), or at least one of gold (Au), tin (Sn), silver (Ag), titanium (Ti), aluminum (Al), nickel (Ni), and copper (Cu), as shown in Figure 15.

[0114] In one embodiment, the first electrode 40 may also be fabricated before the light emitter 22 is formed. In this embodiment, the third electrode 401 is first formed on the unetched plurality of light emitters 22 (that is, on the side of the unetched second semiconductor layer 223 facing away from the substrate 10), as shown in FIG16.

[0115] Then, as shown in Figures 17 and 18, multiple light emitters 22 and a third electrode 401 located on each light emitter 22 are formed through the same process steps as steps 1011-1013. Next, as shown in Figures 19 and 20, the dielectric insulating layer 30 is filled and etched. Finally, as shown in Figure 21, a full-surface common electrode 42 needs to be formed on the multiple light emitters 22 to achieve the connection of each light emitter 22 and thus ensure good current spreading performance. That is, in this embodiment, the first electrode 40 is composed of the third electrode 401 and the common electrode 42. The material of the common electrode 42 is the same as the material of the third electrode 401. The thickness of the third electrode 401 is 115nm-120nm, and a high-temperature annealing process is required to form a good ohmic contact between the third electrode 401 and the second semiconductor layer 223. The thickness of the common electrode 42 is preferably greater than 100nm.

[0116] It should be noted that in this embodiment, the etching nodes need to be strictly controlled during etching, and a certain amount of over-etching is used to ensure that the surface of the third electrode 401 is fully exposed while ensuring that the dielectric insulating layer 30 covers the sidewalls of the quantum well material layer 222. Therefore, the etching stop difference needs to be less than 220 nm. It should be noted that 220 nm is not a fixed value; the etching stop difference here is less than the sum of the thicknesses of all film layers on the quantum well material layer. Since the thickness of the first electrode 40 in a commonly used light-emitting chip structure is 120 nm, and the thickness of the second semiconductor layer is approximately 100 nm, the etching stop difference is 220 nm at this point. This value can vary if there are deviations in the film layer thicknesses of the light-emitting chip structure.

[0117] Step 104: A bonding pad 80 is formed on the side of the first electrode 40 away from the substrate 10 to form an intermediate structure.

[0118] Specifically, the bonding pad 80 can be made of MTD / Cu material and fabricated by sputtering, or of Au material and fabricated by vapor deposition. The thickness of the bonding pad 80 is greater than or equal to 1000 nm and less than or equal to 2000 nm. For example, the thickness of the bonding pad 80 can be 1000 nm, 1300 nm, 1500 nm, 1800 nm, 2000 nm, etc., as shown in Figure 22.

[0119] Step 105: Perform a patterning process on the intermediate structure to form multiple mutually separated and insulated light-emitting units 20. Each light-emitting unit 20 includes at least two light-emitting bodies 22, and each light-emitting unit 20 has a first electrode 40 and a bonding pad 80.

[0120] Specifically, the patterning process can include PR adhesive coating, exposure and development, and etching. The etching process employs a step-by-step etching method. That is, the bonding pad 80, the first electrode 40, the light emitter 22, and the dielectric insulating layer 30 are etched sequentially. The bonding pad 80 and the first electrode 40 can be dry-etched using IBE (Ion Beam Etching), the light emitter 22 is etched using ICP (Inductively Coupled Plasma Etching), and the etching gases are typically Cl2 and BCl3. The dielectric insulating layer 30 can be etched using an F-based gas. After the patterning process, multiple light-emitting units 20 and corresponding first electrodes 40 and bonding pads 80 are formed, as shown in Figure 23.

[0121] The light-emitting diode chip prepared by the above method can reduce the polarization electric field and improve the internal quantum efficiency of the quantum well by using the light-emitting unit 20 with multiple light-emitting bodies 22 arranged in an array. It can also overcome the total internal reflection at the interface and enhance the light extraction efficiency, thereby improving the light-emitting effect of the light-emitting diode chip.

[0122] Referring to FIG24, in an optional embodiment, this disclosure also provides a light-emitting diode chip, which includes a substrate 10, a light-emitting unit 20, a dielectric insulating layer 30, a first electrode 40, a fourth electrode 50, a passivation layer, a first connecting electrode 71, and a second connecting electrode 72; wherein the first connecting electrode 71 and the second connecting electrode 72 are used to bond and connect with a backplate 300.

[0123] Specifically, the substrate 10, the light-emitting unit 20, and the dielectric insulating layer 30 are all the same as the relevant structures in the light-emitting diode chip described above in the embodiments of this disclosure, and therefore will not be repeated here. However, unlike them, in this embodiment, the light-emitting diode chip has only one light-emitting unit.

[0124] Referring to FIG24, the fourth electrode 50 is disposed on the semiconductor thin film layer, and the orthogonal projection of the fourth electrode 50 on the substrate 10 is located within the non-light-emitting area of ​​the light-emitting diode chip. The fourth electrode 50 is electrically connected to each light-emitting element 22 through the semiconductor thin film layer 21, thereby enabling the conduction of electrical signals of each light-emitting element 22 using the first electrode 40 and the fourth electrode 50. In this embodiment of the present disclosure, the fourth electrode 50 is a multilayer structure. For example, the fourth electrode 50 can be a Ti / Al / Ni / Au metal stack structure, wherein the thickness of each metal layer in the metal stack structure is 30nm, 175nm, 35nm, and 1000nm, respectively; or, the fourth electrode 50 can be a Cr / Pt / Au metal stack structure, wherein the thickness of each metal layer in the metal stack structure is 20nm, 20nm, and 1000nm.

[0125] Referring to FIG24, a passivation layer 60 is disposed on the side of the first electrode 40 and the fourth electrode 50 facing away from the substrate 10. The passivation layer 60 may be silicon dioxide (SiO2) or silicon nitride (SiN). x At least one of the following.

[0126] Referring to FIG24, the first connecting electrode 71 and the second connecting electrode 72 are disposed on the side of the passivation layer 60 facing away from the substrate 10. The first connecting electrode 71 is connected to the first electrode 40 through a via penetrating the passivation layer 60, and the second connecting electrode 72 is connected to the fourth electrode 50 through a via penetrating the passivation layer 60. When bonding the light-emitting diode chip to the backplane, the first connecting electrode 71 and the second connecting electrode 72 can be used for bonding. The first connecting electrode 71 and the second connecting electrode 72 can be selected as a multilayer metal stack structure. For example, the first connecting electrode 71 and the second connecting electrode 72 can be selected as a Ti / Al / Ni / Au or Cr / Pt / Au metal stack structure. The overall thickness of the first connecting electrode 71 and the second connecting electrode 72 is greater than or equal to 1400 nm and less than or equal to 1500 nm.

[0127] The light-emitting diode chip provided in this embodiment can reduce the polarization electric field and improve the internal quantum efficiency of the quantum well by utilizing the light-emitting unit 20 with multiple light-emitting elements 22 arranged in an array. It can also overcome total internal reflection at the interface and enhance the light extraction efficiency, thereby improving the light-emitting effect of the light-emitting diode chip.

[0128] Based on the same inventive concept, and referring to FIG25, this disclosure also provides a display panel, which includes a back plate 300 and a plurality of light-emitting diode chips as described above in the embodiments of this disclosure disposed on the back plate 300.

[0129] Specifically, a driving circuit and a pixel circuit for driving the display panel are fabricated on the backplate 300. The driving circuit and pixel circuit on the backplate 300 can drive the light-emitting unit 20 to emit light, thereby realizing the display of image content. The material of the backplate 300 includes silicon or LTPS (Low Temperature Poly-Silicon).

[0130] After the LED chip is diced, an electrical connection between the LED chip and the backplane 300 can be achieved using bonding. The bonding method can include Cu-Sn, Cu-Au, or Au-Au, etc. The metal bonded to Cu on one side of the backplane 300 is Sn or Cu, etc. The thickness of the bonding layer on the backplane is 1000nm-2000nm.

[0131] After bonding with the backplane 300, the substrate 10 of the original LED chip needs to be removed. If the substrate 10 is sapphire, it can be removed using LLO (Laser Lift-off); if it is silicon, it can be removed by first thinning with CMP (Chemical Mechanical Polishing) followed by wet etching. If the LED chip also includes a buffer layer, the buffer layer also needs to be thinned. This thinning is achieved using full-surface ICP etching, typically with Cl2 and BCl3 as the etching gases.

[0132] After removing the substrate 10, a second electrode 301 needs to be fabricated on the side of the LED chip facing away from the backplate 300. The second electrode 301 can be fabricated using a lift-off process, and can be a multilayer metal stack structure. For example, the second electrode 301 can be a metal stack structure including Ti / Al / Ni / Au, where the thickness of each metal layer in the metal stack structure is 15nm-30nm, 50nm-200nm, 20nm-50nm, and 50nm-350nm, respectively; the second electrode 301 can also be a metal stack structure including Cr / Pt / Au, where the thickness of each metal layer in the metal stack structure is 50nm, 20nm, and 250nm, respectively.

[0133] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes any of the display panels described above in the embodiments of this disclosure.

[0134] Specifically, the display device may include computer monitors, televisions, billboards, laser printers with display functions, telephones, mobile phones, personal digital assistants (PDAs), laptops, digital cameras, portable camcorders, viewfinders, vehicles, large walls, theater screens, or stadium signs, etc.

[0135] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0136] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0137] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0138] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A light-emitting diode chip, comprising: Substrate; A light-emitting unit, disposed on the substrate, includes a plurality of light-emitting elements arranged in an array; The light emitter includes a first semiconductor layer, a quantum well material layer, and a second semiconductor layer stacked along a direction perpendicular to the plane of the substrate, wherein the first semiconductor layer is disposed close to the substrate; A dielectric insulating layer is disposed on the substrate, including a plurality of through holes corresponding one-to-one with the light-emitting element, wherein the light-emitting element is at least partially located in the through holes; The first electrode is disposed on the side of the light-emitting unit away from the substrate, corresponding to each light-emitting unit, and the orthographic projection of the first electrode on the substrate coincides with the orthographic projection of the light-emitting unit on the substrate; A bonding pad is disposed on the side of the first electrode away from the substrate, corresponding to the first electrode one by one, and the orthographic projection of the bonding pad on the substrate coincides with the orthographic projection of the first electrode on the substrate.

2. The display panel according to claim 1, wherein: The light emitter has a cross-sectional shape that is circular, square, or polygonal, parallel to the plane containing the substrate.

3. The display panel according to claim 2, wherein: The light emitter has a circular cross-sectional shape parallel to the plane of the substrate, and the diameter of the circular cross-section is greater than or equal to 300 nm and less than or equal to 1000 nm.

4. The display panel according to claim 1, wherein: The distance between two adjacent light emitters is greater than or equal to 300 nm and less than or equal to 1000 nm.

5. The display panel according to claim 1, wherein: The thickness of the light emitter is greater than or equal to 400 nm and less than or equal to 2000 nm.

6. The display panel according to claim 1, wherein: The dielectric insulating layer is doped with quantum dot material.

7. The light-emitting diode chip according to any one of claims 1-6, wherein, The light-emitting diode chip also includes: A reflective layer is disposed on the side of the light-emitting layer opposite to the substrate, and the reflective layer... The orthographic projection on the substrate does not overlap with the orthographic projection of the bonding pad on the substrate.

8. The light-emitting diode chip according to any one of claims 1-6, wherein, The light-emitting diode chip also includes: A buffer layer is disposed between the substrate and the light-emitting unit.

9. A display panel, wherein, Includes a backplate and a plurality of light-emitting diode chips as described in any one of claims 1-8 disposed on the backplate; The backplane is provided with a bonding layer, which includes a plurality of mating pads. The mating pads correspond one-to-one with the bonding pads of the light-emitting diode chip and are bonded to each other.

10. The display panel according to claim 9, wherein, The display panel also includes: The second electrode is disposed on the side of the light-emitting unit of the LED chip that is away from the back plate.

11. A display device, wherein, Includes the display panel as described in claim 9 or 10.

12. A method for fabricating a light-emitting diode chip, wherein, The preparation method includes: Provide substrate; Multiple light emitters are formed in an array on one side of the substrate; each light emitter includes a first semiconductor layer, a quantum well material layer, and a second semiconductor layer stacked along a direction perpendicular to the plane of the substrate, with the first semiconductor layer disposed close to the substrate; A dielectric insulating layer is formed on one side of the substrate, the dielectric insulating layer including a plurality of through holes corresponding one-to-one with the light emitter, the light emitter being at least partially located in the through holes; A first electrode is formed on the side of the light-emitting element that is away from the substrate; A bonding pad is formed on the side of the first electrode away from the substrate to form an intermediate structure; The intermediate structure is patterned to form multiple mutually separated and insulated light-emitting units. Each light-emitting unit includes at least two light emitters, and each light-emitting unit has a first electrode and a bonding pad.

13. The method for fabricating a light-emitting diode chip according to claim 12, wherein, In the step of forming an array of multiple light emitters on one side of the substrate, the fabrication method includes: A first semiconductor layer, a quantum well material layer, a second semiconductor layer, and a mask layer are sequentially formed on the substrate; The mask layer is patterned, and the patterned mask layer is etched to expose a portion of the second semiconductor layer. The second semiconductor layer, the quantum well material layer, and the first semiconductor layer are sequentially etched to form multiple light emitters; In this process, the first semiconductor layer is partially etched to form a semiconductor thin film layer.

14. The method for fabricating a light-emitting diode chip according to claim 13, wherein: The thickness of the mask layer is greater than or equal to 100 nm and less than or equal to 400 nm.

15. The method for fabricating a light-emitting diode chip according to claim 12, wherein, In the step of forming an array of multiple light emitters on one side of the substrate, the fabrication method includes: A first semiconductor layer is formed on one side of the substrate; A mask layer is formed on the side of the first semiconductor layer that is away from the substrate; The mask layer is patterned to expose a portion of the first semiconductor layer; A quantum well material layer and a second semiconductor layer are formed on the exposed first semiconductor layer to form a plurality of light emitters.

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