Online Partial Discharge Detection Device and Monitoring System

Abstract

This invention relates to an online partial discharge detection device and monitoring system. The discharge detection device includes a sensor module for acquiring partial discharge signals; a data acquisition system connected to the sensor module, which includes a multiplexer for multi-channel signal selection and switching, a signal conditioning circuit including a low-noise amplifier and bypass control circuit, an analog-to-digital converter, and an FPGA data acquisition module for receiving digital sampled data and power frequency synchronization signals; a data processing system, which includes an FPGA data processing module with data buffering, trigger control, phase detection, waveform management, and digital filtering functions, and an embedded processor communicating with the FPGA for feature extraction, unsupervised clustering, and supervised classification; and a communication system for transmitting the identification results to a remote monitoring platform. This invention can meet the application requirements of large-scale online monitoring of power equipment.

Description

Technical Field

[0001] This invention relates to the field of online monitoring technology for power equipment, and in particular to an online partial discharge detection device and monitoring system. Background Technology

[0002] Power systems require long-term stable operation; unexpected outages can cause significant economic losses and pose potential risks to equipment and personnel safety. Partial discharge is a key indicator of insulation system degradation or internal defects in power equipment. When defects or aging exist within the insulation material, partial discharge signals are often generated under the influence of an electric field. Therefore, monitoring and analyzing partial discharge signals can detect potential insulation problems before serious equipment failures occur, enabling early warning and preventative maintenance. Current methods for detecting partial discharge signals in power equipment mainly include pulse current methods, high-frequency current transformer detection methods, ultra-high frequency detection methods, transient ground voltage detection methods, and ultrasonic detection methods. In practical applications, these partial discharge detection technologies are typically combined with data acquisition devices and back-end analysis systems to form an online partial discharge monitoring system. A typical online monitoring system generally includes a sensor unit, a signal conditioning circuit, a data acquisition module, and a back-end data analysis platform. The sensor unit is used to collect partial discharge signals generated during the operation of power equipment. The signal conditioning circuit is used to amplify, filter, and match the collected high-frequency signals. The data acquisition module digitizes the signals through an analog-to-digital converter. The back-end analysis platform performs waveform analysis, phase distribution analysis, and status assessment on the collected data.

[0003] Although existing partial discharge online monitoring technology has been applied to some extent in the field of power equipment condition monitoring, some shortcomings still exist in practical engineering applications. First, existing partial discharge online monitoring systems typically consist of multiple independent functional modules, such as sensors, signal acquisition devices, signal processing equipment, and a back-end analysis platform. Each module usually needs to be deployed separately and connected via external devices, resulting in low system integration and high equipment and deployment costs. Second, most current partial discharge online monitoring systems mainly possess basic functions such as signal acquisition, data recording, and threshold alarms. Their ability to identify the type of partial discharge signal and determine its risk level is limited, and the system usually requires professional technicians to manually analyze and judge the acquired waveform data or phase distribution diagrams. Furthermore, existing monitoring systems lack comprehensive remote self-checking capabilities during operation. When sensors, acquisition circuits, or communication modules malfunction, the system struggles to perform timely self-checks and status confirmations, still requiring manual inspections for maintenance.

[0004] Therefore, it is necessary to provide an online partial discharge detection device and monitoring system with high structural integration, low deployment cost, and multi-channel data acquisition, real-time signal processing, and intelligent analysis capabilities to meet the application requirements of large-scale online monitoring of power equipment. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an online partial discharge detection device and monitoring system. By integrating multi-channel data acquisition, FPGA real-time signal processing and edge intelligent analysis functions into an integrated device, the system integration can be effectively improved, deployment costs can be reduced, and automatic identification of partial discharge signals, risk level judgment and remote self-test functions can be realized, thereby meeting the application needs of large-scale online monitoring of power equipment.

[0006] To achieve the above objectives, the present invention adopts the following technical solution.

[0007] In a first aspect, the present invention provides an online partial discharge detection device, which adopts the following technical solution: The sensor module is used to collect partial discharge signals generated during the operation of power equipment; The data acquisition system, connected to the sensor module, includes a multi-channel signal acquisition circuit, a signal conditioning circuit, an analog-to-digital converter, and an FPGA data acquisition module, wherein: The multi-channel signal acquisition circuit includes a multiplexer for selectively switching and polling partial discharge signals from multiple sensor channels. The signal conditioning circuit includes a low-noise amplifier and a bypass control circuit, wherein the bypass control circuit is used to control the switching of the signal between the amplification path and the through path; The analog-to-digital converter is used to digitally sample the signal-conditioned analog signal; The FPGA data acquisition module is used to receive digital sampling data output by the analog-to-digital converter and power frequency synchronization signal; The data processing system includes an FPGA data processing module and an embedded processor, wherein: The FPGA data processing module includes a data caching module, a trigger control module, a phase detection module, a waveform data management module, and a digital filtering module, which are used to perform cache management, trigger detection, phase calculation, waveform data extraction, and digital filtering processing on the digital sampled data. The embedded processor communicates with the FPGA via a data interaction interface, and is used to extract partial discharge features and perform pattern recognition on the data output by the FPGA data processing module. The pattern recognition includes clustering analysis of the partial discharge signals using an unsupervised learning model and classifying the clustering results using a supervised learning model. A communication system is used to transmit the results of the pattern recognition to a remote monitoring platform via a network.

[0008] Furthermore, in the above-mentioned online partial discharge detection device, the digital filtering module is a configurable finite impulse response filter. The finite impulse response filter includes a data processing path and a parameter loading path. The data processing path is located between the analog-to-digital converter and the data cache module. The parameter loading path is connected to the embedded processor, and the embedded processor dynamically loads the filter coefficients through the data interaction interface.

[0009] Furthermore, in the aforementioned online partial discharge detection device, the data interaction interface between the embedded processor and the FPGA is built based on the AXI protocol, including an AXI-Lite channel for configuration control and an AXI-Stream channel for data transmission. The waveform data management module is connected to the DMA module through the AXI-Stream channel to transmit the sampled data to the memory of the embedded processor.

[0010] Furthermore, in the aforementioned online partial discharge detection device, the embedded processor is configured to perform adaptive gain control and adaptive trigger control before data acquisition, wherein: The adaptive gain control uses the number of pulses per unit time as the evaluation index, initializes the gain to the minimum value, gradually increases the gain and collects data at each gain level, and determines the current gain as the final gain when the number of pulses per unit time is within the preset upper and lower threshold range. The adaptive trigger control uses the number of pulses per unit time as an evaluation index, initializes the trigger threshold to the maximum value, gradually reduces the trigger threshold and collects data at each trigger level, and determines the current trigger threshold as the final trigger threshold when the number of pulses per unit time is within the preset upper and lower threshold range.

[0011] Furthermore, in the aforementioned online partial discharge detection device, the clustering analysis includes performing a fast Fourier transform on the partial discharge waveform data to extract frequency domain features, and using a clustering algorithm based on the frequency domain features to divide the partial discharge event into multiple data subsets; the classification and identification includes generating phase distribution map data for each of the data subsets, and inputting the phase distribution map data into the supervised learning model to determine the type of partial discharge.

[0012] Furthermore, in the aforementioned online partial discharge detection device, the data acquisition system further includes a self-test signal output circuit. The self-test signal output circuit includes a multiplexer controlled by an FPGA and a series capacitor. The FPGA generates a square wave signal synchronized with the power frequency signal. The square wave signal is selected by the multiplexer through a designated channel and then injected into the sensor with self-test function through the series capacitor. The series capacitor and the equivalent inductance of the sensor form a transient response network to generate a simulated partial discharge pulse signal at the sensor output.

[0013] Furthermore, in the aforementioned online partial discharge detection device, the trigger control module performs real-time trigger judgment on the sampled data based on a set amplitude threshold, and maintains the trigger state after the trigger occurs until a preset length of sampled data is collected, after which the trigger state is cleared; the phase detection module resets the phase counter at the edge of each power frequency cycle, calculates the sampling length of the complete power frequency cycle by accumulating the number of sampling clock cycles, and records the current count value as a phase position indicator when a trigger event occurs.

[0014] Furthermore, in the aforementioned online partial discharge detection device, the data acquisition system further includes a power frequency synchronization signal acquisition circuit. The power frequency synchronization signal acquisition circuit includes a limiting network and a comparator circuit. The limiting network includes a series resistor and two parallel diodes in opposite directions. The series resistor is used to limit the input current, and the parallel diodes are used to perform bidirectional voltage clamping on the input AC signal to protect the comparator circuit. The comparator circuit is used to convert the AC signal after limiting into a square wave signal synchronized with the power frequency.

[0015] Secondly, the present invention provides an online partial discharge monitoring system, which adopts the following technical solution: The online partial discharge detection device as described in any of the first aspects above; and The remote monitoring platform communicates with the online partial discharge detection device via a network. It receives partial discharge waveform data, phase information, and pattern recognition results transmitted by the online partial discharge detection device, and sends control commands to the online partial discharge detection device. The control commands include data acquisition control commands, system operation parameter configuration commands, and artificial intelligence model update commands.

[0016] Furthermore, the embedded processor of the online partial discharge detection device in the aforementioned online partial discharge monitoring system is configured to perform automated polling and data acquisition on multiple monitoring objects, including obtaining a list of monitoring objects, generating data acquisition parameters based on the list of monitoring objects, performing data acquisition tasks and artificial intelligence recognition processing on each object to be detected according to a set mode, and uploading the recognition results to the remote monitoring platform; the embedded processor is also configured to respond to temporary requests and perform separate data acquisition and recognition tasks on specified detection objects outside of the polling process.

[0017] In summary, compared with the prior art, the present invention has at least one of the following beneficial technical effects: The online partial discharge detection device provided by this invention integrates sensor modules, data acquisition systems, data processing systems, and communication systems into a single device, effectively improving system integration and reducing deployment costs. It utilizes a multiplexer to achieve selective switching and polling acquisition of multi-channel signals, increasing the monitoring coverage of a single device. A bypass control circuit in the signal conditioning circuit enables flexible switching between amplification and direct-through paths, enhancing adaptability to partial discharge signals of varying intensities. An FPGA data processing module performs real-time signal processing functions such as data caching, trigger detection, phase calculation, and digital filtering, improving the real-time performance and accuracy of data acquisition. An embedded processor, combined with unsupervised and supervised learning models, enables edge intelligent analysis of partial discharge signals, allowing for automatic identification of partial discharge types locally, reducing reliance on manual analysis by back-end professionals. The communication system transmits the identification results to a remote monitoring platform, achieving remote management and centralized monitoring of partial discharge monitoring data. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A structural block diagram of the online partial discharge monitoring system provided in an embodiment of the present invention is shown.

[0020] Figure 2 A schematic diagram of a digital power supply circuit provided in an embodiment of the present invention is shown.

[0021] Figure 3 A schematic diagram of another digital power supply circuit provided by an embodiment of the present invention is shown.

[0022] Figure 4A schematic diagram of yet another digital power supply circuit provided by an embodiment of the present invention is shown.

[0023] Figure 5 A schematic diagram of another digital power supply circuit provided in an embodiment of the present invention is shown.

[0024] Figure 6 A schematic diagram of the analog positive power supply circuit provided in an embodiment of the present invention is shown.

[0025] Figure 7 A schematic diagram of another analog positive power supply circuit provided by an embodiment of the present invention is shown.

[0026] Figure 8 A schematic diagram of another analog positive power supply circuit provided by an embodiment of the present invention is shown.

[0027] Figure 9 A schematic diagram of the analog negative power supply circuit provided in an embodiment of the present invention is shown.

[0028] Figure 10 A schematic diagram of a negative voltage linear regulator circuit provided in an embodiment of the present invention is shown.

[0029] Figure 11 A schematic diagram of a multi-channel signal acquisition circuit provided in an embodiment of the present invention is shown.

[0030] Figure 12 A schematic diagram of the self-test signal output circuit provided in an embodiment of the present invention is shown.

[0031] Figure 13 A schematic diagram of the bypass control circuit provided in an embodiment of the present invention is shown.

[0032] Figure 14 A schematic diagram of a low-noise amplifier circuit provided in an embodiment of the present invention is shown.

[0033] Figure 15 A schematic diagram of a simulated single-pole double-throw switch circuit provided in an embodiment of the present invention is shown.

[0034] Figure 16 A schematic diagram of the buffer amplifier circuit provided in an embodiment of the present invention is shown.

[0035] Figure 17 The schematic diagram of the power frequency synchronization signal acquisition circuit provided in the embodiment of the present invention is shown.

[0036] Figure 18 A schematic diagram of the front-end circuit of the analog-to-digital converter provided in an embodiment of the present invention is shown.

[0037] Figure 19 A schematic diagram of an analog-to-digital converter circuit provided in an embodiment of the present invention is shown.

[0038] Figure 20 A schematic diagram of the FX8 interface on one side of the FPGA core board provided in an embodiment of the present invention is shown.

[0039] Figure 21 A schematic diagram of the FX8 interface on the other side of the FPGA core board provided in an embodiment of the present invention is shown.

[0040] Figure 22 A structural block diagram of the FPGA data processing module provided in an embodiment of the present invention is shown.

[0041] Figure 23 A flowchart of the multi-channel data acquisition program management provided in an embodiment of the present invention is shown.

[0042] Figure 24 A flowchart of the adaptive gain control program provided in an embodiment of the present invention is shown.

[0043] Figure 25 A flowchart of the adaptive triggering control program provided in an embodiment of the present invention is shown.

[0044] Figure 26 A flowchart of the intelligent partial discharge identification process provided in an embodiment of the present invention is shown. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application.

[0046] It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, the descriptions of each embodiment in the following embodiments have their own emphasis; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0047] The method steps described in this embodiment of the invention can be executed in the order described in the specific implementation, or the execution order of each step can be adjusted according to actual needs, provided that the technical problem can be solved. These are not listed one by one here.

[0048] The present invention will be further described in detail below with reference to the accompanying drawings.

[0049] Reference Figure 1This disclosure provides a structural block diagram of an online partial discharge monitoring system. The online partial discharge monitoring system includes multiple partial discharge sensors, a monitoring host, a power supply module, and a communication network.

[0050] Multiple partial discharge sensors, designated as Partial Discharge Sensor 1, Partial Discharge Sensor 2, Partial Discharge Sensor... and Partial Discharge Sensor N, are used to detect partial discharge signals in the electrical equipment under test. In some embodiments, the partial discharge sensors are high-frequency current transformers used to collect high-frequency current signals in the frequency range of 1–100 MHz. Each partial discharge sensor is connected to a monitoring host to transmit the detected partial discharge signals to the monitoring host.

[0051] like Figure 1 As shown, the external power supply is connected to the power supply module, which in turn is connected to the monitoring host. The power supply module provides the necessary power for the system's operation. It converts the external power supply into the operating voltage required by the various functional modules within the monitoring host.

[0052] The monitoring host, as the processing unit of the online partial discharge monitoring system, receives detection signals from various partial discharge sensors and performs data acquisition, signal processing, and partial discharge pattern recognition on the detection signals. In some embodiments, the monitoring host includes a data acquisition system and a data processing system. The data acquisition system is used to condition and digitize the analog signals output by the sensors. The data processing system is used to perform real-time processing, feature extraction, and partial discharge pattern recognition on the sampled data.

[0053] Continue to refer to Figure 1 The monitoring host connects to remote terminal devices via a communication network. This network connects to a host computer, mobile terminals, and a remote server. The host computer is used for local data analysis and system configuration, the mobile terminals are used for remote monitoring and alarm viewing, and the remote server is used for data storage, model execution, and centralized management.

[0054] In some implementations, the communication network includes an Ethernet communication module and an external network access device. The Ethernet communication module connects to the network device via a standard interface to enable data communication between the monitoring host and a remote server. The external network access device is a routing device that supports cellular network access, thereby enabling remote networking of the device.

[0055] Through the above structural design, the partial discharge online monitoring system can realize the acquisition, analysis, and remote monitoring of partial discharge signals from multiple monitoring points. The monitoring host transmits the acquired waveform data, phase information, and artificial intelligence recognition results to the remote monitoring platform, which monitors the operating status of the power equipment in real time. The remote monitoring platform also sends control commands to the monitoring host to realize equipment parameter configuration and system management functions. The control commands include data acquisition control commands, system operating parameter configuration commands, and artificial intelligence model update commands.

[0056] The data acquisition system includes a power supply circuit, which consists of both analog and digital power supplies. The digital power supply provides operating voltage to the FPGA processing platform and related digital logic circuits to support the operation of data acquisition and control logic.

[0057] Reference Figure 2 The digital power supply circuit employs a multi-stage buck converter structure to convert the input DC voltage into an operating voltage suitable for the FPGA and related digital processing circuits. In some embodiments, the digital power supply circuit includes a 12V to 5V buck converter circuit to convert the externally input 12V DC power supply to a 5V intermediate voltage rail. In some embodiments, the digital power supply circuit also includes a 5V to 3.3V buck converter circuit and a 5V to 1.8V buck converter circuit to provide different voltage levels of operating power to the FPGA core and related digital logic circuits.

[0058] The 12V to 5V buck converter circuit uses an integrated power module U7 as the core buck converter. The integrated power module U7 includes the following pins: VIN, VOUT, EN, FB, PG, SW, and PGND. The VIN pin is the voltage input terminal, connected to a 12V input power supply. The VOUT pin is the voltage output terminal, outputting 5V. The EN pin is the enable control terminal. The FB pin is the feedback terminal. The PG pin is the power good indicator terminal. The SW pin is the switching node. The PGND pin is the power ground.

[0059] On the input side, filter capacitors C29 and C30 are connected in parallel between the input power supply and ground to filter the input voltage, reducing voltage ripple and noise interference. On the output side, filter capacitors C31 and C32 are connected in parallel between the output terminal and ground to filter the output voltage, providing a stable DC output.

[0060] In the feedback network section, resistor R11 and filter capacitor C33 are connected in parallel. One end of this parallel network is connected to the feedback pin of the integrated power module U7, and the other end is connected to ground. Resistor R12 is placed between the output terminal and the feedback pin, forming a voltage divider network with resistor R11 to set the output voltage value. Resistor R13 is connected between the enable pin and the output terminal to control the enable state of the integrated power module U7. Resistor R14 is connected between the power good indicator pin and the power supply to provide a pull-up function to indicate the power output status.

[0061] During operation, the input DC voltage is filtered by filter capacitors C29 and C30 and then enters the integrated power module U7. The integrated power module U7 performs step-down conversion based on the feedback voltage set by the voltage divider network formed by resistors R11 and R12. The output voltage is filtered by filter capacitors C31 and C32 and then supplied to the subsequent digital circuits.

[0062] Reference Figure 3 The 5V to 3.3V step-down converter circuit uses an integrated power module U8 as its core component to step down the 5V input voltage to a 3.3V output voltage. The integrated power module U8 includes the VIN pin, SW pin, VOUT pin, PGND pin, PG pin, EN pin, and FB pin.

[0063] On the input side, a 5V DC power supply is connected to the VIN pin of the integrated power module U8. Filter capacitors C35 and C36 are connected in parallel between the input power supply and ground to filter the input power supply, reducing voltage ripple and high-frequency noise. A bias resistor R16 is connected between the input power supply and the VIN pin of the integrated power module U8. Resistor R17 and filter capacitor C39 are connected in series between the EN enable pin of the integrated power module U8 and ground. This network controls the enable state of the integrated power module U8 and provides a soft-start function.

[0064] On the output side, filter capacitor C34 and feedback resistor R15 are connected in parallel between the output voltage and the FB feedback pin of the integrated power module U8. Together, they form a feedback network to set the output voltage and provide loop compensation. Filter capacitors C37 and C38 are connected in parallel between the output voltage and ground to filter the output voltage and reduce voltage ripple. Resistor R18 is connected between the PG power good indicator pin of the integrated power module U8 and ground to provide power status indication.

[0065] Reference Figure 4The 5V to 1.8V step-down converter circuit uses an integrated power module U9 as the core step-down converter device to convert the input 5V DC power supply to a 1.8V output voltage, providing operating voltage for the FPGA core and related digital logic circuits. The integrated power module U9 includes a VIN pin, a SW pin, a VOUT pin, a PGND pin, a PG pin, an EN pin, and an FB pin. The VIN pin is connected to the 5V input power supply, and the VOUT pin outputs a 1.8V voltage.

[0066] On the input side, capacitors C41 and C42 are connected in parallel between the VIN pin and ground to filter the input power supply and reduce input ripple. Resistor R20 is connected at the node between the 5V input power supply and the VIN pin. Resistor R21 is connected between the enable pin EN and ground, and capacitor C45 is connected in parallel with resistor R21 to filter the enable signal.

[0067] On the output side, capacitor C40 and resistor R19 are connected in series between the VOUT pin and ground, forming an output compensation network. Capacitors C44 and C43 are connected in parallel between the VOUT pin and ground to filter the output voltage, reducing output ripple and improving power supply stability. Resistor R22 is connected between the FB pin and ground, forming a feedback voltage divider network with resistor R19 to set the output voltage value.

[0068] Reference Figure 5 The digital power supply circuit also includes a 12V to 6V buck converter circuit to provide an intermediate power rail for the subsequent analog power supply circuit. This circuit uses an integrated power module U1 as the core buck converter. The integrated power module U1 includes the VIN, VOUT, EN, FB, PG, SW, and PGND pins. The VIN pin is the power input terminal, connected to a 12V input voltage. The VOUT pin is the power output terminal, outputting a 6V voltage.

[0069] On the input side, capacitors C2 and C3 are connected in parallel between the VIN pin and ground, forming an input filter network to filter out high-frequency noise and ripple in the input power supply. Resistor R2 is connected between the 12V input and the VIN pin to provide input bias. Resistor R3 is connected between the EN pin and ground, forming an enable control circuit with capacitor C6, which is connected between the EN pin and ground to implement a soft-start function.

[0070] On the output side, capacitor C1 and resistor R1 are connected in parallel between the VOUT pin and the FB pin, forming a feedback compensation network. Resistor R4 is connected between the FB pin and ground, forming a voltage divider feedback network with resistor R1 to set the output voltage value. Capacitors C4 and C5 are connected in parallel between the VOUT pin and ground, forming an output filter network to reduce output voltage ripple and improve power supply stability.

[0071] Through the aforementioned multi-stage buck converter structure, the digital power supply circuit can convert an externally input 12V DC power supply into stable outputs at multiple voltage levels, including 5V, 3.3V, and 1.8V, to meet the power supply requirements of FPGA and high-speed data processing circuits. Each stage of the buck converter circuit employs a combination of input and output filter capacitors to simultaneously filter out low-frequency and high-frequency noise components, thereby ensuring the stable operation of the digital system.

[0072] The power supply circuit in the data acquisition system also includes an analog power supply. This analog power supply provides low-noise operating voltage to the signal conditioning circuit, multi-channel signal acquisition circuit, power frequency synchronous signal acquisition circuit, and analog-to-digital converter, ensuring signal integrity and system stability during analog signal acquisition. In some implementations, the analog power supply includes an analog positive power supply circuit and an analog negative power supply circuit. The analog positive power supply circuit uses a combination of stepped-down and linear regulation. It converts the 12V input power supply to a 6V intermediate voltage via a switching step-down converter, and then uses a low-dropout linear regulator to sequentially generate 5V, 3.3V, and 1.8V multiple positive power supply outputs. Through this combination of "switching step-down + linear regulation," the analog positive power supply circuit effectively reduces power ripple and noise while ensuring high power supply efficiency, thereby improving signal integrity and signal-to-noise ratio during analog signal acquisition and conditioning.

[0073] As mentioned above, refer to Figure 5 The 12V to 6V step-down converter circuit uses an integrated power module U1 to convert the 12V input voltage to a 6V intermediate voltage, which serves as the input power rail for the subsequent analog positive power linear regulator circuit.

[0074] Reference Figure 6 The 6V to 5V voltage regulator circuit uses a linear regulator to convert a 6V intermediate voltage to a 5V analog power output. The linear regulator has input terminal 3, output terminal 1, enable terminal EN, adjustment / idle terminal ADJ / NC, and a ground terminal. Input terminal 3 is connected to the 6V intermediate voltage input, and output terminal 1 is connected to the 5V power output. The enable terminal EN is connected to input terminal 3, allowing the linear regulator to automatically enable when the input voltage is present. The ground terminal is connected to circuit ground.

[0075] On the input side, capacitors C9 and C10 are connected in parallel between input terminal 3 and ground. Capacitor C9 is a 10uF polarized capacitor, and capacitor C10 is a 100nF ceramic capacitor. Together, they form an input filter network to filter out high-frequency noise and ripple in the input power supply, ensuring the stability of the input voltage. On the output side, capacitors C8 and C7 are connected in parallel between output terminal 1 and ground. Capacitor C8 is a 100nF ceramic capacitor, and capacitor C7 is a 10uF polarized capacitor. Together, they form an output filter network to reduce output voltage ripple and noise, improving the stability of the output power supply. By employing a linear regulator structure, the 6V to 5V voltage regulator circuit can provide a low-noise, stable 5V analog power supply output, meeting the power quality requirements during high-frequency analog signal acquisition and conditioning.

[0076] Reference Figure 7 The 5V to 3.3V voltage regulator circuit uses a linear regulator U3 to convert the 5V analog power supply to a 3.3V analog power output. The linear regulator U3 has an input terminal IN, an output terminal OUT, an enable terminal EN, an adjustment terminal ADJ / NC, and a ground terminal GND. The input terminal IN of the linear regulator U3 is connected to the 5V analog power rail, and the output terminal OUT is connected to the 3.3V analog power rail. The enable terminal EN of the linear regulator U3 is connected to the input power rail for enable control, and the ground terminal GND is connected to the system common ground.

[0077] On the input side, filter capacitors C13 and C14 are connected in parallel between the input terminal IN and the ground terminal. Filter capacitor C13 has a capacitance of 10uF, and filter capacitor C14 has a capacitance of 100nF. This input filter network filters the input power supply to reduce high-frequency noise and ripple interference at the input terminal, thereby ensuring the stable operation of the linear regulator U3. On the output side, filter capacitors C11 and C12 are connected in parallel between the output terminal OUT and the ground terminal. Filter capacitor C11 has a capacitance of 10uF, and filter capacitor C12 has a capacitance of 100nF. This output filter network filters the output voltage to further reduce ripple and noise at the output terminal, thereby providing a stable, low-noise power supply for subsequent analog circuits.

[0078] Reference Figure 8 The 3.3V to 1.8V voltage regulator circuit uses a linear regulator chip U4 to convert the 3.3V analog power supply voltage to a 1.8V analog power supply voltage. The linear regulator chip U4 has an input terminal 3, an output terminal 1, an enable terminal EN, an adjustment / idle terminal ADJ / NC, and a ground terminal 5. Input terminal 3 is connected to the 3.3V analog power supply input, and output terminal 1 is connected to the 1.8V analog power supply output. The enable terminal EN is connected to input terminal 3 via a pin to automatically enable the linear regulator chip U4. Ground terminal 5 is connected to the circuit ground.

[0079] On the input side, electrolytic capacitor C17 and ceramic capacitor C18 are connected in parallel between input terminal 3 and ground. Electrolytic capacitor C17 has a capacitance of 10uF and provides a large energy storage capacity to smooth input voltage fluctuations; ceramic capacitor C18 has a capacitance of 100nF and is used to filter out high-frequency noise. On the output side, ceramic capacitor C16 and electrolytic capacitor C15 are connected in parallel between output terminal 1 and ground. Ceramic capacitor C16 has a capacitance of 100nF and is used to filter out high-frequency ripple at the output; electrolytic capacitor C15 has a capacitance of 10uF and is used to provide low-frequency filtering and stability compensation at the output. The linear regulator chip U4 employs a low dropout design, enabling it to provide a stable, low-noise power output under relatively small input-output voltage differences, supplying operating voltage for analog signal processing circuits.

[0080] In the aforementioned analog positive power supply circuit, both the input and output sides of each stage of the linear voltage regulator circuit employ a filtering structure consisting of a large-capacity polarized capacitor and a small-capacity ceramic capacitor connected in parallel. The large-capacity polarized capacitor smooths low-frequency voltage fluctuations and provides energy storage, while the small-capacity ceramic capacitor filters out high-frequency noise components. Through this parallel filtering structure, the analog positive power supply circuit can effectively suppress power supply ripple and noise over a wide frequency range, thereby providing a low-noise operating power supply that meets signal integrity requirements for the signal conditioning circuit and analog-to-digital converter.

[0081] Based on the aforementioned analog positive power supply circuit, the analog power supply also includes an analog negative power supply circuit, used to provide negative voltage operating power to devices in the signal conditioning circuit that require bipolar power supply. In some embodiments, the analog negative power supply circuit includes a 5V to -5V inverting converter circuit and a -5V to -3.3V negative voltage linear regulator circuit.

[0082] Reference Figure 9 The 5V to -5V inverting converter circuit uses an inverting power supply chip U5 as its core component to convert a 5V positive power supply to a -5V negative voltage output. The inverting power supply chip U5 integrates a low-dropout regulator and employs a charge pump topology to achieve voltage inversion. The inverting power supply chip U5 includes the following pins: VIN, EN, C1-, C1+, CPOUT, VOUT, VFB, GND, and PAD. The VIN pin is the power input, connected to the 5V analog positive power supply AVDD_5V. The VOUT pin is the power output, outputting a -5V negative voltage AVDD_-5V.

[0083] In the enable control section, resistor R5 is connected between the 5V analog positive power supply AVDD_5V and the EN enable pin of the inverting power supply chip U5. Resistor R5 has a resistance of 10k ohms and is used to provide bias to the enable pin. Input capacitor C21 is connected between the 5V analog positive power supply AVDD_5V and ground. Input capacitor C21 has a capacitance of 4.7uF and is used to filter the input power supply.

[0084] In the charge pump circuit, a flying capacitor C22 is connected between the C1- and C1+ pins of the inverting power supply chip U5. The capacitance of flying capacitor C22 is 1uF. As the energy storage element of the charge pump circuit, flying capacitor C22 alternately charges and discharges under the internal switching control of the inverting power supply chip U5, thereby achieving voltage inversion. Resistor R7 is connected between the C1- pin of the inverting power supply chip U5 and ground. The resistance of resistor R7 is 10k ohms. The output filter capacitor C23 is connected between the CPOUT pin of the inverting power supply chip U5 and ground. The capacitance of output filter capacitor C23 is 4.7uF, used to filter the charge pump output.

[0085] In the feedback network section, resistor R6, with a resistance of 330k ohms, is connected between the VOUT pin and the VFB feedback pin of the inverter power supply chip U5. Resistor R8, with a resistance of 100k ohms, is connected between the VFB feedback pin and ground. Resistors R6 and R8 together form a feedback voltage divider network used to set the output voltage value. The inverter power supply chip U5 compares the voltage at the VFB feedback pin with the internal reference voltage and adjusts the operating state of the internal regulator to achieve stable control of the output voltage.

[0086] In the output filtering section, output capacitors C19 and C20 are connected in parallel between the AVDD-5V output terminal and the ground terminal. Output capacitor C19 has a capacitance of 100nF and is used to filter out high-frequency noise. Output capacitor C20 has a capacitance of 2.2uF and is used to filter out low-frequency ripple and improve output stability. The GND and PAD pins of the inverting power supply chip U5 are both connected to the ground terminal.

[0087] Reference Figure 10The -5V to -3.3V negative voltage linear regulator circuit uses a linear regulator U6 as its core component to further regulate the -5V negative voltage to a -3.3V negative voltage output. The linear regulator U6 is an adjustable negative voltage low-dropout regulator with enable control functionality. The linear regulator U6 includes an input terminal IN, an enable terminal EN, a feedback terminal FB, an output terminal OUT, and a ground terminal GND. The input terminal IN receives the -5V negative voltage input AVDD_-5V from the preceding inverting converter circuit. The enable terminal EN is connected to the input terminal IN and is used to control the operating state of the linear regulator U6. The output terminal OUT provides the regulated -3.3V negative voltage output AVDD_-3.3V.

[0088] On the input side, input filter capacitors C26 and C27 are connected in parallel between the input terminal IN and the ground terminal. Input filter capacitor C26 has a capacitance of 10uF, and input filter capacitor C27 has a capacitance of 100nF. This parallel capacitor combination is used to filter the input voltage to reduce input ripple and noise.

[0089] On the output side, output filter capacitors C24 and C25 are connected in parallel between the output terminal OUT and the ground terminal. Output filter capacitor C24 has a capacitance of 100nF, and output filter capacitor C25 has a capacitance of 10uF. This parallel capacitor combination is used to filter the output voltage to improve its stability.

[0090] In the feedback network section, output voltage divider resistors R9 and R10 form a feedback voltage divider network. Output voltage divider resistor R9 is connected between the output terminal OUT and the feedback terminal FB, and its resistance is 50k ohms. Output voltage divider resistor R10 is connected between the feedback terminal FB and the ground terminal, and its resistance is 30k ohms. Through this voltage divider network, the feedback terminal FB receives a feedback voltage proportional to the output voltage. The linear regulator U6 adjusts its output based on this feedback voltage, thereby achieving stable control of the output voltage.

[0091] Through the above-described analog negative power supply circuit structure, the data acquisition system can provide low-noise negative voltage power supply for devices such as bipolar operational amplifiers, analog switches, and analog-to-digital converter drivers in the signal conditioning circuit, thereby meeting the requirements of high-frequency analog signal processing for bipolar power supply.

[0092] The multi-channel signal acquisition circuit is used to receive high-frequency analog signals from multiple partial discharge sensor channels, and selectively connects the signals from multiple channels to the subsequent signal conditioning circuit through multiplexing, thereby realizing the polling acquisition of partial discharge signals from different monitoring points.

[0093] Reference Figure 11The multi-channel signal acquisition circuit includes a multiplexer U11, multiple electrostatic discharge protection devices, and multiple signal input interfaces. The multiplexer U11 employs an 8-to-1 selection structure to selectively switch the partial discharge signals from eight sensor channels. In some embodiments, the multiplexer U11 uses a dual-power supply: the positive power supply VDD is connected to an analog positive power supply AVDD_3.3V, and the negative power supply VSS is connected to an analog negative power supply AVDD_-3.3V. By using a dual-power supply, the multiplexer U11 can process bipolar analog signals to meet the transmission requirements of partial discharge signals.

[0094] The multiplexer U11 includes eight signal input terminals S1 to S8, a common output terminal D, channel selection terminals A0, A1, and A2, and an enable terminal EN. The eight signal input terminals S1 to S8 are connected to signal input lines SIG_IN1 to SIG_IN8, respectively, to receive partial discharge signals from each sensor channel. The common output terminal D is connected to the signal output terminal MUX_OUT1 through output resistor R27, used to output the signal of the selected channel to the subsequent signal conditioning circuit. The enable terminal EN is connected to a low level to keep the multiplexer U11 in an enabled state.

[0095] In terms of channel selection control, the channel selection terminals A0, A1, and A2 of the multiplexer U11 are connected to the control signals CHA_SEL_0, CHA_SEL_1, and CHA_SEL_2, respectively. These control signals are output by the FPGA and selectively switch between the eight input channels through combinations of the three address lines. When the FPGA selects a specific channel via the channel selection signal, the signal from that channel is output to subsequent circuitry via the common output terminal D of the multiplexer U11 and output resistor R27 for processing.

[0096] For power supply filtering, filter capacitor C49 is connected between the analog positive power supply AVDD_3.3V and ground, and filter capacitor C50 is connected between the analog negative power supply AVDD_-3.3V and ground. Both filter capacitors C49 and C50 have a capacitance of 100nF and are used to decouple and filter the positive and negative power supplies of multiplexer U11 to reduce the impact of power supply noise on signal acquisition and ensure the stable operation of multiplexer U11.

[0097] The multi-channel signal acquisition circuit includes eight signal input channels, connected via signal input interfaces J1, J2, J3, J4, J5, J6, J7, and J8. One end of each signal input interface is connected to the corresponding signal input lines SIG_IN1 to SIG_IN8, and the other end is connected to the ground terminal for connecting to the signal output terminal of an external partial discharge sensor.

[0098] To protect the circuit from electrostatic discharge (ESD) damage, ESD protection devices are installed on each signal input channel. ESD protection device U12 is connected between signal input line SIG_IN1 and the ground terminal to provide ESD protection for the channel. The ESD protection devices for the other channels use the same connection method, corresponding to signal input lines SIG_IN2 through SIG_IN8 respectively. By installing ESD protection devices on each signal input channel, the multi-channel signal acquisition circuit can protect downstream circuits from ESD damage, thereby improving system reliability.

[0099] With the above circuit structure, the multi-channel signal acquisition circuit can selectively switch and poll the partial discharge signals of multiple sensor channels, thereby improving the monitoring coverage and channel utilization of a single device.

[0100] Furthermore, the data acquisition system also includes a self-test signal output circuit, which is used to inject test signals into the sensor channels with self-test functions to realize system function self-test and link connectivity verification.

[0101] Reference Figure 12 The self-test signal output circuit includes a multiplexer U28, a resistor R59, multiple series capacitors, and multiple connectors. The multiplexer U28 uses an 8-to-1 selection mechanism to selectively switch between eight self-test signal output channels. The VDD pin of the multiplexer U28 is connected to the analog positive power supply AVDD_3.3V, and both the VSS and GND pins are connected to ground.

[0102] In terms of channel selection control, the channel selection terminals A0, A1, and A2 of the multiplexer U28 are connected to the control signals CHA_HC_SEL0, CHA_HC_SEL1, and CHA_HC_SEL2, respectively. These control signals are output from the FPGA and selectively switch between the eight output channels through combinations of the three address lines. The enable terminal EN of the multiplexer U28 is used to control the operating state of the device.

[0103] The common terminal D of multiplexer U28 is connected to the pulse output signal Pulse_out via resistor R59. Resistor R59 has a resistance of 50 ohms and is used for impedance matching. The eight channel ports S1 to S8 of multiplexer U28 are connected to the corresponding signal lines HC_S1 to HC_S8, respectively.

[0104] At the output terminals of each channel, the circuit includes a filter capacitor network and connectors. The HC_S1 signal line connects to capacitors C88 and C90. C88 has a capacitance of 10pF, and C90 has a capacitance of 10pF and is grounded. The HC_S1 signal line is output through connector J10. The HC_S5 signal line connects to capacitors C89 and C91. C89 has a capacitance of 10pF, and C91 has a capacitance of 10pF and is grounded. The HC_S5 signal line is output through connector J11. The HC_S2 signal line connects to capacitors C92 and C94. C92 has a capacitance of 10pF, and C94 has a capacitance of 10pF and is grounded. The HC_S2 signal line is output through connector J12. The HC_S6 signal line connects to capacitors C93 and C95. C93 has a capacitance of 10pF, and C95 has a capacitance of 10pF and is grounded. The HC_S6 signal line is output through connector J13. The HC_S3 signal line connects to capacitors C97 and C99. Capacitor C97 has a capacitance of 10pF, and capacitor C99 has a capacitance of 10pF and is grounded. The HC_S3 signal line is output through connector J15. The HC_S7 signal line connects to capacitors C96 and C98. Capacitor C96 has a capacitance of 10pF, and capacitor C98 has a capacitance of 10pF and is grounded. The HC_S7 signal line is output through connector J14. The HC_S4 signal line connects to capacitors C101 and C103. Capacitor C101 has a capacitance of 10pF, and capacitor C103 has a capacitance of 10pF and is grounded. The HC_S4 signal line is output through connector J17. The HC_S8 signal line connects to capacitors C100 and C102. Capacitor C100 has a capacitance of 10pF, and capacitor C102 has a capacitance of 10pF and is grounded. The HC_S8 signal line is output through connector J16.

[0105] For self-test signal generation, the FPGA generates a square wave signal synchronized with the power frequency signal as the self-test signal source. In some implementations, the square wave signal has an amplitude of approximately 3.3V and a frequency of approximately 50Hz, maintaining synchronization with the power system's power frequency. After the square wave signal is selected by a multiplexer U28 to a designated channel, it is injected into the sensor with self-test function through series capacitors in the output paths of each channel.

[0106] The series capacitors in the output paths of each channel are used for AC coupling of the square wave signal. The series capacitors limit the amount of charge transferred per unit time by their capacitance value, thereby controlling the energy and amplitude of the injected signal. During signal injection, because the sensor module with self-test function has equivalent inductance characteristics, the series capacitors and the sensor's equivalent inductance together form a transient response network. When the square wave signal changes at the rising or falling edge, the voltage change in the series capacitors excites a transient current response in the sensor, thus forming a short-time pulse signal at the sensor output. The waveform characteristics of the short-time pulse signal are similar to those of an actual partial discharge pulse, thereby simulating the partial discharge signal.

[0107] By adjusting the capacitance of the series capacitor, the amplitude and duration of the pulse signal can be controlled to adapt to different system parameters and detection sensitivity requirements. The capacitor connected in parallel to ground is used to filter out high-frequency noise and improve signal quality. Connectors J10 to J17 are used to output the self-test signal to the corresponding sensor channel.

[0108] In some implementations, the trigger frequency of the self-test signal is synchronized with the power frequency signal, ensuring that the analog pulse has a defined phase position within the power frequency cycle. This facilitates the subsequent data processing module's identification and differentiation of the self-test signal. Through this circuit structure, the data acquisition system can selectively inject self-test pulse signals into designated sensor channels under FPGA control, thereby enabling remote verification of the connectivity of the sensor and detection circuit without the need for an external power supply.

[0109] Furthermore, the partial discharge signal output from the multi-channel signal acquisition circuit needs to undergo amplitude adjustment and dynamic range matching by a signal conditioning circuit before entering the analog-to-digital converter. The signal conditioning circuit in the data acquisition system is used to adjust the amplitude of the input signal to meet the input requirements of the analog-to-digital converter. In some embodiments, the signal conditioning circuit includes a buffer amplifier circuit, a bypass control circuit, and a low-noise amplifier circuit. The buffer amplifier circuit is located between the multi-channel signal acquisition circuit and the bypass control circuit to enhance signal driving capability and improve signal transmission stability. The bypass control circuit controls the switching of the signal between the amplification path and the direct path to adapt to the detection requirements of partial discharge signals with different amplitudes. The low-noise amplifier circuit amplifies weak partial discharge signals to improve detection sensitivity.

[0110] Reference Figure 16The buffer amplifier circuit includes operational amplifier U13, resistors R29 and R30, and filter capacitors C53, C54, C55, and C56. Operational amplifier U13 is a wideband operational amplifier used to provide signal buffering between the multi-channel signal acquisition circuit and the subsequent signal conditioning circuit. The positive power supply terminal VS+ of operational amplifier U13 is connected to the analog positive power supply AVDD_3.3V, and the negative power supply terminal VS- is connected to the analog negative power supply AVDD_-3.3V, thereby achieving bipolar power supply to support the processing of bipolar signals.

[0111] The non-inverting input (IN+) of operational amplifier U13 receives the signal MUX_OUT1 from the output of multiplexer U11. The inverting input (IN-) of operational amplifier U13 is connected to the analog negative power supply AVDD_-3.3V via resistor R30, and simultaneously connected to the output (OUTPUT) of operational amplifier U13, forming a feedback network. Resistor R29 is connected in series between the output (OUTPUT) of operational amplifier U13 and the output (BUF1_OUT) of buffer amplifier U13. The disable control terminal of operational amplifier U13... DIS connection to Ground terminal GND.

[0112] For power supply filtering, filter capacitors C53 and C54 are connected in parallel between the analog positive power supply AVDD_3.3V and the ground terminal GND. Filter capacitor C53 has a capacitance of 100nF, and filter capacitor C54 has a capacitance of 10uF. Filter capacitors C55 and C56 are connected in parallel between the analog negative power supply AVDD_-3.3V and the ground terminal GND. Filter capacitor C55 has a capacitance of 100nF, and filter capacitor C56 has a capacitance of 10uF. These filter capacitors are used to decouple the positive and negative power supplies of operational amplifier U13 to reduce the impact of power supply noise on signal quality. Through this circuit structure, the buffer amplifier circuit can provide high input impedance and low output impedance characteristics, thereby reducing signal attenuation and distortion caused by line load effects and connection structures, providing a stable signal input for subsequent bypass control circuits and low-noise amplifier circuits.

[0113] Reference Figure 13 and Figure 15The bypass control circuit in the signal conditioning circuit includes analog single-pole double-throw (SPDT) switches U14 and U16. These switches are respectively positioned in the signal paths before and after the low-noise amplifier U15, controlling whether the input signal chooses to pass through the low-noise amplifier U15 or bypass it via a direct path. Both switches U14 and U16 are powered by a dual power supply; their positive power supply terminal VDD is connected to the analog positive power supply AVDD_3.3V, and their negative power supply terminal VSS is connected to the analog negative power supply AVDD_-3.3V.

[0114] Reference Figure 15 An analog single-pole double-throw (SPD) switch U16 is located on the input side of the low-noise amplifier U15 and is used to switch the transmission path of the input signal. The common terminal of the analog SPD switch U16 is connected to the input signal CHA_IN, which is pre-processed by a network of resistor R33 and capacitor C62 before being input to the analog SPD switch U16. One selection terminal of the analog SPD switch U16 is connected to the low-noise amplifier input node CHA_LNA_IN, and the other selection terminal is connected to the bypass signal path. The control terminal is connected to the control signal CHA_LNA_CTRL0. The positive power supply terminal VDD is connected to the analog positive power supply AVDD_3.3V, and the negative power supply terminal VSS is connected to the analog negative power supply AVDD_-3.3V. Capacitors C63 and C64 are used to filter the analog positive and negative power supplies, respectively. With this structure, the analog SPD switch U16 can selectively guide the input signal into the low-noise amplifier path or the bypass path under the control signal.

[0115] Capacitor C63 has a capacitance of 100nF. One end of capacitor C63 is connected to the analog positive power supply AVDD_3.3V, and the other end is connected to ground GND. It is used to filter the analog positive power supply. Capacitor C64 has a capacitance of 100nF. One end of capacitor C64 is connected to the analog negative power supply AVDD_-3.3V, and the other end is connected to ground GND. It is used to filter the analog negative power supply.

[0116] Reference Figure 13An analog single-pole double-throw (SPD) switch U14 is located on the output side of the low-noise amplifier U15 to control the switching of the output signal transmission path. The common terminal of the analog SPD switch U14 is connected to the buffer amplifier output signal BUF1_OUT, one selection terminal is connected to the bypass output signal CHA_BP_OUT, the other selection terminal is connected to the amplification path signal corresponding to the low-noise amplifier output node, the control terminal is connected to the control signal CHA_LNA_CTRL0, the positive power supply terminal VDD is connected to the analog positive power supply AVDD_3.3V, and the negative power supply terminal VSS is connected to the analog negative power supply AVDD_-3.3V. Capacitors C57 and C58 are used for decoupling and filtering of the analog positive and negative power supplies, respectively. With this structure, the analog SPD switch U14 can selectively output the amplified signal or bypass signal processed by the low-noise amplifier U15 to the subsequent circuit under the action of the control signal.

[0117] In the power supply filtering section, filter capacitor C57 has a capacitance of 100nF. One end of filter capacitor C57 is connected to the analog positive power supply AVDD_3.3V, and the other end is connected to the ground terminal GND, used for decoupling filtering of the positive power supply. Filter capacitor C58 has a capacitance of 100nF. One end of filter capacitor C58 is connected to the analog negative power supply AVDD_-3.3V, and the other end is connected to the ground terminal GND, used for decoupling filtering of the negative power supply.

[0118] During circuit operation, the control signal CHA_LNA_CTRL0 is simultaneously input to both the analog single-pole double-throw switch U14 and the analog single-pole double-throw switch U16 to synchronously control the conduction state of the two switches. When the control signal CHA_LNA_CTRL0 is at one logic level, the input signal is guided to the input terminal of the low-noise amplifier U15 via the bypass control circuit. After being amplified by the low-noise amplifier U15, the signal is switched to the output terminal by the bypass control circuit, thus forming an amplification path. When the control signal CHA_LNA_CTRL0 is at another logic level, the input signal bypasses the low-noise amplifier U15 and is directly output via the bypass control circuit, thus forming a direct path. Through the above bypass control circuit, the system can select whether to amplify the input signal through the low-noise amplifier U15 according to the amplitude, so as to avoid overload of the low-noise amplifier U15 under large signal conditions, while ensuring the detection sensitivity of weak signals.

[0119] Reference Figure 14The low-noise amplifier circuit includes a low-noise amplifier U15, coupling capacitors C61 and C60, inductor L1, resistor R31, filter capacitor C59, and resistor R32. The low-noise amplifier U15 includes input terminal 3, output terminal 1, ground terminal 2, and ground terminal 4. Input terminal 3 receives the partial discharge signal from the bypass control circuit, output terminal 1 outputs the amplified signal, and ground terminals 2 and 4 are connected to the circuit ground.

[0120] On the input side, a coupling capacitor C61 is connected in series in the signal input path. One end of the coupling capacitor C61 is connected to the signal input node CHA_LNA_IN, and the other end is connected to input terminal 3 of the low-noise amplifier U15. The coupling capacitor C61 has a capacitance of 100nF and is used to achieve AC coupling and isolate the DC component, thereby protecting the input stage of the low-noise amplifier U15.

[0121] On the output side, output terminal 1 of the low-noise amplifier U15 is connected to one end of inductor L1. Inductor L1 has an inductance of 6.8μH, and the other end is connected to resistor R31. Resistor R31 has a resistance of 42Ω, and its other end is connected to the analog positive power supply AVDD_5V. Inductor L1 and resistor R31 form the output bias network, providing operating current to the low-noise amplifier U15. A filter capacitor C59 with a capacitance of 100nF is connected in parallel between the node between resistor R31 and the analog positive power supply AVDD_5V and ground. This filter capacitor filters the power supply to reduce the impact of power supply noise on the performance of the low-noise amplifier U15.

[0122] A coupling capacitor C60 is connected in series in the output signal path. One end of the coupling capacitor C60 is connected to the connection point between the output terminal 1 of the low-noise amplifier U15 and the inductor L1, and the other end is connected to the signal output node CHA_LNA_OUT. The capacitance of the coupling capacitor C60 is 100nF, used to achieve AC coupling of the output signal and isolate the DC bias voltage. A resistor R32 is connected in parallel between the signal output node CHA_LNA_OUT and the ground terminal. The resistance of the resistor R32 is 10kΩ, used to provide a DC bias path for the subsequent circuit.

[0123] With the above circuit structure, the low-noise amplifier U15 can amplify the weak input partial discharge signal with low noise. At the same time, it obtains a stable operating point through the bias network composed of inductor L1 and resistor R31, and realizes AC coupling of input and output through coupling capacitors C61 and C60, thereby meeting the requirements of high-frequency partial discharge signal conditioning.

[0124] In some implementations, the signal conditioning circuit further includes a programmable gain amplifier (PGA) for dynamically adjusting the amplification gain based on the amplitude of the input signal. The gain value of the PGA is configured by the FPGA or embedded processor via control signals, thereby enabling adaptive amplification of partial discharge signals of different amplitudes to further extend the dynamic range of the system.

[0125] Based on the aforementioned signal conditioning circuit, the data acquisition system also includes a power frequency synchronization signal acquisition circuit, which is used to acquire a power frequency reference signal synchronized with the power system and convert the power frequency reference signal into a digital logic signal for subsequent FPGA data processing module to perform phase detection and synchronization analysis.

[0126] Reference Figure 17 The power frequency synchronization signal acquisition circuit consists of two parts: a limiting network and a comparator circuit. The limiting network is used to perform voltage clamping and filtering on the input power frequency AC signal to limit the signal amplitude within the input voltage range allowed by comparator U10. The comparator circuit is used to convert the limited AC signal into a square wave signal synchronized with the power frequency.

[0127] In the limiting network section, the circuit input terminals are marked AC_+ and AC_-, respectively connected to the positive and negative terminals of the power frequency AC signal. In the AC signal input path, resistors R25 and R26 are connected in series to limit the input current. Diodes D1 and D2 are located at the signal input node, connected in parallel with opposite directions, to perform bidirectional voltage clamping on the input AC signal, thereby limiting the signal amplitude within the allowable input voltage range of comparator U10, protecting subsequent circuits and preventing overvoltage damage.

[0128] A capacitor C48 is connected in parallel at the input node to filter out transient interference and high-frequency noise in the input signal, thereby improving signal stability and anti-interference capability. A capacitor C46 is connected between the limiting network and comparator U10 for further filtering.

[0129] In the comparator circuit section, comparator U10 uses a dual comparator chip. The 1IN- pin (pin 2) and 1IN+ pin (pin 3) of comparator U10 serve as the inverting and non-inverting inputs, respectively. The 1OUT pin (pin 1) serves as the output. The GND pin (pin 4) is connected to ground, and the VCC pin (pin 8) is connected to the analog positive power supply AVDD_5V. Capacitor C47 is connected between the analog positive power supply AVDD_5V and ground to provide power filtering for comparator U10.

[0130] Resistor R23 is connected between the analog positive power supply AVDD_5V and the output of comparator U10 as a pull-up resistor. Resistor R24 ​​is connected between the analog positive power supply AVDD_3.3V and the output of comparator U10. After limiting and filtering, the AC signals AC_+ and AC_- are input to comparator U10, and converted by the comparator circuit into a square wave signal PHASE synchronized with the power frequency. The square wave signal PHASE is input as a synchronization signal to the subsequent FPGA data processing module to realize the correlation analysis between the partial discharge signal and the power system phase.

[0131] Through the above circuit structure, the power frequency synchronization signal acquisition circuit can convert the input power frequency AC signal into a square wave signal synchronized with the power frequency, thereby providing a power frequency reference signal for the subsequent phase detection module, so as to determine the phase position of the partial discharge signal within the power frequency cycle.

[0132] Based on the aforementioned power frequency synchronous signal acquisition circuit, the data acquisition system also includes an analog-to-digital converter front-end circuit, which is used to drive and match the analog signal output by the signal conditioning circuit to meet the input requirements of the analog-to-digital converter.

[0133] Reference Figure 18 The front-end circuit of the analog-to-digital converter (ADC) includes an ADC driver U17, an ESD protection device U19, an ESD protection device U18, and multiple resistors and capacitors. The ADC driver U17 is a dual-channel differential amplifier chip used to convert the input single-ended analog signal into a differential signal and input the differential signal to the subsequent ADC, thereby improving signal integrity and common-mode interference immunity under high-speed sampling conditions.

[0134] The analog-to-digital converter driver U17 uses a dual-power supply. The positive power supply is connected to the analog positive power supply AVDD_5V, and the negative power supply is connected to the analog negative power supply AVDD_-5V. On the input side, the circuit includes ESD protection devices U19 and U18, which provide electrostatic discharge protection for the CHB_IN and CHA_IN input signals, respectively. A filter capacitor C65 is connected between the output of ESD protection device U19 and ground to filter out high-frequency noise in the input signal.

[0135] In the input network section, the input signal enters the analog-to-digital converter driver U17 through a resistor network. Resistors R34 and R35 form a voltage divider network at the input. Resistors R37 and R41 are connected to the IN1- and IN1+ pins of the analog-to-digital converter driver U17, respectively. Resistors R36, R39, and R40 form another input network channel. Resistor R38 is connected in the input path for signal matching.

[0136] In the feedback network section, resistors R42 and R43 form the feedback network, which are connected between the feedback pins FB1+ and FB2- of the analog-to-digital converter driver U17 and the input terminal, respectively, to set the gain of the differential amplifier.

[0137] In the common-mode voltage setting section, resistors R44 and R45 are connected between the common-mode voltage setting terminal VCM and the relevant pin. A filter capacitor C67 is connected in parallel with resistor R44 to stabilize the common-mode voltage. A common-mode capacitor C66 is connected between the VCM pin of the analog-to-digital converter driver U17 and ground to filter and stabilize the common-mode voltage. Through the common-mode voltage setting network, the analog-to-digital converter driver U17 can provide an appropriate common-mode reference voltage for the subsequent analog-to-digital converter.

[0138] The power pull-down control pins PD1 and PD2 of the analog-to-digital converter driver U17 are pulled up to the analog positive power supply AVDD_5V through resistors R46 and R47 respectively, used to control the operating state of the device. Filter capacitor C68 is connected between the negative power supply terminal and the ground terminal for power supply filtering.

[0139] In the power supply filtering section, filter capacitors C69 and C70 are connected in parallel between the analog positive power supply AVDD_5V and the ground terminal, and filter capacitors C71 and C72 are connected in parallel between the analog negative power supply AVDD_-5V and the ground terminal. This is used to provide a stable operating power supply for the analog-to-digital converter driver U17 and reduce the impact of power supply noise on signal quality.

[0140] On the output side, the differential output signals VOUT-1 and VOUT+1 of the analog-to-digital converter driver U17 are output through resistors R48 and R52 respectively, and connected to the VIN+A and VIN-A output terminals via resistors R49 and R53. Output filter capacitors C73 and C77 are connected in parallel between the output terminal and the ground terminal respectively, and output filter capacitor C75 is connected between the differential output pairs for filtering the differential signals. The outputs VOUT+2 and VOUT-2 of the other channel are connected to the VIN+B and VIN-B output terminals through resistors R50, R54, R51, and R55. Output filter capacitors C74, C78, ​​and C76 constitute the corresponding output filter network.

[0141] With the above circuit structure, the front-end circuit of the analog-to-digital converter can convert the single-ended analog signal from the signal conditioning circuit into a differential signal output, and perform impedance matching and filtering through the resistor and capacitor network at the output end, thereby providing a differential signal that meets the input requirements for the subsequent analog-to-digital converter.

[0142] After the single-ended to differential signal is converted by the pre-amplifier circuit of the analog-to-digital converter, the differential signal enters the analog-to-digital converter for high-speed digital sampling. (Refer to...) Figure 19 The analog-to-digital converter (ADC) circuit in the data acquisition system includes a high-speed ADC chip and its peripheral circuitry. In some implementations, the ADC chip is a high-speed ADC with a dual-channel differential input structure, a sampling rate of 250 MS / s, and a resolution of 14 bits. It is used to perform high-precision digital sampling of the signal-conditioned partial discharge signal to meet the acquisition requirements of the wide bandwidth and transient characteristics of the partial discharge signal.

[0143] The analog-to-digital converter chip has multiple functional pins, including clock input pins CLK+ and CLK-, synchronization signal input pin SYNC, analog signal input pins VIN+A, VIN-A, VIN+B and VIN-B, common-mode voltage output pin VCM, digital data output pins D0 to D13, data clock output pins DCO+ and DCO-, overflow indicator pins OR+ and OR-, as well as multiple power supply pins and control pins.

[0144] In the clock input section, the differential clock signals ADC_CLK_P and ADC_CLK_N are connected to the CLK+ and CLK- pins of the analog-to-digital converter chip via coupling capacitors, respectively. These coupling capacitors isolate the DC component and transmit the high-frequency clock signal. A series resistor is also included in the clock input path for impedance matching and signal conditioning. The synchronization signal ADC_SYNC is capacitively coupled to the SYNC pin to achieve synchronous control between multiple channels or devices.

[0145] In the analog signal input section, the differential input signals VIN+A and VIN-A of channel A and the differential input signals VIN+B and VIN-B of channel B are respectively connected to the corresponding analog input pins of the analog-to-digital converter (ADC) chip. The differential input signals are provided by the ADC driver U17 in the ADC preamplifier circuit. The common-mode voltage output pin VCM is connected to ground through a filter capacitor to provide a common-mode reference voltage for the preamplifier driver circuit.

[0146] In the digital output section, the analog-to-digital converter chip outputs 14-bit differential digital data signals, including D0+ / D0- to D13+ / D13-, where D0 is the least significant bit and D13 is the most significant bit. The data clock output pins DCO+ and DCO- output differential clock signals ADC_DCO_P and ADC_DCO_N, synchronized with the data. The overflow indicator pins OR+ and OR- output overflow status signals OR_P and OR_N. These differential digital signals are connected to the FPGA via a low-voltage differential signaling (LVDS) interface to meet the signal integrity requirements of high-speed data transmission.

[0147] In the power supply section, the analog-to-digital converter (ADC) chip has multiple analog power supply pins (AVDD) and digital drive power supply pins (DRVDD). The AVDD pin connects to a 1.8V analog power supply (AVDD_1.8V), and the DRVDD pin connects to a 1.8V digital power supply (AVDD_1.8V_D). Multiple 100nF filter capacitors are placed near each power supply pin to filter out power ripple and high-frequency noise, ensuring stable operation of the ADC chip. Both analog and digital power supplies are equipped with decoupling capacitor networks, and each power rail has multiple parallel filter capacitors to provide wideband power filtering.

[0148] In the control interface section, the analog-to-digital converter (ADC) chip has a power-down control pin (PDWN), an output enable pin (OEB), a chip select pin (CSB), a serial clock pin (SCLK), and a serial data pin (SDIO) for configuring and controlling the ADC chip's operating mode. The power-down control pin (PDWN) and the output enable pin (OEB) are each connected to a 1.8V digital power supply via pull-up resistors (4.7 kΩ) to set the default operating state. The chip select pin (CSB), the serial clock pin (SCLK), and the serial data pin (SDIO) are connected to the corresponding control signals of the FPGA, used to configure the ADC chip's internal registers via the serial interface.

[0149] The analog-to-digital converter chip has a heat dissipation pad EPAD on its bottom. The heat dissipation pad EPAD is connected to the analog power supply through a capacitor and to the digital power supply through a zero-ohm resistor, which is used for heat dissipation and grounding.

[0150] In some implementations, digital signal transmission between the analog-to-digital converter chip and the FPGA is achieved through the FX8 series high-speed board-to-board connector. For example... Figure 20 As shown, the FX8 interface on one side of the FPGA core board is configured with differential signal pins corresponding to the analog-to-digital converter (ADC), including data signal pairs such as ADC_D_0_P / ADC_D_0_N to ADC_D_13_P / ADC_D_13_N, data clock signal pairs such as ADC_DCO_P / ADC_DCO_N, overflow indicator signal pairs such as ADC_OR_P / ADC_OR_N, clock signal pairs such as ADC_CLK_P / ADC_CLK_N, and control signal pins such as ADC_PDWN, ADC_OEB, ADC_SYNC, ADC_NCS, and ADC_SCLK. Bank34 of the FPGA core board is configured for a 1.8V power supply mode to receive LVDS digital output signals from the ADC chip, meeting the requirements of high-speed data acquisition for signal integrity and anti-interference capabilities.

[0151] Digital signal transmission between the analog-to-digital converter chip and the FPGA, as well as the FPGA's control signal output to the data acquisition circuit, are both achieved through FX8 series high-speed board-to-board connectors. In some implementations, FX8 series 120-pin high-speed board-to-board connectors are provided on both the left and right sides of the FPGA core board to achieve electrical connection between the FPGA core board and the host PCB, thereby supporting high-speed data interaction and control signal transmission. The I / O resources of the FPGA core board are configured according to function, with each I / O bank undertaking functions such as analog-to-digital converter data reception, channel control signal output, and system peripheral interfaces.

[0152] Reference Figure 20 The FX8 interface on one side of the FPGA core board uses a dual-in-line layout, with pins numbered sequentially from 1 to 120. Multiple VDD_5V power supply pins are located at the top and bottom of the interface to provide a 5V operating voltage to the system. Multiple GND ground pins are positioned between and adjacent to the power supply pins to provide a stable ground reference and reduce signal interference.

[0153] The central area of ​​the interface features I / O pins for Bank13 and Bank34. Bank13 is configured for adjustable voltage, supporting 1.8V, 2.5V, and 3.3V power supplies, with a default configuration of 3.3V. The I / O pins in Bank13 include multiple differential signal pin pairs for digital signal transmission between the FPGA and external circuits. In some implementations, Bank13 resources are only available for specific FPGA chip models.

[0154] Bank34 is also configured for adjustable voltage operation, supporting 1.8V, 2.5V, and 3.3V power supplies. In some implementations, Bank34 is configured for a 1.8V power supply to receive digital output signals from the analog-to-digital converter (ADC) chip. The I / O pins of Bank34 include multiple differential signal pin pairs for LVDS data transmission with the ADC chip.

[0155] The interface is configured with differential signal pins related to the analog-to-digital converter (ADC), including data signal pairs such as ADC_D_0_P / ADC_D_0_N to ADC_D_13_P / ADC_D_13_N, used to receive 14-bit differential digital data output from the ADC chip. The interface also includes an ADC_DCO_P / ADC_DCO_N data clock signal pair for receiving a differential clock signal synchronized with the data. An ADC_OR_P / ADC_OR_N overflow indicator signal pair is used to receive overflow status signals. An ADC_CLK_P / ADC_CLK_N clock signal pair provides a sampling clock to the ADC chip. Control signal pins such as ADC_PDWN, ADC_OEB, ADC_SYNC, ADC_NCS, and ADC_SCLK are used to configure and control the FPGA's operating mode of the ADC chip. The aforementioned differential signal pairs employ an LVDS interface to meet the requirements of high-speed data acquisition for signal integrity and anti-interference capabilities.

[0156] Reference Figure 21 On the other side of the FPGA core board, the FX8 interface pins are numbered from 121 to 240. This interface includes pin configurations for multiple functional zones. For power and ground, the interface has multiple ground pins 121, 122, 137, 144, 155, 162, 166, 185, 186, 194, 196, 205, 208, 219, 220, and 229 to provide a stable ground reference.

[0157] Regarding MIO signal pins, the interface is configured with a fixed 1.8V voltage domain MIO pin group, including pins 123 of MIO28_S01 to 148 of MIO51_S01, used to implement general I / O functions between the embedded processor and external devices. The interface is also configured with a fixed 3.3V voltage domain MIO pin group, including pins 149 of MIO10_S00 to 154 of MIO15_S00.

[0158] Regarding the SD card interface signals, the interface is configured with FPGA_SD_CLK pin 134, FPGA_SD_DATA1 pin 136, and FPGA_SD_DATA3 pin 138 for implementing SD card storage control functions. For serial communication, the interface is configured with UART0_TX pin 142 for supporting serial data transmission.

[0159] Regarding the JTAG debugging interface, the interface is configured with VREF_JTAG pin 157 for providing a reference voltage, nGRST pin 158 for system reset, and FPGA_JTAG_TCK pin 159, FPGA_JTAG_TDO pin 160, JTAG_TDO pin 161, FPGA_JTAG_TDI pin 163, FPGA_JTAG_TMS pin 164, and JTAG_TMS pin 165 to support program download and debugging functions.

[0160] Regarding the Bank35 general-purpose I / O pins, the interface is configured with multiple sets of differential signal pin pairs, including IO_19P_35 pin 167 and IO_19N_35 pin 169, IO_OP_35 pin 168 and IO_ON_35 pin 170, etc. The Bank35 is configured for a 3.3V power supply and is used to output control signals and general-purpose digital signals. In some implementations, the Bank35 is used to drive the channel selection terminals of multiplexers, analog switch control circuits, and related control signals in signal conditioning circuits. The Bank35 is also used to output the square wave signal required for the self-test function to inject test signals into external channels.

[0161] Regarding the Ethernet PHY interface, the interface is configured with TXRXP_A pin 230, TXRXM_A pin 232, TXRXP_B pin 234, TXRXM_B pin 236, TXRXP_C pin 231, TXRXM_C pin 233, TXRXP_D pin 235, TXRXM_D pin 237, GPHY_MDC pin 238, GPHY_MDIO pin 240, and GPHY0_LED_G pin 239, which are used to implement Gigabit Ethernet communication functions.

[0162] Through the above I / O resource allocation and interface design, the FPGA core board can realize functions such as high-speed data acquisition, channel control, self-test signal generation, and system communication, thereby supporting data interaction and collaborative work of the partial discharge online monitoring system.

[0163] After the analog-to-digital converter completes the digital sampling of the partial discharge signal, the digital sampled data enters the FPGA data processing module for real-time processing. (Refer to...) Figure 22 The FPGA data processing module is used to process digital sampled data from the analog-to-digital converter and the power frequency synchronization signal, and performs buffer management, trigger detection, phase calculation, waveform data extraction, and digital filtering on the digital sampled data. The FPGA data processing module includes a digital filtering module 405, a data buffer module 401, a trigger control module 402, a phase detection module 403, and a waveform data management module 404.

[0164] like Figure 22 As shown, the ADC input signal output from the analog-to-digital converter (ADC) enters the digital filtering module 405. The digital filtering module 405 performs digital filtering on the acquired partial discharge signal to improve signal quality and extract effective features. In some embodiments, the digital filtering module 405 is a configurable finite impulse response (FIR) bandpass digital filter. The digital filtering module 405 includes a data processing path and a parameter loading path. The data processing path is located between the ADC and the data buffer module 401 and is used to perform real-time filtering on the acquired raw data. The parameter loading path is connected to the data interface between the FPGA and the embedded processor, whereby the embedded processor dynamically loads the filter coefficients through the data interface, thereby enabling programmable configuration of the filter's passband range. In some embodiments, the digital filtering module 405 is a 128th-order FIR bandpass digital filter. Through the dynamic configuration capability of the parameter loading path, the digital filtering module 405 can support adaptive filtering of signals in different frequency bands.

[0165] The signal processed by the digital filtering module 405 enters the data buffer module 401. The data buffer module 401 continuously buffers the sampled data to ensure that the high-speed sampled data stably enters the subsequent processing flow. In some embodiments, the data buffer module 401 adopts a first-in-first-out (FIFO) structure with a buffer depth of not less than 1024 sampling points. The input of the data buffer module 401 is connected to the output of the digital filtering module 405, and the output is connected to the subsequent data processing module. During operation, the data buffer module 401 continuously writes sampled data and begins to read the corresponding data when a preset trigger condition is reached, thereby realizing the alignment of the trigger position and the extraction of waveform segments containing the trigger point.

[0166] A power frequency synchronization signal is input to the trigger control module 402. The trigger control module 402 also receives control signal input from the embedded processor. The trigger control module 402 is used to perform real-time trigger determination on the sampled data based on a set amplitude threshold. When the amplitude of any data point acquired by the analog-to-digital converter exceeds the amplitude threshold, the trigger control module 402 generates a trigger signal and initiates the waveform extraction process. The trigger control module 402 also includes waveform length control logic, used to maintain the trigger state after triggering until a preset length of sampled data is acquired, after which the trigger state is cleared, thereby avoiding repeated triggering in a single valid waveform acquisition.

[0167] The output of the data buffer module 401 is connected to the phase detection module 403. The phase detection module 403 determines the phase position of the sampled data within the power frequency cycle based on the periodic changes of the power frequency synchronization signal, thereby achieving synchronous analysis between the partial discharge signal and the power system phase. In some embodiments, the phase detection module 403 resets the phase counter at the edge of each power frequency cycle and calculates the sampling length of the complete power frequency cycle by accumulating the number of sampling clock cycles. When a trigger event occurs, the phase detection module 403 uses the current count value as a phase position indicator and writes it along with the complete cycle count value into a preset register, thereby achieving the positioning and synchronous analysis of the partial discharge signal within the power frequency cycle.

[0168] The outputs of both the phase detection module 403 and the trigger control module 402 are connected to the waveform data management module 404. The waveform data management module 404 extracts continuous waveform data segments containing trigger points from the cached data according to the trigger conditions, and then organizes, saves, and outputs the waveform data segments. In some embodiments, the waveform data management module 404 adopts a FIFO structure with separate read and write clocks. The write clock is the sampling clock used by the analog-to-digital converter, and the read clock is the system clock used by the data interaction interface between the FPGA and the embedded processor. Under the control of the trigger control module 402, the waveform data management module 404 performs the writing of fixed-length waveform data and adds an extended write area of ​​no less than four sampling cycles to synchronously write the complete power frequency cycle count value and the phase position count value at the trigger event time. The waveform data management module 404 outputs the processed waveform data to the subsequent embedded processing system.

[0169] Through the above structural design, the FPGA data processing module can realize real-time acquisition, digital filtering, trigger identification and phase correlation processing of partial discharge signals, thereby providing structured data for subsequent embedded processing systems.

[0170] After completing the structural design of the FPGA data processing module, the embedded processor manages the multi-channel data acquisition tasks through an application program. (Refer to...) Figure 23 The embedded processor uses a program management module to complete functions such as initialization, device status detection, model update, acquisition task generation, polling acquisition, artificial intelligence recognition, and data uploading in the runtime environment.

[0171] At the start of the process, the embedded processor performs initialization operations to configure data acquisition parameters, load the artificial intelligence model, and establish a data interaction interface with the FPGA. After initialization, the embedded processor enters an availability check phase to determine whether the device is available. In some implementations, the availability check includes detecting the FPGA communication interface, the operating status of the analog-to-digital converter, and the communication network connection status. If the device is unavailable, the process ends; if the device is available, subsequent steps are executed.

[0172] When the device is available, the embedded processor performs a model update check. In some implementations, the embedded processor queries the remote monitoring platform via a communication network to see if a new version of the artificial intelligence model file exists. If a model update exists, the embedded processor downloads and loads the new version of the model file; if no model update exists, the current model continues to be used.

[0173] The embedded processor acquires a list of monitored objects, which contains information on multiple monitoring points requiring partial discharge detection. In some implementations, the list of monitored objects is issued by a remote monitoring platform or read from a local configuration file. The embedded processor generates corresponding data acquisition parameters based on the list of monitored objects, including channel selection parameters, sampling duration parameters, trigger threshold parameters, and gain parameters.

[0174] The embedded processor determines whether an object to be detected exists. If no object exists, the process returns to the model update check step and waits for the next data acquisition cycle; if an object exists, the data acquisition task continues.

[0175] For an existing object to be detected, the embedded processor determines whether a temporary request exists. In some implementations, the temporary request is sent by a remote monitoring platform to specify a separate data acquisition task for a particular object to be detected. If a temporary request exists, the embedded processor performs a separate data acquisition task, AI recognition processing, and data upload operation on the specified object to be detected outside of the polling process, and then returns to the main process after completion. If no temporary request exists, the embedded processor performs a data acquisition task on the current object to be detected according to a set mode.

[0176] After the data acquisition task is completed, the embedded processor determines whether artificial intelligence (AI) recognition is required. If AI recognition is required, the embedded processor calls the AI ​​model to perform feature extraction and pattern recognition on the acquired partial discharge data; if not, the AI ​​recognition step is skipped. The embedded processor then determines whether data uploading is required. If data uploading is required, the embedded processor transmits the waveform data, phase information, and recognition results to the remote monitoring platform via the communication network; if not, the data uploading step is skipped.

[0177] After completing the above operations, the embedded processor determines whether there are more objects to be detected. If there are more objects to be detected, the process returns to the object detection step to continue processing the next object; if all objects to be detected have been processed, the process returns to the model update check step and begins a new round of monitoring loop.

[0178] Through the above process design, the embedded processor can achieve automated data acquisition and processing scheduling for multiple monitoring objects, and support the execution of background tasks according to a preset cycle. Through a temporary request-response mechanism, the embedded processor can execute separate detection tasks for specified detection objects outside of the regular polling process, thereby improving its responsiveness to sudden detection demands.

[0179] In practical power equipment monitoring scenarios, the amplitude and noise levels of partial discharge signals vary under different substation environments, making it difficult to adapt fixed gain parameters and trigger thresholds to various operating conditions. Therefore, before executing data acquisition tasks, the embedded processor adaptively adjusts the gain parameters in the signal conditioning circuit and the trigger threshold in the trigger control module. In some implementations, the embedded processor uses the number of pulses per second (NOP / s) as an evaluation metric to characterize the number of pulses detected under the current gain and trigger conditions. NOP / s reflects the comprehensive detection of effective partial discharge pulses and noise pulses under the current acquisition parameters: when the gain is too low or the trigger threshold is too high, NOP / s is low, indicating that effective partial discharge pulses are not sufficiently detected; when the gain is too high or the trigger threshold is too low, NOP / s is high, indicating that a large number of noise pulses are introduced. By controlling NOP / s within a preset upper and lower threshold range, the embedded processor can suppress noise interference while ensuring the detection of effective partial discharge pulses.

[0180] Reference Figure 24 The adaptive gain control process is used to automatically adjust the gain parameters in the signal conditioning circuit according to the current signal environment before data acquisition. In some implementations, the adaptive gain control process sets a sampling time parameter AGST, a lower threshold for the number of pulses AGLT, and an upper threshold for the number of pulses AGHT.

[0181] In the adaptive gain control process, the embedded processor initializes the gain to its minimum value. The embedded processor acquires data according to the sampling time parameter AGST and calculates the NOP / s value at the current gain level. The embedded processor determines whether NOP / s is greater than the lower threshold AGLT. If NOP / s is not greater than the lower threshold AGLT, it indicates that the current gain is too low and effective pulses are not being sufficiently detected. The embedded processor increases the gain by a predetermined step size and returns to continue acquiring data. If NOP / s is greater than the lower threshold AGLT, the embedded processor further determines whether NOP / s is less than the upper threshold AGHT. If NOP / s is less than the upper threshold AGHT, it indicates that the current gain keeps the number of pulses within the preset upper and lower threshold range, and the embedded processor determines the current gain as the final gain. If NOP / s is not less than the upper threshold AGHT, it indicates that the current gain is too high, leading to a large number of noise pulses being introduced. The embedded processor reverts the current gain by a predetermined step size and determines the reverted gain as the final gain. After determining the final gain, the embedded processor outputs the gain result and ends the adaptive gain control process.

[0182] Reference Figure 25 The adaptive trigger control process is used to automatically adjust the trigger threshold according to the current environmental conditions before data acquisition, so as to achieve effective detection of partial discharge signals. In some implementations, the adaptive trigger control process is configured with a sampling time parameter ATST, a lower threshold for the number of pulses ATLT, and an upper threshold for the number of pulses ATHT.

[0183] In the adaptive trigger control process, the embedded processor initializes the trigger threshold to its maximum value. The embedded processor acquires data according to the sampling time parameter ATST and calculates the NOP / s value at the current trigger level. The embedded processor determines whether NOP / s is greater than the lower threshold ATLT. If NOP / s is not greater than the lower threshold ATLT, it indicates that the current trigger threshold is too high, and valid pulses have not triggered acquisition. The embedded processor lowers the trigger threshold by a predetermined step size and returns to continue acquiring data. If NOP / s is greater than the lower threshold ATLT, the embedded processor further determines whether NOP / s is less than the upper threshold ATHT. If NOP / s is less than the upper threshold ATHT, it indicates that the current trigger threshold keeps the number of pulses within the preset upper and lower threshold range, and the embedded processor determines the current trigger threshold as the final trigger threshold. If NOP / s is not less than the upper threshold ATHT, it indicates that the current trigger threshold is too low, causing a large number of noise pulses to be triggered. The embedded processor lowers the current trigger threshold by a predetermined step size and determines the lower threshold after the lower threshold adjustment as the final trigger threshold. After determining the final trigger threshold, the embedded processor outputs the trigger result and ends the adaptive trigger control process.

[0184] Through the aforementioned adaptive gain control and adaptive trigger control processes, the embedded processor can automatically adjust the acquisition parameters under different noise environments and signal amplitude conditions, thereby ensuring effective partial discharge pulse detection while suppressing noise interference and improving the stability and accuracy of detection.

[0185] After completing adaptive gain control and adaptive trigger control, the embedded processor performs intelligent recognition processing on the acquired partial discharge data. (Refer to...) Figure 26 The partial discharge intelligent identification process is used to extract features and classify the collected partial discharge signals to determine the specific type of partial discharge.

[0186] In some implementations, the embedded processor generates partial discharge feature data based on the acquired partial discharge waveform data and the corresponding power frequency phase information. The partial discharge feature data includes partial discharge waveform data and phase resolved partial discharge (PRPD) data. PRPD data describes the phase distribution characteristics of the partial discharge signal within the power frequency cycle, providing a basis for partial discharge type identification.

[0187] The intelligent partial discharge identification process employs a combination of unsupervised and supervised learning models. The unsupervised learning model performs preliminary analysis and clustering of the acquired partial discharge signals to initially distinguish different types of partial discharge events from background noise. The supervised learning model classifies and identifies the clustered data to determine the specific type of partial discharge.

[0188] like Figure 26 As shown, the intelligent partial discharge identification process begins with acquiring partial discharge waveform data. The embedded processor reads the partial discharge waveform data and phase information from the data output by the waveform data management module 404.

[0189] In the frequency domain feature extraction stage, the embedded processor performs a Fast Fourier Transform (FFT) on the partial discharge waveform data to extract frequency domain features. The Fast Fourier Transform converts the time-domain waveform data into a frequency-domain representation, thereby obtaining the frequency distribution characteristics of the partial discharge signal. These frequency domain features are used to characterize the differences in frequency components among different types of partial discharge signals.

[0190] In the clustering stage, the embedded processor uses a clustering algorithm to cluster partial discharge events based on the extracted frequency domain features. In some implementations, the K-Means algorithm is used. In other implementations, the Mean-Shift algorithm or other clustering methods are employed. Through clustering, the embedded processor divides the collected partial discharge events into multiple data subsets, thereby forming multiple clustering results. Clustering can group partial discharge events with similar frequency domain features into the same category and perform preliminary separation between background noise and valid partial discharge signals.

[0191] During the PRPD pattern generation phase, the embedded processor generates corresponding PRPD pattern diagrams for each cluster subset. The PRPD pattern diagram uses the power frequency phase as the horizontal axis and the partial discharge amplitude as the vertical axis to show the distribution pattern of partial discharge events within the power frequency cycle. Different types of partial discharge exhibit different distribution characteristics on the PRPD pattern diagram; internal discharge, surface discharge, and corona discharge each have their own characteristic patterns in phase distribution.

[0192] In the classification and recognition phase, the embedded processor inputs the generated PRPD pattern map data into a supervised learning model for classification and recognition. The supervised learning model is trained based on the labeled PRPD data and is used to classify each cluster subset. In some implementations, the supervised learning model employs a Support Vector Machine (SVM) model. In other implementations, the supervised learning model employs a Convolutional Neural Network (CNN) model or other machine learning models. The supervised learning model determines the specific type of partial discharge based on the features of the PRPD pattern map.

[0193] During the output phase, the embedded processor outputs the partial discharge type identification result. In some implementations, the classification results include types such as Internal Discharge (PD), Surface Discharge (Surface PD), Corona Discharge (Corona PD), and Non-Partial Discharge Noise (Non-PD). Internal discharge typically occurs in air gaps or defects within the insulating material and exhibits a symmetrical distribution on the PRPD pattern diagram. Surface discharge typically occurs on the surface of the insulating material and exhibits a different phase distribution on the PRPD pattern diagram compared to internal discharge. Corona discharge typically occurs at conductor tips or edges and exhibits a unipolar distribution on the PRPD pattern diagram. Non-partial discharge noise is a background interference signal and exhibits a random distribution on the PRPD pattern diagram.

[0194] By combining unsupervised clustering and supervised classification, the embedded processor can effectively separate and accurately identify partial discharge signals in complex electromagnetic environments, thereby improving the accuracy and reliability of partial discharge detection.

[0195] The communication system is used to realize data exchange and system management functions between the partial discharge detection device and the remote monitoring platform.

[0196] In some implementations, the communication system includes an Ethernet communication module in an embedded processor and an external network access device. The Ethernet communication module connects to the network device via a standard RJ45 interface to enable data communication between the online partial discharge detection device and a remote server. In some implementations, the external network access device is a 4G router that supports SIM card access, thereby enabling remote network connectivity for the device via a cellular network. Through these network access methods, the communication system can adapt to the network conditions of different field deployment environments, using Ethernet connections in locations with wired network access and cellular network connections in remote substations or outdoor monitoring points lacking wired networks.

[0197] In some implementations, the communication system is based on an operating system environment running on an embedded processor. The embedded processor runs on a Linux system and implements TCP / IP-based network communication functions through a network protocol stack. The communication program uses socket communication to send and receive data.

[0198] Regarding data uploading, the communication system transmits waveform data, phase information, and artificial intelligence recognition results collected by the partial discharge detection device to the remote monitoring platform. The communication data includes raw waveform data, PRPD phase distribution data, and partial discharge type identification results. In some implementations, the communication data is encapsulated in a predefined data format, including JSON or binary data formats, to improve the versatility and efficiency of data transmission.

[0199] In some implementations, during the execution of data acquisition tasks, the embedded processor receives and buffers data from the FPGA and uploads the data according to a preset strategy. Upload methods include periodic uploading and event-triggered uploading. Periodic uploading is used to transmit monitoring data periodically at preset time intervals. Event-triggered uploading is used to prioritize sending critical data when a partial discharge event is detected, thereby improving the system's response speed to abnormal events.

[0200] On the remote monitoring platform side, the platform is implemented using a web-based monitoring system or a Windows-based client program. Users can monitor the equipment's operating status in real time through a web browser or Windows client software, and view partial discharge signal waveforms, PRPD diagrams, and partial discharge type identification results, thereby achieving remote monitoring and analysis of the power equipment's operating status.

[0201] Regarding command issuance, the remote monitoring platform sends control commands to the online partial discharge detection device to achieve device parameter configuration and system management functions. These control commands include data acquisition control commands, system operating parameter configuration commands, and artificial intelligence model update commands. Data acquisition control commands are used to control the start and stop of data acquisition tasks and the adjustment of acquisition parameters. System operating parameter configuration commands are used to configure operating parameters such as trigger thresholds, gain parameters, sampling duration, and channel selection. Artificial intelligence model update commands are used to issue new versions of the artificial intelligence model file to the online partial discharge detection device to achieve online model updates.

[0202] In some implementations, after receiving control commands, the embedded processor writes relevant parameters to FPGA registers or updates the local model file through an internal interface, thereby enabling system parameter adjustment and online model updates. The embedded processor transmits configuration parameters to the FPGA data processing module via the data interaction interface between the FPGA and the embedded processor. The FPGA data processing module then performs data acquisition and processing tasks based on the updated parameters.

[0203] Through the above communication system design, the online partial discharge detection device can realize remote transmission and centralized management of detection data, while supporting remote monitoring and system configuration, thereby improving the intelligence level and operation and maintenance efficiency of the partial discharge monitoring system.

[0204] This invention also provides an online partial discharge monitoring system.

[0205] Reference Figure 1 An online partial discharge monitoring system includes at least one online partial discharge detection device and a remote monitoring platform. The online partial discharge detection device includes a sensor module, a data acquisition system, a data processing system, and a communication system, used to collect, process, and intelligently identify partial discharge signals generated during the operation of power equipment. The remote monitoring platform communicates with the online partial discharge detection device via a communication network, receiving partial discharge waveform data, phase information, and pattern recognition results transmitted by the online partial discharge detection device, and sending control commands to the online partial discharge detection device. In some embodiments, the online partial discharge monitoring system includes multiple online partial discharge detection devices, which are deployed at monitoring points of different power equipment and connected to the remote monitoring platform via a communication network, thereby achieving centralized monitoring and management of multiple power equipment.

[0206] like Figure 1As shown, the remote monitoring platform connects to a host computer, a mobile terminal, and a remote server via a communication network. In some implementations, the remote monitoring platform is implemented using a web-based monitoring system or a Windows-based client program. Users can monitor the operating status of the online partial discharge detection device in real time through a web browser or client software, and view the partial discharge signal waveform, PRPD diagram, and partial discharge type identification results, thereby achieving remote monitoring and analysis of the operating status of power equipment.

[0207] Regarding command issuance, the remote monitoring platform sends control commands to the online partial discharge detection device. These commands include data acquisition control commands, system operating parameter configuration commands, and artificial intelligence model update commands. Data acquisition control commands are used to control the start and stop of data acquisition tasks and the adjustment of acquisition parameters. System operating parameter configuration commands are used to configure operating parameters such as trigger thresholds, gain parameters, sampling duration, and channel selection. Artificial intelligence model update commands are used to issue new versions of the artificial intelligence model file to the online partial discharge detection device to achieve online model updates. In some implementations, after receiving the control commands, the embedded processor of the online partial discharge detection device writes relevant parameters into the FPGA registers or updates the local model file through an internal interface, thereby realizing system parameter adjustment and online model updates.

[0208] Reference Figure 23 The embedded processor in the online partial discharge detection device performs automated polling and data acquisition on multiple monitored objects. At the start of the process, the embedded processor performs initialization operations to configure data acquisition parameters, load the artificial intelligence model, and establish a data interaction interface with the FPGA. After initialization, the embedded processor enters an availability check phase to determine if the device is available. If the device is unavailable, the process ends; if the device is available, subsequent steps are executed.

[0209] When the device is available, the embedded processor performs a model update check. In some implementations, the embedded processor queries the remote monitoring platform via a communication network to see if a new version of the artificial intelligence model file exists. If a model update exists, the embedded processor downloads and loads the new version of the model file; if no model update exists, the current model continues to be used.

[0210] Continue to refer to Figure 23The embedded processor acquires a list of monitored objects, which contains information on multiple monitoring points requiring partial discharge detection. In some implementations, the list of monitored objects is issued by a remote monitoring platform or read from a local configuration file. The embedded processor generates corresponding data acquisition parameters based on the list of monitored objects, including channel selection parameters, sampling duration parameters, trigger threshold parameters, and gain parameters.

[0211] The embedded processor determines whether an object to be detected exists. If no object exists, the process returns to the model update check step, waiting for the next data acquisition cycle; if an object exists, the data acquisition task continues. For an existing object, the embedded processor determines whether a temporary request exists. In some implementations, the temporary request is sent by a remote monitoring platform to specify a separate data acquisition task for a particular object. If a temporary request exists, the embedded processor performs a separate data acquisition task, AI recognition processing, and data upload operation on the specified object outside of the polling process, and then returns to the main process. If no temporary request exists, the embedded processor performs a data acquisition task on the current object according to a set mode.

[0212] After the data acquisition task is completed, the embedded processor determines whether artificial intelligence (AI) recognition is required. If AI recognition is required, the embedded processor calls the AI ​​model to perform feature extraction and pattern recognition on the acquired partial discharge data; if not, the AI ​​recognition step is skipped. The embedded processor then determines whether data uploading is required. If data uploading is required, the embedded processor transmits the waveform data, phase information, and recognition results to the remote monitoring platform via the communication network; if not, the data uploading step is skipped.

[0213] After completing the above operations, the embedded processor determines whether there are more objects to be detected. If there are more objects to be detected, the process returns to the object detection step to continue processing the next object; if all objects to be detected have been processed, the process returns to the model update check step and begins a new monitoring cycle. Through the above polling mechanism, the online partial discharge monitoring system can achieve automated data acquisition and processing scheduling for multiple monitoring objects, and execute separate detection tasks for designated objects outside the regular polling process through a temporary request response mechanism, thereby improving the response capability to sudden detection needs.

[0214] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An online partial discharge detection device, characterized in that, include: The sensor module is used to collect partial discharge signals generated during the operation of power equipment; The data acquisition system, connected to the sensor module, includes a multi-channel signal acquisition circuit, a signal conditioning circuit, an analog-to-digital converter, and an FPGA data acquisition module, wherein: The multi-channel signal acquisition circuit includes a multiplexer for selectively switching and polling partial discharge signals from multiple sensor channels. The signal conditioning circuit includes a low-noise amplifier and a bypass control circuit, wherein the bypass control circuit is used to control the switching of the signal between the amplification path and the through path; The analog-to-digital converter is used to digitally sample the signal-conditioned analog signal; The FPGA data acquisition module is used to receive digital sampling data output by the analog-to-digital converter and power frequency synchronization signal; The data processing system includes an FPGA data processing module and an embedded processor, wherein: The FPGA data processing module includes a data caching module, a trigger control module, a phase detection module, a waveform data management module, and a digital filtering module, which are used to perform cache management, trigger detection, phase calculation, waveform data extraction, and digital filtering processing on the digital sampled data. The embedded processor communicates with the FPGA via a data interaction interface, and is used to extract partial discharge features and perform pattern recognition on the data output by the FPGA data processing module. The pattern recognition includes clustering analysis of the partial discharge signals using an unsupervised learning model and classifying the clustering results using a supervised learning model. A communication system is used to transmit the results of the pattern recognition to a remote monitoring platform via a network.

2. The online partial discharge detection device according to claim 1, characterized in that, The digital filtering module is a configurable finite impulse response filter. The finite impulse response filter includes a data processing path and a parameter loading path. The data processing path is located between the analog-to-digital converter and the data cache module. The parameter loading path is connected to the embedded processor, and the embedded processor dynamically loads the filter coefficients through the data interaction interface.

3. The online partial discharge detection device according to claim 1, characterized in that, The data interaction interface between the embedded processor and the FPGA is built based on the AXI protocol, including an AXI-Lite channel for configuration control and an AXI-Stream channel for data transmission. The waveform data management module is connected to the DMA module through the AXI-Stream channel to transmit sampled data to the memory of the embedded processor.

4. The online partial discharge detection device according to claim 1, characterized in that, The embedded processor is configured to perform adaptive gain control and adaptive trigger control before data acquisition, wherein: The adaptive gain control uses the number of pulses per unit time as the evaluation index, initializes the gain to the minimum value, gradually increases the gain and collects data at each gain level, and determines the current gain as the final gain when the number of pulses per unit time is within the preset upper and lower threshold range. The adaptive trigger control uses the number of pulses per unit time as an evaluation index, initializes the trigger threshold to the maximum value, gradually reduces the trigger threshold and collects data at each trigger level, and determines the current trigger threshold as the final trigger threshold when the number of pulses per unit time is within the preset upper and lower threshold range.

5. The online partial discharge detection device according to claim 1, characterized in that, The clustering analysis includes performing a fast Fourier transform on the partial discharge waveform data to extract frequency domain features, and using a clustering algorithm based on the frequency domain features to divide the partial discharge event into multiple data subsets; the classification and identification includes generating phase distribution map data for each of the data subsets, and inputting the phase distribution map data into the supervised learning model to determine the type of partial discharge.

6. The online partial discharge detection device according to claim 1, characterized in that, The data acquisition system also includes a self-test signal output circuit, which includes a multiplexer controlled by an FPGA and a series capacitor. The FPGA generates a square wave signal synchronized with the power frequency signal. The square wave signal is selected by the multiplexer and then injected into the sensor with self-test function through the series capacitor. The series capacitor and the equivalent inductance of the sensor form a transient response network to generate a simulated partial discharge pulse signal at the sensor output.

7. The online partial discharge detection device according to claim 1, characterized in that, The trigger control module performs real-time trigger judgment on the sampled data based on the set amplitude threshold, and maintains the trigger state after the trigger occurs until the sampled data of the preset length is collected and then clears the trigger state; the phase detection module resets the phase counter at the edge of each power frequency cycle, calculates the sampling length of the complete power frequency cycle by accumulating the number of sampling clock cycles, and records the current count value as the phase position indicator when the trigger event occurs.

8. The online partial discharge detection device according to claim 1, characterized in that, The data acquisition system also includes a power frequency synchronization signal acquisition circuit, which includes a limiting network and a comparator circuit. The limiting network includes a series resistor and two parallel diodes in opposite directions. The series resistor is used to limit the input current, and the parallel diodes are used to perform bidirectional voltage clamping on the input AC signal to protect the comparator circuit. The comparator circuit is used to convert the AC signal after limiting into a square wave signal synchronized with the power frequency.

9. An online partial discharge monitoring system, characterized in that, include: The online partial discharge detection device as described in any one of claims 1-8; as well as The remote monitoring platform communicates with the online partial discharge detection device via a network. It receives partial discharge waveform data, phase information, and pattern recognition results transmitted by the online partial discharge detection device, and sends control commands to the online partial discharge detection device. The control commands include data acquisition control commands, system operation parameter configuration commands, and artificial intelligence model update commands.

10. The online partial discharge monitoring system according to claim 9, characterized in that, The embedded processor of the online partial discharge detection device is configured to perform automated polling and data acquisition on multiple monitoring objects, including obtaining a list of monitoring objects, generating data acquisition parameters based on the list of monitoring objects, performing data acquisition tasks and artificial intelligence recognition processing on each object to be detected according to a set mode, and uploading the recognition results to the remote monitoring platform; the embedded processor is also configured to respond to temporary requests and perform separate data acquisition and recognition tasks on specified detection objects outside of the polling process.

Images