Power semiconductor dynamic characteristic test system, method, device and storage medium

Abstract

This invention relates to the field of power electronics technology and discloses a power semiconductor dynamic characteristic testing system, method, device, and storage medium. The system includes a hardware support layer and a software algorithm layer. The hardware support layer acquires the raw waveform data of the power semiconductor device under test and transmits it to the software algorithm layer. The software algorithm layer includes an adaptive delay debiasing module, an intelligent switching loss calculation module, a parasitic parameter extraction and de-embedding module, and an intelligent diagnosis and test sequence module. This invention improves the data reliability of the entire testing system and reduces testing costs.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically to a power semiconductor dynamic characteristic testing system, method, device, and storage medium. Background Technology

[0002] Dynamic characteristic testing technology for power semiconductors is a core support for the development of the power electronics industry. It provides data for device research and development, production and application by measuring and analyzing indicators such as switching losses, parasitic parameters and dynamic response of power semiconductor devices. With the rapid development of downstream fields such as new energy vehicles, energy storage and industrial automation, as well as the popularization of wide bandgap power semiconductor devices such as SiC and GaN, higher requirements are placed on the accuracy, efficiency, intelligence and adaptability to complex operating conditions of dynamic testing technology.

[0003] Existing dynamic testing technologies for power semiconductors are mostly based on dual-pulse testing, coupled with basic testing hardware, and the testing process is completed manually. Probe delay calibration uses fixed-parameter filtering and manual feature point identification, which is susceptible to complex noise interference, leading to timing alignment errors and affecting the accuracy of loss calculation. The positioning of the switching loss integral boundary relies only on the differential features of a single waveform, without combining the physical characteristics of the device and the operating conditions, resulting in insufficient accuracy under high-frequency operating conditions of wide-bandgap devices. Parasitic parameter extraction uses a single FFT analysis, which has a large deviation in extracting the frequency of non-stationary drain-source voltage turn-off oscillation waveforms. Traditional deconvolution de-embedding is prone to overfitting and waveform distortion. The ability to identify complex nonlinear abnormal waveforms is weak, and the batch test sequences are set with fixed parameters, resulting in operating condition redundancy, low testing efficiency, poor adaptability to different devices and operating conditions, and difficulty in meeting the testing requirements of wide-bandgap devices. Summary of the Invention

[0004] The purpose of this invention is to solve the above-mentioned problems by designing a power semiconductor dynamic characteristic testing system, method, device, and storage medium.

[0005] The first aspect of this invention provides a power semiconductor dynamic characteristic testing system, comprising a hardware support layer and a software algorithm layer. The hardware support layer acquires raw waveform data of the power semiconductor device under test and transmits it to the software algorithm layer. The software algorithm layer includes: The adaptive delay de-biasing module is used to adaptively reduce noise and identify feature points on the original waveform data, and complete timing alignment to output waveform data without timing deviation. The intelligent switching loss calculation module is used to locate the integration boundary of waveform data without timing deviation, calculate the turn-on loss and turn-off loss, and output the loss value and integration interval. The parasitic parameter extraction and de-embedding module is used to extract the oscillation segment of turn-on loss and turn-off loss based on the loss value and integral interval, and to perform wavelet denoising on the drain-source voltage turn-off waveform. The main resonant frequency is extracted by combining FFT frequency domain analysis and wavelet transform, the parasitic inductance of the loop is calculated, and then the equal transfer function is constructed and the waveform de-embedding is completed by deconvolution algorithm to obtain the de-embedding waveform data. The intelligent diagnosis and test sequence module is used to extract parameters and identify abnormal waveforms from the de-embedding waveform data, perform diagnosis, output diagnostic reports and optimization suggestions, and optimize the working conditions of batch test sequences based on reinforcement learning algorithms, and output a batch test summary table.

[0006] Optionally, in a first implementation of the first aspect of the present invention, the adaptive delay debiasing module includes: The first decomposition submodule is used to decompose the original waveform data using a variational mode decomposition algorithm to obtain multiple intrinsic mode functions, wherein the original waveform data includes at least the drain-source voltage waveform, the collector current waveform, and the drive voltage waveform. The reconstruction submodule is used to calculate the correlation coefficient between each intrinsic mode function and the original waveform data, remove noise-dominant intrinsic mode functions with a correlation coefficient less than 0.3, and reconstruct the remaining effective intrinsic mode functions to obtain the preliminary reconstructed waveform after denoising. The noise reduction submodule is used to input the initially reconstructed denoised waveform into a Butterworth low-pass filter for noise reduction and output the denoised waveform data. The first calculation submodule is used to identify feature points of the noise-reduced driving voltage waveform using the second-order difference extremum method, traverse the noise-reduced collector current waveform, calculate the timing deviation between the driving voltage waveform and the collector current waveform, and perform timing adjustment of the collector current waveform based on the timing deviation using the linear interpolation method. The comparison submodule is used to perform a timing comparison between the adjusted collector current waveform and the original noise-reduced drive voltage waveform, and output waveform data without timing deviation.

[0007] Optionally, in a second implementation of the first aspect of the present invention, the computing submodule includes: Calculate the first-order difference of the driving voltage waveform after noise reduction. : in, This represents the waveform of the driving voltage after noise reduction. Indicates the first The time of each sampling point , Indicates the total number of sampling points; Calculate the second difference based on the first difference result. : By iterating through all the calculated second-order difference data, the extreme points with the largest values ​​are selected to obtain the inflection points of the rising edges of the corresponding driving voltage waveform. Based on the inflection point, the driving voltage waveform is extracted from the interval from 10% to 90% amplitude, and the 50% rise point of the interval is determined as the reference feature point. ; The collector current waveform after noise reduction is iterated through, and the time of each sampling point is compared with the time of the reference feature point to determine the sampling point with the smallest difference from the collector current waveform. ; Calculate the timing deviation between the drive voltage waveform and the collector current waveform. : in, A value greater than 0 indicates that the collector current waveform lags behind the drive voltage waveform. A value less than 0 indicates that the collector current waveform leads the drive voltage waveform. A value of 0 indicates no timing bias; The number of sampling points that need to be adjusted is determined based on the timing deviation. ,like Before deleting the collector current waveform if it is greater than 0 Each sampling point is used to supplement the tail of the collector current waveform. A zero value is used to shift the collector current waveform forward; like A value less than 0 is added to the header of the collector current waveform. A zero value was obtained, and the tail of the collector current waveform was deleted. A number of sampling points are used to shift the collector current waveform backward.

[0008] Optionally, in a third implementation of the first aspect of the present invention, the intelligent switching loss calculation module includes: The acquisition submodule is used to acquire the physical parameters and test condition parameters of the power semiconductor device under test. The physical parameters include junction temperature, package type, and device model, while the test condition parameters include bus voltage and gate resistance. The differential operation submodule is used to perform differential operations on waveform data without timing deviations, and extract the waveform differential features corresponding to the collector current change rate, drive voltage change rate, and drain-source voltage change rate. The extraction submodule is used to extract the device physical features corresponding to junction temperature and package type from physical parameters, and then extract the test condition features corresponding to bus voltage and gate resistance from test condition parameters. The waveform differential features, device physical features and test condition features are integrated to form a multi-feature dataset. The first selection submodule is used to compare the start time of the driving voltage and the moment when the collector current change rate first reaches one-tenth of its maximum value, and select the later of the two moments as the starting point of the turn-on loss integration. The first correction submodule is used to extract the moment when the drain-source voltage drops to 5% of the stable value and the moment when the collector current drops to 5% of the peak value after reaching the peak value. It is then corrected in conjunction with the junction temperature. The later moment of the two corrected moments is compared as the end point of the turn-on loss integration to obtain the integration interval of the turn-on loss. The second selection submodule is used to select the moment when the rate of change of the driving voltage first reaches one-tenth of its minimum absolute value as the starting point for the integration of turn-off loss. The second correction submodule is used to extract the moment when the drain-source voltage rises to the peak value and then drops to 5% of the peak value and the moment when the collector current drops to 5% of the initial value, and to make corrections in combination with the bus voltage. The later moment of the two corrected moments is compared as the end point of the turn-off loss integration to obtain the integration interval of the turn-off loss. The second calculation submodule is used to divide the integral interval of turn-on loss and the integral interval of turn-off loss into several equal micro sub-intervals according to the sampling interval of the original waveform data, and calculate the product of drain-source voltage and collector current at both ends of each micro sub-interval. The product values ​​at both ends of each micro sub-interval are added together and the average value is taken. Then, the average value is multiplied by the time interval of the current micro sub-interval to obtain the loss value corresponding to the current micro sub-interval. The accumulation submodule is used to accumulate the loss values ​​of the small sub-intervals within the integral interval of the turn-on loss and the integral interval of the turn-off loss, respectively, to obtain the final loss value of the turn-on loss and the final loss value of the turn-off loss.

[0009] Optionally, in a fourth implementation of the first aspect of the present invention, the parasitic parameter extraction and de-embedding module includes: The interception submodule is used to obtain the loss value and integration interval output by the intelligent switching loss calculation module. Based on the integration interval, it extracts the drain-source voltage oscillation segment waveform corresponding to the turn-on loss and turn-off loss from the drain-source voltage waveform data without timing deviation. The second decomposition submodule is used to perform wavelet decomposition on the drain-source voltage oscillation waveform using the db4 wavelet basis. The number of decomposition layers is set to 3, and the drain-source voltage oscillation waveform is decomposed into 1 low-frequency layer and 3 high-frequency layers. The threshold processing submodule is used to perform threshold processing on the high-frequency layer using a soft threshold denoising algorithm to remove high-frequency noise. The denoised high-frequency layer and the low-frequency layer are then reconstructed to obtain the drain-source voltage oscillation reconstructed waveform. The third calculation submodule is used to extract the main resonant frequency through a combination of FFT frequency domain analysis and wavelet transform, and to calculate the parasitic inductance of the circuit using a resonance formula inversion algorithm. in, Indicates the parasitic inductance of the circuit. Indicates the main resonant frequency. This indicates the output capacitance of the power semiconductor device under test; The fitting submodule is used to construct an equivalent circuit model based on the parasitic inductance of the loop. The equivalent circuit model is fitted by a vector fitting algorithm to establish the transfer function of the equivalent circuit model, where the parasitic resistance in the equivalent circuit model is taken as 0.1Ω. The fourth calculation submodule is used to perform Fourier transform on the original drain-source voltage waveform data and the original collector current waveform data to obtain frequency domain data. In the frequency domain, deconvolution is performed using the following formula to calculate the de-embedded frequency domain data. : in, This represents the inverse function of the transfer function; The execution submodule is used to perform an inverse fast Fourier transform on the de-embedded frequency domain data to obtain the de-embedded drain-source voltage waveform data and the de-embedded collector current waveform data.

[0010] Optionally, in a fifth implementation of the first aspect of the present invention, the third computing submodule includes: Perform a fast Fourier transform on the drain-source voltage oscillation reconstructed waveform to convert the time-domain waveform into a frequency-domain spectrum, and obtain a preliminary frequency distribution curve; Wavelet transform is performed on the reconstructed waveform of drain-source voltage oscillation to obtain the time-frequency distribution map of wavelet coefficients. Combining the preliminary frequency distribution curve and the time-frequency distribution map of wavelet coefficients, the frequency points of clutter interference are eliminated, and the frequency corresponding to the main peak of the spectrum is extracted as the main resonant frequency.

[0011] Optionally, in a sixth implementation of the first aspect of the present invention, the intelligent diagnosis and testing sequence module includes: The traversal submodule is used to traverse the output of the parasitic parameter extraction and de-embedding module, extract feature parameters, and form a parameter dataset. The feature parameters include at least the drain-source voltage overshoot amplitude, oscillation frequency, turn-on time, turn-off time, and loop parasitic inductance. The input submodule is used to convert the de-embedding waveform data into a 224×224 two-dimensional feature map and input it into the anomaly detection model based on the MobileNetV3 network. The mapping submodule is used to extract the depth features of the two-dimensional feature map through convolutional layers, pooling layers, and attention mechanism layers, and to map the depth features to the anomaly type classification space through a fully connected layer, outputting the type of the abnormal waveform and its corresponding confidence level. The types of abnormal waveforms include at least voltage overshoot, oscillation anomaly, current spike, and timing distortion. The generation submodule is used to generate diagnostic conclusions and risk levels based on the output of the anomaly detection model, and match corresponding optimization suggestions to form a preliminary diagnostic report; A submodule is established to establish a Markov decision process for Q-Learning reinforcement learning, with the range of test condition parameters as the state space, the condition selection and number of tests as the action space, and the minimum test time and maximum test coverage as the joint reward function. The third selection submodule is used to initialize the Q-value table, randomly select the initial working condition from the state space, select and execute the action in the action space according to the ε-greedy strategy, and obtain the current reward value. The iterative submodule is used to repeatedly iterate the training until the Q-value table converges, thereby obtaining the optimal test sequence strategy for working condition adaptation. The batch testing submodule is used to execute batch tests according to the optimal test sequence strategy and output a batch test summary table.

[0012] A second aspect of the present invention provides a method for testing the dynamic characteristics of power semiconductors, the method comprising: Adaptive noise reduction and feature point recognition are performed on the original waveform data, and timing alignment is completed to output waveform data without timing deviation. For waveform data without timing deviation, the integral boundary is located, the turn-on loss and turn-off loss are calculated, and the loss value and integral interval are output. Based on the loss value and the integral interval, the oscillation segment of the turn-on loss and turn-off loss is extracted, and wavelet denoising is performed on the drain-source voltage turn-off waveform. The main resonant frequency is extracted by combining FFT frequency domain analysis and wavelet transform. The parasitic inductance of the circuit is calculated inversely. Then, the equal transfer function is constructed and the waveform is de-embedded by the deconvolution algorithm to obtain the de-embedded waveform data. The de-embedding waveform data is processed to extract parameters and identify abnormal waveforms. Diagnostic reports and optimization suggestions are then generated. Simultaneously, the batch test sequences are optimized based on reinforcement learning algorithms, and a batch test summary table is generated.

[0013] A third aspect of the present invention provides a power semiconductor dynamic characteristic testing device, the power semiconductor dynamic characteristic testing device including a memory and at least one processor, the memory storing instructions; the at least one processor calling the instructions in the memory to cause the power semiconductor dynamic characteristic testing device to perform the various steps of the power semiconductor dynamic characteristic testing method as described above.

[0014] A fourth aspect of the present invention provides a computer-readable storage medium storing instructions that, when executed by a processor, implement the steps of the power semiconductor dynamic characteristic testing method as described above.

[0015] The technical effects and advantages provided by the present invention in the above technical solution are as follows: 1. The adaptive delay debiasing module removes the original V. gs I c Compared to traditional fixed-parameter filtering, this method can adaptively adjust the filtering parameters according to the noise intensity of the waveform, avoiding waveform distortion caused by noise and effectively eliminating V. gs with I c Timing deviations between waveforms improve the data reliability of the entire testing system; 2. The intelligent switching loss calculation module adopts integral boundary positioning, which integrates waveform differential features, device physical features and test condition features, avoiding the deviation problem of traditional single feature positioning of integral boundary under high frequency conditions; effectively avoiding loss calculation errors caused by inaccurate positioning of integral interval, and ensuring that the loss value calculation result can truly reflect the actual loss state of power semiconductor device; 3. The parasitic parameter extraction and de-embedding module solves the problem of large noise interference in non-stationary oscillation waveforms, effectively eliminates waveform distortion caused by parasitic effects in the test circuit, and restores the true waveform of the device terminals. Compared with traditional single FFT analysis, it can effectively remove clutter interference and improve the accuracy of resonant frequency extraction. 4. The intelligent diagnosis and test sequence module can accurately identify various complex abnormal waveforms such as voltage overshoot and abnormal oscillation, effectively solving the problem of insufficient identification capability for complex nonlinear abnormal waveforms; the batch test sequence is optimized to effectively eliminate redundant test conditions, prioritize the test of key conditions, significantly reduce the time consumption of batch testing, improve test efficiency, and adapt to the needs of large-scale mass production testing, multi-condition R&D verification and other scenarios. 5. It can adapt to the dynamic testing requirements of semiconductor devices with different power levels, without requiring major modifications to the system hardware, thus meeting the testing needs of multiple scenarios, reducing testing costs, and improving the practicality of the system. Attached Figure Description

[0016] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0017] Figure 1 This is a schematic diagram of the power semiconductor dynamic characteristic testing system provided in an embodiment of the present invention; Figure 2 A flowchart of a power semiconductor dynamic characteristic testing method provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the power semiconductor dynamic characteristic testing equipment provided in an embodiment of the present invention. Detailed Implementation

[0018] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” or “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0019] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 A schematic diagram of the power semiconductor dynamic characteristic testing system provided in this embodiment of the invention. The system includes a hardware support layer 101 and a software algorithm layer 102. The hardware support layer acquires the raw waveform data of the power semiconductor device under test and transmits it to the software algorithm layer, wherein the software algorithm layer includes: The adaptive delay de-biasing module 1021 is used to adaptively reduce noise and identify feature points on the original waveform data, and complete timing alignment to output waveform data without timing deviation. The intelligent switching loss calculation module 1022 is used to locate the integration boundary of waveform data without timing deviation, calculate the turn-on loss and turn-off loss, and output the loss value and integration interval. The parasitic parameter extraction and de-embedding module 1023 is used to extract the oscillation segment of turn-on loss and turn-off loss based on the loss value and integral interval, perform wavelet denoising on the drain-source voltage turn-off waveform, extract the main resonant frequency through FFT frequency domain analysis and wavelet transform, calculate the parasitic inductance of the loop, construct the equal transfer function and complete the waveform de-embedding through the deconvolution algorithm to obtain the de-embedding waveform data. The intelligent diagnosis and test sequence module 1024 is used to extract parameters and identify abnormal waveforms from the de-embedding waveform data, perform diagnosis, output a diagnosis report and optimization suggestions, and optimize the working conditions of the batch test sequence based on the reinforcement learning algorithm, and output a batch test summary table.

[0020] In this embodiment, the dual-pulse test hardware platform in the hardware support layer first provides the power semiconductor device under test with test stress that conforms to the actual working scenario, generates a dual-pulse drive signal to drive the device to complete the switching action, and simulates the turn-on and turn-off conditions of the device when it is working in real time. Then, using an oscilloscope linked to the dual-pulse test hardware platform, along with a high-voltage probe and a high-current probe, the system accurately captures the switching process of the power semiconductor device under test, including the drive voltage (V). gs ), collector current (I c ), drain-source voltage (V) ds The original waveform data of the three categories are collected. During the acquisition process, the oscilloscope sampling rate is not less than 1GS / s and the sampling duration is not less than 10μs to fully capture the waveform characteristics of the high-frequency switching transient. After the acquisition is completed, the oscilloscope will transmit the acquired continuous time series original waveform data to the computer / industrial control computer in the hardware support layer in real time through the data transmission interface. The computer / industrial control computer will then push the original waveform data to the software algorithm layer deployed therein.

[0021] In this embodiment, the adaptive delay de-polarization module includes: The first decomposition submodule is used to decompose the original waveform data using a variational mode decomposition algorithm to obtain multiple intrinsic mode functions, wherein the original waveform data includes at least the drain-source voltage waveform, the collector current waveform, and the drive voltage waveform. The reconstruction submodule is used to calculate the correlation coefficient between each intrinsic mode function and the original waveform data, remove noise-dominant intrinsic mode functions with a correlation coefficient less than 0.3, and reconstruct the remaining effective intrinsic mode functions to obtain the preliminary reconstructed waveform after denoising. The noise reduction submodule is used to input the initially reconstructed denoised waveform into a Butterworth low-pass filter for noise reduction and output the denoised waveform data. The first calculation submodule is used to identify feature points of the noise-reduced driving voltage waveform using the second-order difference extremum method, traverse the noise-reduced collector current waveform, calculate the timing deviation between the driving voltage waveform and the collector current waveform, and perform timing adjustment of the collector current waveform based on the timing deviation using the linear interpolation method. The comparison submodule is used to perform a timing comparison between the adjusted collector current waveform and the original noise-reduced drive voltage waveform, and output waveform data without timing deviation.

[0022] In this embodiment, the calculation submodule includes: Calculate the first-order difference of the driving voltage waveform after noise reduction. : in, This represents the waveform of the driving voltage after noise reduction. Indicates the first The time of each sampling point , Indicates the total number of sampling points; Calculate the second difference based on the first difference result. : By iterating through all the calculated second-order difference data, the extreme points with the largest values ​​are selected to obtain the inflection points of the rising edges of the corresponding driving voltage waveform. Based on the inflection point, the driving voltage waveform is extracted from the interval from 10% to 90% amplitude, and the 50% rise point of the interval is determined as the reference feature point. ; The collector current waveform after noise reduction is iterated through, and the time of each sampling point is compared with the time of the reference feature point to determine the sampling point with the smallest difference from the collector current waveform. ; Calculate the timing deviation between the drive voltage waveform and the collector current waveform. : in, A value greater than 0 indicates that the collector current waveform lags behind the drive voltage waveform. A value less than 0 indicates that the collector current waveform leads the drive voltage waveform. A value of 0 indicates no timing bias; The number of sampling points that need to be adjusted is determined based on the timing deviation. ,like Before deleting the collector current waveform if it is greater than 0 Each sampling point is used to supplement the tail of the collector current waveform. A zero value is used to shift the collector current waveform forward; like A value less than 0 is added to the header of the collector current waveform. A zero value was obtained, and the tail of the collector current waveform was deleted. A number of sampling points are used to shift the collector current waveform backward.

[0023] In this embodiment, the original waveform data is preprocessed to remove isolated outliers caused by transmission interference during data acquisition. Then, the core parameters of the variational mode decomposition algorithm are initialized, including the preset number of decomposition layers, penalty factor, and convergence threshold. Based on the initialized parameters, a variational decomposition model of the original waveform data is constructed. By iteratively optimizing and solving the constrained variational problem of the variational decomposition model, the original waveform data is gradually decomposed into multiple independent intrinsic mode functions with non-overlapping frequencies. Each intrinsic mode function corresponds to a signal of different frequency components in the original waveform, which includes both effective signal components reflecting the switching characteristics of the device and noise signal components introduced during the acquisition process.

[0024] In this embodiment, noise intensity is first detected on the initially reconstructed waveform after denoising. Based on the detected noise intensity value, the cutoff frequency of the Butterworth low-pass filter is adaptively adjusted within the range of 80MHz to 120MHz to ensure that the filter parameters match the noise characteristics of the reconstructed waveform. Then, the filter is activated to filter the reconstructed waveform. Through the frequency selection characteristics of the filter, the low-frequency effective signal components reflecting the switching characteristics of the power semiconductor device in the reconstructed waveform are retained, while the high-frequency noise components that remain are filtered out. After filtering, the waveform data after secondary denoising is directly output.

[0025] In this embodiment, the intelligent switching loss calculation module includes: The acquisition submodule is used to acquire the physical parameters and test condition parameters of the power semiconductor device under test. The physical parameters include junction temperature, package type, and device model, while the test condition parameters include bus voltage and gate resistance. The differential operation submodule is used to perform differential operations on waveform data without timing deviations, and extract the waveform differential features corresponding to the collector current change rate, drive voltage change rate, and drain-source voltage change rate. The extraction submodule is used to extract the device physical features corresponding to junction temperature and package type from physical parameters, and then extract the test condition features corresponding to bus voltage and gate resistance from test condition parameters. The waveform differential features, device physical features and test condition features are integrated to form a multi-feature dataset. The first selection submodule is used to compare the start time of the driving voltage and the moment when the collector current change rate first reaches one-tenth of its maximum value, and select the later of the two moments as the starting point of the turn-on loss integration. The first correction submodule is used to extract the moment when the drain-source voltage drops to 5% of the stable value and the moment when the collector current drops to 5% of the peak value after reaching the peak value. It is then corrected in conjunction with the junction temperature. The later moment of the two corrected moments is compared as the end point of the turn-on loss integration to obtain the integration interval of the turn-on loss. The second selection submodule is used to select the moment when the rate of change of the driving voltage first reaches one-tenth of its minimum absolute value as the starting point for the integration of turn-off loss. The second correction submodule is used to extract the moment when the drain-source voltage rises to the peak value and then drops to 5% of the peak value and the moment when the collector current drops to 5% of the initial value, and to make corrections in combination with the bus voltage. The later moment of the two corrected moments is compared as the end point of the turn-off loss integration to obtain the integration interval of the turn-off loss. The second calculation submodule is used to divide the integral interval of turn-on loss and the integral interval of turn-off loss into several equal micro sub-intervals according to the sampling interval of the original waveform data, and calculate the product of drain-source voltage and collector current at both ends of each micro sub-interval. The product values ​​at both ends of each micro sub-interval are added together and the average value is taken. Then, the average value is multiplied by the time interval of the current micro sub-interval to obtain the loss value corresponding to the current micro sub-interval. The accumulation submodule is used to accumulate the loss values ​​of the small sub-intervals within the integral interval of the turn-on loss and the integral interval of the turn-off loss, respectively, to obtain the final loss value of the turn-on loss and the final loss value of the turn-off loss.

[0026] In this embodiment, the three sets of waveform data—drive voltage, collector current, and drain-source voltage—without timing deviation are first smoothed and preprocessed to avoid the small fluctuations remaining after noise reduction and timing adjustment affecting the accuracy of the differential calculation. Then, a numerical differential method is used to calculate each sample point of each set of waveform data. For the collector current waveform, the collector current change rate corresponding to each sample point is obtained by the ratio of the current difference to the time difference between adjacent sample points. For the drive voltage waveform, the same numerical differential method is used to calculate the drive voltage change rate corresponding to each sample point. For the drain-source voltage waveform, the drain-source voltage change rate corresponding to each sample point is calculated similarly. Finally, the three sets of change rate data are integrated into a continuous time series to form a complete waveform differential feature dataset.

[0027] In this embodiment, the parasitic parameter extraction and de-embedding module includes: The interception submodule is used to obtain the loss value and integration interval output by the intelligent switching loss calculation module. Based on the integration interval, it extracts the drain-source voltage oscillation segment waveform corresponding to the turn-on loss and turn-off loss from the drain-source voltage waveform data without timing deviation. The second decomposition submodule is used to perform wavelet decomposition on the drain-source voltage oscillation waveform using the db4 wavelet basis. The number of decomposition layers is set to 3, and the drain-source voltage oscillation waveform is decomposed into 1 low-frequency layer and 3 high-frequency layers. The threshold processing submodule is used to perform threshold processing on the high-frequency layer using a soft threshold denoising algorithm to remove high-frequency noise. The denoised high-frequency layer and the low-frequency layer are then reconstructed to obtain the drain-source voltage oscillation reconstructed waveform. The third calculation submodule is used to extract the main resonant frequency through a combination of FFT frequency domain analysis and wavelet transform, and to calculate the parasitic inductance of the circuit using a resonance formula inversion algorithm. in, Indicates the parasitic inductance of the circuit. Indicates the main resonant frequency. This indicates the output capacitance of the power semiconductor device under test; The fitting submodule is used to construct an equivalent circuit model based on the parasitic inductance of the loop. The equivalent circuit model is fitted by a vector fitting algorithm to establish the transfer function of the equivalent circuit model, where the parasitic resistance in the equivalent circuit model is taken as 0.1Ω. The fourth calculation submodule is used to perform Fourier transform on the original drain-source voltage waveform data and the original collector current waveform data to obtain frequency domain data. In the frequency domain, deconvolution is performed using the following formula to calculate the de-embedded frequency domain data. : in, This represents the inverse function of the transfer function; The execution submodule is used to perform an inverse fast Fourier transform on the de-embedded frequency domain data to obtain the de-embedded drain-source voltage waveform data and the de-embedded collector current waveform data.

[0028] In this embodiment, the specific values ​​of turn-on loss and turn-off loss transmitted by the intelligent switching loss calculation module are first received, along with the pre-positioned turn-on loss integration interval and turn-off loss integration interval. At the same time, the drain-source voltage waveform data without timing deviation output by the adaptive delay debiasing module is called. Based on the two integration intervals, the drain-source voltage waveform within the corresponding time period is extracted as the oscillation segment waveform. The turn-on loss oscillation segment extracts the time period from the start of integration to the oscillation decay to 10% of the peak value, and the turn-off loss oscillation segment extracts the time period from the start of integration to the oscillation decay to 10% of the peak value, ensuring that the extracted oscillation segment waveform completely contains the resonance characteristics reflecting the parasitic parameters.

[0029] In this embodiment, the waveform of the drain-source voltage oscillation segment corresponding to the turn-on loss and turn-off loss output by the truncation submodule is first preprocessed to remove abrupt interference points caused by truncation at the waveform edge, ensuring the continuity of the oscillation segment waveform. Then, the wavelet decomposition parameters are initialized, the db4 wavelet basis is selected as the decomposition basis function, the number of decomposition layers is set to 3, and the wavelet decomposition operation is started. The drain-source voltage oscillation segment waveform is decomposed into 1 low-frequency layer and 3 high-frequency layers through layer-by-layer decomposition. The low-frequency layer mainly contains the fundamental wave signal of the oscillation segment waveform, reflecting the core characteristics of the oscillation, while the 3 high-frequency layers mainly contain the high-frequency noise and subtle fluctuations mixed in during the oscillation process.

[0030] In this embodiment, the de-embedding frequency domain data output by the fourth calculation submodule is first received. This data includes the de-embedding drain-source voltage frequency domain data and the de-embedding collector current frequency domain data. Then, inverse fast Fourier transform is performed on the two sets of frequency domain data to convert the complex spectrum data in the frequency domain back to the continuous time series data in the time domain, thereby obtaining the de-embedding drain-source voltage waveform data and the de-embedding collector current waveform data. This waveform data has eliminated the interference of parasitic effects such as parasitic inductance and parasitic resistance in the test circuit, and can truly reflect the actual dynamic waveform characteristics of the terminals of the power semiconductor device under test.

[0031] In this embodiment, the third calculation submodule includes: Perform a fast Fourier transform on the drain-source voltage oscillation reconstructed waveform to convert the time-domain waveform into a frequency-domain spectrum, and obtain a preliminary frequency distribution curve; Wavelet transform is performed on the reconstructed waveform of drain-source voltage oscillation to obtain the time-frequency distribution map of wavelet coefficients. Combining the preliminary frequency distribution curve and the time-frequency distribution map of wavelet coefficients, the frequency points of clutter interference are eliminated, and the frequency corresponding to the main peak of the spectrum is extracted as the main resonant frequency.

[0032] In this embodiment, the intelligent diagnosis and testing sequence module includes: The traversal submodule is used to traverse the output of the parasitic parameter extraction and de-embedding module, extract feature parameters, and form a parameter dataset. The feature parameters include at least the drain-source voltage overshoot amplitude, oscillation frequency, turn-on time, turn-off time, and loop parasitic inductance. The input submodule is used to convert the de-embedding waveform data into a 224×224 two-dimensional feature map and input it into the anomaly detection model based on the MobileNetV3 network. The mapping submodule is used to extract the depth features of the two-dimensional feature map through convolutional layers, pooling layers, and attention mechanism layers, and to map the depth features to the anomaly type classification space through a fully connected layer, outputting the type of the abnormal waveform and its corresponding confidence level. The types of abnormal waveforms include at least voltage overshoot, oscillation anomaly, current spike, and timing distortion. The generation submodule is used to generate diagnostic conclusions and risk levels based on the output of the anomaly detection model, and match corresponding optimization suggestions to form a preliminary diagnostic report; A submodule is established to establish a Markov decision process for Q-Learning reinforcement learning, with the range of test condition parameters as the state space, the condition selection and number of tests as the action space, and the minimum test time and maximum test coverage as the joint reward function. The third selection submodule is used to initialize the Q-value table, randomly select the initial working condition from the state space, select and execute the action in the action space according to the ε-greedy strategy, and obtain the current reward value. The iterative submodule is used to repeatedly iterate the training until the Q-value table converges, thereby obtaining the optimal test sequence strategy for working condition adaptation. The batch testing submodule is used to execute batch tests according to the optimal test sequence strategy and output a batch test summary table.

[0033] In this embodiment, after the two-dimensional feature map in the mapping submodule is input into the MobileNetV3 anomaly recognition model, it first performs layer-by-layer convolution operations on the feature map through the model's convolutional layers to extract local features of the waveform. Then, the pooling layer performs dimensionality reduction processing on the convolutional feature map to retain core features and reduce computation. Subsequently, the attention mechanism layer assigns weights to the dimensionality-reduced features, focusing on regions that reflect abnormal features and strengthening the representation ability of abnormal features. The processed deep features are then input into the fully connected layer of the model. The fully connected layer maps the high-dimensional deep features to a preset anomaly type classification space. The classification space includes four basic anomaly types: voltage overshoot, oscillation anomaly, current spike, and timing distortion, as well as corresponding classification nodes. The model calculates the probability value of the feature map corresponding to each anomaly type using the Softmax function, uses the probability value as the confidence level, and outputs the anomaly type with the highest confidence level and its corresponding confidence level. If the confidence level of each anomaly is lower than the preset threshold, it is determined that there is no anomaly.

[0034] In this embodiment, the generation submodule first receives the abnormal waveform type and corresponding confidence level output by the mapping submodule. Simultaneously, it calls the parameter dataset formed by the traversal submodule, jointly comparing the abnormality type, confidence level, and feature parameters in the parameter dataset. Referring to a preset diagnostic rule library, if no abnormality is determined, a diagnostic conclusion of "device dynamic characteristics are normal, no abnormal indicators" is generated, with the risk level set to "no risk" and the optimization suggestion set to "maintain current test conditions." If a certain type of abnormality is determined, the risk level is divided into low, medium, and high based on the degree of feature parameter exceedance and the confidence level. A diagnostic conclusion including the abnormality type, exceedance parameters, and confidence level is generated. Then, according to the preset abnormality and optimization suggestion matching rules, targeted optimization suggestions are matched for the corresponding abnormality type. For example, for voltage overshoot exceedance, the suggestion of "optimizing gate resistance value and reducing parasitic inductance" is matched. The diagnostic conclusion, risk level, and optimization suggestions are organized according to a preset template to form a preliminary diagnostic report.

[0035] In this embodiment, the Q-value table is first initialized, and the initial Q-values ​​corresponding to all states and actions in the Q-value table are set to preset constants. The dimension of the Q-value table matches the size of the state space and action space. Then, a test case is randomly selected from the state space defined by the establishment submodule as the initial state. The initial ε value of the ε-greedy strategy is set, and a random number is generated. If the random number is less than ε, an action is randomly selected from the action space and executed. If the random number is greater than or equal to ε, the action with the largest Q-value in the current state is selected and executed. After the action is executed, the current test time and test coverage are recorded. The reward value corresponding to the current action is calculated by substituting it into the joint reward function. The reward value and state transition information, including the current state, the executed action, the next state, and the reward value, are saved.

[0036] In this embodiment, the iterative submodule first calls the state transition information and current reward value obtained from the third selection submodule, and updates the Q value of the corresponding state-action in the Q-value table according to the Q-value update rule of the Q-Learning algorithm. During the update process, a learning rate and a discount factor are introduced. The learning rate controls the step size of the Q-value update, and the discount factor controls the impact of future rewards on the current Q value. Then, it is determined whether the Q-value table has converged. The convergence criterion is that after a preset number of consecutive iterations, the change in Q value corresponding to all states-actions in the Q-value table is less than a preset convergence threshold. If it has not converged, it returns to the third selection submodule and starts from the next state, continues to select actions, execute actions, calculate reward values ​​and update the Q-value table according to the ε-greedy strategy, and repeats the above iterative process. If it has converged, it stops iterating. Based on the converged Q-value table, the action with the largest Q value in each state is extracted, and it is organized according to the state transition logic to obtain the optimal test sequence strategy for adaptive working conditions, clarifying the working condition execution order and the number of tests for each working condition in the batch test.

[0037] In this embodiment, the batch testing submodule first receives the optimal test sequence strategy output by the iterative submodule, parses the test condition order and the number of tests for each condition contained in the strategy, and establishes linkage with the modules of the hardware support layer and the software algorithm layer. Then, according to the optimal test sequence strategy, each test condition is called in sequence to start the batch testing process. After each condition is tested, the preceding modules are automatically called to complete waveform acquisition, noise reduction, timing alignment, loss calculation, parasitic parameter extraction, anomaly diagnosis and other operations, and the test parameters, characteristic parameters and diagnostic conclusions of the condition are recorded. After all condition tests are completed, the test data of each condition are organized according to a preset format to form a batch test summary table. The summary table clearly includes information such as the condition number, test parameters, characteristic parameters, anomaly diagnosis results and test time, and the batch test summary table is output according to a preset output format.

[0038] Please see Figure 2 The flowchart of the power semiconductor dynamic characteristic testing method provided in this embodiment of the invention includes the following steps: Step 201: Perform adaptive noise reduction and feature point recognition on the original waveform data, and complete timing alignment to output waveform data without timing deviation; Step 202: Locate the integration boundary for the waveform data without timing deviation, calculate the turn-on loss and turn-off loss, and output the loss value and integration interval. Step 203: Based on the loss value and the integral interval, the oscillation segment of the turn-on loss and turn-off loss is extracted, and the drain-source voltage turn-off waveform is denoised by wavelet. The main resonant frequency is extracted by FFT frequency domain analysis and wavelet transform. The parasitic inductance of the circuit is calculated inversely. Then, the equal transfer function is constructed and the waveform is de-embedded by the deconvolution algorithm to obtain the de-embedded waveform data. Step 204: Extract parameters and identify abnormal waveforms from the de-embedded waveform data, perform diagnosis, output a diagnostic report and optimization suggestions, and simultaneously optimize the working conditions of the batch test sequences based on reinforcement learning algorithms, and output a batch test summary table.

[0039] In this embodiment of the invention, by performing adaptive noise reduction, feature point recognition, and timing alignment on the original waveform data, compared with traditional fixed parameter noise reduction and manual feature point recognition, noise components in the original waveform can be accurately removed. At the same time, the precise positioning of feature points and the precise alignment of waveform timing are achieved, outputting waveform data without timing deviation. This eliminates the interference of noise and timing deviation on all subsequent test steps from the source of the test process, effectively solving the problems of noise interference and timing deviation in the original waveform, improving the reliability of the test base data, and ensuring the accuracy of the entire test process. For waveform data without timing deviation, the integral boundary is located. The positioning accuracy of the integral boundary is optimized by combining multi-feature fusion and other technologies, avoiding the deviation problem caused by the traditional single feature positioning of the integral boundary. Then, the turn-on loss and turn-off loss are accurately calculated by standardized calculation methods, and the loss value and integral interval are output. This ensures that the calculated loss value can truly reflect the actual loss state of the power semiconductor device, improves the accuracy and stability of switching loss calculation, and provides accurate data support for device loss analysis. Based on the loss value and the integral interval, the oscillation waveform is accurately extracted. High-frequency noise in the oscillation waveform is eliminated by wavelet denoising. Then, the main resonant frequency is extracted by combining FFT frequency domain analysis and wavelet transform. Compared with the traditional single FFT analysis, it can effectively eliminate clutter interference and improve the extraction accuracy of the main resonant frequency, thereby accurately calculating the parasitic inductance of the circuit. At the same time, the waveform de-embedding is completed by constructing the equivalent transfer function and deconvolution algorithm, which effectively eliminates the waveform distortion caused by the parasitic effect of the test circuit, restores the real waveform data of the device terminals, and makes the test results more consistent with the actual working state of the device. The system extracts parameters and identifies abnormal waveforms from the de-embedded real waveform data. Combining intelligent recognition and rule matching, it achieves accurate diagnosis of anomalies, comprehensively identifying various anomaly types such as voltage overshoot and abnormal oscillation, and outputting targeted diagnostic reports and optimization suggestions. This solves the problems of low efficiency and incomplete identification in traditional manual diagnosis. At the same time, it optimizes the working conditions of batch test sequences based on reinforcement learning algorithms, effectively eliminating redundant test conditions and prioritizing key test conditions, significantly shortening batch test time and improving batch test efficiency, adapting to batch test needs in various scenarios such as R&D verification and production quality inspection.

[0040] Figure 3 This is a schematic diagram of the structure of a power semiconductor dynamic characteristic testing device 600 provided in an embodiment of the present invention. The power semiconductor dynamic characteristic testing device 600 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 610 (e.g., one or more processors) and a memory 620, and one or more storage media 630 (e.g., one or more mass storage devices) storing application programs 633 or data 632. The memory 620 and storage media 630 can be temporary or persistent storage. The program stored in the storage media 630 may include one or more modules (not shown in the diagram), each module may include a series of instruction operations on the power semiconductor dynamic characteristic testing device 600. Furthermore, the processor 610 may be configured to communicate with the storage media 630 and execute the series of instruction operations in the storage media 630 on the power semiconductor dynamic characteristic testing device 600 to implement the method provided in the above embodiment.

[0041] The power semiconductor dynamic characteristic testing equipment 600 may also include one or more power supplies 640, one or more wired or wireless network interfaces 650, one or more input / output interfaces 660, and / or one or more operating systems 631, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will understand that... Figure 3 The power semiconductor dynamic characteristic testing device structure shown does not constitute a limitation on the computer device provided by the present invention. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0042] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when the instructions are executed on a computer, cause the computer to perform each step of the power semiconductor dynamic characteristic testing method provided in the above embodiments.

[0043] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the devices, systems, or units described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0044] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0045] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power semiconductor dynamic characteristic testing system, comprising a hardware support layer and a software algorithm layer, wherein the hardware support layer acquires raw waveform data of the power semiconductor device under test and transmits it to the software algorithm layer, characterized in that, The software algorithm layer includes: The adaptive delay de-biasing module is used to adaptively reduce noise and identify feature points on the original waveform data, and complete timing alignment to output waveform data without timing deviation. The intelligent switching loss calculation module is used to locate the integration boundary of waveform data without timing deviation, calculate the turn-on loss and turn-off loss, and output the loss value and integration interval. The parasitic parameter extraction and de-embedding module is used to extract the oscillation segment of turn-on loss and turn-off loss based on the loss value and integral interval, and to perform wavelet denoising on the drain-source voltage turn-off waveform. The main resonant frequency is extracted by combining FFT frequency domain analysis and wavelet transform, the parasitic inductance of the loop is calculated, and then the equal transfer function is constructed and the waveform de-embedding is completed by deconvolution algorithm to obtain the de-embedding waveform data. The intelligent diagnosis and test sequence module is used to extract parameters and identify abnormal waveforms from the de-embedding waveform data, perform diagnosis, output diagnostic reports and optimization suggestions, and optimize the working conditions of batch test sequences based on reinforcement learning algorithms, and output a batch test summary table.

2. The power semiconductor dynamic characteristic testing system as described in claim 1, characterized in that, The adaptive delay debiasing module includes: The first decomposition submodule is used to decompose the original waveform data using a variational mode decomposition algorithm to obtain multiple intrinsic mode functions, wherein the original waveform data includes at least the drain-source voltage waveform, the collector current waveform, and the drive voltage waveform. The reconstruction submodule is used to calculate the correlation coefficient between each intrinsic mode function and the original waveform data, remove noise-dominant intrinsic mode functions with a correlation coefficient less than 0.3, and reconstruct the remaining effective intrinsic mode functions to obtain the preliminary reconstructed waveform after denoising. The noise reduction submodule is used to input the initially reconstructed denoised waveform into a Butterworth low-pass filter for noise reduction and output the denoised waveform data. The first calculation submodule is used to identify feature points of the noise-reduced driving voltage waveform using the second-order difference extremum method, traverse the noise-reduced collector current waveform, calculate the timing deviation between the driving voltage waveform and the collector current waveform, and perform timing adjustment of the collector current waveform based on the timing deviation using the linear interpolation method. The comparison submodule is used to perform a timing comparison between the adjusted collector current waveform and the original noise-reduced drive voltage waveform, and output waveform data without timing deviation.

3. The power semiconductor dynamic characteristic testing system as described in claim 2, characterized in that, The computation submodule includes: Calculate the first-order difference of the driving voltage waveform after noise reduction. : in, This represents the waveform of the driving voltage after noise reduction. Indicates the first The time of each sampling point , Indicates the total number of sampling points; Calculate the second difference based on the first difference result. : By iterating through all the calculated second-order difference data, the extreme points with the largest values ​​are selected to obtain the inflection points of the rising edges of the corresponding driving voltage waveform. Based on the inflection point, the driving voltage waveform is extracted from the interval from 10% to 90% amplitude, and the 50% rise point of the interval is determined as the reference feature point. ; The collector current waveform after noise reduction is iterated through, and the time of each sampling point is compared with the time of the reference feature point to determine the sampling point with the smallest difference from the collector current waveform. ; Calculate the timing deviation between the drive voltage waveform and the collector current waveform. : in, A value greater than 0 indicates that the collector current waveform lags behind the drive voltage waveform. A value less than 0 indicates that the collector current waveform leads the drive voltage waveform. A value of 0 indicates no timing bias; The number of sampling points that need to be adjusted is determined based on the timing deviation. ,like Before deleting the collector current waveform if it is greater than 0 Each sampling point is used to supplement the tail of the collector current waveform. A zero value is used to shift the collector current waveform forward; like A value less than 0 is added to the header of the collector current waveform. A zero value was obtained, and the tail of the collector current waveform was deleted. A number of sampling points are used to shift the collector current waveform backward.

4. The power semiconductor dynamic characteristic testing system as described in claim 1, characterized in that, The intelligent switching loss calculation module includes: The acquisition submodule is used to acquire the physical parameters and test condition parameters of the power semiconductor device under test. The physical parameters include junction temperature, package type, and device model, while the test condition parameters include bus voltage and gate resistance. The differential operation submodule is used to perform differential operations on waveform data without timing deviations, and extract the waveform differential features corresponding to the collector current change rate, drive voltage change rate, and drain-source voltage change rate. The extraction submodule is used to extract the device physical features corresponding to junction temperature and package type from physical parameters, and then extract the test condition features corresponding to bus voltage and gate resistance from test condition parameters. The waveform differential features, device physical features and test condition features are integrated to form a multi-feature dataset. The first selection submodule is used to compare the start time of the driving voltage and the moment when the collector current change rate first reaches one-tenth of its maximum value, and select the later of the two moments as the starting point of the turn-on loss integration. The first correction submodule is used to extract the moment when the drain-source voltage drops to 5% of the stable value and the moment when the collector current drops to 5% of the peak value after reaching the peak value. It is then corrected in conjunction with the junction temperature. The later moment of the two corrected moments is compared as the end point of the turn-on loss integration to obtain the integration interval of the turn-on loss. The second selection submodule is used to select the moment when the rate of change of the driving voltage first reaches one-tenth of its minimum absolute value as the starting point for the integration of turn-off loss. The second correction submodule is used to extract the moment when the drain-source voltage rises to the peak value and then drops to 5% of the peak value and the moment when the collector current drops to 5% of the initial value, and to make corrections in combination with the bus voltage. The later moment of the two corrected moments is compared as the end point of the turn-off loss integration to obtain the integration interval of the turn-off loss. The second calculation submodule is used to divide the integral interval of turn-on loss and the integral interval of turn-off loss into several equal micro sub-intervals according to the sampling interval of the original waveform data, and calculate the product of drain-source voltage and collector current at both ends of each micro sub-interval. The product values ​​at both ends of each micro sub-interval are added together and the average value is taken. Then, the average value is multiplied by the time interval of the current micro sub-interval to obtain the loss value corresponding to the current micro sub-interval. The accumulation submodule is used to accumulate the loss values ​​of the small sub-intervals within the integral interval of the turn-on loss and the integral interval of the turn-off loss, respectively, to obtain the final loss value of the turn-on loss and the final loss value of the turn-off loss.

5. The power semiconductor dynamic characteristic testing system as described in claim 1, characterized in that, The parasitic parameter extraction and de-embedding module includes: The interception submodule is used to obtain the loss value and integration interval output by the intelligent switching loss calculation module. Based on the integration interval, it extracts the drain-source voltage oscillation segment waveform corresponding to the turn-on loss and turn-off loss from the drain-source voltage waveform data without timing deviation. The second decomposition submodule is used to perform wavelet decomposition on the drain-source voltage oscillation waveform using the db4 wavelet basis. The number of decomposition layers is set to 3, and the drain-source voltage oscillation waveform is decomposed into 1 low-frequency layer and 3 high-frequency layers. The threshold processing submodule is used to perform threshold processing on the high-frequency layer using a soft threshold denoising algorithm to remove high-frequency noise. The denoised high-frequency layer and the low-frequency layer are then reconstructed to obtain the drain-source voltage oscillation reconstructed waveform. The third calculation submodule is used to extract the main resonant frequency through a combination of FFT frequency domain analysis and wavelet transform, and to calculate the parasitic inductance of the circuit using a resonance formula inversion algorithm. in, Indicates the parasitic inductance of the circuit. Indicates the main resonant frequency. This indicates the output capacitance of the power semiconductor device under test; The fitting submodule is used to construct an equivalent circuit model based on the parasitic inductance of the loop. The equivalent circuit model is fitted by a vector fitting algorithm to establish the transfer function of the equivalent circuit model, where the parasitic resistance in the equivalent circuit model is taken as 0.1Ω. The fourth calculation submodule is used to perform Fourier transform on the original drain-source voltage waveform data and the original collector current waveform data to obtain frequency domain data. In the frequency domain, deconvolution is performed using the following formula to calculate the de-embedded frequency domain data. : in, This represents the inverse function of the transfer function; The execution submodule is used to perform an inverse fast Fourier transform on the de-embedded frequency domain data to obtain the de-embedded drain-source voltage waveform data and the de-embedded collector current waveform data.

6. The power semiconductor dynamic characteristic testing system as described in claim 5, characterized in that, The third calculation submodule includes: Perform a fast Fourier transform on the drain-source voltage oscillation reconstructed waveform to convert the time-domain waveform into a frequency-domain spectrum, and obtain a preliminary frequency distribution curve; Wavelet transform is performed on the reconstructed waveform of drain-source voltage oscillation to obtain the time-frequency distribution map of wavelet coefficients. Combining the preliminary frequency distribution curve and the time-frequency distribution map of wavelet coefficients, the frequency points of clutter interference are eliminated, and the frequency corresponding to the main peak of the spectrum is extracted as the main resonant frequency.

7. The power semiconductor dynamic characteristic testing system as described in claim 1, characterized in that, The intelligent diagnosis and testing sequence module includes: The traversal submodule is used to traverse the output of the parasitic parameter extraction and de-embedding module, extract feature parameters, and form a parameter dataset. The feature parameters include at least the drain-source voltage overshoot amplitude, oscillation frequency, turn-on time, turn-off time, and loop parasitic inductance. The input submodule is used to convert the de-embedding waveform data into a 224×224 two-dimensional feature map and input it into the anomaly detection model based on the MobileNetV3 network. The mapping submodule is used to extract the depth features of the two-dimensional feature map through convolutional layers, pooling layers, and attention mechanism layers, and to map the depth features to the anomaly type classification space through a fully connected layer, outputting the type of the abnormal waveform and its corresponding confidence level. The types of abnormal waveforms include at least voltage overshoot, oscillation anomaly, current spike, and timing distortion. The generation submodule is used to generate diagnostic conclusions and risk levels based on the output of the anomaly detection model, and match corresponding optimization suggestions to form a preliminary diagnostic report; A submodule is established to establish a Markov decision process for Q-Learning reinforcement learning, with the range of test condition parameters as the state space, the condition selection and number of tests as the action space, and the minimum test time and maximum test coverage as the joint reward function. The third selection submodule is used to initialize the Q-value table, randomly select the initial working condition from the state space, select and execute the action in the action space according to the ε-greedy strategy, and obtain the current reward value. The iterative submodule is used to repeatedly iterate the training until the Q-value table converges, thereby obtaining the optimal test sequence strategy for working condition adaptation. The batch testing submodule is used to execute batch tests according to the optimal test sequence strategy and output a batch test summary table.

8. A method for testing the dynamic characteristics of power semiconductors, characterized in that, The power semiconductor dynamic characteristic testing method includes: Adaptive noise reduction and feature point recognition are performed on the original waveform data, and timing alignment is completed to output waveform data without timing deviation. For waveform data without timing deviation, the integral boundary is located, the turn-on loss and turn-off loss are calculated, and the loss value and integral interval are output. Based on the loss value and the integral interval, the oscillation segment of the turn-on loss and turn-off loss is extracted, and wavelet denoising is performed on the drain-source voltage turn-off waveform. The main resonant frequency is extracted by combining FFT frequency domain analysis and wavelet transform. The parasitic inductance of the circuit is calculated inversely. Then, the equal transfer function is constructed and the waveform is de-embedded by the deconvolution algorithm to obtain the de-embedded waveform data. The de-embedding waveform data is processed to extract parameters and identify abnormal waveforms. Diagnostic reports and optimization suggestions are then generated. Simultaneously, the batch test sequences are optimized based on reinforcement learning algorithms, and a batch test summary table is generated.

9. A power semiconductor dynamic characteristic testing device, characterized in that, The power semiconductor dynamic characteristic testing device includes a memory and at least one processor, wherein the memory stores instructions; the at least one processor invokes the instructions in the memory to cause the power semiconductor dynamic characteristic testing device to perform the various steps of the power semiconductor dynamic characteristic testing method as described in claim 8.

10. A computer-readable storage medium storing instructions thereon, characterized in that, When the instructions are executed by the processor, they implement the various steps of the power semiconductor dynamic characteristic testing method as described in claim 8.

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