Polycrystalline silicon carbide support for substrates intended to accept power semiconductor devices, and substrates comprising such support.

Abstract

The present invention relates to a polycrystalline silicon carbide support for a substrate intended to receive a power semiconductor device. The support has a first surface indicated as the "front" and a second surface indicated as the "back," and comprises a first surface layer located directly beneath the front and having a resistivity of 1 ohm·cm or more, and a second surface layer located directly beneath the back and having a resistivity of exactly less than 1 ohm·cm.

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to substrates intended to receive devices for applications requiring high power. These may include III-N material-based devices such as gallium nitride. The present invention also relates to supports particularly adapted for forming such substrates. [Background technology]

[0002] Some applications for HEMT ("High Electron Mobility Transistor") type, III-N material-based transistors are in the field of high-power management, such as switches in power converters.

[0003] As schematically shown in Figure 1, such a component 1 has conventionally been, A substrate 2, which is typically a silicon, sapphire, or silicon carbide wafer, A buffer layer 3 formed on the substrate 2, which is generally doped to be semi-insulating, A heterojunction composed of a GaN channel layer 5 and an AlGaN barrier layer 6 continuously formed on a buffer layer, Source S, drain D, and gate G electrode structures on / inside the heterojunction, The metal sheet M is in ohmic contact with the back surface of the support 2. The sheet M may be a copper lead frame for a semiconductor chip housing. To ensure that the back surface of the support 2 is securely bonded to the metal sheet M, an adhesive layer B, such as silver sintered paste, may be used.

[0004] The metal sheet M helps to facilitate the dissipation of heat generated in the heterojunction when the device is operating. Generally, the source electrode S is electrically connected to the substrate 2 to prevent the potential of the substrate from remaining floating. The conductivity state of the transistor between the source S and the drain D is controlled by the voltage applied to the gate G. In power applications, the voltage V applied between the terminals of the source electrode S and the drain electrode DDS When a transistor is turned off, the voltage can reach several hundred to several thousand volts. In the off state, the leakage current flowing between the source S and drain D is low, only a few nanoamperes. In contrast, in the on state, several amperes can flow between the source S and drain D. Furthermore, the switching between the on and off states is extremely fast, taking only a few nanoseconds.

[0005] However, several issues are limiting the widespread adoption of this technology.

[0006] As observed, in the off state, a high voltage is applied between the terminals of the source electrode S and the drain electrode D. This leads to the formation of an electric field, whose lines penetrate very deeply into the buffer layer 3 and the substrate 2. Subsequently, electric fields are generated between the drain electrode D and the substrate 2, and between the source S and the drain D, particularly within the thickness of the buffer layer 3. To prevent the strength of this electric field from exceeding a critical value (called the breakdown electric field) beyond which the material can no longer withstand, a given voltage V DS Regarding electric field strength E=V DS Preparations must be made so that the drain D and source S are separated by a sufficient distance d such that / d is smaller than the breakdown field. Similarly, preparations may be made so that the buffer layer 3 is sufficiently thick such that the value of the electric field at the interface between the buffer layer 3 and the substrate 2 is smaller than the acceptable limit of the relevant material.

[0007] When designing a transistor, it is relatively easy to select the distance d that separates the drain electrode D from the source S. Therefore, a voltage V of approximately 400V to 2,000V is suitable. DS A distance d of approximately 5 to 20 microns can be selected. However, there are limitations to this, as increasing this distance tends to increase the size of the HEMT device, making it more expensive and preventing it from becoming too small.

[0008] However, for reasons of availability and cost, it is far more difficult to provide a sufficiently thick (approximately 3 microns or more) buffer layer 3 of III-N material on device 1, especially when substrate 2 is selected from large silicon (200 mm in diameter) rather than sapphire. This is primarily due to the difference in thermal expansion coefficients between silicon and the III-N material forming the buffer layer. This layer is generated by high-temperature deposition on the silicon substrate, and upon returning to room temperature, it is subjected to extremely high stress, which, if excessive, can lead to cracking and even failure of the substrate. In general, providing a buffer layer thicker than 3 microns on a silicon substrate in the form of a 200 mm wafer is difficult.

[0009] Naturally, to overcome this constraint, attempts can be made to replace the silicon substrate with a substrate having a thermal expansion coefficient closer to that of the buffer layer material. This could include, for example, the use of a silicon carbide substrate. However, aside from the fact that this material is particularly rare and expensive in its crystalline form, it must also be metallized and treated to form ohmic contact with the metal sheet M. The article "Ohmic contacts to SiC" in the International Journal of High Speed ​​Electronics and Systems, Vol. 15, No. 04, pp. 781-820 (2005) states that the contact between the metal layer and SiC is generally non-ohmic immediately after the metal layer is deposited. This interface then needs to be heat-treated, for example using a laser, to promote the formation of silicides, carbides, or ternary phases that effectively make the contact ohmic. It would be beneficial to simplify how the device is housed.

[0010] Documents such as U.S. Patent Application Publication 2013 / 0112997, European Patent Application Publication 3351660, and U.S. Patent Application Publication 2005 / 0269671 propose substrates comprising a polycrystalline silicon carbide support.

[0011] (Subject of the invention) An object of the present invention is to propose a support for a substrate intended to receive a power semiconductor device that addresses these problems at least partially. More specifically, an object of the present invention is to propose a support for a substrate that can receive a relatively thick buffer layer having a thickness of preferably 5 microns or more and that can be simply integrated into a housing without the need to apply heat treatment to the surface that receives the adhesive layer. An object of the present invention is to provide a substrate using such a support and a semiconductor device formed on / within such a substrate.

[0012] (Brief description of the invention) To achieve one of these objectives, the subject of the present invention proposes a polycrystalline silicon carbide support for a substrate intended to receive a power semiconductor device. The support comprises a first surface indicated as the "front" and a second surface indicated as the "back" opposite the first surface. A first surface layer positioned directly below the front surface and having a resistivity of 1 ohm·cm or more, A second surface layer is positioned directly beneath the back surface and has a resistivity of exactly less than 1 ohm·cm. It is equipped with.

[0013] According to other preferred and non-limiting features of the present invention, which are carried out individually or in technically feasible combinations, The minimum thickness of the second layer is 10 micrometers or more. The second layer is 10 20 at / cm 3 Having concentrations of n-type dopants such as nitrogen that exceed this, The concentration of the n-type dopant increases monotonically from the front to the second surface layer. The first layer is either intentionally undoped or 10 15 at / cm 3 Having a vanadium concentration exceeding, The total thickness of the support between the first and second surfaces is in the range of 200 micrometers to 1 mm. The support is preferably in the form of a circular wafer with a diameter of 200 mm.

[0014] According to another aspect, the subject matter of the present invention proposes a substrate intended to receive a semiconductor device, comprising the support described above and a seed layer transferred onto the front surface of the support.

[0015] According to other preferred and non-limiting features of this aspect of the invention, carried out alone or according to technically feasible combinations, the seed layer is composed of gallium nitride, silicon carbide, sapphire or silicon (1,1,1), the substrate comprises a dielectric bonding layer arranged in contact with the support and the seed layer between the support and the seed layer, preferably a dielectric bonding layer made of silicon nitride, the seed layer is in direct contact with the substrate, a gallium nitride-based buffer layer, preferably semi-insulating, is arranged on the seed layer, the buffer layer has a thickness of more than 3 microns, preferably more than 5 micrometers, and even more preferably a thickness in the range of 5 micrometers to 10 micrometers, the substrate is arranged on the buffer layer and comprises a heterojunction capable of forming a two-dimensional electron gas, comprising a channel layer and a barrier layer.

[0016] According to yet another aspect, the present invention proposes a semiconductor component comprising the substrate described above, as well as a source structure, a drain structure and a gate structure arranged on the heterojunction.

[0017] Preferably, a metal sheet is arranged under the back surface of the substrate, in ohmic contact with a metal layer deposited on the second surface layer. An adhesive layer such as a silver sintering paste layer may be arranged between the metal sheet and the metal layer deposited on the second surface layer.

[0018] Further features and advantages of the present invention will become apparent from the following detailed description of the invention, with reference to the accompanying drawings. [Brief explanation of the drawing]

[0019] [Figure 1] This is a diagram showing a substrate equipped with a HEMT transistor using conventional technology. [Figure 2a] This figure shows a substrate intended to accept a semiconductor device according to the present invention. [Figure 2b] This figure shows another substrate intended to accept a semiconductor device according to the present invention. [Figure 3] This figure shows a semiconductor component formed from a substrate according to the present invention. [Modes for carrying out the invention]

[0020] To simplify the following description, the same reference numerals are used for elements that are identical or provide the same function in various embodiments of the present invention or in prior art disclosures.

[0021] Figures 2a and 2b show two embodiments of the substrate 2, which is the subject of this specification and is intended to accommodate a power semiconductor device. As briefly disclosed in the introduction of this application, the substrate 2 is intended to accommodate at least one device comprising a buffer layer made of a III-N material having a thickness of several microns, a heterojunction on the buffer layer having a channel layer and a barrier layer, and a source, drain and gate structure disposed on the heterojunction.

[0022] When substrate 2 still does not contain any devices, it is preferably in the form of a circular wafer, and its diameter is standardized so that it can be handled by standard equipment in the semiconductor industry. Preferably, a diameter of 200 mm is selected.

[0023] Following the steps of forming the device and its individualization, a chip is formed, as is well known, that is intended to integrate a housing for forming a semiconductor component. When the substrate 2 is incorporated into the chip, it takes the form of a rectangular parallelepiped with sides on the order of mm or cm.

[0024] General presentation of board 2

[0025] Regardless of the shape employed by the substrate 2, in very general terms, the substrate 2 comprises a support 2a and a seed layer 2c transferred onto the support 2a. In the embodiment of Figure 2a, a dielectric coupling layer 2b is positioned between the support 2a and the seed layer 2c, in contact with them. In the embodiment of Figure 2b, the substrate 2 does not have a dielectric coupling layer, and the seed layer 2c is transferred directly onto the support 2a in contact with it.

[0026] The support 2a is entirely composed of polycrystalline silicon carbide. The support 2a comprises a first surface, indicated as the "front," and a second surface, opposite the first surface, indicated as the "back." A seed layer is transferred onto the front surface of the substrate, either directly or via a dielectric coupling layer 2c. The primary function of the support 2a is to mechanically support the rest of the stack, leading to the formation of functional semiconductor components, as disclosed in subsequent sections of this detailed description. For this purpose, the thickness of the support, measured between its front and back surfaces, is relatively high, typically ranging from 200 micrometers to 1 mm.

[0027] The function of the seed layer 2c is, as far as it is concerned, to provide an exposed surface on the substrate 2 that can receive the buffer layer 3 of the device. Therefore, the properties of this layer are selected to provide lattice parameters that match the lattice parameters of the III-N material, typically gallium nitride, that forms the buffer layer 3, in order to facilitate epitaxial growth on the substrate 2. Thus, this can include gallium nitride, silicon carbide, sapphire, or silicon (1,1,1) in all cases in their single-crystal forms. Since only its surface properties are utilized, this seed layer 2c does not need to be thick, and therefore a relatively low thickness of less than 2 micrometers is selected.

[0028] The purpose of the dielectric coupling layer 2c is to facilitate the manufacturing of the substrate 2, as disclosed below. A dielectric material having a good thermal diffusivity coefficient, such as silicon nitride, is selected so as not to affect the thermal properties of the substrate 2, as described below, and its thickness is minimized, preferably to less than 1 micrometer.

[0029] It should be noted that the seed layer 2c is much thinner than the support 2a. As a result, due to the compliance effect, the seed layer 2c accepts deformation imposed by the support 2a when exposed to significant temperature fluctuations of several hundred degrees, for example, during the epitaxial formation of the buffer layer 3. In other words, the deformation of the substrate 2 caused by exposure to significant temperature fluctuations is determined by the behavior of the substrate 2a. The thickness of the seed layer is preferably selected to be relatively low, less than 2 micrometers, as already mentioned, in order to promote this compliance effect.

[0030] Also, it should be noted that the polycrystalline silicon on which the support 2a is formed has a coefficient of thermal expansion close to that of the III-N material forming the buffer layer 3, especially when this buffer layer 3 is made of gallium nitride. Also, after the high-temperature epitaxial formation of the buffer layer 3 and when the substrate 2 provided with this layer is returned to room temperature, the stress generated in the structure is minimized. Therefore, it is possible to form a buffer layer 3 much thicker than the buffer layers that can be formed on a prior art silicon substrate. In particular, a buffer layer 3 with a thickness of at least 3 micrometers, preferably more than 5 micrometers, and even more preferably in the range of 5 micrometers to 10 micrometers can be formed.

[0031] Finally, the polycrystalline silicon (representing most of the substrate 2) on which the support 2a is formed has thermal diffusion characteristics that allow the heat generated within the device to be efficiently dissipated. As a reminder, this device is preferably designed to handle a significant amount of power, so it tends to get hot and the heat generated needs to be dissipated to avoid affecting its correct operation. Therefore, the thermal diffusion coefficient of the polycrystalline silicon is approximately three times greater than that of the silicon forming the prior art substrate. By improving the thermal conductivity of the substrate 2 compared to the prior art substrate, it is also possible to increase the power density processed by the device.

[0032] According to an important feature of the substrate 2a, this includes a first surface layer C1 disposed directly beneath the front surface, and the first surface layer C1 has a resistivity of 1 ohm·cm or more, preferably greater than 10 3 ohm·cm. At the depth of the substrate 2, especially in the presence of a high-intensity electric field having a line extending to this first surface layer C1 of the support, the resistive properties of this first surface layer C1 allow the breakdown voltage to be removed. Therefore, the device can withstand a high drain-source voltage exceeding 1,000 V without the risk of damaging the device.

[0033] To obtain these resistivity values, the first layer C1 is intrinsic, i.e., not intentionally doped. Alternatively, the first layer C1 may be further doped to increase its resistivity by 10 15 at / cm 3 It can be doped with vanadium to an extremely high concentration.

[0034] The substrate 2a also comprises a second surface layer C2 located directly beneath the back surface in this case. This second surface layer C2 has a resistivity of strictly less than 1 ohm·cm and may be less than 50 milliohms·cm or less than 10 milliohms·cm. This low resistivity is 10 20 at / cm 3 This can be achieved by n-type doping at dopant concentrations (e.g., nitrogen) exceeding a certain level, and this low resistivity makes it possible to impart nearly metallic behavior to the back surface of the substrate, thus allowing a layer of metal or metallic alloy to be accepted by deposition during the encapsulation step without requiring heat treatment before applying a method for assembling this surface onto a metal sheet.

[0035] This second surface layer C2 does not need to be very thick, but it is still over 10 micrometers thick.

[0036] Preferably, the first layer C1 extends to the depth of the substrate 2 to a second highly doped layer C2. Of course, a transition zone can exist between these two layers C1 and C2 to control the doping gradient required for this transition. In particular, it is possible to consider that the concentration of the n-type dopant in the substrate 2a increases monotonically from the front surface toward the second surface layer C2.

[0037] However, in all cases, regardless of the manner in which the dopant is distributed within the thickness of the support 2a, the support has a first surface layer C1 located as close as possible to the device and directly beneath the front surface, the first surface layer being resistant or highly resistant to counteract any electric field effects that may occur thereon. The support 2a also has a second surface layer C2 located directly beneath the back surface, the second surface layer having extremely low resistivity to provide the back surface with metallic behavior to facilitate reliable assembly of this back surface on a metal sheet when encapsulating the device.

[0038] Manufacturing of polycrystalline silicon carbide substrates

[0039] The present invention relates to the production of a polycrystalline silicon carbide substrate having a first surface layer C1 and a second surface layer C2, which utilizes chemical vapor deposition (CVD) technology. This technology uses a gas mixture comprising at least one silicon precursor gas (such as silane or chlorosilane) and / or at least one carbon precursor gas (such as alkane or alkene) and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, abbreviated as MTCS) to form the bulk portion of the support 2a.

[0040] This technique also uses at least one n-type doping gas to form at least a second surface layer C2. In the case of nitrogen doping of this second surface layer C2, the doping gas may be, for example, NH3, N2H4, or N2.

[0041] In vanadium doping of the first surface layer C1, if such doping is performed, vanadium chloride doping gas (e.g., VCl2) may be used.

[0042] These gases can be diluted in a carrier gas, which may be a reducing gas such as hydrogen and / or an inert gas such as argon. A polycrystalline silicon carbide layer is formed from this gas mixture on a substrate called a “growth” substrate.

[0043] The gaseous mixture is placed in a high-temperature reactor, where the precursor gas is decomposed to form a layer of, for example, 3C polytype polycrystalline silicon carbide, and reacts on the surface of a growth substrate made of preferably purified and refined isotropic graphite, so that the mechanical and thermal resistance properties, thermal expansion coefficient, and purity of the polycrystalline silicon carbide layer are perfectly suited for use as a support 2a for the substrate 2. 3C polytype is also 10 20 atoms / cm 3 It can be doped with nitrogen to an extremely high degree and therefore can have a resistivity of less than 10 mohm·cm.

[0044] The reactor temperature during silicon carbide CVD deposition must be between approximately 1,000°C and 1,600°C, preferably between approximately 1,100°C and 1,400°C, and more preferably between approximately 1,200°C and 1,400°C. Within this temperature range, the deposition rate can vary over a fairly wide range, from 1 micron / hour to over 100 microns / hour. Preferably, the total pressure in the reactor does not exceed 350 mbar, and more preferably 300 mbar.

[0045] To form the substrate 2a according to the present invention, the flow of n-type doping gas is controlled to form a layer of doped polycrystalline silicon carbide of sufficient thickness to ultimately form a second surface layer C2 of the support 2a after all the finishing steps described below, at the start of the growth process, and optionally after the formation of a seed thickness on the graphite surface. This may include forming an n-type doped layer during this growth process, which is 2 to 10 times thicker than the expected thickness in this support, and as a reminder, this thickness typically exceeds 10 micrometers after any thinning of the substrate.

[0046] During this deposition stage, after forming a highly n-doped thickness, the flow of n-type doping gas can be interrupted to form the remaining thickness of intrinsically polycrystalline silicon carbide, which is intentionally undoped. Alternatively, a flow of vanadium-based doping gas can be circulated to further increase the resistivity of the material intended to form the first surface layer C1.

[0047] Once this deposition stage is complete, the graphite growth substrate coated with the polycrystalline silicon carbide deposition layer is machined to remove graphite residue and provide a rough disk of polycrystalline silicon carbide, which is then oxidized in air, typically at 900°C. It should be noted that graphite can also be removed using purely mechanical machining techniques, and even essentially by combustion / oxidation.

[0048] It should be noted that during the deposition stage, it is possible to form an extremely thick polycrystalline silicon carbide to create an ingot of material. Slices can then be cut from this ingot, each slice forming a rough silicon carbide disk. In this method, a heavily n-doped intermediate layer (used to form a second surface layer C2) is carefully inserted between the intrinsic or vanadium-based doped layers (used to form a first surface layer C1) as the ingot is grown. The ingot is cut after all the finishing steps described below at a position that allows the support to be formed according to the present invention.

[0049] In either case, the rough polycrystalline silicon carbide disk resulting from the deposition stage is then mechanically and thermally treated to form a support 2a of selected dimensions. This may include thinning steps using rough grinding and subsequent fine grinding. These steps may be followed by polishing steps to provide a surface finish satisfactory with respect to roughness. These grinding or polishing steps known in the prior art are intended to remove a sufficient thickness from the sides of the disk surface that was in contact with the graphite, in particular, to remove the initial crystal growth zone that generates high stress. These grinding or polishing steps also allow the polycrystalline silicon carbide support 2a to be obtained in the form of a wafer, for example, having a diameter of 200 mm and a thickness typically ranging from 350 to 500 micrometers, but which can be stretched between 200 nm and 1 mm, by removing material from both sides of the rough disk.

[0050] Manufacturing of circuit board 2

[0051] In very general terms, substrate 2 may be produced using a manufacturing method that involves transferring a seed layer onto support 2a, the preparation of which has been described above. Such a transfer method is To form an intermediate structure, the first surface of the support 2a and the main surface of the donor substrate are optionally assembled via a dielectric coupling layer 2b. The steps include removing a portion of the donor substrate from the intermediate structure in order to define the seed layer 2c transferred onto the support 2a, and Includes.

[0052] The dielectric bonding layer 2b may be partially formed by deposition on the donor substrate, on the front surface of the support 2a, or on either of these elements prior to the assembly step. Therefore, the dielectric bonding layer 2b may be produced using LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition) techniques. As already mentioned, this layer is preferably made of silicon nitride for reasons of thermal diffusivity.

[0053] The term “donor substrate” is understood to mean a substrate made of the material of the seed layer 2c, or a substrate including the surface thickness of this material. Thus, a donor substrate may be formed from, as an example, a solid substrate of single-crystal gallium nitride, single-crystal silicon (1,1,1), sapphire, or single-crystal silicon carbide (1,1,1). As an additional example, a donor substrate may take the form of a composite substrate formed by a first substrate supporting a thickness (at least equal to the thickness of the seed layer 2c) of the material intended to form the seed layer. This could be, in particular, the thickness of a III-N material such as gallium nitride formed on a silicon substrate (1,1,1).

[0054] The assembly step of the layer transfer manufacturing method is preferably carried out by molecular bonding. As is well known, during the molecular bonding method, a first surface of a support 2a and a donor substrate, both completely clean, flat, and smooth (optionally, both covered with dielectric layers intended to form a dielectric bonding layer 2b), are in close contact to promote the development of molecular bonds, for example, van der Waals or covalent bonds. The assembly of the two objects is then achieved without the use of adhesive. These bonds can be strengthened by applying heat treatment to the intermediate structure thus formed. When the intention is to form a substrate 2 without a dielectric bonding layer, no dielectric layers are provided on the first surface of the support 2a and the donor substrate, and the first surface of the support 2a and the donor substrate are in direct, close contact with each other.

[0055] The step of removing a portion of the donor substrate can be performed by chemically and mechanically thinning the substrate.

[0056] However, preferably, the substrate 2 is manufactured by applying Smart Cut™ technology, according to this technology, a layer intended to form a seed layer 2c is defined via a weakened surface formed by injecting a “light” seed (typically hydrogen and / or helium) into the donor substrate. After the assembly step, this layer is removed from the donor substrate by fracturing near the weakened surface and thus transferred onto the substrate 2a.

[0057] Regardless of whether the removal of a portion of the donor substrate's thickness is achieved by thinning or crushing, any type of finishing treatment can be applied to the thus formed substrate to conform the seed layer 2c to specifications of thickness, thickness uniformity, or roughness, or any other type of specification.

[0058] In the substrate 2 formed in this manner, the back surface of the support 2, on which the second surface layer C2 is placed beneath it, also forms the back surface of the substrate. On the other hand, the first surface layer C1 is placed directly beneath the seed layer 2c (or, if this layer is present, directly beneath the dielectric coupling layer 2b).

[0059] It should be noted that when the donor substrate material is a polar material, the double transfer of the seed layer 2c taken from it must be performed by first transferring the seed layer 2c to an intermediate substrate, and then, during the second transfer step, transferring the seed layer 2c to a polycrystalline silicon carbide support 2a. In this way, the seed layer 2c has its initial polarity on the support 2a. This is especially true when the donor substrate contains gallium nitride, and this material, in its most widely available form, has a gallium surface and a nitrogen surface, whose exposure is generally desired.

[0060] Manufacturing of semiconductor components

[0061] A substrate 2 in wafer form is used to form at least one semiconductor component. Thus, as disclosed in the previous section and shown in Figure 3, a III-N material-based buffer layer 3 is formed by epitaxy on the exposed surface of the seed layer 2c of the substrate 2. Preferably, the main layer 3 is doped to make it semi-insulating. This is done, for example, by doping the main layer to a concentration of 5.10 in the main layer. 18 ~5.10 19 at / cm 3 This may include carbon doping, which may be within the range of p-type doping, such as iron or magnesium.

[0062] For example, one or more intermediate layers made of AlGaN or more generally AlInGaN may be prepared to be placed within a buffer layer 3 made primarily of gallium nitride. In either case, the lattice parameters of the seed layer 2c and the coefficient of thermal expansion of the polycrystalline silicon carbide support 2a are particularly suited to the material properties of the buffer layer 3 made of III-N material. Thus, it is possible to form this buffer layer 3 on the substrate 2 with a relatively high thickness, for example, greater than 3 micrometers, preferably greater than 5 micrometers, and more preferably in the range of 5 to 10 micrometers.

[0063] In a subsequent step of preparing semiconductor component 1, a heterojunction is formed on the buffer layer 3. As is well known, such a heterojunction combines at least one channel layer 5 (made of, for example, GaN) and a barrier layer 6 (made of, for example, AlGaN). A two-dimensional electron gas can be generated at the interface of these two layers. Then, a source structure S, a drain structure D, and a gate structure G are placed on the heterojunction 5.

[0064] The source structure S can be electrically connected to the second surface layer C2, and the layer can be used as a ground plane for the semiconductor component 1.

[0065] In some cases, the substrate 2 may be prepared to be thinned by removing thickness from the support 2a on the side of the second surface layer C2. However, care must be taken to maintain a sufficient thickness for this layer C2, which is 10 microns or more.

[0066] In a subsequent step, a metal layer is formed on the back surface of the substrate 2a in contact with the second surface layer C2. This metal layer may be of any suitable type, such as titanium, aluminum, nickel, or gold, or it may be a stack formed of these materials. Due to the high doping of the second surface layer C2 and its low resistivity, the contact with the metal layer is ohmic without the need for heat treatment of this interface, which is a particularly preferred feature of the support according to the present invention.

[0067] Numerous devices are typically formed collectively on a substrate 2 in the form of a wafer. These devices are then individualized by cutting the wafer on which they are mounted to form semiconductor chips. These chips are encapsulated to form semiconductor components 1 and assembled on a metal sheet M using an adhesive such as silver sintered paste to form a particularly reliable adhesive layer B for power components.

[0068] Naturally, the present invention is not limited to the embodiments described, and alternative embodiments may be used without departing from the scope of the invention as defined by the claims.

Claims

1. A polycrystalline silicon carbide support (2a) for a substrate (2) intended to receive a power semiconductor device, wherein the support comprises a first surface indicated as the "front" and a second surface opposite the first surface indicated as the "back," and the support comprises, A first surface layer (C1) is positioned directly below the aforementioned front surface and has a resistivity of 1 ohm·cm or more, A second surface layer (C2) is positioned directly beneath the aforementioned back surface and has a resistivity of exactly less than 1 ohm·cm. A polycrystalline silicon carbide support (2a) comprising the above.

2. The polycrystalline silicon carbide support (2a) according to claim 1, wherein the second surface layer (C2) has a thickness of 10 micrometers or more.

3. The second surface layer (C2) is 10 ２０ at / cm ３ A polycrystalline silicon carbide support (2a) according to claim 1 or 2, having a concentration of an n-type dopant such as nitrogen that exceeds [a certain value].

4. The polycrystalline silicon carbide support (2a) according to claim 3, wherein the concentration of the n-type dopant increases monotonically from the front surface toward the second surface layer (C2).

5. The first surface layer (C1) is either intentionally not doped or 10 １５ at / cm ３ A polycrystalline silicon carbide support (2a) according to any one of claims 1 to 4, having a vanadium concentration exceeding [a certain value].

6. A polycrystalline silicon carbide support (2a) according to any one of claims 1 to 5, having a total thickness between the first surface and the second surface in the range of 200 micrometers to 1 mm.

7. A polycrystalline silicon carbide support (2a) according to any one of claims 1 to 6, having the form of a circular wafer and preferably having a diameter of 200 mm.

8. A substrate (2) intended to receive a semiconductor device, comprising a support (2a) according to any one of claims 1 to 7 and a seed layer (2c) transferred onto the front surface of the support (2a).

9. The substrate (2) according to claim 8, wherein the seed layer (2c) is composed of gallium nitride, silicon carbide, sapphire, or silicon (1,1,1).

10. The substrate (2) according to claim 8 or 9, further comprising a dielectric bonding layer (2b), preferably made of silicon nitride, disposed between the support (2a) and the seed layer (2c) in contact with the support (2a) and the seed layer (2c).

11. The substrate (2) according to claim 8 or 9, wherein the seed layer (2c) is in direct contact with the support (2a).

12. The substrate (2) according to any one of claims 8 to 11, comprising a preferably semi-insulating gallium nitride-based buffer layer (3) disposed on the seed layer (2c).

13. The substrate (2) according to claim 12, wherein the buffer layer (3) has a thickness of more than 3 microns, preferably more than 5 micrometers, and more preferably in the range of 5 micrometers to 10 micrometers.

14. The substrate (2) according to claim 12 or 13, comprising a heterojunction disposed on the buffer layer (3), comprising a channel layer (5) and a barrier layer (6), capable of forming a two-dimensional electron gas.

15. A semiconductor component (1) comprising a substrate (2) according to claim 14, and a source structure (S), a drain structure (D), and a gate structure (G) disposed on the heterojunction.

16. The semiconductor component (1) according to claim 15, comprising a metal sheet (M) disposed beneath the back surface of the substrate and in ohmic contact with the second surface layer (C2).

17. The semiconductor component (1) according to claim 16, comprising an adhesive layer (B), such as a silver sintered paste layer, disposed between the metal sheet (M) and the second surface layer (C2).

18. The semiconductor component (1) according to claim 16 or 17, comprising a metal layer disposed on the second surface layer (C2).

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