CARRIER AND METHOD FOR MANUFACTURING A VERTICAL POWER SEMICONDUCTOR DEVICE

Abstract

Support (200) comprising: a support body (202); a bonding material (204) on a first main surface (208) of the support body (202), wherein the support (200) is configured to be attached to a semiconductor wafer via the bonding material (204) by wafer bonding, wherein the support body (202) contains one or more of silicon, boron phosphosilicate glass, borosilicate glass, phosphosilicate glass, boron nitride, polycrystalline silicon, silicon carbide; and dopants integrated in a first part (216) of the support (200) on the first main surface (208), wherein the dopants are configured to eject from the support (200) by thermal processing and are configured to form an n-type or p-type doping in the semiconductor wafer.

Description

TECHNICAL AREA The present disclosure relates to a carrier and a method for manufacturing a vertical power semiconductor device. BACKGROUND Semiconductor wafers are typically available in standard wafer sizes and / or thicknesses. For example, standard wafer diameters are 50 mm (2 inches), 100 mm (4 inches), 150 mm (6 inches), 200 mm (8 inches), or 300 mm (12 inches). For silicon power semiconductor devices, a standard wafer thickness might be, for example, 725 µm. Attempts have been made to reduce the final thickness of a semiconductor material to improve device characteristics. For example, in power semiconductor devices with a vertical load current flow between a front and back face, a thinner semiconductor die may result in a lower on-resistance. Exemplary semiconductor devices are described in US 2007 / 0215981 A1 and DE 102014114683 A1. The heat balance applied to thin wafers can complicate the handling and processing of semiconductor wafers that are thinner than standard wafers.For example, an auxiliary support can be reversibly bonded to a semiconductor wafer to increase mechanical stability, but this can also cause additional challenges in process technology. There is a need to improve vertical power semiconductor devices and the manufacturing processes for them. SUMMARY The invention is defined in the independent patent claims. Further developments are the subject of the dependent patent claims. An example from the present disclosure relates to a vertical power semiconductor device. A vertical power semiconductor device comprises a semiconductor body with a first primary surface and a second primary surface opposite the first primary surface. The thickness of the semiconductor body between the first primary surface and the second primary surface ranges from 40 µm to 200 µm. Active device elements are formed in the semiconductor body at the first primary surface. Edge termination elements at least partially surround the active device elements at the first primary surface. A diffusion region extends from the second primary surface into the semiconductor body. A doping concentration profile of the diffusion region decreases over a vertical distance ranging from 1 µm to 5 µm from a peak concentration Ns at the second primary surface to a concentration Ns / e, where e is Euler's number. Another example from the present disclosure relates to a semiconductor wafer or an array of bare dies. The semiconductor wafer or array of bare dies contains a plurality of semiconductor dies, each or some of the plurality of semiconductor dies containing a vertical power semiconductor device as defined above. Another example in the present disclosure relates to a support. The support comprises a support body. Furthermore, the support comprises a bonding material on a first principal surface of the support body. The support is configured to be attached to a semiconductor wafer via the bonding material by wafer bonding. Dopants are integrated into a portion of the support on the first principal surface. The dopants are configured to egress from the support, e.g., by diffusing out through thermal processing, and are configured to form an n-type or p-type doping in the semiconductor wafer. Another example from the present disclosure relates to a method for fabricating a vertical power semiconductor device. The method comprises forming active device elements in a semiconductor wafer at a first major surface of the semiconductor wafer. The method further comprises forming edge termination elements that at least partially surround the active device elements at the first major surface. The method further comprises reducing the thickness of the semiconductor wafer at a second side opposite the first major surface. The method then further comprises bonding the semiconductor wafer to a support via the second side. The method further comprises introducing dopants from the support into the semiconductor wafer through a second major surface of the semiconductor wafer at the second side. Another example in the present disclosure relates to a different method for fabricating a vertical power semiconductor device. The method comprises forming active device elements in a semiconductor wafer at a first major surface of the semiconductor wafer. The method further comprises forming edge termination elements that at least partially surround the active device elements at the first major surface. The method further comprises reducing the thickness of the semiconductor wafer at a second side opposite the first major surface. The method further comprises bonding the semiconductor wafer to a support via the second side. The method further comprises introducing dopants into the semiconductor wafer through a second major surface of the semiconductor wafer at the second side prior to bonding the semiconductor wafer to a support via the second side. An example from the present disclosure relates to another method for manufacturing a vertical power semiconductor device. The method comprises forming active device elements in a semiconductor wafer on a first major surface of the semiconductor wafer. The method further comprises reducing the thickness of the semiconductor wafer on a second side opposite the first major surface. The method further comprises bonding the semiconductor wafer to a substrate via the second side. The method further comprises subjecting the wafer to a heat treatment at least 600°C. An example in the present disclosure relates to another method for fabricating a vertical power semiconductor device. The method comprises forming active device elements in a semiconductor wafer at a first major surface of the semiconductor wafer. The method further comprises reducing the thickness of the semiconductor wafer at a second side opposite the first major surface. The method then further comprises bonding the semiconductor wafer to a support via the second side. The method further comprises depositing a metallization layer on the first major surface before removing the support. The expert will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are enclosed to provide a further understanding of the embodiments and are incorporated into and form part of this description. The drawings illustrate examples of SiC semiconductor devices and methods for fabricating a silicon carbide device and, together with the description, serve to explain the principles of the examples. Further examples are described in the following detailed description and the claims. Fig. 1 is a schematic cross-sectional view to illustrate an illustrative example of a power semiconductor device. Figs. 2A to 6B are schematic top and cross-sectional views to illustrate examples of supports. Figs. 7A to 9 are schematic cross-sectional views to illustrate methods for fabricating a power semiconductor device. DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings, which form part thereof and in which specific examples are shown for illustration, illustrating how SiC semiconductor devices and methods for fabricating a silicon carbide device can be implemented in practice. It is understood that further examples may be used and structural or logical modifications made without departing from the scope of this disclosure. For example, features illustrated or described for one example may be used in or in connection with other examples to arrive at yet another example. It is intended that this disclosure includes such modifications and changes. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated with the same reference symbols in the various drawings, unless otherwise stated. The terms "have," "contain," "comprise," "exhibit," and the like are open-ended terms, indicating the presence of the identified structures, elements, or features, but not excluding the presence of additional elements or features. Indefinite and definite articles should encompass both the plural and the singular unless the context clearly indicates otherwise. The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" implies that one or more intermediate elements suitable for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. A resistive contact is a non-rectifying electrical junction with a linear or nearly linear current-voltage characteristic. For physical dimensions, specified ranges include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a boundary value such as "at most" and "at least". The term "on" should not be interpreted as meaning only "directly on". Rather, if an element is positioned "on" another element (e.g., a layer is "on" another layer or "on" a substrate), another component (e.g., another layer) can be positioned between the two elements (e.g., another layer can be positioned between a layer and a substrate if the layer is "on" the substrate). An illustrative example of a vertical power semiconductor device can include a semiconductor body with a first primary surface and a second primary surface opposite the first primary surface. The thickness of the semiconductor body between the first primary surface and the second primary surface can range from 40 µm to 200 µm. The vertical power semiconductor device can further include active device elements in the semiconductor body at the first primary surface. The vertical power semiconductor device can also include edge termination elements that at least partially surround the active device elements at the first primary surface. The vertical power semiconductor device can further include a diffusion region extending from the second primary surface into the semiconductor body.A doping concentration profile of the diffusion area can decrease over a vertical distance ranging from 1 µm to 5 µm from a peak concentration Ns at the second main surface to a concentration Ns / e, where e is Euler's number. The vertical power semiconductor device can be a power semiconductor diode, a power semiconductor IGBT (insulated-gate bipolar transistor), or a power semiconductor transistor such as a power semiconductor IGFET (insulated-gate field-effect transistor, e.g., a metal-oxide-semiconductor field-effect transistor). The vertical power semiconductor device can be configured to conduct currents greater than 1 A, 10 A, or even 30 A, and can further be configured to carry voltages between load terminals, e.g., between the drain and source of a MOSFET, between the emitter and collector of an IGBT, or between the cathode and anode of a diode, in the range of a few hundred to a few thousand volts. B. 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV.The blocking voltage can correspond to a voltage class that is specified, for example, in a datasheet of the power semiconductor device. The semiconductor body can contain or consist of a semiconductor material from the elemental semiconductors of Group IV, a IV-IV composite semiconductor material, a III-V composite semiconductor material, or a II-VI composite semiconductor material. Examples of semiconductor materials from the elemental semiconductors of Group IV include silicon (Si) and germanium (Ge). Examples of IV-IV composite semiconductor materials include silicon carbide (SiC) and silicon germanium (SiGe). Examples of a III-V composite semiconductor material include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs). Examples of II-VI composite semiconductor materials include cadmium telluride (CdTe), mercury cadmium telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe).The semiconductor body can be, for example, a silicon semiconductor body produced using a magnetic Czochralski process (MCZ) or a zone melting process (FZ). The active device elements can be located in an active device region of the semiconductor body at the first primary surface. The active device region is a region of the semiconductor body where a load current enters or exits the semiconductor body through the first primary surface. In the case of IGFETs or IGBTs, the active device region can include source regions that are electrically connected to a contact electrode through the first primary surface. A source-drain current or an emitter-collector current can flow from the contact electrode through the first primary surface into the source regions. In the case of diodes, the active device region can include anode or cathode regions that are electrically connected to the contact electrode through the first primary surface. An anode-cathode current can flow from the contact electrode through the first primary surface into the anode or cathode regions.Consequently, the active device area can be limited to a first part of the first main surface, through which, for example, a load current flow is passed. Edge termination elements can be formed in an edge termination region, which is a region of the semiconductor body that partially or completely surrounds the active device area. Since pn junctions within the semiconductor body, such as pn junctions between a body region and a drift region of an IGFET or IGBT, or pn junctions between a cathode and anode of a diode, are not infinite but terminate at the edge regions of the semiconductor body, this edge effect limits the breakdown voltage of the device below the ideal value determined by the infinite parallel plane junction. Care must be taken to ensure a suitable and efficient termination of the pn junction at the edge of the semiconductor body. The edge termination region is one measure to ensure a suitable and efficient termination of the pn junction. Edge termination structures are formed in the edge termination region to reduce the electric field at the edge of the semiconductor body. The lateral dimensions of the edge termination region can vary depending on the voltage class of the semiconductor device. Semiconductor devices with higher voltage classes typically require larger lateral dimensions of their edge termination regions to ensure proper termination of the pn junction. Examples of edge termination structures in the edge termination region include field plates, joint termination extensions (JTE) structures, and various lateral doping (VLD) structures.In addition to the active device area, the edge termination area can be limited to a second part of the first main surface, which i) completely or partially surrounds the first part of the active device area and through which ii) no load current flows through the first main surface to the contact electrode and which iii) contributes to the termination of the pn junction. For example, a transition region can be present between the active device area and the edge termination area to electrically connect the edge termination area. The diffusion region extending from the second main surface into the semiconductor body may contain dopants introduced into the semiconductor body by means of a gas-phase diffusion source and / or a solid-phase diffusion source. For example, a Gaussian function or a complementary error function may fit the doping concentration profile of the diffusion region. The doping concentration profile can be determined by any suitable characterization technique, such as secondary ion mass spectrometry (SIMS) for direct measurements of atomic concentrations, Rutherford backscattering (RBS) for direct measurements of atomic concentrations, or various methods for measuring conductivity as a function of depth for semiconductors, which more or less directly corresponds to the concentration of dopants.For example, capacitance as a function of applied voltage for MOS and transition-state structures, propagation resistance measurements, or microwave absorption can be used to determine the doping concentration profile of the diffusion domain. Fitting the Gaussian function or error function to the experimental values ​​of the doping concentration profile of the diffusion domain can be performed by fitting the experimental results to the model. One example of model fitting is least-squares minimization. Analysis of experimental results can also be performed by fitting the model equations of physical models, such as Fick's laws, to the experimental results to obtain the physical parameters relevant to the diffusion domain. For example, the diffusion region can be a rear emitter region of a power bipolar transistor with an insulated gate, or an anode or cathode region of a power semiconductor diode. Another example of the present disclosure relates to a semiconductor wafer or an array of bare dies comprising a plurality of semiconductor dies. Each of the plurality of semiconductor dies, or some thereof, comprises the vertical power semiconductor device according to one of the above or following examples. For example, the diameter of the semiconductor wafer is 200 mm or larger. Another example in the present disclosure relates to a support. The support may include a support body. The support may further include a bonding material on a first major surface of the support, wherein the support is configured to be attached to a semiconductor wafer via the bonding material by wafer bonding. The support may further include dopants integrated in a first part, e.g., a surface part of the support at the first major surface. The dopants are configured to effloresce from the support by thermal processing and are configured to form an n-type or p-type dopant in the semiconductor wafer. For example, the support may include a second part that is free of dopants. The second part of the support, for example, adjoins a second major surface of the support opposite the first major surface.For example, an area on the first surface where the dopants are integrated into the support can be larger than 70%, 80%, or 90% of the total area of ​​the first main surface. In other words, for example, more than 70%, 80%, or 90% of the first surface is configured as a dopant source. The dopants can evaporate from the substrate via diffusion caused by thermal processing. For example, boron (B), aluminum (Al), gallium (Ga), indium (In), or any combination thereof can be used for p-type doping in silicon semiconductor wafers. Similarly, phosphorus (P), arsenic (As), antimony (Sb), selenium (Se), sulfur (S), or any combination thereof can be used for n-type doping in silicon semiconductor wafers. The support can, for example, be disc-shaped with a diameter of 200 mm or larger. The substrate can contain, for example, one or more silicon, boron phosphosilicate (BPSG) glass, boron silicate (BSG) glass, phosphosilicate (PSG) glass, boron nitride, doped or undoped polycrystalline silicon, or silicon carbide. The dopants can be contained, for example, in the bonding material of the substrate. Examples of bonding materials include any silicon oxides, silicon nitrides, metals, polycrystalline silicon, or any combination thereof. For glass substrates, for instance, polycrystalline silicon can be used as the bonding material. The dopants can, for example, be contained in a semiconductor region of the support material at the first primary surface. The support material can, for example, be a semiconductor substrate containing the dopants in a region at the first primary surface. Alternatively, the support material can be a material other than the semiconductor material, such as glass or any other material with a coefficient of thermal expansion suitable for bonding to the semiconductor wafer material. The dopants can be introduced into the carrier, for example, by an ion implantation step and / or a diffusion step. An arrangement of the bonding material on the first main surface of the carrier body includes, for example, one or more rings or ring segments along a circumference of the carrier body, a structure of regularly arranged islands, or a multitude of parallel strips. The substrate can further include, for example, a semiconductor layer over the substrate. The dopants can be contained within the semiconductor layer, and the bonding material can be placed on top of the semiconductor layer. The substrate can also include a diffusion barrier located between the semiconductor layer and the substrate. This diffusion barrier can prevent the dopants from diffusing through the substrate, which can be undesirable because, for example, the dopants would then not be available for doping a semiconductor wafer. As an example, a diffusion barrier made of or containing SiC can be used for platinum (Pt) doping, for instance, during the lifetime killing adjustment of a high-power diode. Another example from the present disclosure relates to a method for fabricating a vertical power semiconductor device. The method may include forming active device elements in a semiconductor wafer at a first major surface of the semiconductor wafer. Furthermore, the method may include forming edge termination elements that at least partially surround the active device elements at the first major surface. The method may also include reducing the thickness of the semiconductor wafer at a second side opposite the first major surface. After the thickness reduction step, the method may further include bonding the semiconductor wafer to a support via the second side. Finally, the method may include introducing dopants from the support through a second major surface of the semiconductor wafer into the semiconductor wafer at the second side. The support and the semiconductor substrate can be joined, for example, by direct bonding or by reactive bonding. Adhesion between directly bonded layers and substrates can be based on chemical bonds, hydrogen bonds, metallic bonds, ionic bonds, and / or covalent bonds. Direct bonding can involve applying a physical force that presses the semiconductor substrate and the handling substrate against each other, thermal treatment of at least one of the bonded surfaces at a moderate temperature, or a combination of both (fusion bonding, thermo-compressive bonding, bonding by atomic rearrangement). Direct bonding can also involve the absence of any additional intermediate layer, such as an adhesive layer. An adhesive layer, for example, is not required.A nitride layer can, for example, be placed at the interface where the handling substrate and the semiconductor substrate are attached to each other. The dopants can leave the support, for example, via a thermal diffusion process, and enter the semiconductor wafer by diffusion in a state where the support is bonded to the semiconductor wafer. Thus, the support not only serves as mechanical support for the thinned semiconductor wafer but also simultaneously acts as a doping source for introducing dopants into the semiconductor wafer, for example, to form any type of doped region on the back side of the semiconductor wafer, such as emitter regions of power IGBTs or power diodes, or field-stop zones. This can, for example, enable an increase in the depth, electrically active doping dose, and homogeneity of back-side emitters and / or field-stop zones of power semiconductor devices. Therefore, improved electrical characteristics of power semiconductor devices, e.g.,An improved short-circuit withstand capability and / or an improved ability to shut down an overcurrent can be achieved. The thickness of a semiconductor wafer can be reduced, for example, by removing material from the other side of the wafer. This material can be removed using any suitable material removal technique, such as abrasive machining processes like grinding, chemical material removal such as etching, or chemical-mechanical polishing (CMP). Structuring with masks, such as resist masks or hard masks, can allow specific areas of the wafer, such as a ring around one of its circumferences, to be excluded from material removal. The thickness of the semiconductor wafer can be reduced, for example, by separating the wafer into a first part and a second part through a wafer splitting process, e.g., through a so-called cold splitting process and / or a smart cut process. The vertical power semiconductor device can, for example, be a vertical power semiconductor device as described above or below, and the diffusion region can be formed by introducing the dopants from the support into the semiconductor wafer. The support can, for example, be a support as described in any of the above or following examples. For example, the process can further involve separating the semiconductor wafer from the support by at least one etching process that removes at least part of a bonding material. An etching solution can, for example, weaken a bond between the semiconductor wafer and the support by removing the bonding material from an outer periphery of a bonding interface toward the center of the bonding interface. The bonding material on the support can, for example, be configured in such a way as to allow an etching solution to be directed toward the center of the support. For example, channels can be formed at a bonding interface between the semiconductor support and the support. Exemplary configurations of the bonding material on the support can include, among others, separate islands or parallel strips. The thickness of the semiconductor wafer can be reduced, for example, in a central region, while maintaining the thickness of a ring or ring segments around the perimeter of the wafer. This ring or these segments can contribute to the mechanical stability of the thinned semiconductor wafer. The method may, for example, further include the application of a mechanical support element to the first main surface of the semiconductor wafer. Another example in the present disclosure relates to a different method for fabricating a vertical power semiconductor device. The method may include forming active device elements in a semiconductor wafer at a first major surface of the semiconductor wafer. Furthermore, the method may include forming edge termination elements that at least partially surround the active device elements at the first major surface. The method may also include reducing the thickness of the semiconductor wafer at a second side opposite the first major surface. Finally, the method may include bonding the semiconductor wafer to a support via the second side, for example, after the process of reducing the thickness of the semiconductor wafer.The process can further include introducing dopants into the semiconductor wafer through a second primary surface of the semiconductor wafer on the second side prior to bonding the semiconductor wafer to a substrate via this second side. After the bonding step, the process can further include subjecting the wafer to a heat treatment of at least 600°C. The dopants can be introduced into the second main surface of the semiconductor wafer, for example, by ion implantation. Another example in the present disclosure relates to a further method for manufacturing a vertical power semiconductor device. The method may comprise forming active device elements in a semiconductor wafer on a first major surface of the semiconductor wafer. The method may then further comprise reducing the thickness of the semiconductor wafer on a second side opposite the first major surface. The method may then further comprise bonding the semiconductor wafer to a support via the second side. The method may then further comprise subjecting the wafer to a heat treatment at least 600°C. Another example in the present disclosure relates to a different method for fabricating a vertical power semiconductor device. The method may include forming active device elements in a semiconductor wafer on a first major surface of the semiconductor wafer. The method may further include reducing the thickness of the semiconductor wafer on a second side opposite the first major surface. The method may then further include bonding the semiconductor wafer to a support via the second side. Subsequently, a metallization layer may be applied to the first major surface before the support is removed. For example, at least one metallization layer and optional dielectric intermediates, as well as an imide layer(s), may be applied before the support is removed. The diameter of the semiconductor wafer can, for example, be 200 mm or larger. The examples and features described above and below can be combined. Further examples of the methods and power semiconductor devices described herein are explained in detail below, in conjunction with the accompanying drawings. Functional and structural details described in relation to the examples above apply equally to the exemplary embodiments illustrated in the figures and further described below. Fig. 1 is a schematic cross-sectional view illustrating an embodiment of a vertical power semiconductor device 100. The vertical power semiconductor device 100 comprises a semiconductor body 102 having a first main surface 104 and a second main surface 106 opposite the first main surface 104. The thickness d of the semiconductor body 102 between the first main surface 104 and the second main surface 106 ranges from 40 µm to 200 µm. Active device elements 108 are formed in the semiconductor body 102 at the first main surface 104. The active device elements 108 are illustrated in simplified form by a dashed box that defines a region of the semiconductor body 102, e.g., an active region, where active device elements 108 are located. Depending on the type of power semiconductor device, e.g.,In IGBTs, IGFETs, or diodes, the active device elements can, for example, have n- and / or p-doped semiconductor regions of a specific doping and arrangement. Edge termination elements 110 at least partially surround the active device elements 108 on the first main surface 104. The edge termination elements 110 are illustrated in simplified form by dashed boxes that define a region of the semiconductor body, e.g., an edge termination region, where the edge termination elements 110 are located. Examples of edge termination elements 110 include, for example, field plates, joint termination extension (JTE) structures, and a variation of lateral doping (VLD) structures. A diffusion region 112 extends from the second main surface 106 into the semiconductor body 102. A doping concentration profile c of the diffusion region 112 against a vertical direction y is schematically illustrated in a graphical representation below the cross-section. The doping concentration profile c decreases over a vertical distance Δy ranging from 1 µm to 5 µm or from 2 µm to 5 µm from a peak concentration Ns at the second main surface 106 to a concentration Ns / e, where e is Euler's number. The doping concentration profile c of the diffusion region 112 differs, for example, from typical diffusion profiles of ultra-shallow transitions produced by laser activation with respect to profile shape and profile depth. Since the diffusion region 112 may contain dopants introduced into the semiconductor body 102 by means of a gas-phase diffusion source and / or a solid-phase diffusion source, a Gaussian function or a complementary error function may correspond to the doping concentration profile of the diffusion region 112. Since no wiring region has yet formed above the first main surface 104 when the dopants are introduced via the second main surface 106 to form the diffusion region 112, high-temperature processes, e.g., thermal processing above 600°C, can be used to form the diffusion region 112.This allows a desired doping profile and depth to be achieved compared with process technologies that are limited in the heat balance due to a front-side metallization layer(s) that is already present when the thinned semiconductor wafers are processed, for example, on the second main surface 106. Figures 2A to 6B are schematic top and cross-sectional views to illustrate examples of beams 200. Each of the carriers 200 comprises a carrier body 202 and a bonding material 204 on a first main surface 208 of the carrier body 202. The carrier 200 is configured to be attached to a semiconductor wafer via the bonding material 204 by wafer bonding. Exemplary structural and functional details of the carrier body and the bonding material, as described with reference to the examples above, apply equally to the examples illustrated in the figures. Dopants can be integrated into the bonding material 204 of the support 200 and / or a semiconductor region of the support body 202 at the first major surface 208 of the support 200. Referring to the example illustrated in the schematic top view of Fig. 2A and the corresponding cross-sectional view of Fig. 2B, the bonding material 204 is arranged along an edge of the support body 202. The bonding material 204 can, for example, be formed as a ring on a semiconductor wafer extending along a circumference of the semiconductor wafer. In the example illustrated in Fig. 2A and Fig. 2B, the dopants can be integrated into a semiconductor region 210 of the support body 202 at the first major surface 208. For example, the dopants can be introduced into the support body 202 by one or more ion implantation and / or diffusion processes. Referring to the example illustrated in the schematic top view of Fig. 3A and the corresponding cross-sectional view of Fig. 3B, the bonding material 204 is arranged along the edge of the support body 202, similar to the example in Fig. 2A and Fig. 2B. However, the bonding material 204 is arranged as a sequence of ring segments 2041 separated from one another by channels 212. The dimensions of the channels 212 can be the same or different. Likewise, the dimensions of the ring segments 2041 of the bonding material 204 can be the same or different. The dimensions and arrangement of the ring segments 2041 and the channels 212 can be adjusted to achieve desired bonding and separation or detachment properties between the support 200 and a semiconductor wafer.For example, an etching solution can flow through the channels 212 to etch the bonding material 204 when the carrier 202 is separated from a semiconductor wafer. Referring to the example illustrated in the schematic top view of Fig. 4A and the schematic cross-sectional view of Fig. 4B, the bonding material 204 is arranged along an edge of the support body 202, similar to the example in Fig. 2A and Fig. 2B. However, the bonding material 204 is further arranged in the form of parallel strips extending along a first lateral direction x1 and a second lateral direction x2. Regions 214 laterally bounded by the strip-shaped bonding material 204 can, for example, correspond to the die regions of the semiconductor wafer. The strip-shaped bonding material 204 can, for example, be arranged in a kerf region of the semiconductor wafer. The kerf region is an area that is removed when the semiconductor wafer is separated into separate chips or dies by a decomposition process. Similar to the example in Fig.In the example illustrated in Fig. 3A, Fig. 3B, the bonding material 204 can also be in the form of ring segments 2041 with channels 212 between adjacent ring segments 2041, for example, in the example of Fig. 4A, Fig. 4B. Referring to the example illustrated in the schematic top view of Fig. 5A and the schematic cross-sectional view of Fig. 5B, the bonding material 204 is arranged in the form of parallel strips extending along a first lateral direction x1 and further along a second lateral direction x2. In some regions of the support 200, e.g., a first region 2141, the bonding material 204 is arranged as parallel strips extending in only one of the first lateral directions x1 and the second lateral direction x2. In some other regions, e.g., a second region 2142, the bonding material 204 is arranged as parallel strips extending along both the first lateral direction x1 and the second lateral direction x2. In other words, the bonding material 204 can be arranged in some regions of the support 200, e.g.,in the second area 2142, it may be arranged in the form of a grid and in other areas, e.g. the first area 2141, it may be arranged in the form of parallel strips extending along a lateral direction. The number, dimensions, and arrangement of grid-like and strip-like areas may differ from the exemplary and specific arrangement shown in Fig. 5A and Fig. 5B. For example, the first area 2141, compared with the grid-like arrangement of the bonding material 204 in the second area 2142, may enable improved carrier release via wet etching. Referring to the example illustrated in the schematic top view of Fig. 6A and the corresponding cross-sectional view of Fig. 6B, the bonding material 204 is arranged in the form of parallel strips extending along the first lateral direction x1 in the first region 2141 of the support 200. The bonding material 204 is further arranged as separate islands 2042 in the second region 2142 of the support 200. The islands 2042 can be bonded to a region of the semiconductor wafer where dies or chips are integrated, and a space between the islands 2042 can, for example, face an kerf region of the semiconductor wafer. In the example illustrated in the schematic top view of Fig. 6A and the corresponding cross-sectional view of Fig. 6B, the dopants are integrated into the bonding material 204. Thus, the bonding material 204 is configured as a doping source. The number, dimensions and arrangement of island-shaped and strip-shaped areas may differ from the exemplary and specific arrangement shown in Fig. 6A, Fig. 6B. Figures 7A to 9 are schematic cross-sectional views to illustrate examples of methods for manufacturing power semiconductor devices. Referring to the example illustrated in Fig. 7A, active device elements 108 are formed on a first main surface 104 of a semiconductor wafer 101. Edge termination elements 110 are formed and at least partially surround the active device elements 108 on the first main surface 104. Before forming a wiring area containing a metallization layer(s) above the first main surface 104, the thickness of the semiconductor wafer 101 is reduced on a second side 107 opposite the first main surface 104. A ring 114 on a circumference of the semiconductor wafer 101 can be excluded from material removal to increase the mechanical stability of the thinned semiconductor wafer 101. A bonding material 116 can be formed on the ring 114. Alternatively or additionally, a bonding material can also be formed, for example, on the support 200. The support 200 has a shape adapted to the thinned semiconductor wafer 101. Thus, the support has a reduced thickness around one circumference of the support body 202. The support 200 can contain dopants in a surface area 216. Referring to the example illustrated in Fig. 7B, the semiconductor wafer 101 is bonded to the support 200 via the second side 107 of the semiconductor wafer 101. In some examples, bonding the semiconductor wafer 101 to the support 200 results in direct contact between the surface portion 216 of the support 200 and the second side 107 of the semiconductor wafer 101. In other examples, the surface portion 216 of the support 200 does not directly contact the second side 107 of the semiconductor wafer 101 after bonding. Thus, after bonding, an empty space remains between the surface portion 216 of the support 200 and the second side 107 of the semiconductor wafer 101. In this case, the dopants can enter the empty space, i.e., a gas phase, from the support, and the semiconductor wafer 101 is doped via the gas phase on the second side 107. The doping process is schematically illustrated by arrows in Fig. 7B. Doping at high temperatures, e.g.,B. Temperatures above 600°C, is possible because above the first main surface 104 of the semiconductor wafer 101 no wiring area, i.e. no metallization layer(s), has yet formed. After the thermal process, the carrier 200 can remain on the second side 107 of the semiconductor wafer 101 to increase the mechanical stability during subsequent processing on the first main surface 104 of the semiconductor wafer 101, e.g. during the formation of the dielectric layer(s) and metallization layer(s) of a wiring area above the first main surface 104 of the semiconductor wafer 101. Referring to the examples illustrated in Fig. 7C and Fig. 7D, when the support 200 is no longer required on the second side 107 of the semiconductor wafer 101, e.g., before the formation of a metal layer on the second side 107 of the semiconductor wafer 101, the semiconductor wafer 101 is separated from the support 200. Depending on the requirements, a protective layer 118 can be formed over the first surface 104 of the semiconductor wafer 101, e.g., on a wiring area of ​​the semiconductor wafer 101. The protective layer 118 can, for example, protect the first surface 104 of the semiconductor wafer 101 from damage by an etching solution, e.g., fluorine-containing etching solutions, when the semiconductor wafer 101 is separated from the support 200 by etching the bonding material 116. After separation of the carrier 200, the carrier 200 can, for example, be reprocessed. The carrier 200 can be reused, for example, as a doping source if dopants are needed, e.g.They can be reintroduced into the surface part 216 by means of one or more ion implantation processes and / or diffusion processes. A region of the surface part 216 can be removed. Another example of fabricating a power semiconductor device is illustrated in the schematic cross-sectional views of Figures 8A to 8C. The example in Figures 8A to 8C does not require preparation of the carrier 200 or the semiconductor wafer 101 by means of masked material removal to leave a ring on the semiconductor wafer 101 to increase mechanical stability for subsequent processing. Compared to the example in Figures 7A to 7D, complexity can also be reduced when aligning the semiconductor wafer 101 with the carrier 200. Referring to the cross-sectional view of Fig. 8A, the semiconductor wafer 101 is attached to an auxiliary carrier 300 via the first main surface 104 before a wiring area containing a metallization layer(s) is formed above the first main surface 104 of the semiconductor wafer 101. Active device elements are formed on the first main surface 104 of the semiconductor wafer 101. Edge termination regions 110 are formed and at least partially surround the active device elements 108 on the first main surface 104. The thickness of the semiconductor wafer 101 is reduced on a second side 107 opposite the first main surface 104. During the thinning process of the semiconductor wafer 101, the auxiliary carrier 300 provides mechanical support for the workpiece. In the carrier 200, the dopants are formed in the surface region 216. The dopants can be introduced into the surface region 216, for example, by one or more ion implantation processes. If several dopants, e.g., donors and acceptors and / or dopants with different diffusion coefficients such as boron and selenium for IGBTs or phosphorus and selenium for diodes, are implanted, the fabrication process enables the formation of functionally distinct semiconductor regions, such as back-emitter regions and field-stop regions, by means of a common processing step, i.e., a common diffusion step. For example, if field-stop regions are formed using selenium, low energy levels of selenium in the silicon band gap can further improve the electrical characteristics of the power semiconductor devices due to thermal activation.In this way, for example, electrical characteristics such as hot leakage current, smoothness and / or short-circuit resistance can be improved. The bonding material 204 is formed on the first main surface 208. For example, the bonding material 204 can correspond to a hard mask that was previously used when the dopants were introduced into the surface part 216 of the support 200. Details regarding a bonding material(s) and bonding techniques described with reference to the examples above apply equally. After bonding the semiconductor wafer 101 to the support 200, the auxiliary support 300 is removed and the dopants are introduced from the surface part 216 of the support 200 into the semiconductor wafer 101, for example by a diffusion process as described with reference to the example illustrated in Fig. 7A to 7D. After and before forming one or more metallization layers on the second side 107 of the semiconductor wafer 101, a wiring area can be formed above the first main surface 104 of the semiconductor wafer. A mechanical support, e.g., a support ring 120, can be formed above the first main surface 104 of the semiconductor wafer 101 to provide mechanical stability. The support ring 120 provides mechanical support for further processing of the semiconductor wafer, e.g., for processing the second side 107 of the semiconductor wafer 101 once the carrier 200 has been removed. Further processing to finalize the power semiconductor devices, e.g., cutting the semiconductor wafer 101 into dies or chips and chip packaging, may follow. In the examples described above, dopants can be introduced into the surface portion 216 of the support 200 by one or more masked or unmasked ion implantation processes. This makes it possible to create different doping sources, e.g., doping sources that differ in the number and / or type and / or concentration of dopants across the first main surface 208 of the support 200. This allows semiconductor regions with different functionalities to be formed on the second side 107 of the semiconductor wafer 100 by means of a common diffusion process.For example, a common diffusion process as described in the examples above can be used to form doped regions for high dynamic robustness (HDR) in a border region of the IGBT dies, backside emitter regions, structured (p+)-doped strips for short-circuit improvement, or some backside emitter regions with high doping concentration to improve smoothness. When forming power semiconductor diodes, life-consuming processes associated with platinum can pose a challenge due to strong platinum diffusion. Platinum diffusion into the interior of the support 200 reduces the platinum concentration available for doping the semiconductor wafer 101. The support 200 illustrated in the cross-sectional view of Fig. 9 can prevent dopants from diffusing into its interior. The support 200 contains a semiconductor layer 218 over the substrate 202, for example, over a front and / or back face of the substrate 202. The dopants are contained within the semiconductor layer 218, and the bonding material 204 is arranged on the semiconductor layer 218. The support 200 also includes a diffusion barrier 220 located between the semiconductor layer 218 and the support 200.The diffusion barrier 220 prevents the dopants in the semiconductor layer 218 from diffusing into the interior of the substrate 202. In other words, the dopants can contribute to doping the semiconductor wafer 101 instead of diffusing into the interior of the substrate 202. For example, the diffusion barrier 220 can be made of SiC. The semiconductor layer 218 can be, for example, a polycrystalline silicon layer. The substrate 202 can also be made of SiC or polycrystalline SiC, for example.

Claims

Support (200) comprising: a support body (202); a bonding material (204) on a first main surface (208) of the support body (202), wherein the support (200) is configured to be attached to a semiconductor wafer via the bonding material (204) by wafer bonding, wherein the support body (202) contains one or more of silicon, boron phosphosilicate glass, borosilicate glass, phosphosilicate glass, boron nitride, polycrystalline silicon, silicon carbide; and dopants integrated in a first part (216) of the support (200) on the first main surface (208), wherein the dopants are configured to eject from the support (200) by thermal processing and are configured to form an n-type or p-type doping in the semiconductor wafer. Carrier (200) according to the preceding claim, wherein the carrier (200) is disc-shaped with a diameter of 200 mm or larger. Carrier (200) according to one of the two preceding claims, wherein the dopants are contained in the bonding material (204). Carrier (200) according to one of the three preceding claims, wherein the dopants are contained in a semiconductor region of the carrier body (202) at the first main surface (208). Carrier (200) according to one of the four preceding claims, wherein the dopants are introduced by at least one ion implantation step or diffusion step. Carrier (200) according to one of the five preceding claims, wherein an arrangement of the bonding material (204) on the first main surface (208) of the carrier body (202) comprises one or more rings or ring segments along a circumference of the carrier body (202), a structure of regularly arranged islands, a plurality of parallel arranged strips. Carrier (200) according to one of the six preceding claims, further comprising: a semiconductor layer (218) over the carrier body (202), wherein the dopants are contained in the semiconductor layer (218) and the bonding material (204) is arranged on the semiconductor layer (218); and a diffusion barrier (220) arranged between the semiconductor layer (218) and the carrier body (202). A method for producing a vertical power semiconductor device (100), comprising: forming active device elements (108) in a semiconductor wafer (101) at a first main surface (104) of the semiconductor wafer (101); forming edge termination elements (110) that at least partially surround the active device elements (108) at the first main surface (104); reducing the thickness of the semiconductor wafer (101) at a second side (107) opposite the first main surface (104); bonding the semiconductor wafer (101) to a support (200) via the second side (107); and introducing dopants from the support (200) into the semiconductor wafer (101) through a second main surface (106) of the semiconductor wafer (101) at the second side (107). Method according to the preceding claim, wherein the thickness of the semiconductor wafer (101) is reduced by removing material of the semiconductor wafer (101) from the second side (107) of the semiconductor wafer (101). Method according to claim 8, wherein the thickness of the semiconductor wafer (101) is reduced by separating the semiconductor wafer (101) into a first part and a second part by means of a wafer splitting process. A method according to any one of the three preceding claims, wherein the vertical power semiconductor device (100) is a vertical power semiconductor device (100) comprising: a semiconductor body (102) having a first main surface (104) and a second main surface (106) opposite the first main surface (104), wherein a thickness (d) of the semiconductor body (102) between the first main surface (104) and the second main surface (106) ranges from 40 µm to 200 µm; active device elements (108) in the semiconductor body (102) at the first main surface (104); edge termination elements (110) that at least partially surround the active device elements (108) at the first main surface (104);and a diffusion region (112) extending from the second main surface (106) into the semiconductor body (102), wherein a doping concentration profile (c) of the diffusion region (112) decreases over a vertical distance (Δy) ranging from 1 µm to 5 µm from a peak concentration Ns at the second main surface (106) to a concentration Ns / e, where e is Euler's number; and the diffusion region (112) is formed by introducing the dopants from the support (200) into the semiconductor wafer (101). Method according to one of the four preceding claims, wherein the carrier (200) is a carrier (200) according to one of claims 1 to 7. Method according to one of the five preceding claims, further comprising: separating the semiconductor wafer (101) from the support (200) by means of at least one etching process which removes at least part of a bonding material (204). Method according to one of the six preceding claims, wherein the thickness of the semiconductor wafer (101) is reduced in a central region of the semiconductor wafer (101), while maintaining a thickness of a ring of the semiconductor wafer (101) at a circumference of the semiconductor wafer. Method according to one of the seven preceding claims, further comprising: attaching a mechanical support element (120) over the first main surface (104) of the semiconductor wafer (101). A method for manufacturing a vertical power semiconductor device (101), comprising: forming active device elements (108) in a semiconductor wafer (101) at a first main surface (104) of the semiconductor wafer (101); then reducing the thickness of the semiconductor wafer (101) at a second side (107) opposite the first main surface (104); then bonding the semiconductor wafer (101) via the second side (107) to the support (200) according to any one of claims 1 to 7; and then subjecting the semiconductor wafer (101) to a heat treatment of at least 600°C. A method for manufacturing a vertical power semiconductor device (100), comprising: forming active device elements (108) in a semiconductor wafer (101) at a first main surface (104) of the semiconductor wafer (101); reducing the thickness of the semiconductor wafer (101) at a second side (107) opposite the first main surface (104); then bonding the semiconductor wafer (101) via the second side (107) to the support (200) according to any one of claims 1 to 7; and then applying a metallization layer to the first main surface (104) before removing the support (200). Method according to one of the two preceding claims, wherein the diameter of the semiconductor wafer (101) is 200 mm or greater.

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