Parametric photonic unit library generation system and method based on adiabatic performance classification mapping
By using a thermal performance hierarchical mapping mechanism, the problem of poor device design flexibility in the photonic PDK library is solved, enabling efficient automatic optimization of photonic devices, saving chip area and supporting intuitive performance-length decisions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANTONG UNIV
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-30
AI Technical Summary
The existing photonic PDK library has poor device design flexibility and cannot make precise trade-offs between performance and area, resulting in chip design waste or functional failure. Designers cannot intuitively understand the changes in device length required for performance improvement.
By establishing a thermal performance graded mapping mechanism, and using a thermal performance graded definition interface, a local constraint dynamic mapping engine, and a reverse geometry synthesizer, parameterized photonic units that meet the user's efficiency level are generated, thereby achieving automatic optimization of device length.
It enables a shift in photonic device design from geometry-driven to specification-driven, saving chip area, improving design efficiency, and generating reliable and non-redundant devices that support intuitive performance-length trade-offs for users.
Smart Images
Figure CN122307906A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated optoelectronics technology, specifically relating to a parameterized photonic unit library generation system and method based on thermal performance hierarchical mapping. Background Technology
[0002] In the industrial design process of integrated photonic chips, designers typically rely on process design kits (PDKs) provided by foundries. In existing PDKs, thermally insulating devices (such as waveguide tapers and couplers) are usually presented as fixed cells with fixed geometries. For example, a PDK might only provide a standard waveguide taper with a length of 20 micrometers.
[0003] Question 1 (Over-design): If the user's link is not sensitive to loss (e.g., only used for monitoring), using this 20-micron device will result in unnecessary waste of chip area.
[0004] Question 2 (Underdesign): If the user requires extremely high single-pass efficiency (e.g., >99.9% in quantum computing), this standard unit may not meet the requirements, causing the entire chip to malfunction.
[0005] Question 3 (Black Box): Designers cannot intuitively know "how much the device length needs to be increased if the efficiency requirement is increased by 1%". The current process lacks a direct mapping mechanism between "performance and size". Summary of the Invention
[0006] This invention aims to address the problems of poor flexibility and inability to precisely balance performance and area in existing photonic PDK libraries. By establishing a dynamic mapping mechanism between "thermal insulation level (Tier)" and "maximum intermodal coupling loss fraction (MMCLF)," a system is provided that can automatically synthesize the optimally sized parameterized photonic cell (PCell) based on the user-specified efficiency level.
[0007] The technical solution adopted in this invention is as follows:
[0008] A parameterized photonic unit library generation system based on thermal performance hierarchical mapping includes the following core modules:
[0009] Module 1: Tier Definition Interface for Thermal Insulation Performance
[0010] The system can preset or allow users to define their own discretized performance tiers. Unlike traditional geometric parameter inputs, this interface accepts functional parameters:
[0011] (1) Tier I (Acceptable): Target efficiency η ≥ 90%, suitable for monitoring ports or short-distance interconnection;
[0012] (2) Tier II (Good): Target efficiency η ≥ 95%, suitable for conventional on-chip routing;
[0013] (3) Tier III (Excellent): Target efficiency η ≥ 99%, suitable for resonant cavity coupled or cascaded systems.
[0014] (4) Custom Tier: Users can input any floating-point number (such as 99.5%) as the target.
[0015] Module 2: Local Constraint Mapping Engine
[0016] This engine is responsible for setting the global performance target η. target Translated as local geometric constraints.
[0017] (1) Core Algorithm: The system has a built-in data table or calculation formula based on the inter-module coupling physical model. Based on the input η... target The maximum permissible intermodal coupling loss fraction (MMCLF) for each micro-segment along the light propagation direction is calculated.
[0018] (2) Non-uniform distribution: For multimode or complex waveguide systems, the engine will automatically identify “spectrally sensitive areas” (such as avoiding cross points) and automatically adjust the local constraint weights of the area to ensure that the global efficiency meets the standards.
[0019] Module 3: Inverse Geometric Synthesizer
[0020] This is the core computational unit of the system. It does not perform iterative optimization, but instead executes deterministic reverse construction.
[0021] (1) Input: Initial waveguide width W start Termination waveguide width W end And the MMCLF constraint values output by module two.
[0022] (2) Database call: The system pre-stores the "MMCLF-length" dependency library of the standard waveguide cross section under the process node (obtained through pre-full-wave simulation scan, i.e. the lower envelope of the MCTE oscillation curve).
[0023] (3) Execution: The synthesizer directly solves the minimum physical length L required for each micro-segment by looking up tables and interpolating.min = f -1 (MMCLF target ), and then splice all the micro-segments together to generate GDSII layout data.
[0024] Module 4: Trade-off Visualizer
[0025] Before generating the layout, the system displays a "efficiency-length" trade-off curve to the user.
[0026] Users can visually see that increasing efficiency from 99% to 99.5% will increase device length from X μm to Y μm. This allows designers to make informed PPA (performance, power, area) decisions.
[0027] The parameterized photonic unit library generation system and method based on thermal performance hierarchical mapping described in this invention, compared with the prior art, has the following technical advantages:
[0028] (1) Innovation of the PDK paradigm: It changes the design authority of photonic devices from "geometry-driven" to "specification-driven". Designers do not need to care about what the device looks like, but only about what performance is required. The system automatically ensures that the generated device is the physical limit size under that performance.
[0029] (2) Zero waste of resources: Traditional conservative designs often reserve 20%-50% length margin to cope with process fluctuations. The device generated by this system based on the "boundary saturation" algorithm has no redundant length while meeting Tier requirements, which greatly saves expensive chip area.
[0030] (3) Accelerated design convergence: This avoids designers from repeatedly performing EM simulations to verify efficiency. Since the generated PCell is built based on a pre-verified physical envelope, its performance is "correct-by-construction". Attached Figure Description
[0031] Figure 1 This is a system architecture diagram of an embodiment of the present invention. Detailed Implementation
[0032] The present invention will be further explained in detail below with reference to the accompanying drawings, so that those skilled in the art can better understand and implement the present invention. However, the following examples are only used to explain the present invention and are not intended to limit the present invention.
[0033] A parameterized photonic unit library generation system based on thermal performance hierarchical mapping includes the following core modules:
[0034] Module 1: Tier Definition Interface for Thermal Insulation Performance
[0035] The system can preset or allow users to define their own discretized performance tiers. Unlike traditional geometric parameter inputs, this interface accepts functional parameters:
[0036] (1) Tier I (Acceptable): Target efficiency η ≥ 90%, suitable for monitoring ports or short-distance interconnection;
[0037] (2) Tier II (Good): Target efficiency η ≥ 95%, suitable for conventional on-chip routing;
[0038] (3) Tier III (Excellent): Target efficiency η ≥ 99%, suitable for resonant cavity coupled or cascaded systems.
[0039] (4) Custom Tier: Users can input any floating-point number (such as 99.5%) as the target.
[0040] Module 2: Local Constraint Mapping Engine
[0041] This engine is responsible for setting the global performance target η. target Translated as local geometric constraints.
[0042] (1) Core Algorithm: The system has a built-in data table or calculation formula based on the inter-module coupling physical model. Based on the input η... target The maximum permissible intermodal coupling loss fraction (MMCLF) for each micro-segment along the light propagation direction is calculated.
[0043] (2) Non-uniform distribution: For multimode or complex waveguide systems, the engine will automatically identify “spectrally sensitive areas” (such as avoiding cross points) and automatically adjust the local constraint weights of the area to ensure that the global efficiency meets the standards.
[0044] Module 3: Inverse Geometric Synthesizer
[0045] This is the core computational unit of the system. It does not perform iterative optimization, but instead executes deterministic reverse construction.
[0046] (1) Input: Initial waveguide width W start Termination waveguide width W end And the MMCLF constraint values output by module two.
[0047] (2) Database call: The system pre-stores the "MMCLF-length" dependency library of the standard waveguide cross section under the process node (obtained through pre-full-wave simulation scan, i.e. the lower envelope of the MCTE oscillation curve).
[0048] (3) Execution: The synthesizer directly solves the minimum physical length L required for each micro-segment by looking up tables and interpolating. min = f -1 (MMCLF target ), and then splice all the micro-segments together to generate GDSII layout data.
[0049] Module 4: Trade-off Visualizer
[0050] Before generating the layout, the system displays a "efficiency-length" trade-off curve to the user.
[0051] Users can visually see that increasing efficiency from 99% to 99.5% will increase device length from X μm to Y μm. This allows designers to make informed PPA (performance, power, area) decisions.
[0052] like Figure 1 The diagram shown is an overall architecture diagram of the system of the present invention, illustrating the data flow from "user input Tier" to "GDSII output".
[0053] In practical implementation, a "smart thermal insulation tape library" was developed for a specific 130nm silicon photonics process node.
[0054] 1. Preprocessing stage (database construction):
[0055] (1) For the standard waveguide of this process (220nm top silicon), the width range is selected as 0.4 μm - 2.0 μm.
[0056] (2) Divide the range into 100 micro-segments.
[0057] (3) Use FDTD to perform a length scan on each micro-segment, extract the envelope data under MMCLF, and store it in the system's binary database file (.db). This process is completed in one go and does not need to be repeated on the user side.
[0058] 2. User Invocation Phase:
[0059] (1) The user calls the PCell in layout design software (such as Cadence Virtuoso or KLayout).
[0060] (2) Parameter settings: Input Width In= 0.5 μm, Width Out = 2.0 μm, Target Efficiency =0.99 (Tier III).
[0061] (3) System response:
[0062] ① The engine queries the database to find the MMCLF threshold (e.g., 0.005) corresponding to Tier II.
[0063] ②The engine performs a reverse lookup on 100 micro-segments to calculate the length of each segment.
[0064] ③ The system found that the length of the 0.5 μm - 0.6 μm region (single-mode region) is extremely short, while the length of the 0.8 μm - 0.9 μm region (multi-mode interference region) needs to be significantly increased.
[0065] ④ The system automatically generates a multi-segment polygonal profile with a total length of 25.4 μm.
[0066] (4) Comparison: If the user changes the parameter to Target Efficiency = 0.90 (Tier I), the system updates the layout in real time, the total length is reduced to 8.2 μm, and the outline becomes steeper.
[0067] 3. Chip fabrication verification:
[0068] Tests show that the system-generated Tier III devices have a measured efficiency of 99.1%, and the Tier I devices have a measured efficiency of 90.5%. Both accurately hit the target, and compared to traditional fixed cells, the Tier I version saves 68% of the area.
[0069] The specific implementation schemes described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific implementation schemes of the present invention and are not intended to limit the scope of the present invention. Any equivalent changes and modifications made by those skilled in the art without departing from the concept and principles of the present invention should fall within the scope of protection of the present invention.
Claims
1. A parameterized photonic unit library generation system based on thermal performance hierarchical mapping, characterized in that, It includes the following modules connected in sequence: Module 1: Thermal performance classification definition interface, Module 2: Local constraint dynamic mapping engine, Module 3: Inverse geometry synthesizer, and Module 4: Visual trade-off analyzer; Module 1: Insulation performance grading definition interface, used for system presets or user-defined discrete performance tiers; Module 2: Local Constraint Dynamic Mapping Engine, used to map the global performance target η target Translated as local geometric constraints; Module 3: Reverse Geometry Synthesizer, used to perform deterministic reverse construction; Module 4: Visual Trade-off Analyzer, which displays the efficiency-length trade-off curve to the user before generating the layout.
2. The method for generating the system according to claim 1, characterized in that, Specifically, the following steps are included: S1. The system presets or allows users to customize discrete performance tiers; S2, Set the global performance target η target Translated as local geometric constraints; S3, Perform deterministic reverse construction; S4. Before generating the layout, the system displays an efficiency-length trade-off curve to the user.
3. The generation method according to claim 2, characterized in that, In S1, the performance tiers include: Tier I, with a target efficiency η ≥ 90%, suitable for monitoring ports or short-distance interconnects; Tier II, with a target efficiency η ≥ 95%, suitable for conventional on-chip routing; Tier III, with a target efficiency η ≥ 99%, suitable for resonant cavity coupling or cascaded systems; and a custom Tier, where the user can input any floating-point number as the target.
4. The generation method according to claim 3, characterized in that, In S2, the system has a built-in data table or calculation formula based on the inter-module coupling physical model; according to the input η target The engine calculates the maximum permissible intermode coupling loss fraction (MMCLF) for each micro-segment along the light propagation direction. For multimode or complex waveguide systems, the engine automatically identifies spectrally sensitive regions and automatically adjusts the local constraint weights in those regions to ensure that the global efficiency meets the target.
5. The generation method according to claim 4, characterized in that, S3 includes: input, initial waveguide width W start Termination waveguide width W end The system retrieves the MMCLF constraint values output from Module 2; it also retrieves the database access information; the system pre-stores the MMCLF-length dependency library for the standard waveguide cross-section at this process node, obtained through pre-simulated full-wave scanning, i.e., the lower envelope of the MCTE oscillation curve; the synthesizer directly solves for the minimum physical length L required for each micro-segment through table lookup and interpolation. min = f -1 (MMCLF target ), and then splice all the micro-segments together to generate GDSII layout data.