An IEC61131-3 controller extension module based on AnyControl

Abstract

This invention relates to the field of industrial automation control technology, specifically an AnyControl-based IEC61131-3 controller extension module. It includes a four-layer local extended control architecture consisting of an AnyControl Runtime main control module, an extended communication protocol module, an FPGA communication module, and extension modules. The DI / DO, AI / AO, CAN, and UART interfaces are encapsulated as standardized configuration devices. Standard data frames are designed, including frame header identifiers, address fields, data length, valid data, and CRC16 checksums. A high-speed FPGA data transmission channel is built based on the SPI protocol and LVDS interface, with a transmission rate of no less than 100Mbps, supporting up to 32 cascaded extension modules. Configuration device integration and automatic variable mapping are achieved using XML description files, enabling seamless access to extension modules. Simultaneously, the extended CAN and UART interfaces are mapped as virtual interfaces for localized adaptation. This invention offers high module compatibility, stable data transmission, user-friendly operation, and strong system maintainability and scalability.

Description

Technical Field

[0001] This invention relates to the field of industrial automation control technology, and in particular to an IEC61131-3 controller extension module based on AnyControl. Background Technology

[0002] In industrial automation control systems, the IEC61131-3 controller serves as a core control unit and is widely used in various industrial scenarios. As the functional requirements of industrial sites continue to evolve, the interface resources of a single controller are often insufficient to meet the access needs of multiple devices and signals. Therefore, it is necessary to expand the types and number of interfaces through local expansion modules.

[0003] Existing local expansion solutions for IEC61131-3 controllers mostly adopt customized communication protocols and hard-coded development methods, which have the following problems: First, the expansion modules have poor compatibility; different types of expansion modules require the development of dedicated drivers, which results in a long development cycle. Secondly, the user operation is complex, requiring manual configuration of communication parameters and variable mapping relationships, which places high demands on the professional skills of the operators. Third, the data transmission stability is insufficient, lacking standardized frame formats and verification mechanisms, making it susceptible to data loss due to interference in industrial settings. Fourth, the system has poor maintainability. Upgrading or replacing modules requires modifying the program code, which is not conducive to later maintenance.

[0004] However, AnyControl, as a programmable system conforming to the IEC 61131-3 international standard, consists of upper-level configuration software development tools and runtime software, supporting graphical configuration and library file integration, thus providing a technical foundation for solving the aforementioned problems. Based on this, this invention proposes a design scheme for an IEC 61131-3 controller extension module based on AnyControl. Summary of the Invention

[0005] The purpose of this invention is to overcome the problems of the prior art and provide an IEC61131-3 controller expansion module based on AnyControl to solve the problems of poor compatibility, complex operation, insufficient stability and poor maintainability of existing expansion solutions, and to achieve rapid integration, seamless access and stable operation of the expansion module.

[0006] The above objectives are achieved through the following technical solutions: An IEC61131-3 controller expansion module based on AnyControl includes an AnyControl Runtime main control module, an extended communication protocol module, an FPGA communication module, and an expansion module; The AnyControl Runtime main control module is the core scheduling unit, which encapsulates the DI / DO, AI / AO, CAN, and UART interface functions into a standardized configuration device; The extended communication protocol module is used to assemble user data into standard data frames and complete data frame parsing, thereby realizing standardized encapsulation and link transmission of user data. The FPGA communication module constructs a high-speed data transmission channel based on the SPI protocol and LVDS interface, realizing bidirectional data interaction between the AnyControl Runtime main control module and each of the expansion modules, as well as multi-module link cascading and data distribution; The configuration device is integrated into the AnyControl host computer configuration software through an XML description file, realizing automatic mapping of variables of the physical interface between the configuration device and the expansion module. Users can complete the seamless control and data reading and writing of the expansion module by accessing the mapped variables.

[0007] Furthermore, in the standardized configuration device, the DI / DO interface uses Boolean data, and the AI / AO interface uses 16-bit integer data; the CAN interface baud rate is adjustable from 250Kbps to 1Mbps, and the UART interface baud rate is adjustable from 1200bps to 115200bps, and it is configured with a fault-tolerant processing mechanism for data filtering and timeout retransmission.

[0008] Furthermore, the standard data frame includes a 2-byte frame header, a 1-byte address field, a 2-byte data length, variable-length valid data, and a 2-byte CRC16 checksum. The frame header is fixed at 0xAA55, the address field has a value of 0x01 to 0x20, which is used to distinguish up to 32 extension modules. The maximum length of the valid data is 128 bytes and it supports packet transmission.

[0009] Furthermore, the FPGA communication module has a data transmission rate of no less than 100Mbps, integrates data transmission verification and retransmission mechanisms, and has a data transmission error rate of less than 0.001%; ​​the LVDS interface conforms to the ANSI / TIA / EIA-644 standard and has a maximum transmission distance of 10 meters.

[0010] Furthermore, the FPGA communication module uses a Unisoc FPGA chip, integrating an SPI interface controller and an LVDS transceiver, with a reserved interrupt pin connected to the controller body for transmitting interrupt signals of data verification anomalies; the SPI interface operates in Mode 0, with a clock frequency of 10MHz, and uses full-duplex communication.

[0011] Furthermore, the XML description file includes device identifier, interface type, variable name, data type, memory address mapping, and device version fields, which are used for automatic parsing, device loading, and identity matching by the host computer configuration software. An example of an XML description file includes... <deviceidentification>and <parameter>Node definition.

[0012] Furthermore, the automatic mapping of variables is as follows: the host computer configuration software maps the configuration device logical variables to the controller soft element address through the XML description file. CH0 to CH15 of the 16-channel DI module correspond to soft elements %IX116.0 to %IX117.7. Users can read and write the physical interface data of the expansion module by accessing the soft elements through the configuration interface or ST language.

[0013] Furthermore, the expansion module includes a DI / DO digital quantity module, an AI / AO analog quantity module, a CAN communication module, and a UART serial port module. Specifically, it includes a 16-channel DI / DO module (16X / 16Y), a 4-channel AI / AO module (E4AD / E4DA), a CAN communication module (E1CAN), and a multi-serial port module (E2COM24). Each module is plug-and-play via the LVDS standardized interface.

[0014] Furthermore, the CAN and UART physical interfaces of the expansion module are mapped to the virtual CAN port and virtual COM port of the AnyControl Runtime main control module, reuse the platform's native CANBus / Modbus device library, support the CAN_Send and Modbus_Read standard function block calls, and realize consistent and seamless access between the expansion interface and the controller body interface.

[0015] Furthermore, after the system is powered on, the AnyControl Runtime main control module automatically scans the link extension module, matches the XML device identifier, and generates the device topology; when a data transmission verification error occurs, the FPGA triggers an interrupt through the interrupt pin, the Runtime responds to the interrupt and initiates data retransmission to ensure the integrity of data transmission.

[0016] This invention provides an IEC61131-3 controller extension module based on AnyControl. By building a four-layer control architecture, encapsulating standardized configuration equipment, designing standard data frames and a high-speed FPGA transmission channel, and relying on XML to achieve automatic variable mapping, it improves the compatibility of the extension module, simplifies user operation, stabilizes data transmission, and enhances system maintainability and scalability. Compared with existing technologies, it has the following advantages: 1. Simplify the development process for local expansion of IEC61131-3 controllers, improve the compatibility of expansion modules, and support plug-and-play functionality for multiple types of modules; 2. Standardized data frames and high-speed FPGA transmission improve data transmission stability, with a bit error rate of less than 0.001%; 3. Automatic variable mapping and seamless access reduce the difficulty of user operation, eliminating the need to concern oneself with underlying communication details; 4. Enhanced system maintainability and scalability; module upgrades and replacements do not require modification of the source code; supports up to 32 cascaded modules. Attached Figure Description

[0017] Figure 1 This is a general design block diagram of an IEC61131-3 controller extension module based on AnyControl as described in this invention; Figure 2 This is the configuration design interface for the expansion module in the AnyControl-based IEC61131-3 controller expansion module of the present invention. It can be added to the host computer configuration with one click by scanning. Figure 3 This is a design block diagram of the module communication interface in the AnyControl-based IEC61131-3 controller extension module described in this invention. Figure 4 This invention describes a service data access method for each module in an IEC61131-3 controller extension module based on AnyControl. Figure 5 This is a design block diagram of the input and output data flow of each module in the AnyControl-based IEC61131-3 controller extension module described in this invention. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0019] like Figures 1-3 As shown, this solution provides an IEC61131-3 controller expansion module based on AnyControl, constructing a control architecture consisting of an AnyControl Runtime main control module, an extended communication protocol module, an FPGA communication module, and expansion modules. The specific steps of the design solution are as follows: S1: Control Architecture Setup: The core control architecture is built based on the AnyControl platform, clarifying the functional positioning and interaction logic of each module. Specifically, the AnyControl Runtime main control module is responsible for global scheduling, configuration device management, and user data processing; the extended communication protocol module is responsible for data frame assembly and parsing; the FPGA communication module is responsible for physical layer data transmission; and the extended modules are responsible for executing specific I / O acquisition, communication interaction, and other functions. All modules achieve data interoperability through standardized interfaces. S2: Configuration Device Encapsulation: In the AnyControl Runtime main control module, commonly used interface functions such as DI / DO, AI / AO, CAN, and UART are encapsulated into standardized configuration devices. Specifically, a unified input / output parameter format is defined for different interface types. For example, the DI / DO interface uses Boolean data, and the AI / AO interface uses 16-bit integer data. The data transmission rate is configured to adapt to industrial field requirements; the CAN interface supports adjustable speeds from 250Kbps to 1Mbps, and the UART interface supports adjustable speeds from 1200bps to 115200bps. Fault-tolerant processing mechanisms such as data filtering and timeout retransmission are added to improve data reliability. S3: Communication Protocol Module Creation: Develop an extended communication protocol module, design a standardized data frame format, and complete data frame assembly and parsing. Specifically, the standardized data frame format includes a frame header (2 bytes, fixed identifier 0xAA / 0x55), an address field (1 byte, distinguishing different extended modules), a data length (2 bytes), valid data (variable length, maximum 128 bytes, supports packet transmission), and a checksum (2 bytes, CRC16 check). After receiving user data from the communication protocol module, the module assembles data frames according to the above format. After receiving data frames uploaded by the FPGA communication module, the communication protocol module parses the valid data and transmits it to the AnyControl Runtime main control module. S4: FPGA Communication Module Configuration: Implements SPI and LVDS encoding conversion, constructs a high-speed data transmission channel, and supports multi-module cascading and data distribution. Specifically, the SPI protocol is responsible for high-speed data interaction between the main control module and the FPGA, while the LVDS interface is responsible for link transmission between the FPGA and expansion modules. The FPGA communication module is configured to support multi-extension module cascading, achieving precise data distribution through the address field; data transmission timing is optimized to ensure a transmission rate of no less than 100Mbps; when a checksum error is detected, the main control chip is notified via an interrupt pin, and the main control chip uses the interrupt to implement retransmission and other functions, ensuring a bit error rate of less than 0.001%. S5: XML Description File Creation: Write an XML description file to define the attributes of the configured device, variable mapping rules, and module relationships; specifically, fully define the attribute information of the configured device, including device identifier, interface type, supported parameter range, etc.; clarify the variable mapping rules to associate the logical variables of the configured device with the physical interfaces of the extension modules; and mark the module relationships to ensure the address uniqueness when multiple extension modules are cascaded. S6: Automatic Variable Mapping Configuration: Import an XML description file to achieve automatic mapping between logical variables and physical interfaces, enabling seamless user access. Specifically, import the XML description file into the AnyControl host computer configuration software. The software automatically parses the file content, loads the configured device, and completes the mapping between logical variables and the physical interfaces of the expansion modules. Users only need to access the mapped logical variables (such as channels Ch0, Ch1, etc.) in the configuration software to control and read / write data to the corresponding interfaces of the expansion modules, without needing to manually configure communication parameters or write low-level driver code, achieving seamless access. S7: Localized Access to Module Communication Interfaces: Create virtual interfaces, reuse native device libraries, and achieve consistent use of extended interfaces and main interfaces; specifically, a PLC typically only has a few COM / CAN ports, mainly due to limitations in the number of PLC chip pins or cost, which cannot meet the needs of scenarios requiring a large number of COM / CAN ports. By modifying the chip's underlying driver and the linkage between the extended communication protocol module and the AnyControl Runtime module, it is possible to achieve... Figure 3 The seamless binding effect shown. With the help of the CAN / COM device library that comes with the AnyControl platform, customers can use the 232 / 485 on the E2COM24 module and the CAN port on the E1CAN just like using the main CANBus / Modbus device, supporting all control methods of CANBus / Modbus devices on AnyControl; S8: System Integration and Testing: Integrate all modules into the Runtime environment to complete functional, stability, and anti-interference tests; specifically, compile the extension module communication protocol module and FPGA communication module into library files, integrate them into the AnyControl Runtime environment through the AnyControl Runtime SDK development package, and compile to generate executable programs; set up a test environment, connect different types of extension modules such as DI / DO digital quantity modules, AI / AO analog quantity modules, and CAN communication modules, and test data transmission stability, module compatibility, and user-unobstructed access functionality; conduct anti-interference tests for common industrial scenarios such as electromagnetic interference and power fluctuations to ensure stable system operation.

[0020] I. Hardware Environment Setup The hardware system in this embodiment consists of the AnyControl controller body, FPGA communication module, expansion module, and host computer, with the following specific configuration: 1. AnyControl controller body: It adopts an industrial controller that supports the IEC61131-3 standard, has a built-in AnyControl Runtime operating environment, provides an SPI interface for interaction with the FPGA communication module, and supports XML description file parsing and variable mapping functions; 2. FPGA Communication Module: Adopts Unisoc FPGA chip, integrates SPI interface controller and LVDS transceiver, realizes bidirectional conversion between SPI protocol and LVDS signal. The module reserves interrupt pin to connect to the controller body for transmitting interrupt signals such as data verification exceptions. 3. Expansion Modules: Various types of standard modules were selected for testing, including a 16-channel DI / DO digital input module (16X / 16Y), a 4-channel AI / AO analog input module (E4AD / E4DA), a CAN communication expansion module (E1CAN), and a multi-serial port expansion module (E2COM24). Each module is equipped with an LVDS interface and standardized address encoding. 4. Host computer: Install AnyControl configuration software, which supports graphical configuration, device scanning and variable access functions, and is used to realize the visual configuration and control of extended modules.

[0021] like Figure 1 As shown, the connection relationship of each hardware module is as follows: the AnyControl controller body establishes a data link with the FPGA communication module through the SPI interface, the FPGA communication module realizes the cascading with multiple expansion modules through the LVDS bus, and the host computer connects to the controller body through Ethernet to complete the configuration and data interaction.

[0022] II. Software Module Implementation (a) Control architecture initialization (corresponding to step S1 above) like Figure 1 As shown, the software deployment of a four-layer control architecture is completed based on the AnyControl platform: 1. AnyControl Runtime Main Control Module: Loads the system's core scheduling components, configures task priorities, sets data transmission tasks to the highest priority (1ms cycle), and sets XML parsing and device initialization tasks to the secondary priority (event-triggered); This module complies with the IEC61131-3 international standard, supports graphical configuration development and integration with underlying library files, and has task scheduling, data caching, and exception handling functions; 2. Extended Communication Protocol Module: Integrated into the Runtime environment as an independent function library, this module registers data frame assembly and parsing callback functions, and establishes a data flow interface with the FPGA communication module. This module supports address differentiation among multiple extended modules, and achieves precise data distribution through the address field in the frame header identifier. It supports a maximum of 32 cascaded extended modules. 3. FPGA Communication Module: The SPI-LVDS conversion logic and data distribution control logic are written in Verilog and embedded into the FPGA chip. The LVDS transmission rate is configured to be 100Mbps, and it supports address recognition for up to 32 expansion modules. The data transmission rate of this module is no less than 100Mbps, and it supports data transmission verification and retransmission mechanisms with a bit error rate of less than 0.001%. 4. Expansion Modules: Built-in MCU IP core to realize LVDS signal reception / transmission, interface data acquisition and instruction execution functions, with a preset unique DeviceID for device identification; expansion modules include but are not limited to DI / DO digital quantity modules, AI / AO analog quantity modules, CAN communication modules, and UART serial port modules. Each module can be plugged and played with the FPGA communication module through standardized interfaces.

[0023] (ii) Configuration device encapsulation and protocol implementation (corresponding to steps S2-S3 above) 1. Configuration device packaging In AnyControl Runtime, create a standardized configuration device template and define the parameter specifications for each interface: DI / DO interface: data type is BOOL, supports independent channel enable and filter time configuration (adjustable from 1ms to 100ms); AI / AO interface: Data type is 16-bit integer; AI supports -10V to 10V voltage input or 4mA to 20mA current input; AO output accuracy is ±0.1%. CAN interface: Supports CAN 2.0A / B protocol, baud rate adjustable from 250Kbps to 1Mbps, supports standard frame and extended frame; UART interface: Supports Modbus RTU protocol, baud rate adjustable from 1200bps to 115200bps, data bits, stop bits, and parity bits are configurable.

[0024] 2. Communication Protocol Implementation The protocol processing logic was developed according to the designed data frame format. The data frame structure is as follows: Frame header (2 bytes): fixed at 0xAA55, used for frame synchronization identification; Address field (1 byte): Value range 0x01~0x20, corresponding to the unique address of 32 extension modules; Data length (2 bytes): Identifies the number of bytes in the valid data area, ranging from 1 to 128 bytes; Valid data area (variable length): Stores interface data or control commands. When it exceeds 128 bytes, it is automatically packetized and transmitted. The packet identifier is embedded in the first byte of the valid data area. Checksum (2 bytes): Calculated using the CRC16 algorithm, covering all bytes from the frame header to the valid data area.

[0025] The protocol module assembles and parses data frames: after receiving user data sent by the Runtime, it encapsulates the data in the above format and adds a checksum; after receiving data frames uploaded by the FPGA, it first verifies the checksum. If the verification passes, it parses the valid data and transmits it to the Runtime; if the verification fails, it triggers an interruption request for retransmission.

[0026] (III) FPGA communication module configuration (corresponding to step S4 above) like Figure 1 As shown, the FPGA communication module completes the following configuration: 1. SPI-LVDS Conversion Configuration: The FPGA internally implements protocol conversion between the SPI interface and the LVDS interface. The SPI interface operates in Mode 0 with a clock frequency of 10MHz and uses full-duplex communication. The LVDS interface uses differential signal transmission, conforms to the ANSI / TIA / EIA-644 standard, and has a maximum transmission distance of 10 meters. 2. Data distribution logic: After receiving the data frame sent by the controller, the FPGA parses the address field and accurately distributes the data to the corresponding expansion module; at the same time, it receives the data uploaded by each expansion module, sorts it by address, packages it, and transmits it to the controller. 3. Anomaly Handling Mechanism: The FPGA performs real-time verification on the received data frames. When a CRC16 check error is detected, a high-level signal is output through the interrupt pin to notify the controller. After the controller responds to the interrupt, it triggers data retransmission to ensure that the bit error rate is less than 0.001%.

[0027] (iv) XML description file writing and configuration integration (corresponding to steps S5-S6 above) 1. Writing XML description files Two types of XML files should be written according to the specifications: one for device identity matching and the other for variable mapping configuration. Device identity matching file: contains fields such as device type (Type), unique identifier (Id), and version number (Version), as shown in the example below: <deviceidentification> <type> 40204< / type> <id> 19D08< / id> <version> 1.0.0.1< / version> < / deviceidentification> Variable mapping configuration file: Defines the parameter ID, data type, attribute configuration, default value, and description information of the input / output channels. An example is shown below: <parameter parameterid="1000" type="std:BOOL"> <attributes channel="input" download="true" functional="false" offlineaccess="readwrite" onlineaccess="readwrite" / > <default> 0< / default> <name> CH0< / name> <description> Channel 0 input value< / description> < / parameter> <parameter parameterid="1001" type="std:BOOL"> <attributes channel="input" download="true" functional="false" offlineaccess="readwrite" onlineaccess="readwrite" / > <default> 0< / default> <name> CH1< / name> <description> Channel 1 input value< / description> < / parameter> <parameter parameterid="1015" type="std:BOOL"> <attributes channel="input" download="true" functional="false" offlineaccess="readwrite" onlineaccess="readwrite" / > <default> 0< / default> <name> CH15< / name> <description> Channel 15 input value< / description> < / parameter> like Figure 2 As shown, AnyControl Runtime reads the DeviceID of each device in the link through the communication protocol module and matches it with the / DeviceIdentification / @Id field in the XML. After matching, the device can be scanned through the host computer configuration interface, and finally the device topology is generated on the left side of the configuration interface.

[0028] like Figure 4 As shown, taking the 16X module as an example, the Input bit type with ParameterId of 1000-1015 corresponds to the soft element %IX116-%IX117 bound to the IO mapping interface. The actual input point information of the module on the physical link can be obtained in real time by inputting through the interface or by accessing it using the ST language.

[0029] 2. Configuration integration and variable mapping Import the XML description file into the AnyControl host computer configuration software. The software will automatically complete the following operations: Device scanning: The runtime reads the DeviceID of all extension modules on the link through the extended communication protocol module and compares it with the ID in the XML file. <id>Field matching; once a match is successful, the device topology is generated on the left side of the configuration interface. Automatic variable mapping: The channel parameters (such as CH0~CH15) defined in the XML are mapped to the soft device addresses of the controller. CH0~CH15 of the 16-channel DI module correspond to soft devices %IX116.0~%IX117.7. Visual configuration: Users can view or modify the addresses of the soft components corresponding to the channels through the "IO mapping configuration" function in the configuration interface, which supports offline configuration and online modification.

[0030] (v) Local access to module communication interface (corresponding to step S7 above) like Figure 3 As shown, by modifying the linkage logic between the controller's underlying driver and the extended communication protocol module, localized access to the extended module's interface is achieved: 1. Virtual Interface Creation: Create virtual COM ports and virtual CAN ports in AnyControl Runtime, and map the physical interfaces of the expansion modules (the 232 / 485 interface of the E2COM24 module and the CAN interface of the E1CAN module) to virtual interfaces; 2. Device Library Adaptation: Reuses the CANBus / Modbus device library that comes with the AnyControl platform. Users can directly call the standard function blocks (such as CAN_Send, Modbus_Read) in the device library to access the extension module interface without distinguishing between the controller body interface and the extension interface. It supports all control methods of CANBus / Modbus devices on AnyControl. 3. Data Interaction Process: User-sent interface access commands via configuration software or ST language are routed to the corresponding virtual interface by the Runtime. The extended communication protocol module encapsulates the commands into standard data frames, which are then transmitted to the extension module via the FPGA communication module, enabling data read and write interaction.

[0031] (vi) System integration and testing (corresponding to step S8 above) 1. System Integration: Compile the extended communication protocol module and FPGA driver module into static library files (.a format), integrate them into the Runtime environment through AnyControl's Runtime SDK development package, compile them to generate an executable program, and download it to the controller body; 2. Functional testing: Module compatibility test: 16X / 16Y, E4AD / E4DA, E1CAN, E2COM24 and other expansion modules were connected in sequence. The configuration software could accurately scan and identify them, and the device topology was displayed normally. Seamless access test: When a user modifies the variable values ​​of %IX116.0 to %IX117.7 through the configuration interface, the corresponding 16X module channel status changes in real time; the 485 interface data of the E2COM24 module is read by calling the Modbus_Read function block through ST language, and the data transmission delay is ≤10ms; Data transmission stability test: Data transmission was conducted continuously for 24 hours, with a data volume of 100GB sent. There was no data loss or verification error, and the bit error rate was less than 0.001%. 3. Anti-interference test: Under industrial electromagnetic interference environment (noise voltage 1000Vp-p, 1us pulse), the system can still operate stably, data transmission is normal, and the module does not disconnect from the network.

[0032] III. Workflow Description like Figure 1 , Figure 5 As shown, the complete workflow of this invention is as follows: 1. After the system is powered on, the AnyControl controller starts the AnyControl Runtime, loads the extended communication protocol module and the FPGA driver module, and initializes the SPI and LVDS interfaces of the FPGA communication module; 2. The runtime reads the XML description file, parses the device identity information and variable mapping rules, and scans the extended modules in the link through the extended communication protocol module to complete device matching and topology generation; 3. Users can access the mapped soft component variables, issue control commands, or read data through the host computer configuration software or ST language; 4. After receiving the user's instruction, the runtime transmits it to the extended communication protocol module. The protocol module assembles the data frame according to the standardized format and adds a checksum. 5. After receiving the data frame, the FPGA communication module converts it into an LVDS signal and distributes it to the target expansion module according to the address; 6. The extension module executes instructions, collects interface data or performs control operations, and encapsulates the response data in the same protocol format before uploading it to the FPGA communication module; 7. The FPGA communication module converts the response data into an SPI signal and transmits it to the Runtime. The protocol module parses the data frame and verifies the checksum, then feeds back the valid data to the user. 8. If a verification error occurs during data transmission, the FPGA triggers an interrupt, and the Runtime responds to the interrupt and initiates data retransmission to ensure data integrity.

[0033] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.< / id> < / parameter> < / deviceidentification>

Claims

1. An IEC61131-3 controller expansion module based on AnyControl, characterized in that, Includes AnyControlRuntime main control module, extended communication protocol module, FPGA communication module, and expansion module; The AnyControl Runtime main control module is the core scheduling unit, which encapsulates the DI / DO, AI / AO, CAN, and UART interface functions into a standardized configuration device; The extended communication protocol module is used to assemble user data into standard data frames and complete data frame parsing, thereby realizing standardized encapsulation and link transmission of user data. The FPGA communication module constructs a high-speed data transmission channel based on the SPI protocol and LVDS interface, realizing bidirectional data interaction between the AnyControl Runtime main control module and each of the expansion modules, as well as multi-module link cascading and data distribution; The configuration device is integrated into the AnyControl host computer configuration software through an XML description file, realizing automatic mapping of variables of the physical interface between the configuration device and the expansion module. Users can complete the seamless control and data reading and writing of the expansion module by accessing the mapped variables.

2. The AnyControl-based IEC61131-3 controller expansion module according to claim 1, characterized in that, In the standardized configuration equipment, the DI / DO interface uses Boolean data, and the AI / AO interface uses 16-bit integer data; the CAN interface baud rate is adjustable from 250Kbps to 1Mbps, and the UART interface baud rate is adjustable from 1200bps to 115200bps, and it is configured with a fault-tolerant processing mechanism for data filtering and timeout retransmission.

3. The AnyControl-based IEC61131-3 controller expansion module according to claim 1, characterized in that, The standard data frame includes a 2-byte frame header, a 1-byte address field, a 2-byte data length, variable-length valid data, and a 2-byte CRC16 checksum. The frame header is fixed at 0xAA55, the address field has a value of 0x01 to 0x20, which is used to distinguish up to 32 extension modules. The maximum length of the valid data is 128 bytes and it supports packet transmission.

4. The AnyControl-based IEC61131-3 controller expansion module according to claim 1, characterized in that, The FPGA communication module has a data transmission rate of no less than 100Mbps, integrates data transmission verification and retransmission mechanisms, and has a data transmission error rate of less than 0.001%; ​​the LVDS interface conforms to the ANSI / TIA / EIA-644 standard and has a maximum transmission distance of 10 meters.

5. An IEC61131-3 controller expansion module based on AnyControl according to claim 1 or 4, characterized in that, The FPGA communication module uses a Unisoc FPGA chip, integrating an SPI interface controller and an LVDS transceiver. An interrupt pin is reserved for connection to the controller body to transmit interrupt signals for data verification errors. The SPI interface operates in Mode 0 with a clock frequency of 10MHz and uses full-duplex communication.

6. The AnyControl-based IEC61131-3 controller expansion module according to claim 1, characterized in that, The XML description file includes fields for device identifier, interface type, variable name, data type, memory address mapping, and device version. These fields are used by the host computer configuration software for automatic parsing, device loading, and identity matching. An example of an XML description file is provided. <deviceidentification>and <parameter> Node definition.< / parameter> < / deviceidentification> 7. The AnyControl-based IEC61131-3 controller expansion module according to claim 1, characterized in that, The automatic variable mapping is as follows: the host computer configuration software maps the configuration device logical variables to the controller soft element addresses through the XML description file. CH0 to CH15 of the 16-channel DI module correspond to soft elements %IX116.0 to %IX117.

7. Users can read and write the physical interface data of the expansion module by accessing the soft elements through the configuration interface or ST language.

8. The AnyControl-based IEC61131-3 controller expansion module according to claim 1, characterized in that, The expansion module includes a DI / DO digital quantity module, an AI / AO analog quantity module, a CAN communication module, and a UART serial port module. Specifically, it includes a 16-channel DI / DO module, a 4-channel AI / AO module, a CAN communication module, and a multi-serial port module. Each module is plug-and-play via the LVDS standardized interface.

9. An IEC61131-3 controller expansion module based on AnyControl according to claim 1 or 8, characterized in that, The physical interfaces of the expansion module, namely CAN and UART, are mapped to the virtual CAN port and virtual COM port of the AnyControl Runtime main control module. The platform's native CANBus / Modbus device library is reused, and the standard function block calls of CAN_Send and Modbus_Read are supported, so as to realize the consistent and seamless access between the expansion interface and the controller body interface.

10. The AnyControl-based IEC61131-3 controller expansion module according to claim 1, characterized in that, After the system is powered on, the AnyControl Runtime main control module automatically scans the link extension modules, matches the XML device identifiers, and generates the device topology; When a data transmission verification error occurs, the FPGA triggers an interrupt via the interrupt pin, and the Runtime responds to the interrupt and initiates a data retransmission.

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