A multi-channel pressure and temperature acquisition system and method

Abstract

This application discloses a multi-channel pressure and temperature acquisition system and method, relating to the field of industrial automation measurement and control. In this system, a channel selection module selects multiple differential signals using a polling method; a signal conditioning module amplifies and filters the selected differential signals and ambient temperature signals; a data acquisition module acquires the conditioned differential signals and the conditioned ambient temperature signals, and performs analog-to-digital conversion; the core control module includes an acquisition-end FPGA, a transmission-end FPGA, and an ARM processor; the acquisition-end FPGA controls the polling timing and analog-to-digital conversion; preprocesses the digital signals; the transmission-end FPGA analyzes the preprocessed signals; and the ARM processor performs temperature compensation on the conditioned differential signals based on the analyzed signals and the fitting coefficients of the channel pressure sensors, combined with the conditioned ambient temperature signals. This application can improve the sampling rate, sampling accuracy, reliability, and scalability of multi-channel pressure and temperature acquisition.

Description

Technical Field

[0001] This application relates to the field of industrial automation measurement and control, and in particular to a multi-channel pressure and temperature acquisition system and method. Background Technology

[0002] With the increasing demands for pressure testing in industrial equipment monitoring, aerospace, and wind tunnel experiments, pressure scanning valves, a core component, play a crucial role. Researchers are increasingly demanding high-speed, high-precision acquisition of multi-channel differential signals. However, existing technologies still have significant shortcomings in data synchronization, sampling rate, sampling accuracy, system scalability, and adaptability to complex environments. For example, while high-speed acquisition cards based on Peripheral Component Interconnect Express (PCIE) or PCI extensions for Instrumentation (PXI) offer high sampling rates, they suffer from high power consumption, high cost, and difficulty in embedded deployment. In contrast, Field-Programmable Gate Array (FPGA) + Advanced RISC Machines (ARM) architecture systems can achieve high-speed sampling, low-power operation, and flexible system integration. However, current FPGA+ARM architecture acquisition schemes are relatively large in size for precision equipment like pressure scanning valves due to the complexity of their peripheral circuitry, making them difficult to deploy in confined spaces.

[0003] Furthermore, existing multiplexer cascade solutions often employ independent address line control, resulting in high wiring complexity, significant crosstalk between channels, and low polling efficiency, making them unsuitable for the sampling rates of high-speed analog-to-digital converters (ADCs). Regarding the accuracy drift issue in wide temperature range environments, some solutions lack a synchronous temperature acquisition link, failing to provide real-time compensation for the temperature drift characteristics of the ADC, operational amplifiers, and sensors. In extreme high and low temperature environments, the acquisition error is high, failing to meet the high-precision requirements of industrial applications. Summary of the Invention

[0004] The purpose of this application is to provide a multi-channel pressure and temperature acquisition system and method that can improve the sampling rate, sampling accuracy, reliability and scalability of multi-channel pressure and temperature acquisition.

[0005] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a multi-channel pressure and temperature acquisition system, including: a channel selection module, a signal conditioning module, a data acquisition module, and a core control module; The channel selection module is used to connect to the multi-channel pressure sensor array inside the instrument structure and select the multi-channel differential signal in a polling manner. The signal conditioning module is connected to the channel selection module and integrates a temperature signal conditioning channel. The signal conditioning module is used to amplify and filter the selected differential signal and the ambient temperature signal synchronously acquired by the temperature signal conditioning channel, respectively, to obtain the conditioned differential signal and the conditioned ambient temperature signal. The data acquisition module is connected to the signal conditioning module and is used to acquire the conditioned differential signal and the conditioned ambient temperature signal, and perform analog-to-digital conversion to obtain a digital signal. The core control module is connected to the channel selection module and the data acquisition module respectively; the core control module includes an acquisition end FPGA, a transmission end FPGA and an ARM processor; The FPGA at the acquisition end is used to control the polling timing of the channel selection module and the analog-to-digital conversion of the data acquisition module; and to preprocess the digital signal; the preprocessing includes: data splicing and frame format encapsulation; The transmission FPGA is connected to the acquisition FPGA and is used to analyze the preprocessed signal; the analysis includes serial-to-parallel conversion and protocol conversion. The ARM processor is used to perform real-time temperature compensation on the conditioned differential signal based on the parsed signal and the fitting coefficient of the channel pressure sensor, combined with the conditioned ambient temperature signal; the fitting coefficient of the channel pressure sensor is determined by linear fitting of the calibrated temperature and the differential signal.

[0006] Secondly, this application provides a multi-channel pressure and temperature acquisition method, applied to the aforementioned multi-channel pressure and temperature acquisition system, comprising: The FPGA control channel selection module at the acquisition end polls and selects multiple differential signals, and synchronously controls the analog-to-digital converter to convert the conditioned analog signals into digital signals; After the acquisition-end FPGA preprocesses the digital signal, it transmits the preprocessed signal to the transmission-end FPGA. The FPGA at the transmission end performs protocol conversion on the preprocessed signal, generates the parsed signal, and then transmits it to the ARM processor. The ARM processor performs real-time temperature compensation on the conditioned differential signal based on the parsed signal and the fitting coefficient of the channel pressure sensor, combined with the conditioned ambient temperature signal; and transmits the temperature-compensated differential signal to the host computer.

[0007] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a multi-channel pressure and temperature acquisition system and method. It employs a modular, highly integrated design and includes a channel selection module, a signal conditioning module, a data acquisition module, and a core control module. By utilizing a dual-FPGA architecture (FPGA at the acquisition end and FPGA at the transmission end) and high-speed ARM computing, this application solves the problems of insufficient single-FPGA multi-protocol adaptation and slow processing speed for massive multi-channel data. This application enables high-speed, high-precision, synchronous acquisition of multi-channel pressure and temperature data in a compact structure. While meeting the requirements of high density, high precision, high efficiency, and compactness of a miniature pressure scanning valve, it addresses the issues of low sampling rate and poor sampling accuracy, while simultaneously improving system reliability and scalability. This application can be widely applied in fields requiring large-scale, high-speed pressure data acquisition, such as industrial equipment monitoring, aerospace, and wind tunnel testing. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a multi-channel pressure and temperature acquisition system according to one embodiment of this application; Figure 2 A schematic diagram of a two-stage multiplexer logic design; Figure 3 This is a schematic diagram of the core control module; Figure 4 This is a schematic diagram of the data acquisition system. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0011] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] In one exemplary embodiment, such as Figure 1As shown, a multi-channel pressure and temperature acquisition system is provided, including: a channel selection module, a signal conditioning module, a data acquisition module, and a core control module; The channel selection module is used to connect to the multi-channel pressure sensor array inside the instrument structure and selects multi-channel differential signals in a polling manner to provide a stable input signal for signal conditioning and data acquisition. The signal conditioning module is connected to the channel selection module and integrates a temperature signal conditioning channel. The signal conditioning module amplifies and filters the selected differential signal and the ambient temperature signal synchronously acquired by the temperature signal conditioning channel, respectively, to obtain the conditioned differential signal and the conditioned ambient temperature signal. The signal conditioning module can reduce noise interference, amplify the signal amplitude, and optimize the signal characteristics to match the input requirements of the ADC in the data acquisition module, and provide a reference for temperature compensation of the differential signal (pressure data) through the synchronously acquired ambient temperature signal. The data acquisition module is connected to the signal conditioning module and is used to acquire the conditioned differential signal and the conditioned ambient temperature signal, and perform analog-to-digital conversion to obtain a digital signal. The core control module is connected to the channel selection module and the data acquisition module respectively. The core control module undertakes core functions such as channel selection control, analog-to-digital conversion management, data preprocessing, protocol conversion, data parsing and compensation. It adopts a heterogeneous architecture of "acquisition-end FPGA + transmission-end FPGA + ARM processor" to improve the synchronization accuracy and transmission efficiency of the system. The core control module includes an acquisition-end FPGA, a transmission-end FPGA and an ARM processor. The FPGA at the acquisition end is used to control the polling timing of the channel selection module and the analog-to-digital conversion of the data acquisition module; and to preprocess the digital signal; the preprocessing includes: data splicing and frame format encapsulation; The transmission FPGA is connected to the acquisition FPGA and is used to analyze the preprocessed signal; the analysis includes serial-to-parallel conversion and protocol conversion. The ARM processor is used to perform real-time temperature compensation on the conditioned differential signal based on the parsed signal and the fitting coefficient of the channel pressure sensor, combined with the conditioned ambient temperature signal; the fitting coefficient of the channel pressure sensor is determined by linear fitting of the calibrated temperature and the differential signal.

[0013] Specifically, the channel selection module includes: cascaded multiplexers; the channel selection module adopts a two-stage cascaded approach with multiple multiplexers to achieve high-speed selection of multi-channel differential signals, while also taking into account the scalability of the channels; The address pins of the multi-chip multiplexer in the front stage are connected in parallel to the address control terminal of the acquisition terminal FPGA; the enable pins of the multi-chip multiplexer in the front stage are connected to the enable control terminal of the acquisition terminal FPGA; the acquisition terminal FPGA controls the polling selection of multi-channel differential signals through address signals and enable signals; The input terminals of the subsequent multiplexer are connected to the output terminals of each of the preceding multiplexers, and the address pins and enable pins of the subsequent multiplexer are connected to the acquisition FPGA. The output terminal of the subsequent multiplexer is connected to the signal conditioning module.

[0014] As a specific embodiment, the two-stage cascaded configuration of multiple multiplexers is as follows: The front-end uses an 8-to-1 low on-resistance multiplexer, with each multiplexer corresponding to eight differential pressure signals. The address pins of all front-end multiplexers are connected in parallel to the address control terminal of the acquisition-end FPGA to achieve synchronous output of address signals. The enable pin of each front-end multiplexer is connected to the independent enable control terminal of the acquisition-end FPGA to achieve independent chip selection control of each multiplexer. The rear-end uses one 8-to-1 multiplexer, whose address and enable pins are independently controlled by the acquisition-end FPGA. Its input terminals are connected one-to-one with the differential output terminals of each front-end multiplexer, and its output terminal is connected to the input terminal of the signal conditioning module to achieve the aggregated output of the front-end selection signals. This parallel address line and independent enable line control significantly simplifies the wiring complexity of the acquisition-end FPGA and reduces signal crosstalk between channels.

[0015] Specifically, the signal conditioning module includes a voltage follower, a filter circuit, and a fully differential amplifier connected in sequence; The voltage follower is used to buffer and isolate the differential signal; the filter circuit is used to suppress high-frequency noise in the isolated differential signal; and the fully differential amplifier is used to amplify the gain and optimize the common-mode level of the filtered differential signal.

[0016] As a specific embodiment, the voltage follower employs a zero-drift, low-noise operational amplifier to isolate and buffer the channel selection module from the subsequent filtering circuit, avoiding the influence of multiplexer on-resistance changes and load changes on the pressure signal; the filtering circuit employs an RC low-pass filter circuit to filter out noise in the signal; the fully differential amplifier employs a high-precision fully differential operational amplifier configured with a fixed gain to amplify the weak millivolt-level differential signal output by the pressure sensor to the 0~5V full-scale range adapted by the ADC, while optimizing the common-mode level of the signal, improving the signal's anti-interference capability, and ensuring that the signal acquired by the ADC has sufficient amplitude and signal-to-noise ratio; Specifically, the temperature signal conditioning channel includes an onboard temperature sensor; The output of the onboard temperature sensor is connected in sequence to the voltage follower, the filter circuit, and the fully differential amplifier.

[0017] As a specific embodiment, the onboard temperature sensor is an onboard temperature sensor PT1000 platinum resistance thermometer. The PT1000 platinum resistance thermometer uses a simple voltage divider method to convert the resistance signal into a voltage signal, which then passes through the same voltage follower, filter circuit and fully differential amplifier as the pressure signal conditioning link. Its output terminal is connected to the second channel of the analog-to-digital converter (ADC) of the data acquisition module to realize the synchronous acquisition of temperature signal and pressure signal.

[0018] Specifically, the data acquisition module includes: an analog-to-digital converter; the first channel of the analog-to-digital converter is used to perform analog-to-digital conversion on the conditioned differential signal; the second channel of the analog-to-digital converter is used to perform analog-to-digital conversion on the conditioned ambient temperature signal.

[0019] The data acquisition module preferably uses a dual-channel 24-bit high-precision analog-to-digital converter to convert the analog signal output by the signal conditioning module into a digital signal, providing digital signal input for the data processing of the core control module; Furthermore, the first channel of the high-precision analog-to-digital converter is used to acquire differential signals; the second channel is connected to the output of the temperature signal conditioning auxiliary channel and is used to acquire ambient temperature signals; the ADC is connected to the acquisition terminal FPGA through the SPI interface, and the acquisition terminal FPGA controls the ADC to start conversion synchronously through the CONVST pin, and judges the ADC conversion completion status in real time through the BUSY pin. When the BUSY signal is detected to be pulled low, the 24-bit quantized digital signal output by the ADC is read through the CS chip select signal and the SDO data pin.

[0020] Specifically, the preprocessing process of digital signals by the FPGA at the acquisition end includes: The byte-by-byte data of the digital signal is concatenated into a complete bit-width data; the complete bit-width data is then encapsulated according to a preset format; the encapsulation includes: a frame header, a frame count, an ambient temperature signal, and a differential signal; the preprocessed signal is then transmitted to the transmission terminal FPGA through a parallel PCM interface.

[0021] The acquisition-end FPGA uses a pre-defined multi-channel polling order in a custom ROM file within its ROM IP core to output address and enable signals to the multiplexer of the channel selection module, controlling the channel selection timing of the multi-channel differential signals. Simultaneously, the acquisition-end FPGA communicates with the analog-to-digital converter (ADC) via an SPI interface, sending conversion start signals, reading conversion completion status, and receiving quantized digital signals to achieve synchronous control of the ADC conversion process, thereby ensuring the real-time performance and accuracy of data acquisition. Furthermore, the acquisition-end FPGA preprocesses the 24-bit digital signal acquired by the analog-to-digital converter, including data splicing and frame format encapsulation. The acquisition-end FPGA first splices the byte-by-byte data output by the analog-to-digital converter into complete 24-bit data, and then encapsulates it according to a preset frame format. The frame format includes, in sequence, a frame header 0xEB90 for frame synchronization identification, a frame count for data frame sequence verification, an ambient temperature signal, and a differential signal. Finally, the encapsulated data frame is output to the transmission-end FPGA through a parallel PCM interface.

[0022] Specifically, the FPGA at the transmission end integrates a FIFO buffer unit and a protocol conversion module. The protocol conversion module is driven by a finite state machine and is used to debouncing and converting the preprocessed signal from serial to parallel before transmitting it to the FIFO buffer unit; and to encapsulate the buffered data in the FIFO buffer unit into parallel frame format data that matches the CSI interface of the ARM processor.

[0023] Specifically, the transmission-end FPGA performs debouncing on the preprocessed signal input from the acquisition-end FPGA to filter out signal glitches introduced by electromagnetic interference in the industrial environment. Through serial-to-parallel conversion logic, the transmission-end FPGA concatenates the two input 4-bit PCM data into 8-bit standard byte data. Internally, it integrates a protocol conversion module driven by a 6-state finite state machine, which encapsulates the 8-bit byte data in the FIFO buffer unit into parallel frame format data that matches the ARM processor CSI interface. It outputs a pixel clock csi_pclk, a line synchronization signal csi_hsync, a field synchronization signal csi_vsync, and an 8-bit parallel data bus csi_data that match the ARM processor CSI interface, realizing high-speed data transmission to the ARM processor.

[0024] The ARM processor is developed using the Ubuntu system based on the Linux kernel. It is connected to the CSI interface of the FPGA at the transmission end to receive data and perform parsing, compensation calculation and forwarding. Furthermore, the ARM processor first performs linear fitting of the calibrated temperature and differential signals using cubic spline interpolation based on the least squares method to generate fitting coefficients for all channel pressure sensors. Combined with the conditioned ambient temperature signal, it performs real-time temperature compensation on the conditioned differential signal to reduce the temperature drift error of devices such as ADC, operational amplifier, and pressure sensor under wide temperature conditions, thereby improving the accuracy of pressure acquisition. At the same time, it converts the quantized value of the pressure sample into the actual physical quantity of pressure and performs further filtering on the data. Finally, the processed pressure data is uploaded.

[0025] In order to enable real-time display, storage and analysis of data, this application also includes a data transmission module; The data transmission module is connected to the ARM processor and is used to transmit the compensated differential signal to the host computer.

[0026] Specifically, the data transmission module includes an Ethernet PHY chip and a network transformer; preferably, a gigabit Ethernet architecture is adopted to improve data transmission bandwidth and meet the data transmission requirements of multi-channel high-speed acquisition. The Ethernet PHY chip is used to connect to the Ethernet controller integrated inside the ARM processor through the RGMII interface of the ARM processor; it supports an adaptive transmission rate of 10 / 100 / 1000Mbps. This application uses the UDP protocol for data transmission to realize real-time display, storage and analysis of data. The network transformer is connected to the Ethernet PHY chip via a differential signal line and to the host computer via an RJ45 interface.

[0027] To provide a stable and reliable multi-channel regulated power supply for each module of the system, this application also includes a power management module. The power management module includes multiple low-noise linear regulator circuits and DC-DC converter circuits, used to supply power to analog and digital circuits separately, reducing the interference of digital noise on analog signals.

[0028] The specific acquisition process for the multi-channel pressure and temperature acquisition system provided in this application is as follows: 1. After power-on, each module completes initialization. The acquisition terminal FPGA loads the custom ROM file in the ROM IP core to obtain the preset multi-channel polling order. Then, it outputs address signals and enable signals according to the polling order to control the two-stage cascaded multiplexer to poll and select all channels in sequence. The channel switching timing is strictly synchronized with the ADC sampling period to ensure accurate acquisition of each channel signal and avoid missed or incorrect acquisition.

[0029] 2. The selected differential pressure signal is processed by the signal conditioning module, and then sequentially passes through a zero-drift low-noise voltage follower isolation buffer, an RC low-pass filter circuit to filter out noise, and a high-precision fully differential amplifier with fixed gain amplification to match the ADC input range. At the same time, the onboard PT1000 platinum resistor converts the resistance signal into a voltage signal through voltage division, and after being processed by the same conditioning circuit, it is input into the second channel of the ADC. The FPGA at the acquisition end triggers the ADC synchronous conversion through the CONVST pin. After detecting that the BUSY signal is pulled low, it reads the 24-bit pressure and temperature quantization data through the CS chip select and SDO data pins to complete the conversion of analog signal to digital signal.

[0030] 3. The acquisition-end FPGA concatenates the byte-by-byte data output by the ADC into a complete 24-bit data, encapsulates it according to the preset format of frame header, frame count, temperature sampling data, and pressure sampling data, writes the data frame into the FIFO IP core buffer to avoid data accumulation, and then sends the encapsulated data frame to the transmission-end FPGA through the parallel PCM interface.

[0031] 4. After receiving the parsed signal (PCM data signal) at the transmission end FPGA, it first performs debouncing to filter out signal glitches. Then, it concatenates the two 4-bit PCM data into an 8-bit standard byte through serial-to-parallel conversion and writes it into the internal synchronous FIFO buffer unit to eliminate the rate difference. Then, through the protocol conversion module driven by a 6-state finite state machine, it encapsulates the buffered data into a parallel frame format that matches the ARM processor CSI interface, generates the corresponding pixel clock, line synchronization signal, and field synchronization signal, and sends them to the ARM processor through the CSI interface.

[0032] 5. The ARM processor receives data frames via the CSI interface, parses and verifies them to identify the frame header, frame count, and temperature and pressure sampling data, discarding invalid and erroneous frames. It then performs cubic spline interpolation based on least squares to linearly fit the calibration data, generating fitting coefficients. Combined with temperature data, it performs real-time temperature compensation for pressure data, converting the 24-bit pressure quantization value into a true pressure physical quantity. Finally, it connects to the Ethernet PHY chip via the internal GMAC Ethernet controller and RGMII interface, uploading the processed data to the host computer using the UDP protocol for real-time data display, storage, and analysis.

[0033] The core of this application lies in achieving high-speed, high-precision, multi-channel pressure and temperature acquisition for a miniature pressure scanning valve through a heterogeneous architecture of dual FPGAs and ARM. The following is combined with... Figures 1 to 4 The specific implementation methods of this application will be described in detail.

[0034] like Figure 1 The entire system shown includes a pressure sensor array, a channel selection module, a signal conditioning module, a data acquisition module, a core control module, a data transmission module, and a power management module.

[0035] The pressure sensor array consists of 64 high-precision gauge pressure sensors, distributed in 8 arrays on the PCB hardware circuit board. The matrix of 8 is powered by 8 reference voltage source chips, providing a continuous supply of pressure signals to the 64 pressure channels in the multi-channel pressure and temperature acquisition system.

[0036] like Figure 4As shown, the channel selection module uses the ADG1607 multiplexer chip. This chip has extremely low on-resistance and on-resistance flatness of its internal switches, making it suitable for low-distortion data acquisition scenarios and precision signal channel management requiring frequent gain switching. The two-stage multiplexer logic design in this multi-channel pressure and temperature acquisition is as follows: Figure 2 As shown, the address pins of eight first-stage multiplexer chips (ADG1607) are connected in parallel to the acquisition-end FPGA, while the eight enable pins (EN) are independently connected to the acquisition-end FPGA. The address and enable pins of the second-stage multiplexer chip (ADG1607) are also independently connected to the acquisition-end FPGA for control. Furthermore, the output of the first-stage multiplexer chip is connected to the input of the second-stage multiplexer chip, achieving the aggregated output of the pre-stage selection signals. This configuration, through parallel address lines and independent enable lines, significantly simplifies the wiring complexity of the acquisition-end FPGA, reduces signal crosstalk between channels, and allows for flexible expansion of the number of channels by increasing or decreasing the number of pre-stage multiplexers to adapt to different acquisition scenarios.

[0037] The signal conditioning module uses the ADA4945, a low-noise, low-distortion fully differential amplifier chip. This chip requires only a simple external feedback network consisting of four resistors to achieve differential gain configuration, and this network determines the amplifier's closed-loop gain. The multi-channel pressure and temperature acquisition is configured with a fixed gain of 20x, amplifying the weak millivolt-level differential signal output from the pressure sensor to the 0-5V full-scale range adapted by the ADC, while optimizing the signal common-mode level. The pressure signal conditioning circuit uses the AD8034, and the temperature signal conditioning channel uses the AD8627 to build voltage follower circuits respectively, achieving isolation and buffering between the preceding and following stages to avoid the influence of multiplexer on-resistance changes and load variations on the pressure signal.

[0038] The data acquisition module uses a 24-bit dual-channel, synchronous sampling SAR ADC, the AD4630, with a dual-channel sampling rate of up to 500KSPS. In this application, to balance sampling accuracy, system bandwidth, and data transmission capability, a sampling rate of 80KSPS is configured. For the digital interface, the AD4630 employs an enhanced SPI interface, including a chip select. The AD4630 chip features serial input SDI, clock SCK, and 8-bit parallel outputs SDO0~SDO7 for high-speed data communication with the FPGA at the acquisition end. The AD4630 chip's configuration and data transmission are controlled by default using the flexible SPI protocol in mode 00. After power-on reset upon completion of multi-channel pressure and temperature acquisition, the driver first enters the IDLE state to complete a 16'hFFFF cycle delay, then sequentially sends configuration commands. The AD4630 chip executes the initialization process, and after initialization, the chip enters the data acquisition state.

[0039] like Figure 3As shown, the core control module adopts a heterogeneous architecture of "acquisition-end FPGA + transmission-end FPGA + ARM processor". The acquisition-end FPGA is Zhongke Yihaiwei EQ6HL9S industrial-grade FPGA, the transmission-end FPGA is Ziguang Tongchuang PGL25G industrial-grade FPGA, and the ARM processor is Allwinner T3 industrial-grade quad-core Cortex-A7 processor.

[0040] The EQ6HL9S's internal integrated ROM IP core stores a custom ROM file to control the channel selection timing. Simultaneously, it communicates with the AD4630 via the SPI interface to manage the analog-to-digital conversion process, preprocesses and encapsulates the 24-bit digital signal acquired by the AD4630, uses an internally integrated FIFO IP core to buffer the encapsulated data frames, and finally sends the data frames to the PGL25G via a 4-bit parallel PCM interface.

[0041] The PGL25G integrates a synchronous FIFO buffer unit, serial-to-parallel conversion logic, and a protocol conversion module driven by a 6-state finite state machine. After receiving PCM data from the EQ6HL9S, it first performs debouncing to filter out signal glitches. Then, it concatenates two 4-bit PCM data into an 8-bit standard byte through serial-to-parallel conversion and writes it into the FIFO buffer to resolve rate differences. The protocol conversion module then encapsulates the buffered data into a parallel frame format that matches the Allwinner T3 processor's CSI interface. The frame format is configured as 200 bytes per line, 64 lines per frame, and an 8-cycle line blanking period. It outputs a pixel clock csi_pclk, a line synchronization signal csi_hsync, a field synchronization signal csi_vsync, and an 8-bit parallel data bus csi_data, which are then sent to the Allwinner T3 processor through the CSI interface.

[0042] The Allwinner T3 processor runs an Ubuntu system based on the Linux kernel. It receives frame data via a CSI interface driver, parses the data through software programming, and performs linear fitting using cubic spline interpolation based on least squares on the calibrated temperature and pressure sampling data. This generates fitting coefficients for the 64-channel pressure sensor, and combined with synchronously acquired temperature data, performs real-time temperature compensation for the pressure data, converting the 24-bit pressure quantization value into the actual pressure physical quantity. It also integrates a GMAC Ethernet controller for data uploading.

[0043] The data transmission module adopts a gigabit Ethernet architecture, using the YT8521S gigabit Ethernet PHY chip and the KRJ-320DNL Ethernet connector to construct the Ethernet circuit. The GMAC Ethernet controller integrated within the ARM processor connects to the YT8521S via the RGMII interface, supporting adaptive transmission rates of 10 / 100 / 1000Mbps. To ensure real-time data transmission, this application uses the UDP protocol as the transport layer protocol, reducing protocol stack overhead.

[0044] The power management module includes a DC-DC conversion circuit and multiple low-noise linear regulators (LDOs). It receives an external 12VDC industrial power supply, which is protected by a TVS diode and a reverse connection protection circuit. The power supply is then divided into two independent power supply paths, one for analog circuits and one for digital circuits. The analog ground and digital ground are connected at a single point through a 0-ohm resistor to avoid noise coupling caused by ground potential difference, thereby improving the system's noise immunity.

[0045] In summary, this application, through modular and highly integrated design, realizes a miniature, high-speed, multi-channel pressure and temperature acquisition system for pressure scanning monitoring. Its applications are wide-ranging, suitable for industrial equipment monitoring, aerospace, and wind tunnel testing, demonstrating significant practical value and technological advantages. Based on the same inventive concept, this application also provides a multi-channel pressure and temperature acquisition method, including: S1, the acquisition terminal FPGA control channel selection module polls and selects multiple differential signals, and synchronously controls the analog-to-digital converter to convert the conditioned analog signal into a digital signal; S2, after the acquisition terminal FPGA preprocesses the digital signal, it transmits the preprocessed signal to the transmission terminal FPGA. S3, the FPGA at the transmission end performs protocol conversion on the preprocessed signal, generates the parsed signal, and then transmits it to the ARM processor; The S4 ARM processor performs real-time temperature compensation on the conditioned differential signal based on the parsed signal and the fitting coefficient of the channel pressure sensor, combined with the conditioned ambient temperature signal; and transmits the temperature-compensated differential signal to the host computer.

[0046] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0047] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A multi-channel pressure and temperature acquisition system, characterized in that, include: The module includes a channel selection module, a signal conditioning module, a data acquisition module, and a core control module. The channel selection module is used to connect to the multi-channel pressure sensor array inside the instrument structure and select the multi-channel differential signal in a polling manner. The signal conditioning module is connected to the channel selection module and integrates a temperature signal conditioning channel. The signal conditioning module is used to amplify and filter the selected differential signal and the ambient temperature signal synchronously acquired by the temperature signal conditioning channel, respectively, to obtain the conditioned differential signal and the conditioned ambient temperature signal. The data acquisition module is connected to the signal conditioning module and is used to acquire the conditioned differential signal and the conditioned ambient temperature signal, and perform analog-to-digital conversion to obtain a digital signal. The core control module is connected to the channel selection module and the data acquisition module respectively; the core control module includes an acquisition end FPGA, a transmission end FPGA and an ARM processor; The FPGA at the acquisition end is used to control the polling timing of the channel selection module and the analog-to-digital conversion of the data acquisition module; The digital signal is preprocessed; the preprocessing includes: data splicing and frame format encapsulation. The transmission FPGA is connected to the acquisition FPGA and is used to analyze the preprocessed signal; the analysis includes serial-to-parallel conversion and protocol conversion. The ARM processor is used to perform real-time temperature compensation on the conditioned differential signal based on the parsed signal and the fitting coefficient of the channel pressure sensor, combined with the conditioned ambient temperature signal; the fitting coefficient of the channel pressure sensor is determined by linear fitting of the calibrated temperature and the differential signal.

2. The multi-channel pressure and temperature acquisition system according to claim 1, characterized in that, The channel selection module includes: cascaded multiplexers; The address pins of the multi-chip multiplexer in the front stage are connected in parallel to the address control terminal of the acquisition terminal FPGA; the enable pins of the multi-chip multiplexer in the front stage are connected to the enable control terminal of the acquisition terminal FPGA; the acquisition terminal FPGA controls the polling selection of multi-channel differential signals through address signals and enable signals; The input terminals of the subsequent multiplexer are connected to the output terminals of each of the preceding multiplexers, and the address pins and enable pins of the subsequent multiplexer are connected to the acquisition FPGA. The output terminal of the subsequent multiplexer is connected to the signal conditioning module.

3. The multi-channel pressure and temperature acquisition system according to claim 1, characterized in that, The signal conditioning module includes a voltage follower, a filter circuit, and a fully differential amplifier connected in sequence; The voltage follower is used to buffer and isolate the differential signal; the filter circuit is used to suppress high-frequency noise in the isolated differential signal; and the fully differential amplifier is used to amplify the gain and optimize the common-mode level of the filtered differential signal.

4. The multi-channel pressure and temperature acquisition system according to claim 3, characterized in that, The temperature signal conditioning channel includes an onboard temperature sensor; The output of the onboard temperature sensor is connected in sequence to the voltage follower, the filter circuit, and the fully differential amplifier.

5. The multi-channel pressure and temperature acquisition system according to claim 1, characterized in that, The data acquisition module includes: an analog-to-digital converter; the first channel of the analog-to-digital converter is used to perform analog-to-digital conversion on the conditioned differential signal; the second channel of the analog-to-digital converter is used to perform analog-to-digital conversion on the conditioned ambient temperature signal.

6. The multi-channel pressure and temperature acquisition system according to claim 1, characterized in that, The preprocessing process of digital signals by the FPGA at the acquisition end includes: To concatenate byte-by-byte data of a digital signal into a complete bit-width data; Based on the complete bit-width data, it is encapsulated according to a preset format; the encapsulation includes: frame header, frame count, ambient temperature signal and differential signal; The preprocessed signal is transmitted to the transmission terminal FPGA via a parallel PCM interface.

7. The multi-channel pressure and temperature acquisition system according to claim 1, characterized in that, The FPGA at the transmission end integrates a FIFO buffer unit and a protocol conversion module. The protocol conversion module is driven by a finite state machine and is used to debouncing and converting the preprocessed signal from serial to parallel before transmitting it to the FIFO buffer unit; and to encapsulate the buffered data in the FIFO buffer unit into parallel frame format data that matches the CSI interface of the ARM processor.

8. The multi-channel pressure and temperature acquisition system according to claim 1, characterized in that, It also includes a data transmission module; The data transmission module is connected to the ARM processor and is used to transmit the compensated differential signal to the host computer.

9. The multi-channel pressure and temperature acquisition system according to claim 8, characterized in that, The data transmission module includes an Ethernet PHY chip and a network transformer; The Ethernet PHY chip is used to connect to the Ethernet controller integrated inside the ARM processor via the RGMII interface of the ARM processor. The network transformer is connected to the Ethernet PHY chip via a differential signal line and to the host computer via an RJ45 interface.

10. A multi-channel pressure and temperature acquisition method, applied to the multi-channel pressure and temperature acquisition system according to any one of claims 1-9, characterized in that, include: The FPGA control channel selection module at the acquisition end polls and selects multiple differential signals, and synchronously controls the analog-to-digital converter to convert the conditioned analog signals into digital signals; After the acquisition-end FPGA preprocesses the digital signal, it transmits the preprocessed signal to the transmission-end FPGA. The FPGA at the transmission end performs protocol conversion on the preprocessed signal, generates the parsed signal, and then transmits it to the ARM processor. The ARM processor performs real-time temperature compensation on the conditioned differential signal based on the parsed signal and the fitting coefficient of the channel pressure sensor, combined with the conditioned ambient temperature signal; and transmits the temperature-compensated differential signal to the host computer.

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