Sequential read method for flash memory controller
By using a sequential read method in the flash memory controller and pre-issuing sequential cache read commands, the cache read hit rate is improved, the problem of long read operation time is solved, and system performance is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 深圳市欣芯半导体有限公司
- Filing Date
- 2024-12-31
- Publication Date
- 2026-06-30
AI Technical Summary
Existing flash memory controllers have long read operation times, which affects system performance.
By pre-issuing sequential cache read commands, the cache read hit rate is improved and the read waiting time is reduced. The sequential read method is used to save read operation time.
This effectively reduces read latency and improves the read performance of the flash memory controller.
Smart Images
Figure CN122308712A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of control methods for flash memory controllers, and more particularly to a sequential read method for flash memory controllers. Background Technology
[0002] The flash memory controller performs read operations on the flash memory by sending read commands to it. The flash memory includes multiple chip enable spaces, and each chip enable space includes multiple chips. Furthermore, each chip enable space is coupled to the flash memory controller via a channel to transmit data and commands.
[0003] Figure 1 This is a timing diagram showing the flash memory controller performing read operations on all chips in all chip enable spaces 811-814 on one of the channels CH(#) in response to read commands 91-98 from the host. The data read includes data 721-728 stored in the flash memory. The flash memory controller sequentially transmits a sequence of read commands to each chip enable space 811-814 according to the host's read commands 91-98. Figure 1 It can be seen that each read operation includes a read latency tR. Depending on the design specifications, the read latency is approximately 56 microseconds (μS).
[0004] In today's world where every second counts, further reducing the time spent on the aforementioned read operations would help improve system performance. Therefore, providing a sequential read method for a flash memory controller that can save read operation time is one of the most important research topics at present. Summary of the Invention
[0005] To achieve the above objectives, the present invention provides a sequential read method for a flash memory controller, which improves the cache read hit rate by pre-issuing a sequential cache read command, thereby saving read waiting time and improving sequential read performance.
[0006] This invention provides a sequential read method for a flash memory controller, comprising the following steps: Step 1: sequentially receiving multiple read instructions from a host; Step 2: determining whether the multiple read instructions have consecutive logical block addresses (LBAs); Step 3: entering a sequential read state when the number of read instructions with consecutive logical addresses reaches a preset value; and Step 4: executing the sequential cache read instructions.
[0007] In one embodiment, the consecutive logical addresses are the starting logical address (SLBA) of the received read instruction plus the read length equal to the starting logical address of the next read instruction.
[0008] In one embodiment, the sequence read state is achieved by adding a sequence cache read instruction to the read instruction, and there is no read wait time in subsequent read instructions.
[0009] In one embodiment, the processing time of the sequence cache read instruction is less than the processing time of the read wait.
[0010] In one embodiment, during the sequence read state, the sequence read state ends when the pre-issued sequence cache read instruction fails to hit the next read instruction.
[0011] In one embodiment, the flash memory controller issues an abort sequence cache read instruction to end the sequence read state.
[0012] In one embodiment, a miss means that the data read by the sequence cache read instruction is different from the data to be read by the next read instruction from the host.
[0013] In one embodiment, before executing the sequence cache read instruction, the method further includes, in the sequence read state, confirming that the flash memory controller has instructed a flash memory module to start a read operation, but the flash memory module has not yet output the corresponding data.
[0014] In one embodiment, the read operation is initiated by the flash memory module reading the data and temporarily storing it in the flash memory module's temporary storage area.
[0015] In one embodiment, before executing the sequence cache read instruction, the method further includes, while in the sequence read state, confirming that the flash memory controller has not received any new read instructions from the host.
[0016] As described above, the sequential read method of the flash memory controller of the present invention uses sequential read instructions under specific conditions to save read waiting time and improve the read performance of the flash memory controller. Attached Figure Description
[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0018] Figure 1 This is a timing diagram for executing a read instruction in a known technique.
[0019] Figure 2 A block diagram showing a memory device used in conjunction with the sequence reading method of a preferred embodiment of the present invention.
[0020] Figure 3 This is a flowchart of a sequential read method for a flash memory controller according to a preferred embodiment of the present invention.
[0021] Figure 4 A timing diagram illustrating the execution of a typical read instruction by the flash memory controller.
[0022] Figure 5 This is a timing diagram of a sequential read method for a flash memory controller according to a preferred embodiment of the present invention.
[0023] Figure 6 This is a detailed flowchart of the sequence read method for the flash memory controller.
[0024] Figure label:
[0025] 100: Memory device
[0026] 110: Flash memory module
[0027] 111: The First Chip Enables Space
[0028] 112: Second Chip Enablement Space
[0029] 113: The Third Chip Enables Space
[0030] 114: The Fourth Chip Enablement Space
[0031] 120: Flash memory controller
[0032] 121: Processor
[0033] 122: Memory
[0034] 721~728, D10~D18: Data
[0035] 811-814: Chip-Enabled Space
[0036] 91~98, h0, h1~h8: Read instructions
[0037] CH(0)~CH(3): Channels
[0038] C1~C16: Chips
[0039] ALE: Address Information
[0040] tR: Read wait time
[0041] S11~S16, S21~S26: Steps Detailed Implementation
[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0043] Figure 2 This is a schematic diagram of a memory device 100 used in conjunction with the sequence reading method of a preferred embodiment of the present invention. The memory device 100 includes a flash memory module 110 and a flash memory controller 120. The flash memory controller 120 is used to access the flash memory module 110 according to a command from a host.
[0044] The memory device 100 can be a portable memory device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards), and the host is another electronic device that can be connected to the memory device 100, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the memory device 100 can be a solid-state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, to be installed in an electronic device, such as a mobile phone, laptop, or desktop computer, and in this case, the host can be a processing unit of the electronic device.
[0045] The flash memory controller 120 includes a processor 121 and a memory 122 coupled to each other. The memory 122 is used to store program code.
[0046] The flash memory module 110 may include multiple flash memory chips, such as chips C1, C2…CN, where N is a positive integer greater than 1. In this embodiment, the flash memory module 110 includes 16 chips, but this is not a limitation. Each chip C1 to C16 of the flash memory module 110 includes multiple blocks, and each block includes multiple pages. A page is typically the smallest unit of programming. That is, a page is the smallest unit for writing or reading data. When accessing one or more pages of data, the flash memory controller 120 accesses one or more pages of data according to preset access parameters and performs decoding operations on the accessed page data. In this embodiment, the flash memory module 110 is a NAND-type flash memory module, but this is not a limitation.
[0047] Continue reading Figure 2The flash memory controller 120 accesses the flash memory module 110 in parallel via multiple channels. In this embodiment, the processor 121 of the flash memory controller 120 includes four channels CH(0) to CH(3), and each channel is shared by four chips, unless otherwise specified. The flash memory module 110 includes a first chip enable space 111, a second chip enable space 112, a third chip enable space 113, and a fourth chip enable space 114. The processor 121 of the flash memory controller 120 is coupled to the first chip enable space 111, the second chip enable space 112, the third chip enable space 113, and the fourth chip enable space 114 of the flash memory module 110 through channels CH(0) to CH(3) to transmit data and instructions. The processor 121 of the flash memory controller 120 transmits chip enable signals CE(0) to CE(3) to access the corresponding chip enable space on the corresponding channel. In this embodiment, the processor 121 uses multiple electronic signals to coordinate data and instruction transmission between the flash memory controller 120 and the flash memory module 110, including data lines, frequency signals, and control signals. The data lines can be used to transmit instructions, addresses, and data for reading and writing. The control signal lines can be used to transmit control signals such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), and Write Enable (WE).
[0048] Chip enable signal CE(0) enables chips C1 to C4 located on all channels CH(0) to CH(3) and in the first chip enable space 111. Chip enable signal CE(1) enables chips C5 to C8 located on all channels CH(0) to CH(3) and in the second chip enable space 112. Chip enable signal CE(2) enables chips C9 to C12 located on all channels CH(0) to CH(3) and in the third chip enable space 113. Chip enable signal CE(3) enables chips C13 to C16 located on all channels CH(0) to CH(3) and in the fourth chip enable space 114. In this embodiment, chip enable signals CE(0), CE(1), CE(2), and CE(3) are enabled in an interleaved manner. Through multiple channels CH(0)~CH(3), the chip enable space 111~114, which is enabled by the chip enable signals CE(0)~CE(3) in one cycle, is accessed in parallel.
[0049] Next, please refer to Figure 3 The following diagram illustrates a sequential read method for a flash memory controller according to a preferred embodiment of the present invention, which includes steps S11 to S13.
[0050] Before proceeding with the sequential read method of the flash controller, the operating procedure of the flash controller 120 in normal mode in response to read commands from the host will be described first. Please refer to... Figure 4 As shown, the host's read instruction h0 is used as an example. Read instruction h0 is a typical read instruction sequence, including instructions 00h, 30h, 06h, and E0h. The processor 121 of the flash memory controller 120 transmits instruction "00h" to the flash memory module 110. Instruction "00h" instructs the flash memory module 110 to receive address information ALE, i.e., an address receive instruction. Next, the flash memory controller 120 transmits the address information ALE to the flash memory module 110. Then, the flash memory controller 120 transmits instruction "30h" to the flash memory module 110. Instruction "30h" instructs the flash memory module 110 to begin a read operation based on the received instruction and address information, so that data is read and temporarily stored in the temporary storage area of the flash memory module 110. If the chip's register stores instruction "30h", the read operation begins, and the device changes from a ready state to a busy state. That is, in... Figure 4 The value in tR represents the read wait time during the read operation, during which the chip remains in a busy state.
[0051] like Figure 4 As shown, in response to the completion of the read operation, the flash memory controller 120 receives the data D10 read by the flash memory module 110. In this embodiment, firstly, the flash memory controller 120 transmits the instruction "06h" to the flash memory module 110. The instruction "06h" is an instruction instructing the flash memory module 110 to receive the address information ALE, i.e., an address reception instruction. Secondly, the flash memory controller 120 transmits the address information ALE corresponding to the transmitted data to the flash memory module 110. Next, the flash memory controller 120 transmits the instruction "E0h" to the flash memory module 110. The instruction "E0h" is an instruction used to instruct the flash memory module 110 to output data to the flash memory controller 120 based on the previously transmitted address information ALE. According to the read instruction... h0 The flash memory controller 120 is able to instruct the transmission of data D10 to the flash memory module 110.
[0052] Please see Figure 3 In conjunction with the above, step S11 involves the flash memory controller 120 sequentially receiving multiple read commands from the host. In this embodiment, the flash memory controller 120 sequentially receives the read commands from the host as described above. In the following description, only the host read commands h1 to h8 are used as examples, but they are not intended to be limiting.
[0053] Step S12 is to determine whether multiple read instructions have consecutive logical addresses. In this embodiment, consecutive logical addresses are determined based on the address information in the aforementioned read instructions. Specifically, if the start logical block address (SLBA) of the first received read instruction plus the read length equals the start logical address of the next (i.e., the second) read instruction, then it is determined to be "consecutive".
[0054] Step S13 is to enter the sequence read state and issue a sequence cache read instruction in advance when the number of read instructions with consecutive logical addresses reaches a preset value.
[0055] like Figure 5 As shown, it displays the timing diagram of the response to the host's read commands h1 to h8 after entering the sequence read state. Figure 5 As can be seen from the text, in the read instructions during the sequential read state, after the instruction "30h" instructing the flash memory module 110 to start the read operation, the flash memory controller 120 also transmits the sequential cache read instruction "31h". It is worth noting that the function of instruction "31h" is to immediately pre-read the next piece of data after instruction "30h" has finished reading the data. Therefore, instruction "31h" does not contain address information, but directly continues reading the next piece of data based on the position read by instruction "30h". Because it does not require the tR time, including the time for decoding address information, as instruction "30h" does, instruction "31h" has a faster read speed.
[0056] In response to the sequential cache read instruction "31h", the first chip enable space 111, in response to the host's read instruction h5, can directly instruct the flash memory module 110 to transmit data D15 without the aforementioned read wait time tR. Since the data pre-read from the flash memory module 110 and stored in its temporary storage area by instruction "31h" is precisely the data that instruction "h5" needs to read (this data can be determined by the read address carried by instruction "h5"), the data stored in the temporary storage area of the flash memory module 110 can be immediately returned to instruction "h5", thus avoiding the wait time tR. In this embodiment, the processing time of the sequential cache read instruction "31h" is approximately 3 microseconds (μS), far less than the 56μS read wait time, thus significantly saving execution time. Furthermore, the preset values in this embodiment can be defined by the user, for example, 3 times, 5 times, or 50 times, without limitation.
[0057] On the other hand, the prerequisite for executing the sequence cache read instruction "31h" also includes that, in the sequence read state, before directly instructing the flash memory module 110 to transmit data, the flash memory controller 120 is in a state where it has issued the instruction "30h" to instruct the flash memory module 110 to start the read operation, but has not yet issued the instruction "E0h" to output data to the flash memory controller 120 (as in step S14), and has not received a new read instruction from the host (as in step S15). That is, the execution of the sequence cache read instruction in step S16 is only executed after confirmation in steps S14 and S15.
[0058] In other words, in this embodiment, the following conditions must be met for the sequential cache read instruction "31h" to be executed: (1) the number of read instructions with consecutive logical addresses reaches a preset value; (2) the flash controller does not receive a new read instruction from the host; and (3) the flash controller is in a state where the instruction "30h" has been issued but the instruction "E0h" has not been executed.
[0059] Finally, when a sequential cache read instruction misses the next read instruction, meaning the data read by the sequential cache read instruction is different from the data to be read by the next read instruction from the host, the flash controller 120 issues a stop sequential cache read instruction to end the sequential read state. For example, if the data pre-read from the flash module 110 and stored in the temporary storage area of the flash module 110 in response to instruction "31h" is different from the data to be read by read instruction "h5", or if instruction "h5" is a write instruction, both of which result in a miss, the flash controller 120 will issue a stop sequential cache read instruction to end the sequential read state.
[0060] Please refer to the following: Figure 6 The diagram illustrates a preferred embodiment of the sequence reading method of the present invention, which includes steps S21 to S26. Step S21 involves determining whether a read command has been received. If the determination result is "yes", step S22 is executed; if the determination result is "no", step S21 is re-executed or the process ends.
[0061] Step S22 records the address information in the read instruction. Next, step S23 determines whether the recorded address information is "contiguous" with the address information in the previous read instruction. The definition of contiguous is the same as described above and will not be repeated here. If the determination result is "yes," step S24 is executed; if the determination result is "no," step S21 is re-executed or the process ends.
[0062] Step S24 involves accumulating the count value. In this embodiment, the count value starts from 0 and increments by 1 each time the condition is met, and is not restrictive. Next, step S25 is executed, which determines whether the count value is equal to a preset value. If the determination result is "yes", step S26 is executed; if the determination result is "no", step S21 is repeated or the process ends. In this embodiment, the preset value is, for example, 3, and is not restrictive; it can be any integer or symbol.
[0063] Step S26 involves entering the sequence read state. The sequence read state is as described in steps S13 to S16 above, and for the sake of brevity, it will not be repeated here. On the other hand, it should be noted that in the sequence read state, if the sequence cache read instruction does not hit the next read instruction, that is, the predicted instruction or address information is different from the next read instruction and the address it points to, then the sequence read state ends.
[0064] In summary, the sequential read method for a flash memory controller disclosed in this invention improves the cache hit rate and reduces the read latency of the flash memory module by pre-issuing sequential cache read instructions when the host read instructions meet specific conditions, namely, consecutive read instructions and read data from consecutive addresses. Therefore, this invention effectively improves the performance of sequential reads and reduces the performance loss caused by latency.
[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the methods and techniques disclosed above without departing from the scope of the present invention to create equivalent embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A method for sequential reading of a flash memory controller, characterized in that, The method includes: A flash memory controller sequentially receives multiple read commands from a host computer; Determine whether the multiple read instructions have consecutive logical addresses; When the number of read instructions with consecutive logical addresses reaches a preset value, a sequential read state is entered; and Execute a series of cache read instructions.
2. The sequence reading method as described in claim 1, characterized in that, The consecutive logical addresses are the starting logical address of the received read instruction plus the read length, which equals the starting logical address of the next read instruction.
3. The sequence reading method as described in claim 1, characterized in that, The sequence read state is achieved by adding the sequence cache read instruction to the read instruction.
4. The sequence reading method as described in claim 3, characterized in that, The processing time of the sequence cache read instruction is less than the processing time of the read wait time.
5. The sequence reading method as described in claim 1, characterized in that, In the sequence read state, the sequence read state ends when the next read instruction is not hit by the sequence cache read instruction.
6. The sequence reading method as described in claim 5, characterized in that, The flash memory controller issues an abort sequence cache read instruction to end the sequence read state.
7. The sequence reading method as described in claim 5, characterized in that, A miss occurs when the data read by the sequence cache read instruction is different from the data to be read by the next read instruction from the host.
8. The sequence reading method as described in claim 1, characterized in that, Before executing the sequence cache read instruction, the method further includes confirming, in the sequence read state, that the flash controller has instructed a flash module to start a read operation, but the flash module has not yet output the corresponding data.
9. The sequence reading method as described in claim 8, characterized in that, The start-read operation is performed by the flash memory module reading out the data and temporarily storing it in the temporary storage area of the flash memory module.
10. The sequence reading method as described in claim 1, characterized in that, Before executing the sequential cache read instruction, the method also includes, while in sequential read mode, confirming that the flash memory controller has not received any new read instructions from the host.