A hybrid instruction system pre-decoding method, device, processor and electronic equipment

Abstract

This invention discloses a pre-decoding method, apparatus, and electronic device for a hybrid instruction set, relating to the field of processor technology, which can improve the accuracy and efficiency of instruction boundary estimation. The pre-decoding method is executed during instruction fetch-back instruction cache execution and applied to instruction groups written to the instruction cache; the instruction group includes at least one instruction of a first length and / or at least one instruction of a second length, the second length being twice the first length; wherein the second length instruction has an identifier code characterizing its instruction boundary; the method includes: instruction boundary estimation: determining the instruction boundary of the first instruction of the instruction group based on the identifier code; and estimating the instruction boundaries of subsequent instructions based on the previous instruction boundary and the identifier code, following a serial direction from the first instruction to the last instruction. This invention is applicable to the design field of CPUs with hybrid instruction sets.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a pre-decoding method, apparatus, processor, and electronic device for a hybrid instruction set. Background Technology

[0002] When designing a multi-issue CPU (Central Processing Unit), the instruction execution process must be considered. For example, the instruction decoding stage requires splitting mixed instruction sets containing both 16-bit and 32-bit instructions to determine the relative position of each instruction within the set, thus identifying the boundaries of each instruction and facilitating correct execution. Instruction decoding also requires determining the instruction type and function; completing these tasks within a single cycle results in a very long logic chain in the instruction decoding stage.

[0003] If instruction splitting were performed in a separate pipeline stage, it would consume a significant amount of combinational logic resources, making the timing of subsequent instruction decoding operations even more demanding. This would lead to longer processor cycles, lower operating frequencies, and severely impact processor performance. Therefore, instruction pre-decoding was developed to address this issue, performing some instruction splitting operations in the pre-decoding stage to alleviate timing burdens on the instruction decoding phase.

[0004] Current instruction pre-decoding methods cannot obtain accurate instruction boundaries. The key to timing convergence is to calculate the correct instruction boundaries during pre-decoding. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a pre-decoding method, apparatus, processor, and electronic device for hybrid instruction systems, which can improve the accuracy and efficiency of instruction boundary inference.

[0006] In a first aspect, embodiments of the present invention provide a pre-decoding method for a hybrid instruction system. The method is executed during instruction fetch-write-back instruction buffering and applied to instruction groups written to the instruction buffer. The instruction group includes at least one instruction of a first length and / or at least one instruction of a second length, the second length being twice the first length. The second length instruction has an identifier code characterizing its instruction boundary. The method includes: instruction boundary estimation: determining the instruction boundary of the first instruction in the instruction group based on the identifier code; if the first instruction has the identifier code, it is a second length instruction; if it does not have the identifier code, it is a first length instruction; and estimating the instruction boundaries of subsequent instructions based on the previous instruction boundary and the identifier code, following a serial direction from the first instruction to the last instruction.

[0007] According to a specific implementation of an embodiment of the present invention, for two logically adjacent instruction groups, if there is a first incomplete instruction at the end of the preceding instruction group, the first incomplete instruction is merged with a second incomplete instruction at the beginning of the following instruction group to form a complete instruction, and then the instruction boundary is inferred from the complete instruction and other instructions in the following instruction group.

[0008] According to a specific implementation of an embodiment of the present invention, if the starting address of the instruction group is not zero, the instruction pointed to by the starting address is taken as the first instruction of the instruction group.

[0009] According to a specific implementation of an embodiment of the present invention, the hybrid instruction system is RISC-V; the first length is 16 bits; the second length is 32 bits, including a high half-word and a low half-word, and the identifier code is located in the low half-word.

[0010] According to a specific implementation of an embodiment of the present invention, if the length of the instruction group is 16 × 16 bits = 32 B, the instruction boundary of the instruction group is inferred in two clock cycles. In the first cycle, the instruction boundary of the lower 16 B bits and the instruction boundary of the higher 16 B bits of the instruction group are inferred with a granularity of 16 B bits. In the second cycle, the instruction boundary of the higher 16 B bits is verified based on the instruction boundary of the lower 16 B bits, thereby obtaining the instruction boundary of the instruction group with a length of 32 B bits.

[0011] According to a specific implementation of an embodiment of the present invention, the instruction boundary of the first instruction obtained by inferring the first instruction is used as the pre-decoding first boundary, and the instruction boundary of the first instruction obtained by splitting the instruction group to be decoded in the decoding stage is used as the decoding first boundary. Based on the relative position of the decoding first boundary in the instruction group, the pre-decoding first boundary with the same relative position is suitable for matching with the decoding first boundary, so as to map each instruction boundary of the instruction group starting from the pre-decoding first boundary to the instruction decoding stage for direct instruction splitting.

[0012] According to a specific implementation of an embodiment of the present invention, the method further includes: instruction boundary repair: when an instruction boundary error occurs, the instruction boundary estimation is restarted from the error location; the instruction boundary error is: the instruction boundary estimation result should be the location of the instruction boundary, but the actual stored instruction content is not the instruction boundary; or, the instruction boundary estimation result is not the location of the instruction boundary, but the actual stored instruction content is the instruction boundary.

[0013] According to a specific implementation of an embodiment of the present invention, the instruction boundary error state is as follows: the boundary prediction result of the 32-bit instruction should be the position of the instruction boundary, but the high half-word of the 32-bit instruction is actually stored; or, the boundary prediction result of the 32-bit instruction is not the position of the instruction boundary, but the low half-word of the 32-bit instruction is actually stored.

[0014] Secondly, embodiments of the present invention provide a pre-decoding apparatus for a hybrid instruction system. The apparatus pre-decodes an instruction group written to the instruction cache during instruction fetch-write-back. The instruction group includes at least one instruction of a first length and / or at least one instruction of a second length, the second length being twice the first length. The second length instruction has an identifier code characterizing its instruction boundary. The apparatus includes: an instruction boundary estimation circuit: used to determine the instruction boundary of the first instruction in the instruction group based on the identifier code; if the first instruction has the identifier code, it is a second length instruction; if it does not have the identifier code, it is a first length instruction; and to estimate the instruction boundaries of subsequent instructions based on the previous instruction boundary and the identifier code, following a serial direction from the first instruction to the last instruction.

[0015] According to a specific implementation of an embodiment of the present invention, the instruction boundary estimation circuit is further configured to: for two logically adjacent instruction groups, if the tail of the preceding instruction group contains a first incomplete instruction, merge the first incomplete instruction with the head of the following instruction group to form a complete instruction, and then perform the instruction boundary estimation on the complete instruction and other instructions of the following instruction group.

[0016] According to a specific implementation of an embodiment of the present invention, the instruction boundary speculation circuit is further configured to: when the starting address of the instruction group is non-zero, take the instruction pointed to by the starting address as the first instruction of the instruction group.

[0017] According to a specific implementation of an embodiment of the present invention, the hybrid instruction system is RISC-V; the first length is 16 bits; the second length is 32 bits, including a high half-word and a low half-word, and the identifier code is located in the low half-word.

[0018] According to a specific implementation of an embodiment of the present invention, the instruction boundary estimation circuit is further configured to: if the length of the instruction group is 16 × 16 bits = 32 B, then in the timing, the instruction boundary of the instruction group is estimated in two steps, wherein the first step estimates the instruction boundary of the lower 16 B bits and the instruction boundary of the higher 16 B bits of the instruction group in 16 B granularity, and the second step verifies the instruction boundary of the higher 16 B bits based on the instruction boundary of the lower 16 B bits, thereby obtaining the instruction boundary of the instruction group with a length of 32 B bits.

[0019] According to a specific implementation of an embodiment of the present invention, the instruction boundary estimation circuit is further configured to: use the estimated instruction boundary of the first instruction as the pre-decoding first boundary, and use the instruction boundary of the first instruction obtained by splitting the instruction group to be decoded in the decoding stage as the decoding first boundary; based on the relative position of the decoding first boundary in the instruction group, the pre-decoding first boundary with the same relative position is adapted to be matched with the decoding first boundary, so as to map each instruction boundary of the instruction group starting from the pre-decoding first boundary to the instruction decoding stage for direct instruction splitting.

[0020] According to a specific implementation of an embodiment of the present invention, the apparatus further includes: an instruction boundary repair circuit: used to return to the instruction boundary estimation circuit from the error position to re-perform instruction boundary estimation when an instruction boundary error state occurs; the instruction boundary error state is: the instruction boundary estimation result should be the position of the instruction boundary, but the actual stored instruction content is not the instruction boundary; or, the instruction boundary estimation result is not the position of the instruction boundary, but the actual stored instruction content is the instruction boundary.

[0021] According to a specific implementation of an embodiment of the present invention, the instruction boundary error state is as follows: the boundary prediction result of the 32-bit instruction should be the position of the instruction boundary, but the high half-word of the 32-bit instruction is actually stored; or, the boundary prediction result of the 32-bit instruction is not the position of the instruction boundary, but the low half-word of the 32-bit instruction is actually stored.

[0022] Thirdly, embodiments of the present invention provide a processor, including: a pre-decoding device for a hybrid instruction set as described in any embodiment of the first aspect, wherein the pre-decoding device for a hybrid instruction set is adapted to perform a pre-decoding method for a hybrid instruction set as described in any embodiment of the second aspect.

[0023] Fourthly, embodiments of the present invention provide an electronic device, the electronic device comprising: a housing, a processor as described in any embodiment of the third aspect, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; and the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory.

[0024] This invention provides a pre-decoding method, apparatus, processor, and electronic device for a hybrid instruction set. It infers the boundaries of each instruction in an instruction group using pre-defined pre-decoding rules. Specifically, it determines the instruction boundary of the first instruction based on an identifier code, and then sequentially infers the boundaries of subsequent instructions starting from the first instruction boundary. That is, it infers the instruction boundaries of each subsequent instruction based on the previous instruction boundary and its identifier code. The previous instruction boundary serves as the position reference for the next instruction, used to infer the expected starting position of the next instruction. The identifier code serves as a boundary determination marker for the next instruction. By determining whether the identifier code actually exists at the expected starting position, if it does, the position is the instruction boundary, and the previously inferred position is correct; if it does not exist, the position is not actually the instruction boundary, and the previously inferred position is incorrect. For instruction groups where instructions are executed sequentially, this embodiment ensures the correctness of the instruction boundary inference, thereby effectively sharing the timing burden of the instruction decoding stage. The instruction boundary inference in this embodiment is performed sequentially and systematically, resulting in fast inference speed and high inference efficiency. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the first embodiment of the pre-decoding method for the hybrid instruction system of the present invention; Figure 2 This is a schematic diagram of the first embodiment of the pre-decoding device for the hybrid instruction system of the present invention; Figure 3 This is a schematic diagram illustrating the matching process between the first decoding boundary and two pre-decoding first boundaries in any embodiment of the pre-decoding method for the hybrid instruction system of the present invention; Figure 4 This is a schematic diagram of three decoding first boundaries in any embodiment of the pre-decoding method for the hybrid instruction system of the present invention; Figure 5 This is a schematic diagram of an error state requiring instruction boundary repair in any embodiment of the pre-decoding method for the hybrid instruction system of the present invention. Detailed Implementation

[0027] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] This embodiment provides a pre-decoding method for hybrid instruction systems, which can improve the accuracy and efficiency of instruction boundary inference.

[0029] Figure 1 This is a schematic diagram of the first embodiment of the pre-decoding method for the hybrid instruction system of the present invention, as shown below. Figure 1 As shown, the application scenario of this embodiment is the design of a CPU with a hybrid instruction set.

[0030] The method of this embodiment is executed during instruction fetch-write-back instruction buffering and applied to instruction groups written to the instruction buffer; the instruction group includes at least one instruction of a first length and / or at least one instruction of a second length, the second length being twice the first length; wherein, the second length instruction has an identifier code characterizing its instruction boundary; the method includes: instruction boundary estimation: determining the instruction boundary of the first instruction of the instruction group based on the identifier code, if the first instruction has the identifier code, it is the second length instruction, if it does not have the identifier code, it is the first length instruction; according to the serial direction from the first instruction to the last instruction, estimating the instruction boundaries of subsequent instructions based on the previous instruction boundary and the identifier code.

[0031] In this embodiment, taking the RISC-V instruction set as an example, it includes mixed instructions of two different lengths: 16-bit and 32-bit. The first length is 16-bit, and the second length is 32-bit. A 32-bit instruction consists of two equal-length half-words. The boundary of a 32-bit instruction is determined by whether the lowest two bits of a half-word are binary "11". For example... Figure 1 As shown, the length of the previous instruction block is 32bit + 32bit + 16bit + 32bit + 16bit. Figure 1 Each square in the code represents a half word. The instruction code is arranged from the least significant bit to the most significant bit, from left to right. Accordingly, for a 32-bit instruction, the half word on the left is the least significant half word (or simply the low half word), and the half word on the right is the most significant half word (or simply the high half word).

[0032] In this embodiment, the instruction boundary estimation is performed serially for the instruction code, and the serial direction is... Figure 1The direction is from left to right. The lowest 2 bits of the lower half-word of the first 32-bit instruction are binary "11". This lower half-word is determined to be the instruction boundary of the first instruction. Together with the upper half-word on the right, it forms the complete 32-bit instruction; that is, the upper half-word is the end position of the 32-bit instruction. It should be noted that, according to... Figure 1 From left to right, this instruction boundary is the start boundary, indicating the beginning of an instruction, not the end boundary. Next, to infer the boundary of the second instruction, since the first instruction ends at the second half-word, the starting position of the second instruction, i.e., the instruction boundary, should be at... Figure 1 At the third half-word, then analyze whether the lowest 2 bits of the instruction code at the third half-word are binary "11". Figure 1 The code shows "11", so the boundary of the second 32-bit instruction is determined to be at the third half-word. Next, to deduce the boundary of the third instruction, since the second 32-bit instruction ends at the fourth half-word, the starting position of the third instruction, i.e., the instruction boundary, should be at... Figure 1 At the fifth half-word, then analyze whether the lowest 2 bits of the instruction code at the fifth half-word are binary "11". Figure 1 If the value shown is not "11", then the fifth half-word is determined to be the boundary of a 16-bit instruction, not a 32-bit instruction. Next, to deduce the boundary of the fourth instruction, since the third instruction is a 16-bit instruction, occupying only one half-word, and ends at the fifth half-word, the starting position of the fourth instruction, i.e., the instruction boundary, should be at... Figure 1 At the 6th half-word, then analyze whether the lowest 2 bits of the instruction code at the 6th half-word are binary "11". Figure 1 The code shows "11", so the boundary of the fourth instruction (32 bits) is determined to be at the 6th half-word. Next, to deduce the boundary of the fifth instruction, since the fourth 32-bit instruction ends at the 7th half-word, the starting position of the fifth instruction, i.e., the instruction boundary, should be at... Figure 1 At the 8th half-word, which is the last half-word, we then analyze whether the lowest 2 bits of the instruction code at the 6th half-word are binary "11". Figure 1 The example shows "11", so the boundary of the fifth instruction (32 bits) is determined to be at the 8th half-word. It's important to note that the lower half-word of this fifth 32-bit instruction is in the preceding instruction group, and the higher half-word is in the following instruction group; this is considered a cross-instruction-group situation. Of course, if the last half-word of the preceding instruction group is a 16-bit instruction, then it is considered a non-cross-instruction-group situation. Therefore, if each half-word is used as the boundary for instruction determination, whether the following half-word is an instruction boundary is closely related to whether the preceding half-word is an instruction boundary. Figure 1The Fetch Group in this context refers to the instruction group. It should be noted that for cross-instruction group cases, the two instruction groups should be logically adjacent. That is, the half-word at the end of the preceding instruction group and the half-word at the beginning of the following instruction group must form a complete 32-bit instruction. In other words, the following instruction group knows that its own half-word at the beginning is part of the 32-bit instruction starting at the end of the preceding instruction group.

[0033] In this embodiment, the process of inferring instruction boundaries is illustrated using an instruction group of length 16 × 16 bits = 32 bytes as an example. Figure 2 As shown, instruction boundary estimation is performed serially, where Hx represents the x-th Half Word. It is important to note that instruction boundary estimation is performed separately for both cases where the instruction crosses a Fetch Group and cases where the instruction does not cross a Fetch Group, resulting in two different instruction boundary scenarios. Figure 2 In the table, the second line represents cases that cross Fetch Groups, and the third line represents cases that do not cross Fetch Groups.

[0034] Figure 2 In this context, Bry0 represents the case where the lowest half word of the Fetch Group is not an instruction boundary; Bry1 represents the case where the lowest half word of the Fetch Group is an instruction boundary. Considering that instruction boundary speculation is performed serially and the combinational logic chain is relatively long, it is split into two steps. In the first step, Bry0 / Bry1 are speculated in 16-bit units to obtain two instruction boundaries: a high 16-bit boundary and a low 16-bit boundary. In the second step, based on the low 16-bit boundary, the high 16-bit boundary is selected, thus obtaining two 32-bit instruction boundaries.

[0035] Figure 2 In the expression `Bry0LHwLeft`, when performing instruction boundary speculation using `Bry0`, it indicates whether `H8` is the low half word of a 32-bit instruction. If so, then `H9` is the high half word of a 32-bit instruction, and `Bry0H` is chosen as the subsequent instruction boundary for `Bry0L`. Conversely, if `H9` is not a high half word, then `Bry1H` is chosen as the subsequent instruction boundary for `Bry0L`. Similarly, for `Bry1L`, the choice between `Bry0H` or `Bry1H` depends on the condition of `H8`.

[0036] At the same time, when the starting address of a Fetch Group is determined to be non-zero, this address is the target address of a branch jump, and the Half Word pointed to by the starting address is the boundary of the instruction.

[0037] In this embodiment, the instruction boundary of the inferred first instruction is used as the pre-decoding first boundary, and the instruction boundary of the first instruction obtained by splitting the instruction group to be decoded in the decoding stage is used as the decoding first boundary. Based on the relative position of the decoding first boundary in the instruction group, pre-decoding first boundaries with the same relative position are suitable for matching with the decoding first boundary, so that the inferred instruction boundaries of the instruction group starting from the pre-decoding first boundary are mapped to the instruction decoding stage for direct instruction splitting. In the CPU back-end pipeline, instruction splitting is performed. At this time, the position of the first boundary of a Fetch Group is obtained based on the result of instruction splitting, and this position is matched with the pre-decoded instruction boundary to obtain the correct instruction boundary, such as... Figure 3 As shown.

[0038] Figure 3 Each square in the table represents a Half Word, and 1 indicates the boundary of an instruction. Based on the position of the first instruction boundary in the Fetch Group, the parsing result of Bry1 is found to match it, and subsequent instruction boundaries use the data from Bry1.

[0039] Depending on the scenario, the boundary of the first instruction obtained from the instruction decomposition during the decoding stage can be categorized as follows: Figure 4 As shown: 1. The first instruction boundary begins at the first Half Word of a Fetch Group.

[0040] 2. The first instruction boundary begins at the second Half Word of a Fetch Group. 3. The first instruction boundary begins at a branch jump to the target address of a Fetch Group.

[0041] Similar to Figure 3 The matching process shown involves matching these three cases with the pre-decoding results Bry0 / Bry1, and the pre-decoding result that matches is used.

[0042] In this embodiment, the method further includes: instruction boundary repair: when an instruction boundary error occurs, the instruction boundary estimation is restarted from the error location; the instruction boundary error is defined as follows: the instruction boundary estimation result should be the location of the instruction boundary, but the actually stored instruction content is not the instruction boundary; or, the instruction boundary estimation result is not the location of the instruction boundary, but the actually stored instruction content is the instruction boundary. Corresponding to RISC-V instruction exercises, the instruction boundary error can be: the boundary estimation result for a 32-bit instruction should be the location of the instruction boundary, but the actually stored content is the high half-word of the 32-bit instruction; or, the boundary estimation result for a 32-bit instruction is not the location of the instruction boundary, but the actually stored content is the low half-word of the 32-bit instruction.

[0043] like Figure 5 As shown, the lower two Half Words of a Fetch Group are invalid data; their lower two bits are both binary "10". Assuming a branch jump first jumps to address Target0, boundary speculation begins at address Target0, and the speculation result is written to I... (Instruction cache). Afterwards, the instruction jumps to the Target1 address. At this point, boundary speculation can only guarantee that the boundary after the Target0 address is correct. For the address boundary from Target1 to Target0, since I is used... The boundaries were previously inferred based on Target0, so their correctness cannot be guaranteed. This data could lead the instruction boundaries in the wrong direction.

[0044] At this point, instruction boundary repair needs to be performed. Based on the location of the first error from low to high, instruction boundary repair begins here. Specifically: 1. If an instruction boundary is not found at the intended instruction boundary location, an instruction boundary error is detected, and repair begins.

[0045] When the high half word of a 2.32-bit instruction is mistakenly identified as the instruction boundary, an error in instruction boundary determination occurs, and repair begins.

[0046] When repairing instruction boundaries, the pipeline should be replayed, starting from I again. Read the instructions and re-infer the instruction boundaries from the location of the error.

[0047] This embodiment solves most instruction boundary issues through speculation and addresses the case where instructions start in the middle of a FetchGroup through repair. Combining these two approaches, speculating on instruction boundaries reduces timing overhead and improves the success rate of boundary speculation, while repair ensures the accuracy of instruction boundaries.

[0048] This invention discloses a pre-decoding apparatus for a hybrid instruction system. The apparatus pre-decodes an instruction group written to the instruction cache during instruction fetch-write-back. The instruction group includes at least one instruction of a first length and / or at least one instruction of a second length, the second length being greater than the first length. The second length instruction has an identifier code characterizing its instruction boundary. The apparatus includes an instruction boundary estimation circuit: used to determine the instruction boundary of the first instruction of the second length in the instruction group based on the identifier code; and to estimate the instruction boundaries of subsequent instructions based on the previous instruction boundary and the identifier code, following a serial direction from the first instruction to the last instruction. The advantages of this embodiment are similar to those of the related embodiments of the aforementioned method, and will not be repeated here.

[0049] In a preferred embodiment, the instruction boundary estimation circuit is further configured to: when a first incomplete instruction exists at the end of the instruction group, merge the first incomplete instruction with a second incomplete instruction existing at the beginning of the next instruction group to form a complete instruction, and then perform the instruction boundary estimation on the complete instruction and the other instructions in the next instruction group. The advantages of this embodiment are similar to those of the aforementioned related embodiments of the method, and will not be repeated here.

[0050] In a preferred embodiment, the instruction boundary estimation circuit is further configured to: use the estimated instruction boundary of the first instruction as a pre-decoding first boundary, and use the instruction boundary of the first instruction obtained by splitting the instruction group to be decoded in the decoding stage as a decoding first boundary; based on the relative position of the decoding first boundary in the instruction group, pre-decoding first boundaries with the same relative position are suitable for matching with the decoding first boundary, so as to map each instruction boundary of the instruction group starting from the pre-decoding first boundary to the instruction decoding stage for direct instruction splitting. The advantages of this embodiment are similar to those of the aforementioned related embodiments of the method, and will not be repeated here.

[0051] In a preferred embodiment, the apparatus further includes: an instruction boundary repair circuit: used to return to the instruction boundary estimation circuit from the error position and re-evaluate the instruction boundary when an instruction boundary error occurs; the instruction boundary error is characterized by the instruction boundary estimation result indicating the position of the instruction boundary, but the actually stored instruction content is not an instruction boundary. The advantages of this embodiment are similar to those of the aforementioned related embodiments of the method, and will not be repeated here.

[0052] A processor according to an embodiment of the present invention includes: a pre-decoding device for a mixed instruction set as described in any of the foregoing embodiments, wherein the pre-decoding device for the mixed instruction set is adapted to execute a pre-decoding method for a mixed instruction set as described in any of the foregoing embodiments. The advantages of this embodiment are similar to those of the foregoing embodiments, and will not be repeated here.

[0053] An electronic device according to an embodiment of the present invention includes: a housing, a processor as described in any of the foregoing embodiments, a memory, a circuit board, and a power supply circuit. The circuit board is disposed within the space enclosed by the housing, and the processor and memory are mounted on the circuit board. The power supply circuit supplies power to various circuits or devices of the electronic device. The memory stores executable program code. The processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory. The advantages of this embodiment are similar to those of the foregoing embodiments and will not be repeated here.

[0054] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0055] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0056] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0057] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0058] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A pre-decoding method for a hybrid instruction set, characterized in that, The method is executed during instruction fetch-write-back instruction buffering and applied to instruction groups written to the instruction buffer; the instruction group includes at least one instruction of a first length and / or at least one instruction of a second length, the second length being twice the first length; wherein the second length instruction has an identifier code characterizing its instruction boundary; the method includes: Instruction boundary estimation: The instruction boundary of the first instruction in the instruction group is determined based on the identifier code. If the first instruction has the identifier code, it is a second-length instruction; if it does not have the identifier code, it is a first-length instruction. Following the serial direction from the first instruction to the last instruction, the instruction boundaries of subsequent instructions are estimated based on the boundary of the previous instruction and the identifier code.

2. The pre-decoding method for a hybrid instruction system according to claim 1, characterized in that, For two logically adjacent instruction groups, if the first instruction group has a first incomplete instruction at the end, the first incomplete instruction is merged with the second incomplete instruction at the beginning of the next instruction group to form a complete instruction. Then, the instruction boundary is inferred for the complete instruction and the other instructions in the next instruction group.

3. The pre-decoding method for a hybrid instruction system according to claim 1, characterized in that, If the starting address of the instruction group is not zero, then the instruction pointed to by the starting address shall be the first instruction of the instruction group.

4. The pre-decoding method for a hybrid instruction system according to any one of claims 1-3, characterized in that, The hybrid instruction set is RISC-V; the first length is 16 bits; the second length is 32 bits, including a high half-word and a low half-word, with the identifier code located in the low half-word.

5. The pre-decoding method for a hybrid instruction system according to claim 4, characterized in that, If the length of the instruction group is 16 × 16 bits = 32 bytes, then the instruction boundary of the instruction group is inferred in two clock cycles. In the first cycle, the instruction boundary of the lower 16 bytes and the instruction boundary of the higher 16 bytes of the instruction group are inferred with a granularity of 16 bytes. In the second cycle, the instruction boundary of the higher 16 bytes is verified based on the instruction boundary of the lower 16 bytes, thereby obtaining the instruction boundary of the instruction group with a length of 32 bytes.

6. The pre-decoding method for a hybrid instruction system according to claim 4, characterized in that, The instruction boundary of the first instruction obtained by the inference is taken as the pre-decoding first boundary, and the instruction boundary of the first instruction obtained by splitting the instruction group to be decoded in the decoding stage is taken as the decoding first boundary. According to the relative position of the decoding first boundary in the instruction group, the pre-decoding first boundary with the same relative position is suitable for matching with the decoding first boundary, so as to map the instruction boundaries of the instruction group starting from the pre-decoding first boundary to the instruction decoding stage for direct instruction splitting.

7. The pre-decoding method for a hybrid instruction system according to claim 4, characterized in that, The method further includes: Instruction boundary repair: When an instruction boundary error occurs, the instruction boundary estimation is restarted from the error location; the instruction boundary error is when the instruction boundary estimation result should be the location of the instruction boundary, but the actual stored instruction content is not the instruction boundary; or, the instruction boundary estimation result is not the location of the instruction boundary, but the actual stored instruction content is the instruction boundary.

8. The pre-decoding method for a hybrid instruction system according to claim 7, characterized in that, The instruction boundary error states are as follows: the boundary prediction result for the 32-bit instruction should be the location of the instruction boundary, but the actual stored value is the high half-word of the 32-bit instruction; or, the boundary prediction result for the 32-bit instruction is not the location of the instruction boundary, but the actual stored value is the low half-word of the 32-bit instruction.

9. A pre-decoding device for a hybrid instruction system, characterized in that, The device pre-decodes the instruction group written to the instruction cache during instruction fetch and write-back; the instruction group includes at least one instruction of a first length and / or at least one instruction of a second length, the second length being twice the first length; wherein the second length instruction has an identifier code characterizing its instruction boundary; the device includes: Instruction boundary estimation circuit: used to determine the instruction boundary of the first instruction of the instruction group based on the identifier code. If the first instruction has the identifier code, it is the second length instruction; if it does not have the identifier code, it is the first length instruction. Based on the previous instruction boundary and the identifier code, the instruction boundaries of subsequent instructions are estimated in the serial direction from the first instruction to the last instruction.

10. The pre-decoding apparatus for a hybrid instruction system according to claim 9, characterized in that, The instruction boundary estimation circuit is also used to: for two logically adjacent instruction groups, if there is a first incomplete instruction at the end of the preceding instruction group, merge the first incomplete instruction with the second incomplete instruction at the beginning of the following instruction group to form a complete instruction, and then perform the instruction boundary estimation on the complete instruction and other instructions in the following instruction group.

11. The pre-decoding apparatus for a hybrid instruction system according to claim 9, characterized in that, The instruction boundary speculation circuit is also used to: when the starting address of the instruction group is not zero, take the instruction pointed to by the starting address as the first instruction of the instruction group.

12. The pre-decoding apparatus for a hybrid instruction system according to any one of claims 9-11, characterized in that, The hybrid instruction set is RISC-V; the first length is 16 bits; the second length is 32 bits, including a high half-word and a low half-word, with the identifier code located in the low half-word.

13. The pre-decoding apparatus for a hybrid instruction system according to claim 12, characterized in that, The instruction boundary estimation circuit is also used to: if the length of the instruction group is 16×16bit=32B, then in the timing, the instruction boundary of the instruction group is estimated in two steps. In the first step, the instruction boundary of the lower 16B and the instruction boundary of the higher 16B of the instruction group are estimated in 16B granularity. In the second step, the instruction boundary of the higher 16B is verified based on the instruction boundary of the lower 16B, so as to obtain the instruction boundary of the instruction group with a length of 32B.

14. The pre-decoding apparatus for a hybrid instruction system according to claim 12, characterized in that, The instruction boundary estimation circuit is further configured to: use the estimated instruction boundary of the first instruction as the pre-decoding first boundary, and use the instruction boundary of the first instruction obtained by splitting the instruction group to be decoded in the decoding stage as the decoding first boundary; based on the relative position of the decoding first boundary in the instruction group, the pre-decoding first boundary with the same relative position is suitable for matching with the decoding first boundary, so as to map each instruction boundary of the instruction group starting from the pre-decoding first boundary to the instruction decoding stage for direct instruction splitting.

15. The pre-decoding apparatus for a hybrid instruction system according to claim 12, characterized in that, The device further includes: Instruction boundary repair circuit: When an instruction boundary error occurs, it returns to the instruction boundary estimation circuit from the error position to re-evaluate the instruction boundary; the instruction boundary error is: the instruction boundary estimation result should be the position of the instruction boundary, but the actual stored instruction content is not the instruction boundary; or, the instruction boundary estimation result is not the position of the instruction boundary, but the actual stored instruction content is the instruction boundary.

16. The pre-decoding apparatus for a hybrid instruction system according to claim 15, characterized in that, The instruction boundary error state is as follows: the boundary prediction result of the 32-bit instruction should be the position of the instruction boundary, but the high half-word of the 32-bit instruction is actually stored; or, the boundary prediction result of the 32-bit instruction is not the position of the instruction boundary, but the low half-word of the 32-bit instruction is actually stored.

17. A processor, characterized in that, include: The pre-decoding apparatus for a hybrid instruction system as described in any one of claims 9-16, wherein the pre-decoding apparatus for a hybrid instruction system is adapted to perform the pre-decoding method for a hybrid instruction system as described in any one of claims 1-8.

18. An electronic device, characterized in that, The electronic device includes: a housing, a processor as described in claim 17, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; and the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory.

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