Serial data transmission method, dma controller, processor, system and storage medium

Abstract

This application relates to a serial port data transmission method, a DMA controller, a processor, a system, and a storage medium. The method includes: when serial port data needs to be received, sequentially buffering the serial port data to be received into a receive buffer; and when the amount of data in the receive buffer reaches a preset condition, generating a first interrupt signal to the processor, so that the processor can remove data from the receive buffer based on the first interrupt signal; when serial port data needs to be transmitted, sequentially transmitting the serial port data to be transmitted from at least one transmit buffer to the corresponding serial port; and generating a second interrupt signal to the processor when the data in each transmit buffer has been transmitted, so that the processor can control the DMA controller to transmit data in other transmit buffers within the at least one transmit buffer based on the second interrupt signal. This significantly reduces the number of CPU interrupts, thereby reducing CPU utilization and improving system operating efficiency.

Description

Technical Field

[0001] This application relates to the field of serial communication technology, and in particular to a serial data transmission method, DMA controller, processor, system, and storage medium. Background Technology

[0002] In related technologies, serial data transmission typically relies on a Central Processing Unit (CPU). However, this method depends on CPU interrupts to send and receive each byte of data one by one. In other words, every time a byte of data is sent or received, the CPU needs to interrupt once to store or process that byte, resulting in high CPU utilization and low system efficiency. Therefore, reducing CPU utilization during serial data transmission has become a pressing technical problem. Summary of the Invention

[0003] This application provides a serial port data transmission method, a DMA controller, a processor, a system, and a storage medium to solve the problem of high CPU utilization during serial port data transmission, which leads to low system operating efficiency in related technologies.

[0004] In a first aspect, embodiments of this application provide a serial port data transmission method applied to a DMA controller, the method comprising: When serial port data needs to be received, the serial port data to be received is buffered into the receiving buffer in sequence. When the amount of data in the receiving buffer reaches a preset condition, a first interrupt signal is generated for the processor, so that the processor can remove the data in the receiving buffer based on the first interrupt signal. When serial port data needs to be sent, the serial port data to be sent in at least one send buffer is sent sequentially to the corresponding serial port. When the data in each send buffer is sent, a second interrupt signal is generated for the processor, so that the processor can control the DMA controller to send the data in other send buffers in the at least one send buffer based on the second interrupt signal. The serial port data to be sent is copied to the at least one send buffer by the processor.

[0005] Optionally, the preset conditions include at least one of the following: The amount of data in the receive buffer reaches half the capacity of the receive buffer; The amount of data in the receive buffer is equal to the capacity of the receive buffer.

[0006] Optionally, the method further includes: When transmitting data in the first transmit buffer, the first transmit buffer is marked as locked, wherein the first transmit buffer is any one of the at least one transmit buffers; Once all data in the first transmission buffer has been transmitted, the first transmission buffer is marked as unlocked.

[0007] Secondly, embodiments of this application also provide a serial port data transmission method applied to a processor, the method comprising: When serial port data needs to be received, the system receives a first interrupt signal sent by the DMA controller and moves the data out of the receive buffer based on the first interrupt signal. The first interrupt signal is generated by the DMA controller when the amount of data in the receive buffer reaches a preset condition. The data in the receive buffer is pre-buffered by the DMA controller. When serial port data needs to be sent, the processor receives a second interrupt signal sent by the DMA controller and controls the DMA controller to send data in other send buffers within at least one send buffer based on the second interrupt signal. The second interrupt signal is generated by the DMA controller when the data in each send buffer is sent. The data in the at least one send buffer is pre-copied by the processor.

[0008] Optionally, the step of shifting data out of the receive buffer based on the first interrupt signal includes: Based on the first interrupt signal, the data between the first pointer and the second pointer in the receive buffer is moved out to a preset queue; Move the first instruction to the position of the second pointer, and move the second pointer as new data is stored in the receive buffer; Upon receiving a new first interrupt signal, based on the new first interrupt signal, the data between the first pointer and the second pointer is continuously moved out to the preset queue, and this process is repeated in sequence to move out the data continuously stored in the receiving buffer.

[0009] Optionally, the method further includes: When serial port data needs to be received, the system receives a third interrupt signal sent by the serial port and moves the data out of the receive buffer based on the third interrupt signal. The third interrupt signal is generated when the serial port switches from the data transmission state to the idle state.

[0010] Optionally, controlling the DMA controller to send data in other transmit buffers within at least one transmit buffer based on the second interrupt signal includes: Based on the second interrupt signal, determine whether there is a second transmission buffer containing data in the at least one transmission buffer; If it is determined that the second transmission buffer exists within the at least one transmission buffer, the DMA controller is controlled to transmit the data in the second transmission buffer; Upon receiving a new second interrupt signal, the system continues to determine whether there is a third send buffer containing data in the at least one send buffer. If the system determines that the third send buffer exists in the at least one send buffer, the system controls the DMA controller to send the data in the third send buffer. This process is repeated sequentially to send the data continuously stored in the at least one send buffer.

[0011] Optionally, the method further includes: Obtain the data length of each transmission buffer within the at least one transmission buffer, and determine whether there is a free area in each transmission buffer based on the data length of each transmission buffer; If there is free space in each transmit buffer, continue to copy the serial port data to be transmitted to the transmit buffer where there is free space; If there is no free area in any of the transmit buffers, the serial port data to be transmitted will be discarded.

[0012] Thirdly, embodiments of this application also provide a DMA controller, the DMA controller comprising: The first generation module is used to buffer the serial port data to be received into the receiving buffer in sequence when it is necessary to receive serial port data, and generate a first interrupt signal to the processor when the amount of data in the receiving buffer reaches a preset condition, so that the processor can remove the data in the receiving buffer based on the first interrupt signal. The second generation module is used to sequentially send the serial port data to be sent in at least one transmission buffer to the corresponding serial port when serial port data needs to be sent, and to generate a second interrupt signal to the processor when the data in each transmission buffer is sent. The processor can then control the DMA controller to send the data in other transmission buffers in the at least one transmission buffer based on the second interrupt signal. The serial port data to be sent is copied to the at least one transmission buffer by the processor.

[0013] Fourthly, embodiments of this application also provide a processor, the processor comprising: The shift-out module is used to receive a first interrupt signal sent by the DMA controller when serial port data needs to be received, and to shift out the data in the receive buffer based on the first interrupt signal. The first interrupt signal is generated by the DMA controller when the amount of data in the receive buffer reaches a preset condition, and the data in the receive buffer is pre-buffered by the DMA controller. The control module is used to receive a second interrupt signal sent by the DMA controller when serial port data needs to be sent, and to control the DMA controller to send data in other send buffers within at least one send buffer based on the second interrupt signal. The second interrupt signal is generated by the DMA controller when the data in each send buffer is sent. The data in the at least one send buffer is pre-copied by the processor.

[0014] Fifthly, embodiments of this application also provide a serial port data transmission system, the system comprising a DMA controller and a processor: The DMA controller is used to execute the serial port data transmission method described in the first aspect; The processor is used to execute the serial port data transmission method described in the second aspect.

[0015] Sixthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the serial port data transmission method described in the first aspect, or implements the serial port data transmission method described in the second aspect.

[0016] Compared with the prior art, the above-mentioned technical solution provided in this application has the following advantages: The method provided in this application, when it is necessary to receive serial port data, sequentially buffers the serial port data to be received into a receive buffer, and when the amount of data in the receive buffer reaches a preset condition, generates a first interrupt signal to the processor, so that the processor can remove the data from the receive buffer based on the first interrupt signal; when it is necessary to send serial port data, sequentially sends the serial port data to be sent in at least one send buffer to the corresponding serial port, and generates a second interrupt signal to the processor when the data in each send buffer is sent, so that the processor can control the DMA controller to send the data in other send buffers in the at least one send buffer based on the second interrupt signal, wherein the serial port data to be sent is copied to the at least one send buffer by the processor. In this way, the DMA controller only sends the first interrupt signal to the processor when the amount of data in the receive buffer reaches a preset condition during the process of receiving serial port data. And during the process of sending serial port data, it only sends the second interrupt signal to the processor when the data in each send buffer has been sent. This greatly reduces the number of CPU interrupts and significantly reduces the CPU utilization rate. In this way, the CPU can be freed from the low-level and frequent data transfer work and can handle other system tasks more efficiently, thereby achieving the technical effect of improving system operating efficiency. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 A flowchart illustrating a serial port data transmission method provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a serial port data receiving process provided in related technologies; Figure 3 This is a flowchart illustrating a serial port data transmission process provided in related technologies. Figure 4 A flowchart illustrating yet another serial port data transmission method provided in an embodiment of this application; Figure 5 A flowchart illustrating a serial port data receiving process provided in an embodiment of this application; Figure 6 A flowchart illustrating a serial port data transmission process provided in an embodiment of this application; Figure 7 A schematic diagram illustrating the interaction between a CPU and a DMA controller, provided as an embodiment of this application; Figure 8 A schematic diagram of the CPU processing flow during serial port data reception provided in an embodiment of this application; Figure 9 A schematic diagram of the CPU processing flow during serial port data transmission provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a DMA controller provided in an embodiment of this application; Figure 11 A schematic diagram of a processor provided in an embodiment of this application; Figure 12 This is a schematic diagram of a serial port data transmission system provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0023] To address the problem of high CPU utilization during serial data transmission, which leads to low system efficiency, this application provides a serial data transmission method, a DMA controller, a processor, a system, and a storage medium that can reduce CPU utilization during serial data transmission.

[0024] See Figure 1 , Figure 1 This is a flowchart illustrating a serial port data transmission method provided in an embodiment of this application. Figure 1 As shown, this serial port data transmission method can be applied to Direct Memory Access (DMA) controllers, and the method may include the following steps: Step S101: When serial port data needs to be received, the serial port data to be received is buffered into the receiving buffer in sequence. When the amount of data in the receiving buffer reaches a preset condition, a first interrupt signal is generated for the processor, so that the processor can remove the data in the receiving buffer based on the first interrupt signal.

[0025] Specifically, the aforementioned receive buffer can be understood as a storage area in memory used to store received serial port data. The number and capacity of the receive buffer can be set according to actual needs and are not specifically limited here. As an optional implementation, the number of receive buffers can be one, and the receive buffer has half-transmission completion interrupt (i.e., an interrupt is triggered when the DMA controller receives N / 2 bytes of data) and full-transmission completion interrupt (i.e., an interrupt is triggered when the DMA controller receives N bytes of data), where N refers to the capacity of the receive buffer.

[0026] Step S102: When serial port data needs to be sent, the serial port data to be sent in at least one send buffer is sent to the corresponding serial port in sequence. When the data in each send buffer is sent, a second interrupt signal is generated to the processor so that the processor can control the DMA controller to send the data in other send buffers in at least one send buffer based on the second interrupt signal. The serial port data to be sent is copied to at least one send buffer by the processor.

[0027] Specifically, the aforementioned transmit buffer can be understood as a memory storage area used to store serial port data to be transmitted. The number and capacity of the transmit buffer can be set according to actual needs and are not specifically limited here. As an optional implementation, there can be multiple transmit buffers. When the DMA controller transmits data in a certain transmit buffer, the processor can continue to store data in other transmit buffers with free areas, achieving the effect of storing and transmitting simultaneously.

[0028] In related technologies, the process of receiving serial port data is as follows: Figure 2 As shown, when the serial port receives a byte of data, it generates a CPU interrupt. The CPU then needs this interrupt to store or process that byte of data. After the CPU has stored or processed the byte, the serial port continues to receive the next byte, and so on in a loop. The serial data transmission process is as follows: Figure 3 As shown, the serial port generates a CPU interrupt after each byte of data is sent. At this time, the CPU can write the next byte of data into the serial port transmit register. After the CPU writes the next byte of data into the serial port transmit register, the serial port continues to send the next byte of data, generating another CPU interrupt. When the amount of data to be received or sent is large, a large number of interrupts will be generated, thus consuming system resources.

[0029] In this embodiment, during the process of receiving serial port data, the DMA controller only sends the first interrupt signal to the processor when the amount of data in the receive buffer reaches a preset condition. Furthermore, during the process of sending serial port data, the DMA controller only sends the second interrupt signal to the processor when the data in each send buffer has been sent. This greatly reduces the number of CPU interrupts, resulting in a significant reduction in CPU utilization. In this way, the CPU can be freed from the low-level, frequent data transfer work and can handle other system tasks more efficiently, thereby achieving the technical effect of improving system operating efficiency.

[0030] In one optional embodiment, the above-mentioned preset conditions include at least one of the following: The amount of data in the receive buffer has reached half of the receive buffer capacity; The amount of data in the receive buffer is equal to the capacity of the receive buffer.

[0031] Specifically, when serial port data needs to be received, the DMA controller can sequentially buffer the serial port data to be received into the receive buffer. When the amount of data in the receive buffer reaches half of the receive buffer capacity, and / or when the amount of data in the receive buffer is equal to the receive buffer capacity, a first interrupt signal can be generated for the processor. In this way, the processor can promptly remove the data in the receive buffer based on the first interrupt signal, so that the DMA controller can continue to store new data into the receive buffer.

[0032] When the amount of data in the receive buffer reaches half of its capacity, the interrupt triggered by the DMA controller can be called a half-transmission completion interrupt; when the amount of data in the receive buffer is equal to its capacity, the interrupt triggered by the DMA controller can be called a full-transmission completion interrupt. When there is continuous data in the transmission link that is longer than the length of the receive buffer, the half-transmission completion interrupt and the full-transmission completion interrupt can be used to achieve the effect of receiving and storing data simultaneously, thus allowing a smaller receive buffer to receive larger data packets.

[0033] It should be noted that during serial data reception, in addition to the aforementioned half-transmission completion interrupt and full-transmission completion interrupt, the CPU can also receive a serial port idle interrupt generated by the serial port. This serial port idle interrupt is an interrupt signal generated by the serial port after the entire packet reception has ended for a preset number of bytes (such as 1 byte). After receiving this serial port idle interrupt, the CPU can also remove data from the receive buffer based on this interrupt signal. In other words, even if the length of the entire packet of data received by the serial port is not equal to half or the entire capacity of the receive buffer, the CPU can still remove the data from the receive buffer promptly after the serial port has finished receiving the entire packet of data, based on the serial port idle interrupt signal.

[0034] In an optional embodiment, the method further includes: When transmitting data in the first transmit buffer, the first transmit buffer is marked as locked, wherein the first transmit buffer is any one of at least one transmit buffer; Once all data in the first transmit buffer has been transmitted, the first transmit buffer is marked as unlocked.

[0035] Specifically, when serial port data needs to be transmitted, the DMA controller can sequentially send the serial port data to be transmitted from at least one transmit buffer to the corresponding serial port, and generate a second interrupt signal to the processor when the data in each transmit buffer has been transmitted. At the same time, the DMA controller can mark a transmit buffer as locked while transmitting data in a transmit buffer, and mark the transmit buffer as unlocked when the data in the transmit buffer has been transmitted.

[0036] In this way, the DMA controller can lock the transmit buffer that is currently transmitting data, preventing the CPU from storing data in it and causing data to be incorrectly overwritten. At the same time, by locking the transmit buffer that is currently transmitting data, the CPU can accurately determine the idle or busy state of the DMA controller based on the calibration status of each transmit buffer, that is, accurately determine whether the DMA controller is currently transmitting data.

[0037] See Figure 4 , Figure 4 This is a flowchart illustrating a serial port data transmission method provided in an embodiment of this application. Figure 4 As shown, this serial port data transmission method can be applied to a processor, and the method may include the following steps: Step S401: When serial port data needs to be received, receive the first interrupt signal sent by the DMA controller, and remove the data in the receive buffer based on the first interrupt signal. The first interrupt signal is generated by the DMA controller when the amount of data in the receive buffer reaches a preset condition. The data in the receive buffer is pre-buffered by the DMA controller.

[0038] Specifically, the aforementioned receive buffer can be understood as a storage area in memory used to store received serial port data. The number and capacity of the receive buffer can be set according to actual needs and are not specifically limited here. As an optional implementation, the number of receive buffers can be one, and the receive buffer has half-transmission completion interrupt (i.e., an interrupt is triggered when the DMA controller receives N / 2 bytes of data) and full-transmission completion interrupt (i.e., an interrupt is triggered when the DMA controller receives N bytes of data), where N refers to the capacity of the receive buffer.

[0039] Step S402: When serial port data needs to be sent, receive the second interrupt signal sent by the DMA controller, and control the DMA controller to send the data in other send buffers in at least one send buffer based on the second interrupt signal. The second interrupt signal is generated by the DMA controller when the data in each send buffer is sent. The data in at least one send buffer is pre-copied by the processor.

[0040] Specifically, the aforementioned transmit buffer can be understood as a memory storage area used to store serial port data to be transmitted. The number and capacity of the transmit buffer can be set according to actual needs and are not specifically limited here. As an optional implementation, there can be multiple transmit buffers. When the DMA controller transmits data in a certain transmit buffer, the processor can continue to store data in other transmit buffers with free areas, achieving the effect of storing and transmitting simultaneously.

[0041] In this embodiment, during the process of receiving serial port data, the DMA controller only sends a first interrupt signal to the processor when the amount of data in the receive buffer reaches a preset condition. Furthermore, during the process of sending serial port data, it only sends a second interrupt signal to the processor when the data in each send buffer has been sent. This greatly reduces the number of CPU interrupts, resulting in a significant reduction in CPU utilization. In this way, the CPU can be freed from the low-level, frequent data transfer work and can handle other system tasks more efficiently, thereby achieving the technical effect of improving system operating efficiency.

[0042] In an optional embodiment, step S401, shifting data out of the receive buffer based on the first interrupt signal, includes: Based on the first interrupt signal, the data between the first and second pointers in the receive buffer is moved out to a preset queue; Move the first instruction to the position of the second pointer, and move the second pointer as new data is stored in the receive buffer; Upon receiving a new first interrupt signal, based on the new first interrupt signal, the data between the first pointer and the second pointer is continuously moved out to the preset queue, and this process is repeated in sequence to move out the data continuously stored in the receive buffer.

[0043] Specifically, such as Figure 5 As shown, the CPU can achieve cyclic reception of data in the receive buffer by controlling the positions of the first and second pointers. Specifically, the first pointer indicates the cutoff position of data in the receive buffer after the DMA controller has finished transmitting data. The second pointer indicates the position of the most recently stored data in the receive buffer.

[0044] When the CPU receives the first interrupt signal, it can move the data between the first and second pointers in the receive buffer to a preset queue, then move the first instruction to the position of the second pointer, and move the second pointer as new data is stored in the receive buffer. Then, when a new first interrupt signal is received, it can continue to move the data between the first and second pointers to the preset queue based on the new first interrupt signal, and so on, so as to move the continuously stored data in the receive buffer out sequentially.

[0045] For example, assuming the initial positions of the first and second pointers are 0, as serial data is continuously stored in the receive buffer, the position of the second pointer moves accordingly. When the second pointer moves to N / 2 (where N represents the total length of the receive buffer), the DMA controller triggers a first interrupt signal to the processor. This allows the processor to remove data from positions 0 to N / 2 in the receive buffer and also moves the first pointer to N / 2. The DMA controller then continues storing serial data into the receive buffer. When the second pointer moves to N, the DMA controller triggers a new first interrupt signal to the processor. This allows the processor to remove data from positions N / 2 to N in the receive buffer and also moves the first pointer to N. Then, the cycle begins again, and the first and second pointers return to position 0 and start moving again.

[0046] By controlling the positions of the first and second pointers, the cyclic reception effect of the receive buffer can be achieved, allowing a smaller receive buffer to receive larger data packets.

[0047] In an optional embodiment, the method further includes: When serial port data needs to be received, the system receives the third interrupt signal sent by the serial port and moves the data out of the receive buffer based on the third interrupt signal. The third interrupt signal is generated when the serial port switches from the data transmission state to the idle state.

[0048] Specifically, during serial data reception, in addition to receiving half-transfer completion interrupts and full-transfer completion interrupts generated by the DMA controller, the CPU can also receive a serial port idle interrupt (i.e., a third interrupt signal) generated by the serial port. This serial port idle interrupt is an interrupt signal generated by the serial port after a preset number of bytes (e.g., 1 byte) have been received. After receiving this serial port idle interrupt, the CPU can also remove data from the receive buffer based on this interrupt signal. In other words, even if the length of the entire data packet received by the serial port is not equal to half or the entire capacity of the receive buffer, the CPU can still remove the data from the receive buffer promptly after the serial port has finished receiving the entire data packet, based on the serial port idle interrupt signal.

[0049] In this way, the third interrupt signal can be combined with the first interrupt signal to perfectly adapt to the reception operation of data packets of all data lengths, avoiding the problem that the interrupt signal cannot be triggered when the length of the whole data packet received by the serial port is not equal to half or the entire capacity of the receive buffer.

[0050] In an optional embodiment, step S402, which involves controlling the DMA controller to transmit data in other transmit buffers within at least one transmit buffer based on the second interrupt signal, includes: Based on the second interrupt signal, determine whether there is a second transmission buffer with data cached in at least one transmission buffer; If it is determined that at least one transmit buffer contains a second transmit buffer, the DMA controller is controlled to transmit the data in the second transmit buffer; Upon receiving a new second interrupt signal, the system continues to determine whether there is a third send buffer containing data in at least one send buffer. If it is determined that there is a third send buffer in at least one send buffer, the system controls the DMA controller to send the data in the third send buffer. This process is repeated in a loop to send the data continuously stored in at least one send buffer sequentially.

[0051] Specifically, such as Figure 6 As shown, there can be multiple send buffers. Each time the CPU copies data, it can copy data to only one send buffer or to multiple send buffers, depending on the amount of serial data to be transmitted each time. After the CPU copies data to the send buffers, it can control the DMA controller to start data transmission based on the received second interrupt signal and the amount of data buffered in the send buffers.

[0052] Specifically, when the CPU receives the second interrupt signal, it checks if any send buffers contain cached data. If a send buffer with cached data exists, it controls the DMA controller to send the data in that send buffer. Once the DMA controller has finished sending the data in that send buffer, a new second interrupt signal is generated. Upon receiving this new second interrupt signal, the CPU continues to check if any new send buffers contain cached data. If a new send buffer with cached data exists, it controls the DMA controller to send the data in that new send buffer, repeating this process in a loop to sequentially send out the data continuously added to all send buffers.

[0053] For example, suppose the CPU pre-establishes three send buffers: send buffer 1, send buffer 2, and send buffer 3, each with a size of 512 bytes. When the amount of data copied by the CPU in the first pass is less than 512 bytes, the CPU can store the data in send buffer 1. After the data is stored, the CPU will start the DMA controller to send the data in send buffer 1, at which point send buffer 1 is locked. After storing the data in send buffer 1, the CPU can continue with a second data copy. Assuming the amount of data copied in the second pass is 1000 bytes, the CPU can copy the data to send buffers 2 and 3 (because send buffer 1 is locked, even if there is free space in send buffer 1, no new data can be stored). After the DMA controller completes the transmission of data in send buffer 1, it will trigger a second interrupt signal. Upon receiving the second interrupt signal, the CPU can restart the DMA controller to send the data in send buffer 2. After the DMA controller completes the transmission of data in send buffer 2, it will trigger a new second interrupt signal. Upon receiving the new second interrupt signal, the CPU can restart the DMA controller to send the data in send buffer 3. The process is as follows. Figure 7 As shown.

[0054] In this way, with multiple transmit buffers, the DMA controller and the CPU can work together to achieve simultaneous data copying and data transmission, thereby improving the efficiency of serial port data transmission.

[0055] In an optional embodiment, the method further includes: Obtain the data length of each transmit buffer within at least one transmit buffer, and determine whether there is a free area in each transmit buffer based on the data length of each transmit buffer; If there is free space in each transmit buffer, continue to copy the serial port data to be transmitted to the transmit buffer where there is free space; If there is no free area in any of the transmit buffers, the serial data to be transmitted will be discarded.

[0056] Specifically, when the CPU copies data to the transmit buffer, the CPU can obtain the data length of each transmit buffer in real time, and determine whether there is a free area in each transmit buffer based on the data length of each transmit buffer. If it is determined that there is a free area in each transmit buffer, the serial port data to be sent can continue to be copied to the transmit buffer with a free area; if it is determined that there is no free area in each transmit buffer, the serial port data to be sent can be discarded.

[0057] In this way, the CPU can obtain the size of the free area of ​​each transmit buffer in real time. When the data in a certain transmit buffer is sent by the DMA controller, the CPU can continue to copy data to it, so as to realize the continuous transmission of serial port data.

[0058] To better explain the serial port data transmission method in this application, the following example illustrates the process. For instance, this scheme can be used on serial port 1 of the GD32F470 chip, as follows: 1. Initialization: 1) Serial port configuration: Serial port 1 is bound to the transmit DMA and receive DMA (collectively referred to as the DMA controller); Configure the serial port baud rate, parity, stop bits, etc. Enable serial port idle interrupt; 2) DMA controller configuration: a. Send DMA configuration: Data direction: from memory to peripherals; Data width: single byte; Enable full transmission completion interrupt; b. Receive DMA configuration: Data direction: from peripherals to memory; Data width: single byte; Enable half-receive-complete interrupt and full-receive-complete interrupt; Loop receive mode; c. Initialize the receive buffer: Allocate a 512-byte array as a receive buffer; Set the first pointer for receiving data to 0; d. Initialize the transmit buffer: Allocate three 512-byte arrays as send buffers and set their lengths to 0.

[0059] 2. Receiving process: When the CPU receives any of the following interrupt signals: serial port idle interrupt, half-transmission complete interrupt, or full-transmission complete interrupt, it will proceed according to... Figure 8 The process shown is executed as follows: Step S801, Receive interrupt; Step S802: Move the data in the receive buffer to the preset queue and move the first pointer to the position of the second pointer.

[0060] Step S803: Notify the application that data reception is complete.

[0061] 3. Sending process: The CPU will follow Figure 9 The process shown is executed as follows: Step S901: Copy the data to an empty transmit buffer; Step S902: Determine whether the DMA controller is sending data; If the DMA controller is not transmitting data, proceed to step S903; if the DMA controller is transmitting data, proceed to step S904.

[0062] Step S903: Start the DMA controller to send data; Step S904: Wait for the DMA controller to finish sending the data and generate an interrupt signal; Step S905: Determine if there is still data to be sent in the transmit buffer; If there is still data to be sent in the transmit buffer, proceed to step S906; if there is no data to be sent in the transmit buffer, proceed to step S907.

[0063] Step S906: Start the DMA controller to send data.

[0064] Step S907: Stop the DMA controller from sending data.

[0065] Therefore, the serial port data transmission method provided in this application has the following beneficial effects: 1. Solving the problem of high CPU utilization: In response to the problem that traditional serial communication relies on CPU interrupts to send and receive bytes one by one, resulting in excessive CPU interrupt load and low system efficiency, this application establishes a direct data transmission channel between memory and serial port data registers through a DMA controller, completely freeing the CPU from the low-level, frequent data transfer work, so that it can handle upper-level application tasks more efficiently.

[0066] 2. Improve data transmission efficiency and system throughput: To address the bottleneck problem that easily occurs when transmitting large amounts of data, this application utilizes the characteristics of the DMA controller that support burst transmission and block transmission to achieve batch and high-speed data transfer, maximize the bandwidth potential of the serial port hardware, and significantly improve the overall throughput of the communication system.

[0067] 3. Enhanced system real-time performance and reliability: By reducing unnecessary CPU interrupts, system interrupt latency is lowered, enabling high-priority tasks to receive more timely responses. Simultaneously, the hardware reliability of DMA transfers reduces the risk of data loss due to software errors or interrupt conflicts.

[0068] See Figure 10 , Figure 10 This is a schematic diagram of a DMA controller provided in an embodiment of this application. Figure 10 As shown, the DMA controller 1000 includes: The first generation module 1001 is used to buffer the serial port data to be received into the receiving buffer in sequence when it is necessary to receive serial port data, and generate a first interrupt signal to the processor when the amount of data in the receiving buffer reaches a preset condition, so that the processor can remove the data in the receiving buffer based on the first interrupt signal. The second generation module 1002 is used to sequentially send the serial port data to be sent in at least one transmission buffer to the corresponding serial port when serial port data needs to be sent, and to generate a second interrupt signal to the processor when the data in each transmission buffer is sent. The processor can then control the DMA controller to send the data in other transmission buffers in the at least one transmission buffer based on the second interrupt signal. The serial port data to be sent is copied to the at least one transmission buffer by the processor.

[0069] Furthermore, the preset conditions include at least one of the following: The amount of data in the receive buffer has reached half of the receive buffer capacity; The amount of data in the receive buffer is equal to the capacity of the receive buffer.

[0070] Furthermore, the DMA controller 1000 also includes: A first marking module is used to mark the first transmission buffer as locked when transmitting data in the first transmission buffer, wherein the first transmission buffer is any one of at least one transmission buffer; The second marking module is used to mark the first sending buffer as unlocked when all data in the first sending buffer has been sent.

[0071] It should be noted that the DMA controller 1000 can achieve the aforementioned... Figure 1 The serial port data transmission method provided in the illustrated embodiment can achieve the same technical effect, and will not be described in detail here.

[0072] See Figure 11 , Figure 11 This is a schematic diagram of a processor provided in an embodiment of this application. Figure 11 As shown, the processor 1100 includes: The shift-out module 1101 is used to receive a first interrupt signal sent by the DMA controller when serial port data needs to be received, and to shift out the data in the receive buffer based on the first interrupt signal. The first interrupt signal is generated by the DMA controller when the amount of data in the receive buffer reaches a preset condition. The data in the receive buffer is pre-buffered by the DMA controller. The control module 1102 is used to receive a second interrupt signal sent by the DMA controller when serial port data needs to be sent, and to control the DMA controller to send data in other send buffers within at least one send buffer based on the second interrupt signal. The second interrupt signal is generated by the DMA controller when the data in each send buffer is sent. The data in at least one send buffer is pre-copied by the processor.

[0073] Furthermore, the removal module 1101 includes: The remove submodule is used to remove the data between the first pointer and the second pointer in the receive buffer to a preset queue based on the first interrupt signal; The move submodule is used to move the first instruction to the position of the second pointer, and to move the second pointer as new data is stored in the receive buffer; The first loop submodule is used to, upon receiving a new first interrupt signal, continue to move the data between the first pointer and the second pointer to a preset queue based on the new first interrupt signal, and repeat this loop to move the data continuously stored in the receive buffer out sequentially.

[0074] Furthermore, the processor 1100 also includes: The receiving module is used to receive the third interrupt signal sent by the serial port when serial port data needs to be received, and to remove the data in the receiving buffer based on the third interrupt signal. The third interrupt signal is generated when the serial port switches from the data transmission state to the idle state.

[0075] Furthermore, the control module 1102 includes: The judgment submodule is used to determine, based on the second interrupt signal, whether there is a second transmission buffer with buffered data in at least one transmission buffer; The control submodule is used to control the DMA controller to send data in the second transmit buffer when it is determined that at least one transmit buffer contains the second transmit buffer; The second loop submodule is used to continue to determine whether there is a third send buffer with buffered data in at least one send buffer when a new second interrupt signal is received. If it is determined that there is a third send buffer in at least one send buffer, the DMA controller is controlled to send the data in the third send buffer. This process is repeated in a loop to send the data continuously stored in at least one send buffer in sequence.

[0076] Furthermore, the processor 1100 also includes: The acquisition module is used to acquire the data length of each transmission buffer in at least one transmission buffer, and determine whether there is a free area in each transmission buffer based on the data length of each transmission buffer; The copy module is used to continue copying the serial port data to be sent to the transmit buffer where there is free space when there is free space in each transmit buffer; The discard module is used to discard serial port data to be sent when there is no free area in each transmit buffer.

[0077] It should be noted that the processor 1100 can achieve the aforementioned... Figure 4 The serial port data transmission method provided in the illustrated embodiment can achieve the same technical effect, and will not be described in detail here.

[0078] like Figure 12 As shown in the figure, this application embodiment also provides a serial port data transmission system, the system 1200 including a DMA controller 1201 and a processor 1202: The DMA controller 1201 is used to execute the implementation as described above. Figure 1 The serial port data transmission method provided in the illustrated embodiment; Processor 1202 is used to execute the implementation as described above. Figure 4 The serial port data transmission method provided in the illustrated embodiment.

[0079] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the serial port data transmission method provided in any of the foregoing method embodiments.

[0080] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0082] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0083] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A serial port data transmission method, characterized in that, Applied to a DMA controller, the method includes: When serial port data needs to be received, the serial port data to be received is buffered into the receiving buffer in sequence. When the amount of data in the receiving buffer reaches a preset condition, a first interrupt signal is generated for the processor, so that the processor can remove the data in the receiving buffer based on the first interrupt signal. When serial port data needs to be sent, the serial port data to be sent in at least one send buffer is sent sequentially to the corresponding serial port. When the data in each send buffer is sent, a second interrupt signal is generated for the processor, so that the processor can control the DMA controller to send the data in other send buffers in the at least one send buffer based on the second interrupt signal. The serial port data to be sent is copied to the at least one send buffer by the processor.

2. The method according to claim 1, characterized in that, The preset conditions include at least one of the following: The amount of data in the receive buffer reaches half the capacity of the receive buffer; The amount of data in the receive buffer is equal to the capacity of the receive buffer.

3. The method according to claim 1, characterized in that, The method further includes: When transmitting data in the first transmit buffer, the first transmit buffer is marked as locked, wherein the first transmit buffer is any one of the at least one transmit buffers; Once all data in the first transmission buffer has been transmitted, the first transmission buffer is marked as unlocked.

4. A serial port data transmission method, characterized in that, Applied to a processor, the method includes: When serial port data needs to be received, the system receives a first interrupt signal sent by the DMA controller and moves the data out of the receive buffer based on the first interrupt signal. The first interrupt signal is generated by the DMA controller when the amount of data in the receive buffer reaches a preset condition. The data in the receive buffer is pre-buffered by the DMA controller. When serial port data needs to be sent, the processor receives a second interrupt signal sent by the DMA controller and controls the DMA controller to send data in other send buffers within at least one send buffer based on the second interrupt signal. The second interrupt signal is generated by the DMA controller when the data in each send buffer is sent. The data in the at least one send buffer is pre-copied by the processor.

5. The method according to claim 4, characterized in that, The step of shifting data out of the receive buffer based on the first interrupt signal includes: Based on the first interrupt signal, the data between the first pointer and the second pointer in the receive buffer is moved out to a preset queue; Move the first instruction to the position of the second pointer, and move the second pointer as new data is stored in the receive buffer; Upon receiving a new first interrupt signal, based on the new first interrupt signal, the data between the first pointer and the second pointer is continuously moved out to the preset queue, and this process is repeated in sequence to move out the data continuously stored in the receiving buffer.

6. The method according to claim 4, characterized in that, The method further includes: When serial port data needs to be received, the system receives a third interrupt signal sent by the serial port and moves the data out of the receive buffer based on the third interrupt signal. The third interrupt signal is generated when the serial port switches from the data transmission state to the idle state.

7. The method according to claim 4, characterized in that, The step of controlling the DMA controller to send data in other send buffers within at least one send buffer based on the second interrupt signal includes: Based on the second interrupt signal, determine whether there is a second transmission buffer containing data in the at least one transmission buffer; If it is determined that the second transmission buffer exists within the at least one transmission buffer, the DMA controller is controlled to transmit the data in the second transmission buffer; Upon receiving a new second interrupt signal, the system continues to determine whether there is a third send buffer containing data in the at least one send buffer. If the system determines that the third send buffer exists in the at least one send buffer, the system controls the DMA controller to send the data in the third send buffer. This process is repeated sequentially to send the data continuously stored in the at least one send buffer.

8. The method according to claim 4, characterized in that, The method further includes: Obtain the data length of each transmission buffer within the at least one transmission buffer, and determine whether there is a free area in each transmission buffer based on the data length of each transmission buffer; If there is free space in each transmit buffer, continue to copy the serial port data to be transmitted to the transmit buffer where there is free space; If there is no free area in any of the transmit buffers, the serial port data to be transmitted will be discarded.

9. A DMA controller, characterized in that, The DMA controller includes: The first generation module is used to buffer the serial port data to be received into the receiving buffer in sequence when it is necessary to receive serial port data, and generate a first interrupt signal to the processor when the amount of data in the receiving buffer reaches a preset condition, so that the processor can remove the data in the receiving buffer based on the first interrupt signal. The second generation module is used to sequentially send the serial port data to be sent in at least one transmission buffer to the corresponding serial port when serial port data needs to be sent, and to generate a second interrupt signal to the processor when the data in each transmission buffer is sent. The processor can then control the DMA controller to send the data in other transmission buffers in the at least one transmission buffer based on the second interrupt signal. The serial port data to be sent is copied to the at least one transmission buffer by the processor.

10. A processor, characterized in that, The processor includes: The shift-out module is used to receive a first interrupt signal sent by the DMA controller when serial port data needs to be received, and to shift out the data in the receive buffer based on the first interrupt signal. The first interrupt signal is generated by the DMA controller when the amount of data in the receive buffer reaches a preset condition, and the data in the receive buffer is pre-buffered by the DMA controller. The control module is used to receive a second interrupt signal sent by the DMA controller when serial port data needs to be sent, and to control the DMA controller to send data in other send buffers within at least one send buffer based on the second interrupt signal. The second interrupt signal is generated by the DMA controller when the data in each send buffer is sent. The data in the at least one send buffer is pre-copied by the processor.

11. A serial port data transmission system, characterized in that, The system includes a DMA controller and a processor: The DMA controller is used to execute the serial port data transmission method according to any one of claims 1-3; The processor is used to execute the serial port data transmission method according to any one of claims 4-8.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the serial port data transmission method of any one of claims 1-3, or implements the serial port data transmission method of any one of claims 4-8.

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