storage device

Abstract

Embodiments of this disclosure relate to a storage device, comprising: a storage cell array for storing write data in at least one selected storage cell; a high voltage generator for generating a high voltage that slopes from an initial voltage level to a first voltage level during an initial period and remains at the first voltage level during a final period, the initial period being equal to or longer than the final period; a low voltage generator for generating a low voltage that slopes from the initial voltage level to a second voltage level during the initial period; a first decoder for applying one of the high voltage and the low voltage to one end of the selected storage cell; and a second decoder for applying the other of the high voltage and the low voltage to the other end of the selected storage cell.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0200183, filed on December 30, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Various embodiments of this disclosure relate to semiconductor design techniques, and more specifically, to memory devices that support write modes. Background Technology

[0003] Storage devices are broadly classified into volatile storage devices and non-volatile storage devices. Volatile storage devices lose their stored data when power is cut off. In contrast, non-volatile storage devices retain their stored data even when power is off.

[0004] Storage cells in a storage device can have a unified logical state based on the physical or chemical properties of the materials constituting the storage cells. Non-volatile storage devices, including storage cells formed from chalcogenide-based materials, can have slower operating speeds but larger capacities or integration than dynamic random access memory (DRAM), and faster operating speeds but smaller capacities or integrations than NAND flash memory. Summary of the Invention

[0005] Various embodiments of this disclosure relate to a storage device capable of suppressing spike currents that occur in selected memory cells during write mode.

[0006] Various embodiments of this disclosure relate to a storage device capable of performing optimal write operations based on the write data during write mode.

[0007] According to one embodiment of this disclosure, a storage device may include: a storage cell array including a plurality of storage cells coupled between a plurality of first lines and a plurality of second lines, and configured to store write data in at least one selected storage cell among the plurality of storage cells during a write period; a high voltage generator configured to generate a high voltage that slopes from an initial voltage level to a first target voltage level during an initial period of the write period and remains at the first target voltage level during a final period of the write period, the initial period being equal to or longer than the final period of the write period; and a low voltage generator configured to generate a low voltage that slopes from an initial voltage level to a first target voltage level during an initial period of the write period. The voltage level slopes from an initial voltage level to a second target voltage level during a period, and remains at the second target voltage level during the final period; a first decoder, coupled to a high voltage generator, a low voltage generator, and a plurality of first lines, is configured to apply one of a high voltage and a low voltage to one end of a selected memory cell during a write period via a first line selected from the plurality of first lines, based on a first decoded signal; and a second decoder, coupled to a high voltage generator, a low voltage generator, and a plurality of second lines, is configured to apply the other of a high voltage and a low voltage to the other end of a selected memory cell during a write period via a second line selected from the plurality of second lines, based on a second decoded signal.

[0008] According to one embodiment of this disclosure, a storage device may include: a storage cell array configured to store write data in at least one selected storage cell of a plurality of storage cells during a write period; a high voltage generator configured to generate a selected high voltage, either a first high voltage or a second high voltage, based on the logic level of the write data during an initial period within the write period; a low voltage generator configured to generate a selected low voltage, either a first low voltage or a second low voltage, based on the logic level during the initial period; and a first decoder coupled to the high voltage generator, the low voltage generator, and a plurality of first lines, and configured to generate a high voltage during the write period. During a write period, a first decoder applies one of a selected high voltage and a selected low voltage to one end of the memory cell via a first line selected from a plurality of first lines based on a first decoder signal; and a second decoder, coupled to a high voltage generator, a low voltage generator, and a plurality of second lines, and configured to apply the other of a selected high voltage and a selected low voltage to the other end of the selected memory cell via a second line selected from a plurality of second lines based on a second decoder signal during a write period, wherein: the selected high voltage slopes from an initial voltage level to a first target voltage level during an initial period, while the selected low voltage slopes from an initial voltage level to a second target voltage level during an initial period.

[0009] According to one embodiment of this disclosure, a storage device may include: selected storage cells coupled between selected first lines and selected second lines, and configured to store write data therein during one of a first write period and a second write period; a high-voltage generator configured to generate a first voltage based on the logic level of the write data, the first voltage sloping from an initial voltage level to a first target voltage level during a first initial period of the first write period and remaining at the first target voltage level during a first final period of the first write period, the first voltage being a high voltage and the first initial period being equal to or longer than the first final period within the first write period; and a low-voltage generator configured to generate a second voltage based on the logic level, the second voltage sloping from the initial voltage level to the second target voltage level during the first initial period. The system comprises: a first coupling circuit configured to selectively apply a first voltage to one end of a selected memory cell via a selected first line based on a first enable signal and a first address signal; a second coupling circuit configured to selectively apply a second voltage to one end of a selected memory cell via a selected first line based on a second enable signal and a first address signal; a third coupling circuit configured to selectively apply a first voltage to the other end of a selected memory cell via a selected second line based on a second enable signal and a second address signal; and a fourth coupling circuit configured to selectively apply a second voltage to the other end of a selected memory cell via a selected second line based on a first enable signal and a second address signal. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 It is shown Figure 1 The diagram shows a simplified representation of the coupling structure between the storage cell array and the first and second decoders.

[0012] Figures 3 to 6 It is used to describe Figure 1 A diagram illustrating the write operation of the storage device.

[0013] Figure 7 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0014] Figure 8 It is shown Figure 7 A simplified diagram of the coupling structure between the storage cell array, the first decoder, and the second decoder.

[0015] Figures 9 to 11 It is used to describe Figure 7 A diagram illustrating the write operation of the storage device. Detailed Implementation

[0016] Various embodiments of the present disclosure will now be described in conjunction with the accompanying drawings to provide a detailed description of the embodiments of the present disclosure, enabling those skilled in the art to readily implement the technical spirit of the present disclosure.

[0017] It should be understood that when an element is described as being "connected to" or "coupled to" another element, the connection may be direct or it may be physically or electrically indirect through one or more intermediate elements. Furthermore, it should be understood that the terms "comprising," "including," "containing," and "comprise" as used in this specification do not exclude the presence of one or more other elements, but may further include or have one or more other elements, unless otherwise stated. Throughout the description of this disclosure, some components are described in the singular, but the disclosure is not limited thereto, and it should be understood that components may be formed in the plural.

[0018] Figure 1 This is a block diagram illustrating a storage device 100 according to an embodiment of the present disclosure.

[0019] refer to Figure 1 The storage device 100 may include a storage cell array 110, a high voltage generator 120, a low voltage generator 130, a first decoder 140, and a second decoder 150.

[0020] The memory cell array 110 may include multiple memory cells. These memory cells may be coupled between multiple bit lines BL and multiple word lines WL. For example, the multiple memory cells may be coupled at the intersection of multiple bit lines BL and multiple word lines WL.

[0021] During write mode, the storage cell array 110 can store write data in at least one selected storage cell among a plurality of storage cells. During read mode, the storage cell array 110 can read read data from at least one selected storage cell among a plurality of storage cells.

[0022] For example, each of a plurality of memory cells may include a selector-only memory (SOM) element. The SOM element can operate as a self-selecting memory, which functions as both a storage element and a selection element. More specifically, the self-selecting memory can exhibit variable resistance characteristics, enabling it to store data by switching between different resistance states based on the voltage difference applied across the selected memory cell. The self-selecting memory can exhibit threshold switching characteristics, where it blocks or substantially limits current flow through the selected memory cell when the voltage difference across it is less than a predetermined threshold, and allows a sudden increase in current flow through the selected memory cell when the voltage difference is greater than or equal to the predetermined threshold. The predetermined threshold, which may be called the threshold voltage, determines whether the self-selecting memory is turned on or off.

[0023] The threshold voltage of a self-selecting memory can vary depending on its resistance state. That is, a self-selecting memory can have different threshold voltages corresponding to its resistance state. For example, when the self-selecting memory is in a low-resistance state, it can have a first threshold voltage. On the other hand, when the self-selecting memory is in a high-resistance state, it can have a second threshold voltage different from the first threshold voltage. Therefore, this characteristic allows the self-selecting memory to function as both a storage element and a selection element simultaneously.

[0024] For example, self-selective memories can include a variety of materials, such as diodes, bidirectional threshold switch (OTS) materials (e.g., chalcogenide-based materials), mixed ion-electron conduction (MIEC) materials (e.g., metal chalcogenide-based materials), metal-insulator transition (MIT) materials (e.g., NbO2 or VO2), or tunneling dielectric layers with relatively wide band gaps (e.g., SiO2 or Al2O3). Specifically, self-selective memories can include materials containing multiple trapping sites capable of trapping charges, such as OTS materials.

[0025] The high-voltage generator 120 can be enabled based on the write enable signal WT during write mode. The high-voltage generator 120 can generate a high voltage VP during write mode and provide this high voltage VP to the first decoder 140 and the second decoder 150. For example, the high voltage VP can be a positive voltage.

[0026] In one embodiment, the high-voltage generator 120 can generate a high-voltage VP with the same waveform based on the write enable signal WT, regardless of the first enable signal SET_EN and the second enable signal RST_EN. The high-voltage VP is described in more detail below (see [link to documentation]). Figure 3The first enable signal SET_EN can be an enable signal activated during write mode when the write data has a logic level corresponding to a low resistance state. The second enable signal RST_EN can be an enable signal activated during write mode when the write data has a logic level corresponding to a high resistance state.

[0027] In another embodiment, the high-voltage generator 120 can generate a high voltage VP with different waveforms based on the write enable signal WT, the first enable signal SET_EN, and the second enable signal RST_EN, according to the logic level of the written data. The high voltage VP will be described in more detail below (see [link to documentation]). Figure 4 ).

[0028] The low-voltage generator 130 can be enabled based on the write enable signal WT. The low-voltage generator 130 can generate a low voltage VN during write mode and provide the low voltage VN to the first decoder 140 and the second decoder 150. For example, the low voltage VN can be a negative voltage.

[0029] In one embodiment, the low-voltage generator 130 can generate a low-voltage VN with the same waveform based on the write enable signal WT, regardless of the first enable signal SET_EN and the second enable signal RST_EN. The low-voltage VN will be described in more detail below (see [link to documentation]). Figure 3 ).

[0030] In another embodiment, the low-voltage generator 130 can generate a low voltage VN with different waveforms based on the write enable signal WT, the first enable signal SET_EN, and the second enable signal RST_EN, according to the logic level of the written data. The low voltage VN will be described in more detail below (see...). Figure 4 ).

[0031] The first decoder 140 may be coupled to a high-voltage generator 120, a low-voltage generator 130, and multiple bit lines BL. During write mode, the first decoder 140 may apply one of a high voltage VP and a low voltage VN to one end of a selected memory cell via a selectable bit line among the multiple bit lines BL, based on a first decoder signal YADD, SET_EN, and RST_EN. For example, the first decoder signal may include a first address signal YADD, a first enable signal SET_EN, and a second enable signal RST_EN. The first address signal YADD may correspond to a selectable bit line. As described above, during write mode, the first enable signal SET_EN may be activated when the write data has a logic level corresponding to a low-resistance state, and the second enable signal RST_EN may be activated during write mode when the write data has a logic level corresponding to a high-resistance state.

[0032] The second decoder 150 may be coupled to a high-voltage generator 120, a low-voltage generator 130, and multiple word lines WL. During write mode, the second decoder 150 may apply another of a high voltage VP and a low voltage VN to the other end of a selected memory cell via a selected word line from the multiple word lines WL, based on second decoding signals XADD, SET_EN, and RST_EN. For example, the second decoding signals may include a second address signal XADD, a first enable signal SET_EN, and a second enable signal RST_EN. The second address signal XADD may correspond to a selected word line.

[0033] Figure 2 To show Figure 1 A simplified diagram of the coupling structure between the storage cell array 110 and the first decoder 140 and the second decoder 150 shown. For example, Figure 2 The coupling structure is shown only in the memory cell MC# among the multiple memory cells included in the memory cell array 110, the first decoding circuit D1 among the multiple first decoding circuits included in the first decoder 140, and the second decoding circuit D2 among the multiple second decoding circuits included in the second decoder 150.

[0034] The memory cell MC# may include an SOM element. The memory cell MC# may be coupled between the bit line BL# and the word line WL#.

[0035] The first decoding circuit D1 can be coupled to the bit line BL#. The first decoding circuit D1 can apply one of a high voltage VP and a low voltage VN to one end of the memory cell MC# via the bit line BL#, based on the first address signal YADD#, the first enable signal SET_EN, and the second enable signal RST_EN. The first address signal YADD# can represent the bit line BL# and is the signal obtained by decoding the first address signal YADD. For example, the first decoding circuit D1 may include a first coupling circuit C1 and a second coupling circuit C2.

[0036] A first coupling circuit C1 can be coupled between the high-voltage generator 120 and the bit line BL#. The first coupling circuit C1 can selectively couple the high-voltage generator 120 to the bit line BL# based on a first enable signal SET_EN and a first address signal YADD#. For example, during write mode, when the write data has a logic level corresponding to a low-resistance state, the first coupling circuit C1 can electrically couple the high-voltage generator 120 to the bit line BL#. Alternatively, during write mode, when the write data has a logic level corresponding to a high-resistance state, the first coupling circuit C1 can electrically disconnect the high-voltage generator 120 from the bit line BL#.

[0037] The second coupling circuit C2 can be coupled between the low-voltage generator 130 and the bit line BL#. The second coupling circuit C2 can selectively couple the low-voltage generator 130 to the bit line BL# based on the second enable signal RST_EN and the first address signal YADD#. For example, during write mode, when the write data has a logic level corresponding to a high-resistance state, the second coupling circuit C2 can electrically couple the low-voltage generator 130 to the bit line BL#. Alternatively, during write mode, when the write data has a logic level corresponding to a low-resistance state, the second coupling circuit C2 can electrically disconnect the low-voltage generator 130 from the bit line BL#.

[0038] The second decoding circuit D2 can be coupled to word line WL#. The second decoding circuit D2 can apply one of the high voltage VP and low voltage VN to the other end of the memory cell MC# via word line WL#, based on the second address signal XADD#, the first enable signal SET_EN, and the second enable signal RST_EN. The second address signal XADD# can represent word line WL# and is the signal obtained by decoding the second address signal XADD. For example, the second decoding circuit D2 may include a third coupling circuit C3 and a fourth coupling circuit C4.

[0039] The third coupling circuit C3 can be coupled between the high-voltage generator 120 and the word line WL#. The third coupling circuit C3 can selectively couple the high-voltage generator 120 to the word line WL# based on the second enable signal RST_EN and the second address signal XADD#. For example, during write mode, when the write data has a logic level corresponding to a high-resistance state, the third coupling circuit C3 can couple the high-voltage generator 120 to the word line WL#. Alternatively, during write mode, when the write data has a logic level corresponding to a low-resistance state, the third coupling circuit C3 can electrically disconnect the high-voltage generator 120 from the word line WL#.

[0040] A fourth coupling circuit C4 can be coupled between the low-voltage generator 130 and the word line WL#. The fourth coupling circuit C4 can selectively couple the low-voltage generator 130 to the word line WL# based on the first enable signal SET_EN and the second address signal XADD#. For example, during write mode, when the write data has a logic level corresponding to a low-resistance state, the fourth coupling circuit C4 can electrically couple the low-voltage generator 130 to the word line WL#. Alternatively, during write mode, when the write data has a logic level corresponding to a high-resistance state, the fourth coupling circuit C4 can electrically disconnect the low-voltage generator 130 from the word line WL#.

[0041] Below, we will refer to Figures 3 to 6 For those with Figure 1 and Figure 2The write operation of the storage device 100 with the above configuration will be described.

[0042] Figure 3 It is shown Figure 1 A graph showing the operation of the high-voltage generator 120 and the low-voltage generator 130 included in the storage device 100.

[0043] refer to Figure 3 The high-voltage generator 120 can generate a high voltage VP with the same waveform based on the write enable signal WT, regardless of the first enable signal SET_EN and the second enable signal RST_EN. During the write period WW, the high-voltage generator 120 can generate a high voltage VP with a predetermined waveform, regardless of the logic level of the written data. For example, the high voltage VP can ramp up from the initial voltage level VINT to the first target voltage level VT1 during the initial period RR and remain at the first target voltage level VT1 during the final period TT. More precisely, the high voltage VP can remain at the first target voltage level VT1 during the final period TT and then be initialized to the initial voltage level VINT.

[0044] The low-voltage generator 130 can generate a low voltage VN with the same waveform based on the write enable signal WT, regardless of the first enable signal SET_EN and the second enable signal RST_EN. During the write period WW, the low-voltage generator 130 can generate a low voltage VN with a predetermined waveform, regardless of the logic level of the written data. For example, the low voltage VN can slope down from the initial voltage level VINT to the second target voltage level VT2 during the initial period RR, and remain at the second target voltage level VT2 during the final period TT. More precisely, the low voltage VN can remain at the second target voltage level VT2 during the final period TT, and then be initialized to the initial voltage level VINT.

[0045] Specifically, within a write period WW, the initial period RR can be set to be equal to or longer than the final period TT. That is, the high voltage VP can be designed to slowly ramp up during the initial period RR (equivalent to half or more of the write period WW), and the low voltage VN can be designed to slowly ramp down during the initial period RR (equivalent to half or more of the write period WW). This slow ramping of the high voltage VP and low voltage VN allows for the suppression of current spikes that occur when selected memory cells are turned on during write mode.

[0046] Figure 4 It is shown Figure 1A graph illustrating another embodiment of the operation of the high-voltage generator 120 and low-voltage generator 130 included in the storage device 100 shown.

[0047] refer to Figure 4 The high voltage generator 120 can generate high voltages VP with different waveforms based on the write enable signal WT, the first enable signal SET_EN, and the second enable signal RST_EN, according to the logic level of the written data.

[0048] When the written data has a logic level corresponding to a low resistance state (i.e., a SET state), the high voltage generator 120 can generate a high voltage VP with a first waveform during the first write period WW1. For example, the high voltage VP can ramp up from the initial voltage level VINT to the first target voltage level VT1 during the first initial period RR1, and remain at the first target voltage level VT1 during the first final period TT1. More precisely, the high voltage VP can remain at the first target voltage level VT1 during the first final period TT1, and then be initialized to the initial voltage level VINT.

[0049] When the written data has a logic level corresponding to a low resistance state (i.e., the SET state), the low voltage generator 130 can generate a low voltage VN with a first waveform during the first write period WW1. For example, the low voltage VN can ramp down from the initial voltage level VINT to the second target voltage level VT2 during the first initial period RR1 and remain at the second target voltage level VT2 during the first final period TT1. More precisely, the low voltage VN can remain at the second target voltage level VT2 during the first final period TT1 and then be initialized to the initial voltage level VINT.

[0050] Specifically, within the first write period WW1, the first initial period RR1 can be set to be equal to or longer than the first final period TT1. That is, the high voltage VP can be designed to slowly ramp up during the first initial period RR1 (equivalent to half or more of the first write period WW1), and the low voltage VN can be designed to slowly ramp down during the first initial period RR1 (equivalent to half or more of the first write period WW1). The slowly ramping high voltage VP and low voltage VN can be used to suppress spike currents generated when selected memory cells are turned on during write mode.

[0051] When the written data has a logic level corresponding to a high-resistance state (i.e., a RESET state), the high-voltage generator 120 can generate a high voltage VP with a second waveform during the second write period WW2. For example, the high voltage VP can ramp up from the initial voltage level VINT to the first target voltage level VT1 during the second initial period RR2, and remain at the first target voltage level VT1 during the second final period TT2. More precisely, the high voltage VP can remain at the first target voltage level VT1 during the second final period TT2, and then be initialized to the initial voltage level VINT.

[0052] When the written data has a logic level corresponding to a high-resistance state (i.e., a RESET state), the low-voltage generator 130 can generate a low voltage VN with a second waveform during the second write period WW2. For example, the low voltage VN can ramp down from the initial voltage level VINT to the second target voltage level VT2 during the second initial period RR2, and remain at the second target voltage level VT2 during the second final period TT2. More precisely, the low voltage VN can remain at the second target voltage level VT2 during the second final period TT2, and then be initialized to the initial voltage level VINT.

[0053] Specifically, within the second write period WW2, the second initial period RR2 can be set to be longer than the second final period TT2. That is, the high voltage VP can be designed to slowly ramp up during the second initial period RR2 (corresponding to a period longer than half the length of the second write period WW2), and the low voltage VN can be designed to slowly ramp down during the second initial period RR2 (corresponding to a period longer than half the length of the second write period WW2). The slowly ramped high voltage VP and low voltage VN can be used to suppress current spikes that occur when a selected memory cell is turned on during write mode.

[0054] The first initial time period RR1 can be the same as the second initial time period RR2. The first final time period TT1 can be longer than the second final time period TT2. The second final time period TT2 can be shorter than the first final time period TT1. Therefore, the second write time period WW2 can be shorter than the first write time period WW1. When write data with logic levels corresponding to a low resistance state is stored in a selected memory cell, the longer the first final time period TT1 (i.e., the longer the high voltage VP and low voltage VN are maintained at the first target voltage level VT1 and the second target voltage level VT2, respectively), the lower the threshold voltage of the selected memory cell will be. When write data with logic levels corresponding to a high resistance state is stored in a selected memory cell, the shorter the second final time period TT2 (i.e., the shorter the high voltage VP and low voltage VN are maintained at the first target voltage level VT1 and the second target voltage level VT2, respectively), the higher the threshold voltage of the selected memory cell will be. High voltage VP and low voltage VN, which are applied at different final time periods (TT1 or TT2) during write mode according to the logic level of the write data, can ensure sufficient read window margin during read mode following write mode.

[0055] Figure 5 It is used to describe storing write data with logic levels corresponding to a low resistance state. Figure 1 A simplified diagram of the operation in a selected memory cell among the multiple memory cells included in the memory cell array 110 shown. Figure 6 It is used to describe storing write data with logic levels corresponding to a high resistance state. Figure 1 A simplified diagram illustrating operations in a selected memory cell among the plurality of memory cells included in the memory cell array 110 shown. For example, Figure 5 and Figure 6 Based on Figure 2 A simplified diagram. Below, Figure 5 and Figure 6 The bit line BL#, word line WL#, and memory cell MC# shown are referred to as the selected bit line, selected word line, and selected memory cell, respectively.

[0056] refer to Figure 5 When the written data has a logic level corresponding to a low resistance state, the first enable signal SET_EN can be activated during write mode, and the second enable signal RESET_EN can be deactivated during write mode. Therefore, the first coupling circuit C1 and the fourth coupling circuit C4 can be enabled during write mode, and the second coupling circuit C2 and the third coupling circuit C3 can be disabled during write mode.

[0057] The first coupling circuit C1 can apply a high voltage VP to one end of the selected memory cell MC# via the selection line BL#, and the fourth coupling circuit C4 can apply a low voltage VN to the other end of the selected memory cell MC# via the selection word line WL#. Therefore, the cell current can flow through the supply terminal of the high voltage VP, the first coupling circuit C1, the selection line BL#, the selected memory cell MC#, the fourth coupling circuit C4, and the supply terminal of the low voltage VN. In other words, the cell current can flow along... Figure 5 The arrow shown flows from one end of the selected memory cell MC# to the other. Depending on the direction of the cell current, the selected memory cell MC# can be in a low-resistance state, i.e., the SET state.

[0058] refer to Figure 6 When the written data has a logic level corresponding to a high-resistance state, the second enable signal RESET_EN can be activated during write mode, and the first enable signal SET_EN can be deactivated during write mode. Therefore, the second coupling circuit C2 and the third coupling circuit C3 can be enabled during write mode, and the first coupling circuit C1 and the fourth coupling circuit C4 can be disabled during write mode.

[0059] The third coupling circuit C3 can apply a high voltage VP to the other end of the selected memory cell MC# through the selected word line WL#, and the second coupling circuit C2 can apply a low voltage VN to one end of the selected memory cell MC# through the selected word line BL#. Therefore, the cell current can flow through the supply terminal of the high voltage VP, the third coupling circuit C3, the selected word line WL#, the selected memory cell MC#, the second coupling circuit C2, and the supply terminal of the low voltage VN. In other words, the cell current can flow along... Figure 6 The arrow shown flows from one end of the selected memory cell MC# to the other. Depending on the direction of the cell current, the selected memory cell MC# can be in a high-resistance state, i.e., a RESET state.

[0060] According to embodiments of this disclosure, a high voltage VP and a low voltage VN that slope slowly during write mode can be used, which allows for suppression of current spikes generated when the selected memory cell MC# is turned on. Furthermore, high voltage VP and low voltage VN with different waveforms depending on the logic level of the data being written can be used, which allows for optimal write operation.

[0061] Figure 7 This is a block diagram illustrating a storage device 200 according to an embodiment of the present disclosure.

[0062] refer to Figure 7 The storage device 200 may include a storage cell array 210, a high voltage generator 220, a low voltage generator 230, a first decoder 240, and a second decoder 250.

[0063] The memory cell array 210 may include multiple memory cells. These memory cells may be coupled between multiple bit lines BL and multiple word lines WL. For example, the multiple memory cells may be coupled at the intersection of multiple bit lines BL and multiple word lines WL.

[0064] During write mode, the storage cell array 210 can store write data in at least one selected storage cell among a plurality of storage cells. During read mode, the storage cell array 210 can read read data from at least one selected storage cell among a plurality of storage cells.

[0065] For example, each of multiple memory cells can include a selector-only memory (SOM) element. The SOM element can operate as a self-selecting memory, functioning as both a storage element and a selection element. More specifically, the self-selecting memory can exhibit variable resistance characteristics, enabling it to store data by switching between different resistance states based on the voltage difference applied across the selected memory cell. The self-selecting memory can exhibit threshold switching characteristics, where it blocks or substantially limits current flow through the selected memory cell when the voltage difference across it is less than a predetermined threshold, and allows a sudden increase in current flow through the selected memory cell when the voltage difference is greater than or equal to the predetermined threshold. The predetermined threshold, which may be called the threshold voltage, determines whether the self-selecting memory is turned on or off.

[0066] The threshold voltage of a self-selecting memory can vary depending on its resistance state. That is, a self-selecting memory can have different threshold voltages corresponding to its resistance state. For example, when the self-selecting memory is in a low-resistance state, it can have a first threshold voltage. On the other hand, when the self-selecting memory is in a high-resistance state, it can have a second threshold voltage different from the first threshold voltage. Therefore, this characteristic allows a self-selecting memory to be used simultaneously as both a storage element and a selection element.

[0067] For example, self-selective memories can include a variety of materials, such as diodes, bidirectional threshold switch (OTS) materials (e.g., chalcogenide-based materials), mixed ion-electron conduction (MIEC) materials (e.g., metal chalcogenide-based materials), metal-insulator transition (MIT) materials (e.g., NbO2 or VO2), or tunneling dielectric layers with relatively wide band gaps (e.g., SiO2 or Al2O3). Specifically, self-selective memories can include materials containing multiple trapping sites capable of trapping charges, such as OTS materials.

[0068] During write mode, the high voltage generator 220 can be enabled based on the write enable signal WT. During write mode, the high voltage generator 220 can also be enabled based on the first enable signal SET_EN and the second enable signal RESET_EN (see...). Figure 9 A high voltage VP with different waveforms is generated and provided to the first decoder 240 and the second decoder 250. For example, the high voltage VP can be a positive voltage. When the written data has a logic level corresponding to a low resistance state, the first enable signal SET_EN can be activated during the write mode. When the written data has a logic level corresponding to a high resistance state, the second enable signal RST_EN can be activated during the write mode.

[0069] The low-voltage generator 230 can be enabled based on the write enable signal WT. During write mode, the low-voltage generator 230 can also be enabled based on the first enable signal SET_EN and the second enable signal RST_EN (see...). Figure 9 A low voltage VN with a different waveform is generated and provided to the first decoder 240 and the second decoder 250. For example, the low voltage VN can be a negative voltage.

[0070] The first decoder 240 may be coupled to a high-voltage generator 220, a low-voltage generator 230, and multiple bit lines BL. During write mode, the first decoder 240 may apply one of a high voltage VP and a low voltage VN to one end of a selected memory cell via a selected address line among the multiple bit lines BL, based on a first decode signal YADD, SET_EN, and RST_EN. For example, the first decode signal may include a first address signal YADD, a first enable signal SET_EN, and a second enable signal RST_EN. The first address signal YADD may correspond to a selected address line. As described above, the first enable signal SET_EN may be activated during write mode when the write data has a logic level corresponding to a low-resistance state, and the second enable signal RST_EN may be activated during write mode when the write data has a logic level corresponding to a high-resistance state.

[0071] The second decoder 250 can be coupled to a high-voltage generator 220, a low-voltage generator 230, and multiple word lines WL. During write mode, the second decoder 250 can apply another of a high voltage VP and a low voltage VN to the other end of a selected memory cell via a selected word line from the multiple word lines WL, based on second decoding signals XADD, SET_EN, and RST_EN. For example, the second decoding signals may include a second address signal XADD, a first enable signal SET_EN, and a second enable signal RST_EN. The second address signal XADD may correspond to a selected word line.

[0072] Figure 8 yes Figure 7 A simplified diagram of the coupling structure between the storage cell array 210 and the first decoder 240 and the second decoder 250 shown. For example, Figure 8 The coupling structure is shown only in the memory cell MC# of the multiple memory cells included in the memory cell array 210, the first decoding circuit D11 of the multiple first decoding circuits included in the first decoder 240, and the second decoding circuit D22 of the multiple second decoding circuits included in the second decoder 250.

[0073] The memory cell MC# may include an SOM element. The memory cell MC# may be coupled between the bit line BL# and the word line WL#.

[0074] The first decoding circuit D11 can be coupled to the bit line BL#. The first decoding circuit D11 can apply one of a high voltage VP and a low voltage VN to one end of the memory cell MC# via the bit line BL#, based on the first address signal YADD#, the first enable signal SET_EN, and the second enable signal RST_EN. The first address signal YADD# can represent the bit line BL# and is the signal obtained by decoding the first address signal YADD. For example, the first decoding circuit D11 may include a first coupling circuit C11 and a second coupling circuit C22.

[0075] A first coupling circuit C11 can be coupled between the high-voltage generator 220 and the bit line BL#. The first coupling circuit C11 can selectively couple the high-voltage generator 220 to the bit line BL# based on a first enable signal SET_EN and a first address signal YADD#. For example, when the write data has a logic level corresponding to a low-resistance state during write mode, the first coupling circuit C11 can electrically couple the high-voltage generator 220 to the bit line BL#. Alternatively, when the write data has a logic level corresponding to a high-resistance state during write mode, the first coupling circuit C11 can electrically disconnect the high-voltage generator 220 from the bit line BL#.

[0076] The second coupling circuit C22 can be coupled between the low-voltage generator 230 and the bit line BL#. The second coupling circuit C22 can selectively couple the low-voltage generator 230 to the bit line BL# based on the second enable signal RST_EN and the first address signal YADD#. For example, when the write data has a logic level corresponding to a high-resistance state during write mode, the second coupling circuit C22 can electrically couple the low-voltage generator 230 to the bit line BL#. Alternatively, when the write data has a logic level corresponding to a low-resistance state during write mode, the second coupling circuit C22 can electrically disconnect the low-voltage generator 230 from the bit line BL#.

[0077] The second decoding circuit D22 can be coupled to word line WL#. The second decoding circuit D22 can apply one of a high voltage VP and a low voltage VN to the other end of the memory cell MC# via word line WL#, based on the second address signal XADD#, the first enable signal SET_EN, and the second enable signal RST_EN. The second address signal XADD# can represent word line WL# and is the signal obtained by decoding the second address signal XADD. For example, the second decoding circuit D22 may include a third coupling circuit C33 and a fourth coupling circuit C44.

[0078] A third coupling circuit C33 can be coupled between the high-voltage generator 220 and the word line WL#. The third coupling circuit C33 can selectively couple the high-voltage generator 220 to the word line WL# based on the second enable signal RST_EN and the second address signal XADD#. For example, during write mode, when the write data has a logic level corresponding to a high-resistance state, the third coupling circuit C33 can electrically couple the high-voltage generator 220 to the word line WL#. Alternatively, during write mode, when the write data has a logic level corresponding to a low-resistance state, the third coupling circuit C33 can electrically disconnect the high-voltage generator 220 from the word line WL#.

[0079] A fourth coupling circuit C44 can be coupled between the low-voltage generator 230 and the word line WL#. The fourth coupling circuit C44 can selectively couple the low-voltage generator 230 to the word line WL# based on the first enable signal SET_EN and the second address signal XADD#. For example, when the write data has a logic level corresponding to a low-resistance state during write mode, the fourth coupling circuit C44 can electrically couple the low-voltage generator 230 to the word line WL#. Alternatively, when the write data has a logic level corresponding to a high-resistance state during write mode, the fourth coupling circuit C44 can electrically disconnect the low-voltage generator 230 from the word line WL#.

[0080] Below, for reference Figures 9 to 11 For those with Figure 7 and Figure 8 The write operation of the storage device 200 with the above configuration shown will be described.

[0081] Figure 9 It is shown Figure 7 A graph illustrating an embodiment of the operation of the high-voltage generator 220 and the low-voltage generator 230 included in the storage device 200.

[0082] refer to Figure 9The high-voltage generator 220 can generate a high voltage VP with different waveforms based on the write enable signal WT, the first enable signal SET_EN, and the second enable signal RST_EN, according to the logic level of the written data. The low-voltage generator 230 can generate a low voltage VN with different waveforms based on the write enable signal WT, the first enable signal SET_EN, and the second enable signal RST_EN, according to the logic level of the written data.

[0083] First, the operation of the high voltage generator 220 and the low voltage generator 230 is described when the written data has a logic level corresponding to the low resistance state, i.e., the SET state (that is, when the first enable signal SET_EN is activated).

[0084] The high-voltage generator 220 can generate a high voltage VP with a first waveform during the first write period WW11. For example, the high voltage VP can ramp up from the initial voltage level VINT to the first target voltage level VT1 during the first initial period RR11, and remain at the first target voltage level VT1 during the first final period TT11. More precisely, the high voltage VP can remain at the first target voltage level VT1 during the first final period TT11, and then be initialized to the initial voltage level VINT.

[0085] The low-voltage generator 230 can generate a low voltage VN with a first waveform during the first write period WW11. For example, the low voltage VN can ramp down from the initial voltage level VINT to the second target voltage level VT2 during the first initial period RR11 and remain at the second target voltage level VT2 during the first final period TT11. More precisely, the low voltage VN can remain at the second target voltage level VT2 during the first final period TT11 and then be initialized to the initial voltage level VINT.

[0086] Specifically, within the first write period WW11, the first initial period RR11 can be set to be equal to or longer than the first final period TT11. That is, the high voltage VP can be designed to slowly ramp up during the first initial period RR11 (corresponding to half or more of the first write period WW11), and the low voltage VN can be designed to slowly ramp down during the first initial period RR11 (corresponding to half or more of the first write period WW11). The use of slowly ramped high voltage VP and low voltage VN allows for suppression of current spikes generated when selected memory cells are turned on during write mode.

[0087] Next, the operation of the high voltage generator 220 and the low voltage generator 230 is described when the written data has a logic level corresponding to a high resistance state, i.e., the RESET state (that is, when the second enable signal RST_EN is activated).

[0088] The high-voltage generator 220 can generate a high voltage VP with a second waveform during the second write period WW22. For example, the high voltage VP can ramp up from the initial voltage level VINT to the first target voltage level VT1 during the second initial period RR22, and remain at the first target voltage level VT1 during the second final period TT22. More precisely, the high voltage VP can remain at the first target voltage level VT1 during the second final period TT22, and then be initialized to the initial voltage level VINT.

[0089] The low-voltage generator 230 can generate a low voltage VN with a second waveform during the second write period WW22. For example, the low voltage VN can ramp down from the initial voltage level VINT to the second target voltage level VT2 during the second initial period RR22, and remain at the second target voltage level VT2 during the second final period TT22. More precisely, the low voltage VN can remain at the second target voltage level VT2 during the second final period TT22, and then be initialized to the initial voltage level VINT.

[0090] Specifically, within the second write period WW22, the second initial period RR22 can be set to be shorter than the second final period TT22. That is, the high voltage VP can be designed to ramp up rapidly during the second initial period RR22 (corresponding to a period shorter than half the second write period WW22), and the low voltage VN can be designed to ramp down rapidly during the second initial period RR22 (corresponding to a period shorter than half the second write period WW22).

[0091] The first initial time period RR11 can be longer than the second initial time period RR22. The second initial time period RR22 can be shorter than the first initial time period RR11. The first final time period TT11 can be longer than the second final time period TT22. The second final time period TT22 can be shorter than the first final time period TT11. Therefore, the second write time period WW22 can be shorter than the first write time period WW11. When write data with logic levels corresponding to a low resistance state is stored in a selected memory cell, the longer the first final time period TT11 (i.e., the longer the high voltage VP and low voltage VN are maintained at the first target voltage level VT1 and the second target voltage level VT2, respectively), the lower the threshold voltage of the selected memory cell will be. When write data with logic levels corresponding to a high resistance state is stored in a selected memory cell, the shorter the second final time period TT22 (i.e., the shorter the high voltage VP and low voltage VN are maintained at the first target voltage level VT1 and the second target voltage level VT2, respectively), the higher the threshold voltage of the selected memory cell can be. The high voltage VP and low voltage VN can be applied at different final times (TT11 or TT22) during write mode, depending on the logic level of the data being written. This allows for sufficient read window margin to be ensured during read mode after write mode.

[0092] Figure 10 This describes the write data stored having a logic level corresponding to a low resistance state. Figure 7 A simplified diagram of the operation in a selected memory cell among the multiple memory cells included in the memory cell array 210 shown. Figure 11 This describes the write data that is stored with a logic level corresponding to a high resistance state. Figure 7 A simplified diagram illustrating operations in a selected memory cell among multiple memory cells included in the memory cell array 210 shown. For example, Figure 10 and 11 Based on Figure 8 A simplified diagram. Below, Figure 10 and 11 The bit line BL#, word line WL#, and memory cell MC# shown are respectively called the selected bit line, selected word line, and selected memory cell.

[0093] refer to Figure 10 When the written data has a logic level corresponding to a low resistance state, the first enable signal SET_EN can be activated during write mode, and the second enable signal RESET_EN can be deactivated during write mode. Therefore, the first coupling circuit C11 and the fourth coupling circuit C44 can be enabled during write mode, and the second coupling circuit C22 and the third coupling circuit C33 can be disabled during write mode.

[0094] The first coupling circuit C11 can apply a high voltage VP to one end of the selected memory cell MC# via the selection line BL#, and the fourth coupling circuit C44 can apply a low voltage VN to the other end of the selected memory cell MC# via the selection word line WL#. Therefore, the cell current can flow through the supply terminal of the high voltage VP, the first coupling circuit C11, the selection line BL#, the selected memory cell MC#, the fourth coupling circuit C44, and the supply terminal of the low voltage VN. In other words, the cell current can flow along... Figure 10 The arrow shown flows from one end of the selected memory cell MC# to the other. Depending on the direction of the cell current, the selected memory cell MC# can be in a low-resistance state, i.e., the SET state.

[0095] refer to Figure 11 When the written data has a logic level corresponding to a high-resistance state, the second enable signal RESET_EN can be activated during write mode, and the first enable signal SET_EN can be deactivated during write mode. Therefore, the second coupling circuit C22 and the third coupling circuit C33 can be enabled during write mode, while the first coupling circuit C11 and the fourth coupling circuit C44 can be disabled during write mode.

[0096] The third coupling circuit C33 can apply a high voltage VP to the other end of the selected memory cell MC# through the selected word line WL#, and the second coupling circuit C22 can apply a low voltage VN to one end of the selected memory cell MC# through the selected word line BL#. Therefore, the cell current can flow through the supply terminal of the high voltage VP, the third coupling circuit C33, the selected word line WL#, the selected memory cell MC#, the second coupling circuit C22, and the supply terminal of the low voltage VN. In other words, the cell current can flow along... Figure 11 The arrow shown flows from one end of the selected memory cell MC# to the other. Depending on the direction of the cell current, the selected memory cell MC# can be in a high-resistance state, i.e., a RESET state.

[0097] According to embodiments of this disclosure, a high voltage VP and a low voltage VN that slope slowly during write mode can be used, which allows for suppression of current spikes generated when the selected memory cell MC# is turned on. Furthermore, high voltage VP and low voltage VN with different waveforms depending on the logic level of the data being written can be used, which allows for optimal write operation.

[0098] According to embodiments of this disclosure, spike currents that occur in selected memory cells during write mode can be suppressed, thereby improving the durability or lifespan of the memory.

[0099] According to embodiments of this disclosure, an optimal write operation can be performed based on the write data during write mode, which enables sufficient read window margin to be ensured during read mode following write mode.

[0100] While the technical concepts of this disclosure have been illustrated and described with reference to specific embodiments, the disclosed embodiments are provided for descriptive purposes and are not intended to be limiting. Furthermore, it is worth noting that, as those skilled in the art will recognize from this disclosure, the embodiments of this disclosure can be implemented in various ways through substitutions, alterations, and modifications, which fall within the scope of the following claims. These embodiments can be combined to form other embodiments.

Claims

1. A storage device, comprising: A storage cell array comprising a plurality of storage cells coupled between a plurality of first lines and a plurality of second lines, wherein write data is stored in at least one selected storage cell among the plurality of storage cells during a write period; A high voltage generator generates a high voltage that slopes from an initial voltage level to a first target voltage level during the initial period of the write phase and remains at the first target voltage level during the final period of the write phase, wherein the initial period is equal to or longer than the final period within the write phase; A low-voltage generator that generates a low voltage that slopes from an initial voltage level to a second target voltage level during the initial time period and remains at the second target voltage level during the final time period; A first decoder is coupled to the high voltage generator, the low voltage generator, and the plurality of first lines, and applies one of the high voltage and the low voltage to one end of the selected memory cell via a first line selected from the plurality of first lines during the write period based on a first decoded signal. as well as A second decoder is coupled to the high voltage generator, the low voltage generator, and the plurality of second lines, and applies another of the high voltage and the low voltage to the other end of the selected memory cell via a second line selected from the plurality of second lines during the write period, based on a second decoded signal.

2. The storage device according to claim 1, wherein the first decoder comprises: A first coupling circuit is coupled between the high voltage generator and the selected first line, and selectively couples the high voltage generator to the selected first line based on a first enable signal and a first address signal. as well as A second coupling circuit is coupled between the low-voltage generator and the selected first line, and selectively couples the low-voltage generator to the selected first line based on a second enable signal and a first address signal.

3. The storage device according to claim 2, wherein the second decoder comprises: A third coupling circuit is coupled between the high voltage generator and the selected second line, and selectively couples the high voltage generator to the selected second line based on the second enable signal and the second address signal. as well as A fourth coupling circuit is coupled between the low-voltage generator and the selected second line, and selectively couples the low-voltage generator to the selected second line based on the first enable signal and the second address signal.

4. The memory device of claim 1, wherein, When the written data has a logic level corresponding to a low resistance state, the first decoder applies the high voltage to the selected first line, and when the written data has a logic level corresponding to a high resistance state, the first decoder applies the low voltage to the selected first line.

5. The memory device of claim 4, wherein, When the written data has a logic level corresponding to the low resistance state, the second decoder applies the low voltage to the selected second line, and when the written data has a logic level corresponding to the high resistance state, the second decoder applies the high voltage to the selected second line.

6. The storage device according to claim 1, wherein: The first decoding signal includes a first enable signal corresponding to the written data in the low-resistance state and a first address signal corresponding to the selected first line, and The second decoding signal includes a second enable signal corresponding to the written data in the high-resistance state and a second address signal corresponding to the selected second line.

7. The storage device according to claim 1, wherein: The high voltage includes positive voltage, and The low voltage includes negative voltage.

8. A storage device, comprising: A storage cell array that stores write data in at least one selected storage cell among a plurality of storage cells during a write period; A high-voltage generator that generates a selected high voltage, either a first high voltage or a second high voltage, based on the logic level of the written data during an initial period within the write period. A low-voltage generator that generates a selected low voltage, either a first low voltage or a second low voltage, based on the logic level during the initial time period. A first decoder is coupled to the high voltage generator, the low voltage generator, and a plurality of first lines, and applies one of a selected high voltage and a selected low voltage to one end of the selected memory cell via a first line selected from the plurality of first lines during the write period based on a first decoded signal. as well as A second decoder, coupled to the high-voltage generator, the low-voltage generator, and a plurality of second lines, applies, based on a second decoded signal, during the write period another of the selected high voltage and the selected low voltage to the other end of the selected memory cell via a second line selected from the plurality of second lines, wherein: The selected high voltage slopes from the initial voltage level to the first target voltage level during the initial time period, and The selected low voltage slopes from the initial voltage level to the second target voltage level during the initial time period.

9. The storage device of claim 8, wherein the first decoder comprises: A first coupling circuit is coupled between the high voltage generator and the selected first line, and selectively couples the high voltage generator to the selected first line based on a first enable signal and a first address signal. as well as A second coupling circuit is coupled between the low-voltage generator and the selected first line, and selectively couples the low-voltage generator to the selected first line based on a second enable signal and a first address signal.

10. The storage device of claim 9, wherein the second decoder comprises: A third coupling circuit is coupled between the high voltage generator and the selected second line, and selectively couples the high voltage generator to the selected second line based on the second enable signal and the second address signal. as well as A fourth coupling circuit is coupled between the low-voltage generator and the selected second line, and selectively couples the low-voltage generator to the selected second line based on the first enable signal and the second address signal.

11. The storage device according to claim 8, wherein: The high-voltage generator generates the first high voltage during a relatively long initial period when the logic level corresponds to a low-resistance state, and The high-voltage generator generates the second high voltage during the relatively short initial period when the logic level corresponds to a high-resistance state.

12. The storage device according to claim 8, wherein: The low-voltage generator generates the first low voltage during a relatively long initial period when the logic level corresponds to a low-resistance state, and The low-voltage generator generates the second low voltage during a relatively short initial period when the logic level corresponds to a high-resistance state.

13. The storage device according to claim 8, wherein: The high-voltage generator also generates the selected high voltage during the final period of the write period, based on the logic level. The low-voltage generator also generates the selected low voltage during the final time period based on the logic level. The selected high voltage is maintained at the first target voltage level during the final time period, and The selected low voltage is maintained at the second target voltage level during the final period.

14. The storage device according to claim 13, wherein: The high-voltage generator generates the first high voltage during the relatively long final time period when the logic level corresponds to a low-resistance state, and The high-voltage generator generates the second high voltage during the relatively short final period when the logic level corresponds to a high-resistance state.

15. The storage device according to claim 13, wherein: The low-voltage generator generates the first low voltage during the relatively long final time period when the logic level corresponds to a low-resistance state, and The low-voltage generator generates the second low voltage during the relatively short final period when the logic level corresponds to a high-resistance state.

16. The storage device according to claim 8, wherein: Both the first high voltage and the second high voltage include positive voltages, and Both the first low voltage and the second low voltage include negative voltages.

17. A storage device, comprising: The selected storage cell is coupled between the selected first line and the selected second line, and stores the written data therein during one of the first write period and the second write period; A high voltage generator generates a first voltage based on the logic level of the written data. The first voltage slopes from an initial voltage level to a first target voltage level during a first initial period of the first write period and remains at the first target voltage level during a first final period of the first write period. The first voltage is a high voltage, and the first initial period is equal to or longer than the first final period within the first write period. A low voltage generator generates a second voltage based on the logic level, the second voltage sloping from the initial voltage level to a second target voltage level during the first initial time period and remaining at the second target voltage level during the first final time period, the second voltage being a low voltage. A first coupling circuit selectively applies the first voltage to one end of the selected memory cell via the selected first line, based on a first enable signal and a first address signal. A second coupling circuit, based on a second enable signal and a first address signal, selectively applies the second voltage to one end of the selected memory cell via the selected first line; A third coupling circuit, based on the second enable signal and the second address signal, selectively applies the first voltage to the other end of the selected memory cell via the selected second line; as well as A fourth coupling circuit, based on the first enable signal and the second address signal, selectively applies the second voltage to the other end of the selected memory cell via the selected second line.

18. The storage device according to claim 17, wherein: When the logic level corresponds to a low resistance state, the first enable signal is activated, and The second enable signal is activated when the logic level corresponds to a high resistance state.

19. The memory device of claim 17, wherein, When the first enable signal is activated, the high voltage generator generates the first voltage during the first write period, and When the first enable signal is activated, the low voltage generator generates the second voltage during the first write period.

20. The storage device according to claim 19, wherein: The high-voltage generator further comprises: when the second enable signal is activated, generating a third voltage according to the logic level, the third voltage sloping from the initial voltage level to the first target voltage level during the second initial period of the second write period, and remaining at the first target voltage level during the second final period of the second write period, the third voltage being a high voltage, and the second initial period being shorter than the second final period within the second write period; and The low voltage generator further comprises: when the second enable signal is activated, generating a fourth voltage according to the logic level, the fourth voltage sloping from the initial voltage level to the second target voltage level during the second initial period and remaining at the second target voltage level during the second final period, the fourth voltage being a low voltage.

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