A calibration oscillator circuit and oscillator

Abstract

This application discloses a calibration oscillation circuit and an oscillator, applicable to the field of oscillators. The input terminal of a frequency divider circuit is connected to the output terminal of a ring oscillator circuit to acquire the clock frequency signal output by the ring oscillator circuit. The input terminal of a clock calibration circuit is connected to the output terminal of the frequency divider circuit to acquire the voltage signal determined by the frequency divider circuit based on the clock frequency signal. The input terminal of a power supply suppression circuit is connected to the output terminal of the clock calibration circuit to acquire the calibration voltage signal determined by the clock calibration circuit based on the voltage signal and a preset voltage signal. The output terminal of the power supply suppression circuit is connected to the control terminal of the ring oscillator circuit to output a calibration voltage determined based on the calibration voltage signal to the ring oscillator circuit, so that the ring oscillator circuit calibrates the clock frequency signal according to the calibration voltage and outputs the calibrated clock frequency signal. This application, through the calibration oscillation circuit, reduces the influence of external interference on the clock frequency signal, improving stability and accuracy.

Description

Technical Field

[0001] This application relates to the field of oscillators, and in particular to a calibration oscillator circuit and an oscillator. Background Technology

[0002] On-chip clock sources are widely used in microcontroller units (MCUs) due to their small size, low cost, and ease of integration into the chip. As a clock source, the oscillator inside the on-chip clock source needs to output a clock signal of a specific frequency to drive various modules in the chip; therefore, the frequency of its output signal directly affects the chip's performance.

[0003] RC oscillators are commonly used as on-chip clock sources due to their advantages such as simple structure, high operability, ease of integration into chips, and relatively high stability, frequency, and accuracy of output signals. The traditional working principle of an RC oscillator is as follows: charging the internal capacitor to the comparator's threshold voltage triggers the comparator to flip, and subsequent logic units control the capacitor to charge again, forming a cycle and generating a periodic signal. This periodic signal is then buffered and output as a clock signal of a certain frequency. However, in practical applications, the accuracy of the RC oscillator clock signal is related to the temperature coefficient of the internal component resistors and the comparator's delay. When the clock signal frequency is high, the effect of the comparator delay becomes more pronounced, and the frequency of the output clock signal is more susceptible to the influence of process parameters, thus reducing the accuracy of the RC oscillator's output clock signal.

[0004] In view of the above-mentioned technology, finding a calibration oscillation circuit is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a calibration oscillation circuit and oscillator. This solves the problem in the prior art where the frequency of the clock signal output by an RC oscillator is greatly affected by process parameters, resulting in low stability and accuracy of the output clock signal.

[0006] To solve the above-mentioned technical problems, this application provides a calibration oscillation circuit, including: a ring oscillation circuit, a frequency divider circuit, a clock calibration circuit, and a power supply suppression circuit;

[0007] The input terminal of the frequency divider circuit is connected to the output terminal of the ring resonator circuit to obtain the clock frequency signal output by the ring resonator circuit.

[0008] The input terminal of the clock calibration circuit is connected to the output terminal of the frequency divider circuit to obtain the voltage signal determined by the frequency divider circuit based on the clock frequency signal;

[0009] The input terminal of the power supply suppression circuit is connected to the output terminal of the clock calibration circuit to obtain the calibration voltage signal determined by the clock calibration circuit based on the voltage signal and the preset voltage signal.

[0010] The output of the power supply suppression circuit is connected to the control terminal of the ring oscillator circuit. It is used to output a calibration voltage determined according to the calibration voltage signal to the ring oscillator circuit, so that the ring oscillator circuit can calibrate the clock frequency signal according to the calibration voltage and output the calibrated clock frequency signal.

[0011] Preferably, the clock calibration circuit includes: a controllable resistor adjustment circuit, a controlled capacitor adjustment circuit, a voltage-controlled current source, and a current calibration circuit;

[0012] The input terminal of the current calibration circuit is connected to the current signal transmitting terminal.

[0013] The first output terminal of the current calibration circuit is connected to the input terminal of the controllable resistor adjustment circuit and the first input terminal of the voltage-controlled current source. The second output terminal of the current calibration circuit is connected to the input terminal of the controlled capacitor adjustment circuit. The third output terminal of the current calibration circuit is connected to the second input terminal of the voltage-controlled current source. The fourth output terminal of the current calibration circuit is connected to the current terminal of the power supply suppression circuit.

[0014] The output terminal of the controllable resistor adjustment circuit is grounded;

[0015] The control terminal of the controlled capacitor adjustment circuit is connected to the output terminal of the frequency divider circuit as the input terminal of the clock calibration circuit.

[0016] The output of the controlled capacitor regulation circuit is connected to the third input of the voltage-controlled current source;

[0017] The output of the voltage-controlled current source is connected to the input of the power supply suppression circuit, serving as the output of the clock calibration circuit.

[0018] Preferably, the controllable resistor adjustment circuit is a first resistor;

[0019] The first end of the first resistor is connected to the first output end of the current calibration circuit and the first input end of the voltage-controlled current source, serving as the input end of the controllable resistor adjustment circuit.

[0020] The second terminal of the first resistor is grounded as the input terminal of the controllable resistor adjustment circuit.

[0021] Preferably, the controlled capacitor regulation circuit includes: a first MOSFET, a second MOSFET, and a first capacitor;

[0022] In this circuit, the gates of the first MOS transistor and the second MOS transistor are connected together as the control terminal of the controlled capacitor adjustment circuit and the output terminal of the frequency divider circuit.

[0023] The source of the first MOSFET is connected to the second output terminal of the current calibration circuit, which serves as the input terminal of the controlled capacitor regulation circuit.

[0024] The drain of the first MOSFET is connected to the drain of the second MOSFET and the first terminal of the first capacitor, and together they serve as the output terminal of the controlled capacitor regulation circuit and are connected to the third input terminal of the voltage-controlled current source.

[0025] The source of the second MOSFET is connected to the second terminal of the first capacitor and grounded.

[0026] Preferably, the voltage-controlled current source includes: a comparator, a third MOSFET, and a second capacitor;

[0027] The non-inverting input of the comparator is connected to the first input of the voltage-controlled current source, the first output of the current calibration circuit, and the input of the controllable resistor adjustment circuit.

[0028] The inverting input of the comparator is connected to the output of the controlled capacitor regulation circuit as the third input of the voltage-controlled current source.

[0029] The comparator's output is connected to the gate of the third MOSFET;

[0030] The source of the third MOSFET is connected to the third output of the current calibration circuit as the second input terminal of the voltage-controlled current source.

[0031] The drain of the third MOSFET is connected to the first terminal of the second capacitor, and together they serve as the output terminal of the voltage-controlled current source, which is connected to the input terminal of the power supply suppression circuit.

[0032] The second terminal of the second capacitor is grounded.

[0033] Preferably, the ring resonator circuit includes: N output oscillation circuits, where N is an odd number greater than 1;

[0034] Wherein, the input terminal of the Xth output oscillation circuit is connected to the output terminal of the (X-1)th output oscillation circuit; X is an integer greater than 1 and not greater than N;

[0035] The output terminal of the Nth output oscillation circuit is connected to the input terminal of the 1st output oscillation circuit, and is also connected to the input terminal of the frequency divider circuit as the output terminal of the ring oscillation circuit.

[0036] The power supply terminals of each output oscillation circuit are connected together, and together they serve as the control terminal of the ring oscillation circuit and are connected to the output terminal of the power supply suppression circuit.

[0037] Preferably, the output oscillation circuit is an inverter;

[0038] The input terminal of the inverter serves as the input terminal of the output oscillation circuit.

[0039] The output terminal of the inverter serves as the output terminal of the output oscillation circuit.

[0040] The power supply terminal of the inverter is connected to the output terminal of the output oscillation circuit and the output terminal of the power supply suppression circuit.

[0041] Preferably, the frequency division circuit is a frequency divider;

[0042] The input terminal of the frequency divider is connected to the output terminal of the ring resonator circuit as the input terminal of the frequency divider circuit.

[0043] The first and second outputs of the frequency divider are combined and connected to the input of the clock calibration circuit as the output of the frequency divider circuit.

[0044] Preferably, the power supply suppression circuit includes: a fourth MOSFET and a fifth MOSFET;

[0045] Among them, the gate of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, and together they serve as the current terminal of the power supply suppression circuit and are connected to the fourth output terminal of the current calibration circuit.

[0046] The source of the fourth MOSFET is connected to the power supply;

[0047] The drain of the fourth MOSFET is connected to the source of the fifth MOSFET, and together they serve as the output terminal of the power supply suppression circuit and are connected to the control terminal of the ring oscillator circuit.

[0048] The gate of the fifth MOSFET is connected to the output of the clock calibration circuit as the input of the power supply suppression circuit.

[0049] On the other hand, this application also provides an oscillator including the above-described calibration oscillation circuit.

[0050] This application provides a calibration oscillation circuit, comprising: a ring oscillator circuit, a frequency divider circuit, a clock calibration circuit, and a power supply suppression circuit. The input terminal of the frequency divider circuit is connected to the output terminal of the ring oscillator circuit to acquire the clock frequency signal output by the ring oscillator circuit. The input terminal of the clock calibration circuit is connected to the output terminal of the frequency divider circuit to acquire the voltage signal determined by the frequency divider circuit based on the clock frequency signal. The input terminal of the power supply suppression circuit is connected to the output terminal of the clock calibration circuit to acquire the calibration voltage signal determined by the clock calibration circuit based on the voltage signal and a preset voltage signal. The output terminal of the power supply suppression circuit is connected to the control terminal of the ring oscillator circuit to output the calibration voltage determined by the calibration voltage signal to the ring oscillator circuit, so that the ring oscillator circuit calibrates the clock frequency signal according to the calibration voltage and outputs the calibrated clock frequency signal. Therefore, this application converts the clock frequency signal to be transmitted into a voltage signal during the calibration process, avoiding the influence of external interference on the frequency during signal transmission. Furthermore, the use of an additional power supply suppression circuit reduces the impact of power fluctuations on the stability and accuracy of the output clock frequency signal. Attached Figure Description

[0051] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A structural diagram of a calibration oscillation circuit provided in this application;

[0053] Figure 2 Circuit diagrams of the ring resonator circuit, frequency divider circuit, and clock calibration circuit provided in the embodiments of this application;

[0054] Figure 3 A circuit diagram of the power suppression circuit provided in an embodiment of this application. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0056] The core of this application is to provide a calibration oscillation circuit and an oscillator.

[0057] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0058] Figure 1 A structural diagram of a calibration oscillation circuit provided in this application is shown below. Figure 1 As shown, the circuit includes: a ring oscillator circuit 1, a frequency divider circuit 2, a clock calibration circuit 3, and a power supply suppression circuit 4. The connection relationships of the calibration oscillator circuit are as follows: the input terminal of the frequency divider circuit 2 is connected to the output terminal of the ring oscillator circuit 1; the input terminal of the clock calibration circuit 3 is connected to the output terminal of the frequency divider circuit 2; the input terminal of the power supply suppression circuit 4 is connected to the output terminal of the clock calibration circuit 3; and the output terminal of the power supply suppression circuit 4 is connected to the control terminal of the ring oscillator circuit 1.

[0059] In a specific embodiment, the ring resonator circuit 1 first outputs a clock frequency signal (this clock frequency signal can be understood as the first clock frequency signal); the frequency divider circuit 2, through its connection with the ring resonator circuit 1, obtains the clock frequency signal output by the ring resonator circuit 1, avoiding the influence of external interference on the frequency during signal transmission. The frequency divider circuit 2 converts the clock frequency signal into a voltage signal; the clock calibration circuit 3, through its connection with the frequency divider circuit 2, obtains the voltage signal, and then determines the calibration voltage signal based on its stored preset voltage signal. This step mainly determines whether the clock frequency signal output by the ring resonator circuit 1 is stable and... A high-precision signal (which can also be understood as whether the clock frequency signal corresponding to the voltage signal is exactly the same as the preset clock frequency signal corresponding to the preset voltage signal) means that the calibration voltage signal determined by the clock calibration circuit 3 is ultimately used to calibrate the clock frequency signal; the power supply suppression circuit 4 obtains the calibration voltage signal determined by the clock calibration circuit 3 through its connection with the clock calibration circuit 3, and then converts the calibration voltage signal into a calibration voltage; the ring oscillation circuit 1 obtains the calibration voltage at this time through its connection with the power supply suppression circuit 4, and then recalibrates the clock frequency signal through its own function. That is to say, the output signal at this time is the calibrated clock frequency signal.

[0060] It should be noted that the calibrated clock frequency signal output by the circuit will be used again as the clock frequency signal output by the ring oscillator circuit 1 to the frequency divider circuit 2, and will be calibrated again. The clock frequency signal transmitted in this circuit is a continuously calibrated signal, and the process of calibrating the clock frequency signal is a cyclic process.

[0061] The specific working principle of the clock calibration circuit 3 is as follows: It acquires the voltage signal output by the frequency divider circuit 2. Since the voltage signal is obtained by the frequency divider circuit 2 based on the clock frequency signal, its main purpose is to convert the frequency signal into a voltage signal, avoiding external interference from affecting the frequency. Therefore, the voltage signal can also be understood as another form of the clock frequency signal. The clock calibration circuit 3 internally stores a standard preset clock frequency signal, and its preset voltage signal serves as another form of the preset clock frequency signal. After acquiring the voltage signal, the clock calibration circuit 3 compares it with its stored preset voltage signal (which can also be understood as a comparison between the preset clock frequency signal and the clock frequency signal). When there is a difference between the preset voltage signal and the voltage signal (the preset clock frequency signal and the clock frequency signal are different), the calibration voltage signal specifically indicates that the clock frequency signal needs to be calibrated, and the calibration voltage signal specifically includes the calibration amplitude. When there is no difference between the preset voltage signal and the voltage signal (the preset clock frequency signal and the clock frequency signal are the same), the calibration voltage signal specifically indicates that the clock frequency signal does not need to be calibrated.

[0062] This application provides a calibration oscillation circuit, comprising: a ring oscillator circuit, a frequency divider circuit, a clock calibration circuit, and a power supply suppression circuit. The input terminal of the frequency divider circuit is connected to the output terminal of the ring oscillator circuit to acquire the clock frequency signal output by the ring oscillator circuit. The input terminal of the clock calibration circuit is connected to the output terminal of the frequency divider circuit to acquire the voltage signal determined by the frequency divider circuit based on the clock frequency signal. The input terminal of the power supply suppression circuit is connected to the output terminal of the clock calibration circuit to acquire the calibration voltage signal determined by the clock calibration circuit based on the voltage signal and a preset voltage signal. The output terminal of the power supply suppression circuit is connected to the control terminal of the ring oscillator circuit to output the calibration voltage signal to the ring oscillator circuit, so that the ring oscillator circuit calibrates the clock frequency signal according to the calibration voltage signal and outputs the calibrated clock frequency signal. Therefore, this application converts the clock frequency signal to be transmitted into a voltage signal during the signal correction process, avoiding the influence of external interference on the frequency during signal transmission. Furthermore, the use of an additional power supply suppression circuit reduces the impact of power fluctuations on the stability and accuracy of the output clock frequency signal.

[0063] Based on the above embodiments, as a preferred option, such as Figure 2As shown, the clock calibration circuit 3 includes: a controllable resistor adjustment circuit 31, a controlled capacitor adjustment circuit 32, a voltage-controlled current source 33, and a current calibration circuit 34. The connections of the clock calibration circuit 3 are as follows: the input terminal of the current calibration circuit 34 is connected to the current signal transmitting terminal; the first output terminal of the current calibration circuit 34 is connected to the input terminal of the controllable resistor adjustment circuit 31 and the first input terminal of the voltage-controlled current source 33; the second output terminal of the current calibration circuit 34 is connected to the input terminal of the controlled capacitor adjustment circuit 32; the third output terminal of the current calibration circuit 34 is connected to the second input terminal of the voltage-controlled current source 33; and the fourth output terminal of the current calibration circuit 34 is connected to the current terminal of the power supply suppression circuit 4. The output terminal of the controllable resistor adjustment circuit 31 is grounded; the control terminal of the controlled capacitor adjustment circuit 32 serves as the input terminal of the clock calibration circuit 3 and is connected to the output terminal of the frequency divider circuit 2; the output terminal of the controlled capacitor adjustment circuit 32 is connected to the third input terminal of the voltage-controlled current source 33; and the output terminal of the voltage-controlled current source 33 serves as the output terminal of the clock calibration circuit 3 and is connected to the input terminal of the power supply suppression circuit 4. In addition, the controllable resistor adjustment circuit 31, the controlled capacitor adjustment circuit 32, the voltage-controlled current source 33, and the current calibration circuit 34 are also connected to the power supply VDD.

[0064] In a specific embodiment, the input terminal of the current calibration circuit 34 is connected to the current signal transmitting terminal to acquire two sets of currents: one set is the zero temperature coefficient current IREF, and the other set is the positive temperature coefficient current IPTAT. The current calibration circuit 34 generates four bias currents, namely Iref1, Iref2, Iref3, and Iref4, based on the zero temperature coefficient current IREF and the positive temperature coefficient current IPTAT. The first output terminal of the current calibration circuit 34 corresponds to Iref1. When the first output terminal of the current calibration circuit 34 is connected to the input terminal of the controllable resistor adjustment circuit 31 and the first input terminal of the voltage-controlled current source 33, it mainly sends Iref1 to the controllable resistor adjustment circuit 31 and the voltage-controlled current source 33. The second output terminal of the current calibration circuit 34 corresponds to Iref2. When the second output terminal of the current calibration circuit 34 is connected to the input terminal of the controlled capacitor adjustment circuit 32, it mainly sends Iref2 to the controlled capacitor adjustment circuit 32. The third output terminal of the current calibration circuit 34 corresponds to Iref3. When the third output terminal of the current calibration circuit 34 is connected to the second input terminal of the voltage-controlled current source 33, it mainly sends Iref3 to the voltage-controlled current source 33. The fourth output terminal of the current calibration circuit 34 corresponds to Iref4. When the fourth output terminal of the current calibration circuit 34 is connected to the current terminal of the power supply suppression circuit 4, it mainly sends Iref4 to the power supply suppression circuit 4.

[0065] Iref1 is determined based on the difference between the zero-temperature coefficient current IREF and the positive temperature coefficient current IPTAT. The main reason for this is to introduce the positive temperature coefficient current IPTAT, which varies linearly with temperature, to reduce the impact of temperature changes in components such as resistors and capacitors on the accuracy of the output signal. Iref2, Iref3, and Iref4 are obtained by replicating the zero-temperature coefficient current IREF.

[0066] Furthermore, such as Figure 2 As shown, the controllable resistor adjustment circuit 31 is the first resistor R1. The circuit connections are as follows: the first end of the first resistor R1 serves as the input terminal of the controllable resistor adjustment circuit 31, connected to the first output terminal of the current calibration circuit 34 and the first input terminal of the voltage-controlled current source 33; the second end of the first resistor R1 serves as the input terminal of the controllable resistor adjustment circuit 31 and is grounded. The controllable resistor adjustment circuit obtains Iref1, which is mainly used to adjust the resistance value of the first resistor R1, thereby changing the voltage VIP at the first input terminal of the voltage-controlled current source 33.

[0067] Furthermore, such as Figure 2 As shown, the controlled capacitor adjustment circuit 32 includes a first MOSFET Q1, a second MOSFET Q2, and a first capacitor C1. The circuit connections are as follows: the gates of the first MOSFET Q1 and the second MOSFET Q2 together serve as the control terminal of the controlled capacitor adjustment circuit 32 and are connected to the output terminal of the frequency divider circuit 2; the source of the first MOSFET Q1 is connected to the second output terminal of the current calibration circuit 34, which serves as the input terminal of the controlled capacitor adjustment circuit 32; the drain of the first MOSFET Q1 is connected to the drain of the second MOSFET Q2 and the first terminal of the first capacitor C1, and together they serve as the output terminal of the controlled capacitor adjustment circuit 32 and are connected to the third input terminal of the voltage-controlled current source 33; the source of the second MOSFET Q2 is connected to the second terminal of the first capacitor C1 and grounded. The controlled capacitor adjustment circuit 32 is used to obtain Iref2, and by controlling the on / off state of the first MOSFET Q1 and the second MOSFET Q2, it controls the charging and discharging of the first capacitor C1, thereby changing the voltage VIN at the third input terminal of the voltage-controlled current source 33. The signal controlling the on / off state of the first MOSFET Q1 is S1, and the signal controlling the on / off state of the second MOSFET Q2 is S2. Both signals S1 and S2 are output through the frequency divider circuit 2.

[0068] Furthermore, such as Figure 2As shown, the voltage-controlled current source 33 includes: a comparator U, a third MOSFET Q3, and a second capacitor C2. The circuit connections are as follows: the non-inverting input of the comparator U serves as the first input of the voltage-controlled current source 33, connected to the first output of the current calibration circuit 34 and the input of the controllable resistor adjustment circuit 31; the inverting input of the comparator U serves as the third input of the voltage-controlled current source 33, connected to the output of the controlled capacitor adjustment circuit 31; the output of the comparator U is connected to the gate of the third MOSFET Q3; the source of the third MOSFET Q3 serves as the second input of the voltage-controlled current source 33, connected to the third output of the current calibration circuit 34; the drain of the third MOSFET Q3 is connected to the first terminal of the second capacitor C2, and together they serve as the output of the voltage-controlled current source 33, connected to the input of the power supply suppression circuit 4; the second terminal of the second capacitor C2 is grounded. The non-inverting input of comparator U is connected to the first output of current calibration circuit 34 and the input of controllable resistor adjustment circuit 31 (the first end of the first resistor R1). At this time, the voltage at the non-inverting input of comparator U is VIP. The inverting input of comparator U is connected to the output of controlled capacitor adjustment circuit 32 (the drain of the first MOS transistor Q1, the drain of the second MOS transistor Q2, and the first end of the first capacitor C1). At this time, the voltage at the inverting input of comparator U is VIN.

[0069] Combination Figure 2 The controllable resistor adjustment circuit 31 and the controlled capacitor adjustment circuit 32 shown herein, wherein when the first capacitor C1 in the controlled capacitor adjustment circuit 32 is charged and discharged, it converts the clock frequency signal into a voltage signal and feeds it back to the inverting input terminal of the comparator U. The expression for the voltage VIN at the inverting input terminal of the comparator U generated by the first capacitor C1 is as follows:

[0070] VIN = Iref2 / (F*C1);

[0071] In the voltage-controlled current source 33, based on the comparator, the relationship between the voltage at its non-inverting output terminal and the voltage at its inverting input terminal is expressed as follows:

[0072] VIP = Iref1 * R1 = VIN;

[0073] In this circuit, R1 represents the resistance of the first resistor, C1 represents the capacitance of the first capacitor, and F represents the frequency of the clock signal. At this time, the output of comparator U drives the third MOSFET Q3 to conduct, charging the second capacitor C2. This generates a voltage Vb, which is input to the power supply suppression circuit 4 to output a calibration voltage Vo. Therefore, in the current circuit structure, the frequency of the clock signal is only related to the resistance of the first resistor R1 and the capacitance of the first capacitor C1. In other words, the resistance of the first resistor R1 and the capacitance of the first capacitor C1 can be adjusted at any time to ensure that the frequency of the output clock signal meets the design requirements, reducing the influence of process parameters on the frequency.

[0074] It should be noted that this application is only one possible method, but it is not limited to this method. Users can set it up according to their own needs.

[0075] This application provides a specific structure for a clock calibration circuit. In this structure, the frequency of the clock frequency signal is only related to the capacitance and resistance, which means that the clock frequency signal is converted into a voltage signal, reducing the influence of process parameters on the frequency.

[0076] Based on the above embodiments, as a preferred embodiment, the ring oscillation circuit includes: N output oscillation circuits, where N is an odd number greater than 1. The circuit connections are as follows: the input terminal of the Xth output oscillation circuit is connected to the output terminal of the (X-1)th output oscillation circuit; X is an integer greater than 1 and not greater than N; the output terminal of the Nth output oscillation circuit is connected to the input terminal of the 1st output oscillation circuit, and serves as the output terminal of the ring oscillation circuit, connected to the input terminal of the frequency divider circuit; the power supply terminals of each output oscillation circuit are connected, and together serve as the control terminal of the ring oscillation circuit, connected to the output terminal of the power supply suppression circuit.

[0077] like Figure 2 As shown (using a three-output oscillation circuit as an example), the current ring oscillation circuit includes three inverters: a first inverter U1, a second inverter U2, and a third inverter U3. The circuit connections are as follows: the output of the first inverter U1 is connected to the input of the second inverter U2; the output of the second inverter U2 is connected to the input of the third inverter U3; the output of the third inverter U3 is connected to the input of the first inverter U1, and serves as the output of the ring oscillation circuit, connected to the input of the frequency divider circuit; the power supply terminal of the first inverter U1 is connected to the power supply terminals of the second inverter U2 and the third inverter U3, and together they serve as the control terminal of the ring oscillation circuit, connected to the output of the power supply suppression circuit.

[0078] In a specific embodiment, the calibration voltage Vo output by the power supply suppression circuit enters the first inverter U1, the second inverter U2 and the third inverter U3 respectively to calibrate the clock frequency signal generated by its own oscillation. At the same time, the calibrated clock frequency signal output by the third inverter U3 is CLK.

[0079] like Figure 2 As shown, the frequency divider circuit 2 is specifically a frequency divider D. Its connection is as follows: the input terminal of the frequency divider D is connected to the output terminal of the ring resonator circuit 1 as the input terminal of the frequency divider circuit 2; the first and second output terminals of the frequency divider D together serve as the output terminals of the frequency divider circuit 2 and are connected to the input terminal of the clock calibration circuit 1.

[0080] In a specific embodiment, the frequency divider D is used to acquire the calibrated clock frequency signal CLK, and then outputs signals S1 and S2 through its own frequency division function. Signal S1 is used to control the on / off state of the first MOSFET Q1, and signal S2 is used to control the on / off state of the second MOSFET Q2.

[0081] like Figure 3 As shown, the power supply suppression circuit 4 includes a fourth MOSFET Q4 and a fifth MOSFET Q5. The gate of the fourth MOSFET is connected to the drain of the fifth MOSFET, and together they serve as the current terminal of the power supply suppression circuit 4, which is connected to the fourth output terminal of the current calibration circuit 34. The source of the fourth MOSFET Q4 is connected to the power supply VDD. The drain of the fourth MOSFET Q4 is connected to the source of the fifth MOSFET Q5, and together they serve as the output terminal of the power supply suppression circuit 4, which is connected to the control terminal of the ring oscillation circuit 1. The gate of the fifth MOSFET Q5 serves as the input terminal of the power supply suppression circuit 4, which is connected to the output terminal of the clock calibration circuit 3.

[0082] In a specific embodiment, the power supply suppression circuit determines the output calibration voltage Vo based on the power supply VDD, Iref4, and voltage Vb. The specific correspondence is not limited in this application and can be set according to the user's needs.

[0083] It should be noted that the embodiments provided in this application are only one possible implementation method, but are not limited to this only implementation method. Users can set their own implementation methods according to their needs.

[0084] Therefore, this application converts the clock frequency signal to be transmitted into a voltage signal during the calibration process of the output signal, avoiding the influence of external interference on the frequency during signal transmission. Furthermore, this application employs an additional power supply suppression circuit to reduce the impact of power supply fluctuations on the stability and accuracy of the output clock frequency signal.

[0085] On the other hand, this application also provides an oscillator including the above-described calibration oscillation circuit, and has the same beneficial effects.

[0086] The embodiments of the oscillator provided in this application are the same as those of the calibration oscillator circuit described above, so they will not be described again here.

[0087] The calibration oscillation circuit and oscillator provided in this application have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0088] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A calibration oscillator circuit, characterized by, include: Ring resonator circuit, frequency divider circuit, clock calibration circuit, and power supply suppression circuit; The input terminal of the frequency divider circuit is connected to the output terminal of the ring resonator circuit, and is used to obtain the clock frequency signal output by the ring resonator circuit. The input terminal of the clock calibration circuit is connected to the output terminal of the frequency divider circuit, and is used to obtain the voltage signal determined by the frequency divider circuit according to the clock frequency signal; The input terminal of the power supply suppression circuit is connected to the output terminal of the clock calibration circuit, and is used to obtain the calibration voltage signal determined by the clock calibration circuit based on the voltage signal and the preset voltage signal. The output terminal of the power suppression circuit is connected to the control terminal of the ring oscillation circuit, and is used to output a calibration voltage determined according to the calibration voltage signal to the ring oscillation circuit, so that the ring oscillation circuit calibrates the clock frequency signal according to the calibration voltage and outputs the calibrated clock frequency signal.

2. The calibration oscillator circuit of claim 1, wherein, The clock calibration circuit includes: a controllable resistor adjustment circuit, a controlled capacitor adjustment circuit, a voltage-controlled current source, and a current calibration circuit. The input terminal of the current calibration circuit is connected to the current signal transmitting terminal. The first output terminal of the current calibration circuit is connected to the input terminal of the controllable resistor adjustment circuit and the first input terminal of the voltage-controlled current source; the second output terminal of the current calibration circuit is connected to the input terminal of the controlled capacitor adjustment circuit; the third output terminal of the current calibration circuit is connected to the second input terminal of the voltage-controlled current source; and the fourth output terminal of the current calibration circuit is connected to the current terminal of the power supply suppression circuit. The output terminal of the controllable resistor adjustment circuit is grounded; The control terminal of the controlled capacitor adjustment circuit is connected to the output terminal of the frequency divider circuit as the input terminal of the clock calibration circuit. The output terminal of the controlled capacitor regulation circuit is connected to the third input terminal of the voltage-controlled current source; The output terminal of the voltage-controlled current source is connected to the input terminal of the power supply suppression circuit, serving as the output terminal of the clock calibration circuit.

3. The calibration oscillator circuit of claim 2, wherein, The controllable resistor adjustment circuit is the first resistor; Wherein, the first end of the first resistor serves as the input end of the controllable resistor adjustment circuit and is connected to the first output end of the current calibration circuit and the first input end of the voltage-controlled current source; The second end of the first resistor is grounded as the input terminal of the controllable resistor adjustment circuit.

4. The calibration oscillator circuit of claim 2, wherein, The controlled capacitor regulation circuit includes: a first MOSFET, a second MOSFET, and a first capacitor; The gates of the first MOS transistor and the second MOS transistor are connected together as the control terminal of the controlled capacitor adjustment circuit and the output terminal of the frequency divider circuit. The source of the first MOS transistor is connected to the second output terminal of the current calibration circuit, which serves as the input terminal of the controlled capacitor adjustment circuit. The drain of the first MOS transistor is connected to the drain of the second MOS transistor and the first terminal of the first capacitor, and together they serve as the output terminal of the controlled capacitor regulation circuit and are connected to the third input terminal of the voltage-controlled current source. The source of the second MOS transistor is connected to the second terminal of the first capacitor and grounded.

5. The calibration oscillator circuit of claim 2, wherein, The voltage-controlled current source includes: a comparator, a third MOSFET, and a second capacitor; The non-inverting input of the comparator is connected to the first input of the voltage-controlled current source, the first output of the current calibration circuit, and the input of the controllable resistor adjustment circuit. The inverting input terminal of the comparator is connected to the output terminal of the controlled capacitor adjustment circuit as the third input terminal of the voltage-controlled current source. The output of the comparator is connected to the gate of the third MOS transistor; The source of the third MOS transistor is connected to the third output terminal of the current calibration circuit as the second input terminal of the voltage-controlled current source. The drain of the third MOS transistor is connected to the first terminal of the second capacitor, and together they serve as the output terminal of the voltage-controlled current source and are connected to the input terminal of the power supply suppression circuit. The second terminal of the second capacitor is grounded.

6. The calibration oscillator circuit of claim 2, wherein, The ring resonator circuit includes: N output oscillation circuits, where N is an odd number greater than 1; Wherein, the input terminal of the Xth output oscillation circuit is connected to the output terminal of the (X-1)th output oscillation circuit; X is an integer greater than 1 and not greater than N; The output terminal of the Nth output oscillation circuit is connected to the input terminal of the 1st output oscillation circuit, and is also connected to the input terminal of the frequency divider circuit as the output terminal of the ring oscillation circuit. The power supply terminals of each of the output oscillation circuits are connected, and together they serve as the control terminal of the ring oscillation circuit, which is connected to the output terminal of the power supply suppression circuit.

7. The calibration oscillator circuit of claim 6, wherein, The output oscillation circuit is an inverter; The input terminal of the inverter serves as the input terminal of the output oscillation circuit. The output terminal of the inverter serves as the output terminal of the output oscillation circuit. The power supply terminal of the inverter is connected to the output terminal of the output oscillation circuit and the output terminal of the power supply suppression circuit.

8. The calibration oscillator circuit of claim 2, wherein, The frequency division circuit is a frequency divider; The input terminal of the frequency divider is connected to the output terminal of the frequency divider circuit as the input terminal of the frequency divider circuit. The first and second output terminals of the frequency divider together serve as the output terminals of the frequency divider circuit and are connected to the input terminals of the clock calibration circuit.

9. A calibration oscillator circuit according to any one of claims 2 to 8, characterised in that, The power supply suppression circuit includes: a fourth MOSFET and a fifth MOSFET; The gate of the fourth MOS transistor is connected to the drain of the fifth MOS transistor, and together they serve as the current terminal of the power supply suppression circuit and are connected to the fourth output terminal of the current calibration circuit. The source of the fourth MOS transistor is connected to the power supply; The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor, and together they serve as the output terminal of the power supply suppression circuit and are connected to the control terminal of the ring oscillation circuit. The gate of the fifth MOS transistor is connected to the output of the clock calibration circuit as the input of the power supply suppression circuit.

10. An oscillator characterized by Includes the calibration oscillation circuit as described in any one of claims 1-9.

Images