Method and system for arbitrary multiple sampling rate conversion in a communication system

By constructing a hierarchical sampling clock adjustment mechanism in the communication system, and using a high-precision reference clock and DAC to correct the frequency of the voltage-controlled crystal oscillator, the high complexity and low real-time performance of sampling rate transformations of integer multiples, fractional multiples, and irrational multiples in the communication system are solved. This achieves high-precision, wide-range sampling rate adjustment, improving the system's flexibility and stability.

CN122293084APending Publication Date: 2026-06-26HUNAN ECONOVEL TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
HUNAN ECONOVEL TECH CO LTD
Filing Date
2026-03-20
Publication Date
2026-06-26

AI Technical Summary

Technical Problem

Existing communication systems suffer from high complexity, high resource consumption, and poor real-time performance when converting sampling rates to integer multiples, fractional multiples, and irrational multiples. In particular, it is difficult to achieve high-precision adjustment in irrational multiple conversions.

Method used

By constructing a hierarchical sampling clock adjustment mechanism among the FPGA unit, ADC unit, DAC unit, voltage-controlled crystal oscillator and frequency divider unit, the frequency of the voltage-controlled crystal oscillator is corrected using a high-precision reference clock and DAC, achieving accurate sampling rate conversion of integer multiples, fractional multiples and irrational multiples.

Benefits of technology

It achieves high-precision and wide-range adjustable sampling rate, improves system flexibility and versatility, enhances stability and anti-jitter capability, and is suitable for high-performance and broadband communication.

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Abstract

This invention discloses a method and system for arbitrary sampling rate conversion in a communication system. The method includes: setting a target sampling rate; determining the multiple relationship between the target sampling rate and the nominal frequency of the reference clock of a voltage-controlled crystal oscillator (VCO), wherein the multiple relationship includes integer multiples, fractional multiples, and irrational multiples; configuring a frequency divider unit according to the multiple relationship, so that the frequency divider unit outputs a sampling clock driven by the nominal frequency of the reference clock; using the sampling clock to drive the ADC unit to work, outputting a follow-up clock to the FPGA unit, and the FPGA unit performing frequency division based on the follow-up clock to obtain a buffered follow-up clock; when the multiple relationship is an irrational multiple, the FPGA unit uses a high-precision reference clock as a reference, and outputs a finely tuned sampling clock based on the error between the frequency of the buffered follow-up clock and the target sampling rate to control the DAC unit, and the DAC unit modifies the clock frequency of the VCO to obtain a precise sampling clock that meets the target sampling rate requirements. This invention can achieve high-precision adjustment of arbitrary sampling rates.
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