A vertical channel junction field-effect transistor and its manufacturing method
By designing a vertical channel junction field-effect transistor structure and utilizing the vertical current path of the deep masking region and deep gate region, the problems of high cost and long current path in the prior art are solved, and the miniaturization and high current density of the device are realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING THIRD GENERATION SEMICON TECH INNOVATION CENT CO LTD
- Filing Date
- 2026-05-29
- Publication Date
- 2026-06-30
AI Technical Summary
The deep trench etching and sidewall implantation processes of existing vertical channel JFET devices increase mass production costs, and the device conduction current path is relatively long, making it difficult to reduce the cell size.
By adopting a vertical channel junction field-effect transistor structure, a vertical current path is designed by forming a deep masking region and a deep gate region of the second conductivity type on the substrate, and the source region and gate are formed by ion implantation process, avoiding trench etching process and reducing process cost.
This approach achieves a reduction in device cell size and an increase in current density, while providing a good pinch-off effect in the off state, reducing process costs and improving device manufacturability.
Smart Images
Figure CN122318271A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a vertical channel junction field-effect transistor and its manufacturing method. Background Technology
[0002] As power electronics technology continues to develop towards higher power density, lower switching losses, and miniaturization, the performance of power semiconductor devices urgently needs improvement. Commonly used power semiconductor devices include metal-oxide-semiconductor field-effect transistors (MOSFETs) and junction field-effect transistors (JFETs). Compared to MOSFETs, JFETs, due to the absence of a gate dielectric, fundamentally avoid the instability problem of MOSFET structures at high temperatures, thus achieving superior high-temperature reliability.
[0003] JFET devices are mainly divided into two types: horizontal channel JFET devices and vertical channel JFET devices. A typical horizontal channel JFET device structure is shown below. Figure 1 As shown, the device includes a second conductivity type masking region 4 and a second conductivity type gate region 7 located within the structure. The pinch-off effect between the masking region and the gate region is used to achieve device turn-off. The disadvantages of this device are the introduction of a horizontal channel, a more tortuous current path, difficulty in minimizing the cell size, and difficulty in reducing the device's on-resistance. A typical vertical channel JFET device is shown below. Figure 2 As shown, trench 10 is formed by etching process, and the sidewalls and bottom of the trench are injected to form a masking area. This structure is widely used because of its relatively short current conduction path and easy miniaturization of cell size. However, deep trench etching and sidewall injection process significantly increase the process difficulty, resulting in a significant increase in mass production cost. Summary of the Invention
[0004] Technical objective: To address the deficiencies in existing technologies, this invention provides a vertical channel junction field-effect transistor and its manufacturing method, which simultaneously achieves a significant reduction in the on-current path and good pinch-off of the off state within a relatively low process cost range, thereby obtaining excellent forward conduction characteristics and reverse turn-off capability.
[0005] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.
[0006] A vertical channel junction field-effect transistor, comprising: Drain; A first conductivity type substrate located above the drain electrode; a first conductivity type epitaxial layer located on the first conductivity type substrate; Several deep masking regions of the second conductivity type are located within the epitaxial layer of the first conductivity type; source regions of the second conductivity type are located within the deep masking regions of the second conductivity type; The first conductivity type source region is located in the deep masking region of the second conductivity type, in the epitaxial layer of the first conductivity type, and on both sides of the source region of the second conductivity type. The second conductivity type deep gate region is located within the first conductivity type epitaxial layer and between adjacent second conductivity type deep masking regions; the lower surface of the second conductivity type deep masking region is lower than the lower surface of the first conductivity type source region, and the depth difference D between the second conductivity type deep gate region and the first conductivity type source region is greater than or equal to 0.1 μm; the horizontal spacing between the second conductivity type deep gate region and adjacent second conductivity type deep masking regions is greater than or equal to 0.2 μm. A gate located above a deep gate region of the second conductivity type; a source located above a source region of the first conductivity type and a source region of the second conductivity type.
[0007] This embodiment also discloses a method for manufacturing a vertical channel junction field-effect transistor (VFET), used to prepare the VFET described above, comprising the following steps: Step 1: Form an epitaxial layer of the first conductivity type on a substrate of the first conductivity type; Step 2: Form several deep masking regions of the second conductivity type in the epitaxial layer of the first conductivity type; Step 3: Form a second conductivity type deep gate region in the first conductivity type epitaxial layer, located between adjacent second conductivity type deep masking regions; Step 4: Form a first conductivity type source region in the first conductivity type epitaxial layer and the second conductivity type deep masking region, and form a second conductivity type source region in the first conductivity type source region and the second conductivity type deep masking region; the second conductivity type source region divides the first conductivity type source region into two non-connected parts; Step 5: Form a gate on the deep gate region of the second conductivity type, form a source on the source region of the first conductivity type and the source region of the second conductivity type, and form a drain on the bottom layer of the substrate of the first conductivity type.
[0008] Beneficial effects: 1. The vertical channel junction field-effect transistor structure of the present invention suppresses leakage current in the off state by means of the pinch-off effect between the deep masking region of the second conductivity type and the deep gate region of the second conductivity type, and forms a vertical current path in the on state. Through structural design, the cell size of the device can be further reduced, thereby significantly improving the current density and avoiding the inherent disadvantages of horizontal channel JFET devices. 2. The vertical channel junction field-effect transistor structure of the present invention, through the structural design of the deep masking region and the deep gate region of the second conductivity type, can achieve a good pinch-off effect without the need for trench etching process, thereby significantly reducing process cost, significantly improving the manufacturability of JFET devices, and making up for the biggest shortcoming of vertical channel JFET devices. Attached Figure Description
[0009] Figure 1 This is a schematic diagram of a typical horizontal channel junction field-effect transistor structure in the prior art; Figure 2 This is a schematic diagram of a typical vertical channel junction field-effect transistor structure in the prior art; Figure 3 This is a schematic diagram of a vertical channel junction field-effect transistor structure according to Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of a vertical channel junction field-effect transistor structure according to Embodiment 2 of the present invention; Figures 5-10 This is a schematic diagram of a manufacturing method for a vertical channel junction field-effect transistor according to Example 1; Explanation of reference numerals in the attached figures: 1. Drain; 2. Substrate of the first conductivity type; 3. Epitaxial layer of the first conductivity type; 4. Masking region of the second conductivity type; 5. Source region of the second conductivity type; 6. Source region of the first conductivity type; 7. Gate region of the second conductivity type; 8. Source; 9. Gate; 10. Trench; 11. Deep masking region of the second conductivity type; 12. Deep gate region of the second conductivity type; 13. Pillar region of the first conductivity type. Detailed Implementation
[0010] The following description, in conjunction with the accompanying drawings and embodiments, further explains and illustrates a trench gate electrode self-alignment formation method of the present invention.
[0011] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.
[0012] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In this invention, the horizontal direction of the device is defined as the x-direction, i.e., the width of the corresponding structure, and the vertical direction of the device is defined as the y-direction, i.e., the depth of the corresponding structure.
[0013] Example 1: As shown in the attached document Figure 3 As shown, a vertical channel junction field-effect transistor of the present invention includes: Drain 1; A first conductivity type substrate 2 is located above the drain electrode 1; the first conductivity type substrate 2 is a first conductivity type SiC substrate; a first conductivity type epitaxial layer 3 is located on the first conductivity type substrate 2, the first conductivity type epitaxial layer 3 is a first conductivity type SiC epitaxial layer; A plurality of second conductivity type deep masking regions 11 located in the first conductivity type epitaxial layer 3; a second conductivity type source region 5 located in the second conductivity type deep masking regions 11; The first conductivity type source region 6 is located in the second conductivity type deep masking region 11, in the first conductivity type epitaxial layer 3, and on both sides of the second conductivity type source region 5; A second conductive type deep gate region 12 is located within the first conductive type epitaxial layer 3, between adjacent second conductive type deep masking regions 11; the lower surface of the second conductive type deep masking region 11 is lower than the lower surface of the second conductive type deep gate region 12, and the depth difference between the second conductive type deep masking region 11 and the second conductive type deep gate region 12 is greater than or equal to 0.1 μm; the lower surface of the second conductive type deep masking region 11 is lower than the lower surface of the first conductive type source region 6, and the depth difference D between the second conductive type deep gate region 12 and the first conductive type source region 6 is not less than 0.1 μm, preferably ranging from 0.2 µm to 1.0 µm; the horizontal spacing between the second conductive type deep gate region 12 and adjacent second conductive type deep masking regions 11 is greater than or equal to 0.2 µm; Gate 9 located above the deep gate region 12 of the second conductivity type; source 8 located above the source region 6 of the first conductivity type and the source region 5 of the second conductivity type.
[0014] In this embodiment, a vertical channel junction field-effect transistor (VFET) significantly reduces the device cell size and increases the current density in the forward conduction state through its vertical channel design. In the off state, the pinch-off effect of the deep masking region and the deep gate region of the second conductivity type reduces the electric field and leakage current.
[0015] This embodiment also provides a method for manufacturing a vertical channel junction field-effect transistor, such as... Figures 5-10 As shown, it includes the following steps: Step 1: Form a first conductivity type epitaxial layer 3 on a first conductivity type substrate 2; like Figure 5 , Figure 6 As shown, a first conductivity type epitaxial layer 3 is formed on a first conductivity type substrate 2 by epitaxial growth. The depth of the first conductivity type epitaxial layer 3 is greater than or equal to 5 μm, and the doping concentration ranges from 1e15 cm⁻¹. -3 ~ 1e17cm -3 The semiconductor materials used in the device include Si and SiC.
[0016] Step 2: Form several deep masking regions 11 of the second conductivity type in the epitaxial layer 3 of the first conductivity type; like Figure 7 As shown, a patterned ion implantation mask layer is formed on the surface of the first conductivity type epitaxial layer 3 prepared in step 1. Ion implantation is performed using the patterned ion implantation mask layer to form a second conductivity type deep masking region 11. The depth of the second conductivity type deep masking region 11 is greater than or equal to 1 μm, preferably in the range of 1.5 µm to 3.5 µm, and the doping concentration range is 5e17 cm⁻¹. -3 ~ 5e18cm -3 Then the ion implantation mask layer is removed; the upper surface of the second conductivity type deep masking region 11 is flush with the upper surface of the first conductivity type epitaxial layer 3.
[0017] Step 3: Form a second conductivity type deep gate region 12 located between adjacent second conductivity type deep masking regions 11 in the first conductivity type epitaxial layer 3; like Figure 8 As shown, a patterned ion implantation mask layer is formed on the surface of the first conductivity type epitaxial layer 3 prepared in step 2. Ion implantation is performed using the patterned ion implantation mask layer to form a second conductivity type deep gate region 12. The depth of the second conductivity type deep gate region 12 is greater than or equal to 0.5 μm, preferably in the range of 1.0 µm to 2.5 µm, and the doping concentration range is 1e17 cm⁻¹. -3 ~ 2e18cm -3 The ion implantation mask layer is then removed; wherein, the second conductivity type deep gate region 12 is located between adjacent second conductivity type deep mask regions 11, and the upper surface of the second conductivity type deep gate region 12 is flush with the upper surface of the first conductivity type epitaxial layer 3. The horizontal spacing between the second conductivity type deep gate region 12 and the adjacent second conductivity type deep mask region 11 is greater than or equal to 0.2 μm.
[0018] The lower surface of the second conductivity type deep masking region 11 is lower than the lower surface of the second conductivity type deep gate region 12, and the depth difference between the second conductivity type deep masking region 11 and the second conductivity type deep gate region 12 is greater than or equal to 0.1 μm; Step 4: Form a first conductivity type source region 6 in the first conductivity type epitaxial layer 3 and the second conductivity type deep masking region 11, and form a second conductivity type source region 5 in the first conductivity type source region 6 and the second conductivity type deep masking region 11; the second conductivity type source region 5 divides the first conductivity type source region 6 into two non-connected parts; like Figure 9As shown, a patterned ion implantation mask layer is formed on the surface of the first conductivity type epitaxial layer 3 prepared in step 3. Ion implantation is performed using the patterned ion implantation mask layer, such as by random implantation. The first conductivity type source region 6 and the second conductivity type source region 5 are formed sequentially through the ion implantation process. The second conductivity type source region 5 separates the first conductivity type source region 6 into two non-connected parts. The depth of the second conductivity type source region 5 is greater than or equal to 0.1 μm, preferably in the range of 0.2 µm to 1.0 µm, and the doping concentration range is 1e19 cm⁻¹. -3 ~ 2e20cm -3 The depth of the first conductivity type source region 6 is greater than or equal to 0.1 μm, preferably in the range of 0.2 µm to 1.0 µm, and the doping concentration ranges from 1e19 cm⁻¹. -3 ~ 2e20cm -3 The implantation depth is controlled by adjusting the implantation energy and dose, ensuring that the depth difference D between the second conductivity type deep gate region 12 and the first conductivity type source region 6 is not less than 0.1 μm, preferably ranging from 0.2 µm to 1.0 µm. The value of D determines the length of the vertical channel, thereby determining the on-resistance of the device. The upper surfaces of the first conductivity type source region 6 and the second conductivity type source region 5 are flush with the upper surface of the first conductivity type epitaxial layer 3. The width of the first conductivity type source region 6 is greater than the width of the second conductivity type deep masking region 11, and the width of the second conductivity type source region 5 is less than the width of the second conductivity type deep masking region 11. The horizontal distance between the second conductivity type deep gate region 12 and the nearest first conductivity type source region 6 is greater than or equal to 0.1 μm.
[0019] Step 5: Form a gate 9 on the deep gate region 12 of the second conductivity type, form a source 8 on the source region 6 of the first conductivity type and the source region 5 of the second conductivity type, and form a drain 1 on the bottom layer of the substrate 2 of the first conductivity type. like Figure 10 As shown, gate material is grown on the device surface prepared in step 4, and excess gate material is removed by etching to form gate 9 on the deep gate region 12 of the second conductivity type. Subsequently, source metal is grown on the device surface to form source ohmic contacts on the source region 6 of the first conductivity type and the source region 5 of the second conductivity type. Drain metal is deposited on the bottom layer of the first conductivity type substrate to form drain ohmic contacts. Source 8 is formed on the source ohmic contact surface, and drain 1 is formed on the drain ohmic contact surface.
[0020] In this configuration, the width of the second conductivity type deep gate region 12 is greater than the width of the gate 9. The source 8 simultaneously contacts both sides of the second conductivity type source region 5 and portions of the first conductivity type source region 6. The source and drain materials include one or more combinations of metals such as Ti, Al, Ni, and Pt, while the gate material includes a metal or doped polysilicon. The first conductivity type can be N-type or P-type, and the second conductivity type can correspondingly be P-type or N-type.
[0021] In addition, the ion implantation methods in steps 2 and 3 can be different, such as random implantation or tunnel implantation.
[0022] Example 2: A vertical channel junction field-effect transistor of this example, such as... Figure 4 As shown, the difference from Example 1 is as follows: It also includes a first conductive type pillar region 13 located between the second conductive type deep masking region 11 and the second conductive type deep gate region 12. The second conductive type deep gate region 12 is in contact with the first conductive type pillar region 13 on both sides, and the first conductive type pillar region 13 is in contact with the second conductive type deep masking region 11. The lower surfaces of the second conductive type deep masking region 11, the second conductive type deep gate region 12, and the first conductive type pillar region 13 are flush.
[0023] The doping concentration range of the second conductivity type deep masking region 11, the second conductivity type deep gate region 12, and the first conductivity type pillar region 13 is 5e16cm. -3 ~ 5e17cm -3 Furthermore, the doping concentrations of the second conductivity type deep masking region 11, the second conductivity type deep gate region 12, and the first conductivity type pillar region 13 are greater than the doping concentration of the first conductivity type epitaxial layer 3, and the concentration difference is greater than or equal to 5e16cm. -3 .
[0024] In this embodiment, the second conductivity type deep masking region 11, the second conductivity type deep gate region 12, and the first conductivity type pillar region 13 form an alternating pillar region structure. The resulting charge balance effect can further increase the current density and improve the forward conduction characteristics of the device without sacrificing the device's withstand voltage.
[0025] The method for manufacturing a vertical channel junction field-effect transistor in this embodiment differs from that in Embodiment 1 in that: Step 2: Form a plurality of second conductivity type deep masking regions 11 in the first conductivity type epitaxial layer 3; the depth of the second conductivity type deep masking regions 11 ranges from 2.0µm to 8.0µm, and the doping concentration ranges from 5e16cm. -3 ~ 5e17cm -3 Then the ion implantation mask layer is removed; the upper surface of the second conductivity type deep masking region 11 is flush with the upper surface of the first conductivity type epitaxial layer 3.
[0026] Step 3: A second conductivity type deep gate region 12 is formed in the first conductivity type epitaxial layer 3, located between adjacent second conductivity type deep masking regions 11. A first conductivity type pillar region 13 is disposed between the second conductivity type deep gate region 12 and the second conductivity type deep masking region 11. The two sides of the second conductivity type deep gate region are in contact with the first conductivity type pillar region, and the first conductivity type pillar region is in contact with the second conductivity type deep masking region. The second conductivity type deep masking region, the second conductivity type deep gate region, and the first conductivity type pillar region constitute an alternating pillar region structure, and the doping concentration of the second conductivity type deep masking region, the second conductivity type deep gate region, and the first conductivity type pillar region is greater than the doping concentration of the first conductivity type epitaxial layer. A patterned ion implantation mask layer is formed on the surface of the first conductivity type epitaxial layer 3 prepared in step 2. Ion implantation is performed using the patterned ion implantation mask layer to form a second conductivity type deep gate region 12. A first conductivity type pillar region 13 is formed between the second conductivity type deep gate region 12 and the second conductivity type deep mask region 11 through the ion implantation process. The depth range of the second conductivity type deep gate region 12 is 2.0µm to 8.0µm, and the doping concentration ranges from 5e16cm. -3 ~ 5e17cm -3 The depth of the first conductivity type pillar region 13 ranges from 2.0µm to 8.0µm, and the doping concentration ranges from 5e16cm. -3 ~ 5e17cm -3 Subsequently, the ion implantation mask layer is removed; the doping concentrations of the second conductivity type deep mask region, the second conductivity type deep gate region, and the first conductivity type pillar region are greater than the doping concentration of the first conductivity type epitaxial layer, and the concentration difference is greater than or equal to 5e16cm. -3 .
[0027] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A vertical channel junction field-effect transistor, characterized in that, include: Drain; The first type of conductive substrate located above the drain; A first conductivity type epitaxial layer located on a first conductivity type substrate; Several deep masking regions of the second conductivity type are located within the epitaxial layer of the first conductivity type; source regions of the second conductivity type are located within the deep masking regions of the second conductivity type; The first conductivity type source region is located in the deep masking region of the second conductivity type, in the epitaxial layer of the first conductivity type, and on both sides of the source region of the second conductivity type. The second conductivity type deep gate region is located in the epitaxial layer of the first conductivity type and between the adjacent deep masking regions of the second conductivity type; the lower surface of the second conductivity type deep masking region is lower than the lower surface of the first conductivity type source region, and the depth difference D between the second conductivity type deep gate region and the first conductivity type source region is greater than or equal to 0.1 μm; The horizontal spacing between the second conductivity type deep gate region and the adjacent second conductivity type deep mask region is greater than or equal to 0.2 μm; A gate located above a deep gate region of the second conductivity type; a source located above a source region of the first conductivity type and a source region of the second conductivity type.
2. The vertical channel junction field-effect transistor according to claim 1, characterized in that: The lower surface of the deep masking region of the second conductivity type is lower than the lower surface of the deep gate region of the second conductivity type, and the depth difference between the deep masking region of the second conductivity type and the deep gate region of the second conductivity type is greater than or equal to 0.1 μm.
3. A vertical channel junction field-effect transistor according to claim 1, characterized in that: The depth difference D between the deep gate region of the second conductivity type and the source region of the first conductivity type ranges from 0.2µm to 1.0µm.
4. A vertical channel junction field-effect transistor according to claim 1, characterized in that: It also includes a first conductivity type pillar region located between the second conductivity type deep masking region and the second conductivity type deep gate region. The second conductivity type deep gate region is in contact with the first conductivity type pillar region on both sides, and the first conductivity type pillar region is in contact with the second conductivity type deep masking region. The second conductivity type deep masking region, the second conductivity type deep gate region, and the first conductivity type pillar region form an alternating pillar region structure, and the doping concentration of the second conductivity type deep masking region, the second conductivity type deep gate region, and the first conductivity type pillar region is greater than the doping concentration of the first conductivity type epitaxial layer.
5. A vertical channel junction field-effect transistor according to claim 4, characterized in that: The doping concentrations of the deep masking region of the second conductivity type, the deep gate region of the second conductivity type, and the pillar region of the first conductivity type are greater than the doping concentration of the epitaxial layer of the first conductivity type, and the concentration difference is greater than or equal to 5e16cm. -3 .
6. A vertical channel junction field-effect transistor according to claim 4, characterized in that: The lower surfaces of the second conductivity type deep masking region, the second conductivity type deep gate region, and the first conductivity type pillar region are flush.
7. A method for manufacturing a vertical channel junction field-effect transistor, used to prepare a vertical channel junction field-effect transistor as described in any one of claims 1-6, characterized in that, Includes the following steps: Step 1: Form an epitaxial layer of the first conductivity type on a substrate of the first conductivity type; Step 2: Form several deep masking regions of the second conductivity type in the epitaxial layer of the first conductivity type; Step 3: Form a second conductivity type deep gate region in the first conductivity type epitaxial layer, located between adjacent second conductivity type deep masking regions; Step 4: Form a first conductivity type source region in the first conductivity type epitaxial layer and the second conductivity type deep masking region, and form a second conductivity type source region in the first conductivity type source region and the second conductivity type deep masking region; the second conductivity type source region divides the first conductivity type source region into two non-connected parts; Step 5: Form a gate on the deep gate region of the second conductivity type, form a source on the source region of the first conductivity type and the source region of the second conductivity type, and form a drain on the bottom layer of the substrate of the first conductivity type.
8. A method for manufacturing a vertical channel junction field-effect transistor according to claim 7, characterized in that: The ion implantation methods in steps 2 and 3 are random implantation or tunnel implantation.
9. A method for manufacturing a vertical channel junction field-effect transistor according to claim 7, characterized in that: Step 3 further includes: setting a first conductivity type pillar region between the second conductivity type deep gate region and the second conductivity type deep masking region; the second conductivity type deep gate region is in contact with the first conductivity type pillar region on both sides, and the first conductivity type pillar region is in contact with the second conductivity type deep masking region; the second conductivity type deep masking region, the second conductivity type deep gate region, and the first conductivity type pillar region constitute an alternating pillar region structure, and the doping concentration of the second conductivity type deep masking region, the second conductivity type deep gate region, and the first conductivity type pillar region is greater than the doping concentration of the first conductivity type epitaxial layer.