Semiconductor device and method of forming the same

Abstract

The integrated circuit includes a complementary field-effect transistor (CFET). The CFET includes a first transistor comprising a first source / drain region pair and a plurality of stacked first channels extending in a first lateral direction between the first source / drain region pair. The CFET includes a second transistor located above the first transistor, and the second transistor includes a second source / drain region pair and a plurality of stacked second channels extending in the first lateral direction between the second source / drain region pairs. The CFET includes a gate spacer layer defining a gate trench adjacent to the second channels and gate metal located in the gate trench and between the second channels. The gate metal has a first length in the gate trench in the first lateral direction and a second length in the first lateral direction between the second channels. The first length is greater than the second length. Embodiments of this application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] There is a continuous demand for increasing computing power in electronic devices, including smartphones, tablets, desktop computers, laptops, and many other types of electronic devices. Integrated circuits provide the computing power for these electronic devices. One way to increase the computing power in integrated circuits is to increase the number of transistors and other integrated circuit components that can be included in a given area of ​​a semiconductor substrate.

[0003] Complementary field-effect transistors (CFETs) can be used to increase the transistor density in integrated circuits. CFETs can include vertically stacked N-type and P-type transistors. The gate electrodes of the N-type and P-type transistors can be electrically shorted together.

[0004] However, various difficulties exist associated with the formation of CFETs. For example, as scaling continues, there is a possibility of reduced carrier mobility in the channel. Furthermore, short-channel effects may also increase.

[0005] All topics discussed in the Background section are not necessarily prior art, and should not be considered prior art simply because they are discussed in the Background section. Following this line of thought, any awareness of problems in prior art discussed in the Background section or related to such topics should not be considered prior art unless explicitly stated otherwise. Instead, the discussion of any topic in the Background section should be considered as part of the inventor's method for solving a particular problem, which may itself be inventive. Summary of the Invention

[0006] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a plurality of stacked first channels of a first transistor of a complementary field-effect transistor, the first channels extending in a first lateral direction between first source / drain region pairs of the first transistor; forming a plurality of stacked second channels of a second transistor of the complementary field-effect transistor over the first channels, the second channels extending in a second lateral direction between second source / drain region pairs of the second transistor; forming a gate trench between gate spacer layer pairs adjacent to the second channels; and forming a gate metal in the gate trench and between the second channels. The gate metal has a first length in the first lateral direction in the gate trench and a second length in the first lateral direction between the second channels, wherein the first length is greater than the second length; a first dielectric layer is formed over the second source / drain regions; a silicide is formed on one of the source / drain regions in the second source / drain regions; and a source / drain contact is formed extending through the first dielectric layer to contact the silicide, wherein a portion of the source / drain contact is surrounded by the first dielectric layer, and wherein at least a portion of the source / drain contact is covered by a second dielectric layer.

[0007] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming an active region extending longitudinally in a first direction; forming an isolation structure extending longitudinally in the first direction adjacent to the active region; forming a plurality of stacked first channels of a first transistor of a complementary field-effect transistor in the active region; forming a first source / drain region pair of the first transistor, the first channel extending between the first source / drain regions; forming a plurality of stacked second channels of a second transistor of the complementary field-effect transistor over the first channel; forming a second source / drain region pair of the second transistor over the first source / drain region pair, the second channel extending between the second source / drain regions; forming an interface gate dielectric layer enclosing the second channel; forming a high-k gate dielectric layer on the interface gate dielectric layer; forming a gate metal enclosing the first channel and the second channel, wherein the first channel and the second channel have the same semiconductor material, wherein the first channel has a first crystal orientation, and the second channel has a second crystal orientation different from the first crystal orientation.

[0008] Further embodiments of this application provide a semiconductor device comprising: a substrate; an active region disposed above the substrate and extending longitudinally along a first lateral direction; an isolation structure disposed adjacent to the active region above the substrate; a complementary field-effect transistor located in the active region, comprising: a first transistor including: a first source / drain region pair; and a plurality of stacked first channels extending in the first lateral direction between the first source / drain region pairs, such that the sidewalls of the first channels are in contact with the first source / drain regions; a second transistor located above the first transistor, including: a second source / drain region pair; and a plurality of stacked second channels extending in the first lateral direction between the second source / drain region pairs; a pair of gate spacer layers defining a gate trench adjacent to the second channel; and a gate metal located in the gate trench and between the second channel, wherein the gate metal has a first length in the gate trench in the first lateral direction and a second length in the first lateral direction between the second channels, wherein the first length is greater than the second length. Attached Figure Description

[0009] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0010] Figures 1A to 1B and Figures 2A to 30B These are cross-sectional and top views of an integrated circuit according to some embodiments at an intermediate stage of the process used to form a CFET.

[0011] Figures 1C to 1E This is a diagram of a unit cell of monocrystalline silicon according to some embodiments.

[0012] Figure 31 This is a flowchart of a method for forming an integrated circuit according to some embodiments.

[0013] Figure 32 This is a flowchart of a method for forming an integrated circuit according to some embodiments. Detailed Implementation

[0014] In the following description, numerous thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials are given by way of example for various embodiments. Those skilled in the art will recognize that, given the embodiments of this disclosure, other dimensions and materials may be used in many cases without departing from the scope of these embodiments.

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the described subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] In the following description, certain specific details are set forth to provide a thorough understanding of the various embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In other instances, well-known structures related to electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of embodiments of this disclosure.

[0018] Unless the context otherwise requires, throughout the specification and the following claims, the word “(comprise)” and its variations, such as “(comprises)” and “(comprising)”, shall be interpreted in an open, inclusive sense, i.e., as “including, but not limited to”.

[0019] The use of ordinal numbers such as first, second, and third does not necessarily imply a ranking of order, but can simply distinguish multiple instances of steps or structures.

[0020] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular component, structure, or feature described in connection with an embodiment is included in at least some of those embodiments. Therefore, throughout this specification, the appearance of the phrases "in one embodiment," "in an embodiment," or "in some embodiments" in various places does not necessarily refer to the same embodiment. Furthermore, specific components, structures, or features may be combined in any suitable manner in one or more embodiments.

[0021] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural references, unless otherwise expressly stated. It should also be noted that the term “or” is generally used to mean “and / or”, unless otherwise expressly stated.

[0022] Embodiments of this disclosure provide integrated circuits including CFETs with improved electrical characteristics. A CFET includes NFET transistors and PFET transistors stacked together. Embodiments of this disclosure provide CFETs in which the inner gate length is shorter than the outer gate length, and in which the channel has a reduced vertical thickness. Embodiments of this disclosure also provide CFETs with different crystal orientations for the channels used in the PFET and NFET transistors.

[0023] The reduced internal gate length helps minimize undesirable short-channel effects. Different crystal orientations for the PFET and NFET channels help ensure strong carrier mobility in both NFET and PFET circuits. This further enables reduced vertical channel thickness, resulting in smaller stack heights. The result is integrated circuits with dense arrays of fully functional CFETs exhibiting good conduction and switching characteristics. This leads to better device implementation and higher wafer yields.

[0024] Figures 1A to 1B and Figures 2A to 17D These are cross-sectional and top views of an integrated circuit according to some embodiments at an intermediate stage of the process used to form a CFET.

[0025] A CFET transistor can correspond to a full-around-gate transistor. A full-around-gate transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern a full-around-gate structure. Furthermore, the full-around-gate CFET 101 can include multiple semiconductor nanostructures corresponding to the channel region of the CFET 101. The semiconductor nanostructures can include nanosheets, nanowires, or other types of nanostructures. A full-around-gate transistor can also be referred to as a nanostructure transistor.

[0026] Figure 1AIt is a cross-sectional view of the first wafer 100a including the first semiconductor substrate 102a. Figure 1B This is a cross-sectional view of the second wafer 100b, including the second semiconductor substrate 102b. As will be described in more detail below, wafers 100a and 100b will eventually be bonded together to form a composite wafer 101 in which a CFET is formed.

[0027] In some embodiments, semiconductor substrates 102a and 102b comprise the same semiconductor material. Substrates 102a and 102b may each comprise a single-crystal semiconductor layer on at least a surface portion. Substrates 102a and 102b may comprise single-crystal semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In the primary example shown herein, substrates 102a and 102b each comprise single-crystal silicon, but other materials may be used without departing from the scope of embodiments of this disclosure.

[0028] In some embodiments, substrate 102a will be used to grow a stack of semiconductor layers, which will be used for a PFET transistor of a CFET. The semiconductor layers will be grown from substrate 102a using an epitaxial growth process. Therefore, the semiconductor layers will carry the crystal structure of substrate 102a. In the example where the semiconductor layer grown from substrate 102a will be used to form the channel of the PFET transistor, it is advantageous to select the orientation of the crystal structure of substrate 102a to promote high mobility of holes (P-type charge carriers) moving through the channel in the X direction. As used herein, the orientation of the crystal structure corresponds to the orientation at the XY plane of the top surface of substrate 102a prior to the growth of the epitaxial layer.

[0029] In some embodiments, substrate 102b will be used to grow a stack of semiconductor layers for use as an NFET transistor in a CFET. The semiconductor layers will be grown from substrate 102b using an epitaxial growth process. Therefore, the semiconductor layers will carry the crystal structure of substrate 102b. In instances where the semiconductor layer grown from substrate 102b will be used to form the channel of an NFET transistor, it is advantageous to select the orientation of the crystal structure of substrate 102b to promote high mobility of electrons (P-type charge carriers) moving through the channel in the X direction. As used herein, the orientation of the crystal structure corresponds to the orientation of the XY plane of the top surface of substrate 102b prior to the growth of the epitaxial layer. In some embodiments, the orientation of the crystal structure of substrate 102b differs from the orientation of the crystal structure of substrate 102a.

[0030] Figures 1C to 1EThis is an illustration of a unit cell 104 of single-crystal silicon. Unit cell 104 comprises a plurality of silicon atoms 106. Unit cell 104 is a cube with a side length of length a. In some embodiments, a has a value of 5.431 Å. Figures 1C to 1E It also utilizes a coordinate system with three mutually orthogonal axes labeled j, k, and l. Figure 1C The 100 plane is shown. Figure 1D Plane 110 is shown. Figure 1E Plane 111 is shown.

[0031] According to some embodiments, substrates 102a and 102b each have a crystal orientation. The crystal orientation of the substrate corresponds to a plane (e.g., 100, 110, 111, etc.) constituting the top (XY) plane of the substrate. In one example, when the silicon channel has a 100 orientation, the NFET device has higher electron mobility in the X direction. In one example, when the silicon channel has a 110 orientation, the PFET device has higher hole mobility in the X direction. In some embodiments, substrate 102a will be used for a PFET device and has a 110 crystal orientation. In some embodiments, substrate 102b will be used for an NFET device and has a 100 crystal orientation. Other materials and orientations may be used without departing from the scope of embodiments of this disclosure.

[0032] Figure 2A This is a cross-sectional view of wafer 100a according to some embodiments. In some embodiments, semiconductor substrate 102a is single-crystal silicon with an orientation of 110. Figure 2A In some embodiments, a stack 107a of semiconductor layers has been formed over a substrate 102. The stack 107a can be formed by performing a series of epitaxial growth processes from the substrate 102a to form the layers of the stack 107a. The stack 107a includes a plurality of semiconductor layers 108a interleaved and a sacrificial semiconductor layer 110a. As will be described in more detail below, the semiconductor layers 108a are patterned to form the stacked channel of the first transistor of the CFET. As will be described in more detail below, the sacrificial semiconductor layer 110a is patterned and ultimately replaced with gate metal that surrounds the channel.

[0033] In some embodiments, semiconductor layer 108a comprises silicon. Because semiconductor layer 108a is epitaxially grown from substrate 102a, semiconductor layer 108a has the same crystal orientation (e.g., 110) as substrate 102a. In some embodiments, semiconductor layer 108a has a vertical thickness between 0.5 nm and 8 nm. Other materials, thicknesses, and orientations may be used without departing from the scope of embodiments of this disclosure.

[0034] In some embodiments, the sacrificial semiconductor layer 110a comprises a material selectively etchable relative to the semiconductor layer 108a. In some embodiments, the sacrificial semiconductor layer 110a comprises silicon germanium. Other materials may be used without departing from the scope of embodiments of this disclosure.

[0035] According to some embodiments, a bonding dielectric layer 112a has been formed on the stack 107a. The bonding dielectric layer 112a comprises one or more of SiO, SiN, SiCN, SiOCN, or other suitable dielectric materials. The bonding dielectric layer 112a can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes. The bonding dielectric layer 112a can have a thickness between 10 nm and 30 nm, but other thicknesses can be utilized without departing from the scope of embodiments of this disclosure.

[0036] Figure 2B This is a cross-sectional view of wafer 100b according to some embodiments. In some embodiments, semiconductor substrate 102b is single-crystal silicon with a 100 orientation. Figure 2B In some embodiments, a stack 107b of semiconductor layers has been formed over a substrate 102. The stack 107b can be formed by performing a series of epitaxial growth processes from the substrate 102b to form the layers of the stack 107b. The stack 107b includes a plurality of semiconductor layers 108b interleaved and a sacrificial semiconductor layer 110b. As will be described in more detail below, the semiconductor layers 108b are patterned to form the stacked channel of the second transistor of the CFET. As will be described in more detail below, the sacrificial semiconductor layer 110b is patterned and ultimately replaced with gate metal that surrounds the channel.

[0037] In some embodiments, semiconductor layer 108b comprises silicon. Because semiconductor layer 108b is epitaxially grown from substrate 102b, semiconductor layer 108b has the same crystal orientation (e.g., 100) as substrate 102b. In some embodiments, semiconductor layer 108b has a vertical thickness between 0.5 nm and 8 nm. Other materials, thicknesses, and orientations may be used without departing from the scope of embodiments of this disclosure.

[0038] In some embodiments, the sacrificial semiconductor layer 110b comprises a material selectively etchable relative to the semiconductor layer 108b. In some embodiments, the sacrificial semiconductor layer 110b comprises silicon germanium. Other materials may be used without departing from the scope of embodiments of this disclosure.

[0039] According to some embodiments, a bonding dielectric layer 112b has been formed on the stack 107b. The bonding dielectric layer 112b comprises one or more of SiO, SiN, SiON, SiCN, SiOCN, or other suitable dielectric materials. The bonding dielectric layer 112b can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes. The bonding dielectric layer 112b can have a thickness between 10 nm and 30 nm, but other thicknesses can be utilized without departing from the scope of embodiments of this disclosure.

[0040] exist Figure 3A In some embodiments, wafers 100a and 100b have been bonded together to form a composite wafer 101. Wafer 102b has been flipped so that the bonding dielectric layer 112b faces downwards. Wafers 100a and 100b are then stacked such that the bonding dielectric layer 112a contacts the bonding dielectric layer 112b. Subsequently, a thermal annealing process is performed to bond dielectric layers 112a and 112b into a single intermediate dielectric isolation layer 112. As will be described in more detail below, the intermediate dielectric isolation layer 112 serves as dielectric isolation between the PFET transistor and the NFET transistor of the CFET.

[0041] Figure 3B An alternative embodiment is shown, wherein in the composite wafer 101, wafer 100a is located on top of wafer 100b.

[0042] Figure 4A and Figure 4B This is a cross-sectional view of the composite wafer 101 according to some embodiments. Figure 4C This is a top view of a composite wafer 101 according to some embodiments. Figure 4A and Figure 4B The cross-sectional view is along Figure 4C Cut by cutting lines 4A and 4B.

[0043] exist Figure 4A In some embodiments, the semiconductor substrate 102b has been removed. The top sacrificial semiconductor layer 110b has also been removed. However, in some embodiments, the top sacrificial semiconductor layer 110b is not removed.

[0044] exist Figure 4A In some embodiments, a plurality of fins 116 have been formed from the stack 107. The fins 116 can be formed in conjunction with a photolithography process, wherein a mask is formed and patterned over the stack 107. An etching process is then performed to etch in a downward direction to form trenches 118 at locations exposed by the mask. The fins 116 are formed by forming the trenches 118. The trenches 118 extend into the substrate 102a. Each fin 116 is an active region extending longitudinally in the X direction.

[0045] exist Figure 4A In some embodiments, a dielectric isolation structure 120 has been formed in a groove within trench 118. Initially, the material of the dielectric isolation structure 120 can completely cover the fin 116. Subsequently, an etch-back process is performed to reduce the top surface of the dielectric isolation structure 120 to [a smaller area]. Figure 4A The level shown is indicated. The dielectric isolation structure 120 may comprise silicon oxide or another suitable dielectric material. In some embodiments, the dielectric isolation structure 120 corresponds to a shallow trench isolation region.

[0046] According to some embodiments, Figure 4B The cross-sectional view shows layers 108a / 108b, 110a / 110b, and 112 extending in the X direction. In other words, fin 116 extends in the X direction.

[0047] According to some embodiments, Figure 4C The top view shows fins 116 extending in the X direction, with the top semiconductor layer 108 exposed. Trench 118 extends in the X direction between fins 116, with dielectric isolation structure 120 exposed.

[0048] Figures 5A to 5C This is a cross-sectional view of wafer 101 according to some embodiments. Figure 5D This is a top view of wafer 101. According to some embodiments, Figures 5A to 5C The cross-sectional view is along Figure 5D It was cut from the cutting line 5A-5C.

[0049] exist Figures 5A to 5D In some embodiments, a plurality of sacrificial gate structures 122 have been formed. The sacrificial gate structures 122 extend in the Y direction across trench 118 and fin 116. The sacrificial gate structures 122 include a dielectric layer 124, a sacrificial gate layer 126, and a dielectric layer 128.

[0050] In some embodiments, the dielectric layer 124 comprises one or more of SiO, SiN, SiON, SiCN, SiOCN, or other suitable dielectric materials. The dielectric layer 124 is formed by CVD, ALD, PVD, or other suitable deposition processes.

[0051] The sacrificial gate layer 126 may include a material with high etch selectivity relative to the isolation structure 120. In an exemplary embodiment, the sacrificial gate layer 126 includes polysilicon. However, the sacrificial gate layer 126 may be a conductive, semi-conductive, or non-conductive material, and may be or include amorphous silicon, polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 126 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material.

[0052] According to some embodiments, the sacrificial gate structure 122 includes a dielectric layer 128 on the sacrificial gate layer 126. The dielectric layer 128 includes one or more of SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The dielectric layer 128 can be deposited by ALD, CVD, PVD, or other suitable deposition processes.

[0053] The sacrificial gate structure 122 is called a sacrificial gate structure because the gate electrode of the PFET and NFET transistors of the CFET will partially replace the sacrificial gate layer 126.

[0054] The sacrificial gate structure 122 may also include one or more additional dielectric layers above the sacrificial gate layer 126. Various configurations and materials may be used for the sacrificial gate structure 122 without departing from the scope of embodiments of this disclosure.

[0055] According to some embodiments, Figure 5B The cross-sectional view shows the sacrificial gate structure 122 covering the top and sidewalls of the fin 116. Figure 5C The cross-sectional view shows multiple sacrificial gate structures 122 extending in the Y direction across a trench 118 on the top surface of the dielectric isolation structure 120. Figure 5D The sacrificial gate structure 122 extending across trench 118 and semiconductor fin 116 is shown, along with the various exposed layers.

[0056] Figures 6A to 6C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 6A to 6C The cross-sectional view corresponds to cutting lines 5A-5C, but it is in the process of further processing.

[0057] exist Figures 6A to 6CIn this configuration, a gate spacer layer 130 has been formed on the sidewalls of the sacrificial gate layer 126. In one example, the gate spacer layer 130 comprises silicon nitride. Alternatively, the gate spacer layer 130 may comprise silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbonitride, fluorine-doped silicate glass (FSG), or another suitable dielectric material. The gate spacer layer 130 may comprise multiple dielectric layers. The gate spacer layer 130 may also be referred to as a sidewall spacer.

[0058] exist Figure 6A In this process, an etching process has been performed to form source / drain trenches 134 in fin 116. Specifically, the etching process removes portions of the sacrificial semiconductor layers 110a / 110b and semiconductor layers 108a / 108b that are not located directly below the gate spacer layer 130. The etching process may include anisotropic etching selectively etching in the downward (z-) direction. The source / drain trenches 134 extend into the substrate 102a.

[0059] The formation of the source / drain trench 134 results in the formation of multiple channel stacks 109a from the semiconductor layer 108a, a sacrificial semiconductor nanostructure 111a from the sacrificial semiconductor layer 110a, a channel stack 109b from the semiconductor layer 108b, a sacrificial semiconductor nanostructure 111b from the sacrificial semiconductor layer 110b, and an intermediate isolation structure 113 from the intermediate isolation layer 112.

[0060] Figures 7A to 7C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 7A to 7C The cross-sectional view corresponds to cutting lines 5A-5C, but it is in the process of further processing.

[0061] exist Figure 7A In this process, an isotropic etching process is performed to form a groove 140 in the sacrificial semiconductor nanostructures 111a / 111b. The isotropic etching process selectively etches the material of the sacrificial semiconductor nanostructures 111a / 111b relative to the channels 109a / 109b. The isotropic etching process is a timing process that recesses the sacrificial semiconductor nanostructures 111a / 111b without completely removing them.

[0062] like Figure 7AAs can be seen, the sacrificial gate layer 126 is wider in the X direction than the remainder of the sacrificial semiconductor nanostructures 111a / 111b. As will be explained in more detail below, the width of the sacrificial gate layer 126 in the X direction is related to the length of the outer gate, since the sacrificial gate layer 126 will eventually be replaced by the gate metal. The width of the sacrificial semiconductor nanostructures 111a / 111b is related to the length of the inner gate, since the sacrificial semiconductor nanostructures 111a / 111b will eventually be replaced by the gate metal. The recess step is chosen to form a groove 140 with a depth in the X direction, such that the sacrificial semiconductor nanostructures 111a / 111b have a width in the X direction smaller than the width of the sacrificial gate layer 126.

[0063] Figure 8 This is a cross-sectional view of wafer 101 according to some embodiments. Figure 8 The cross-sectional view corresponds to cutting line 5A, but it is in the process of further processing. Figure 8 In the sacrificial semiconductor nanostructures 111a / 111b, internal spacers 142 have been formed in the recesses 140. The internal spacers 142 can be formed by depositing a dielectric layer on the exposed sidewalls of the channels 109a / 109b, on the sidewalls of the gate spacer 130, and in the recesses 140 formed in the sacrificial semiconductor nanostructures 111a / 111b. Without departing from the scope of embodiments of this disclosure, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, FSG, low-k dielectric materials, or other dielectric materials. The dielectric layer can be formed by CVD, PVD, ALD, or via another process. The lateral thickness (in the x-direction) of the dielectric layer can be between 2 nm and 10 nm. Other thicknesses, materials, and deposition processes may be used for the dielectric layer without departing from the scope of embodiments of this disclosure.

[0064] An etching process is then performed to remove portions of the dielectric layer that are not perpendicular to the trenches 109a / 109b or the intermediate isolation structure 113. The etching process defines the internal spacers 142, such as... Figure 8 As shown in the figure. Other processes may be used to form the internal spacer 142 without departing from the scope of embodiments of this disclosure.

[0065] Figure 9 This is a cross-sectional view of wafer 101 according to some embodiments. Figure 9 The cross-sectional view corresponds to cutting line 5A, but it is in the process of further processing. Figure 9In the source / drain trench 134, a sacrificial source / drain structure 144 has been formed. The sacrificial source / drain structure 144 may include a dielectric material such as SiO, SiN, SiON, SiCN, SiOCN, FSG, or another suitable dielectric material. The sacrificial source / drain structure 144 may be deposited by CVD, ALD, PVD, or another suitable deposition process. The top surface of the sacrificial source / drain structure 144 is located in the middle of the intermediate isolation structure 113.

[0066] exist Figure 9 In this process, a dielectric layer 148 has been conformally deposited on the sacrificial source / drain structure, on the sidewalls of the channel 109b and the exposed internal spacer 142, and on the gate spacer layer 130. The dielectric layer 148 comprises one or more of SiO, SiN, SiON, SiCN, SiOCN, FSG, or another suitable dielectric material. The dielectric layer 148 is deposited by CVD, ALD, PVD, or another suitable deposition process.

[0067] Figure 10 This is a cross-sectional view of wafer 101 according to some embodiments. Figure 10 The cross-sectional view corresponds to cutting line 5A, but it is in the process of further processing. Figure 10 An anisotropic etching process has been implemented to remove a portion of the dielectric layer 148 from the top surface of the sacrificial source / drain structure 144. The anisotropic etching process does not remove the thicker vertical portions of the dielectric layer 148 from the sidewalls of the gate spacer 130, the channel 109b, and the internal spacer 142.

[0068] exist Figure 10 In this process, an etching process has been performed to remove the sacrificial source / drain structure 144. The result is that the end portion of the channel 109a and the substrate 102a are exposed. The etching process can be the same as the etching process used to remove portions of the dielectric layer 148 or a different etching process.

[0069] Figure 11 This is a cross-sectional view of wafer 101 according to some embodiments. Figure 11 The cross-sectional view corresponds to cutting line 5A, but it is in the process of further processing. Figure 11 In the middle, the source / drain region 150 has been formed in the lower part of the source / drain trench 134.

[0070] exist Figure 11In some embodiments, a source / drain region 150a has been formed. The source / drain region 150a can be formed from a channel 109a and a substrate 102a during an epitaxial growth process. The source / drain region 150a comprises a semiconductor material. The semiconductor material may include the same semiconductor material as the channel 109a. Alternatively, the semiconductor material of the source / drain region 150a may be different from the semiconductor material of the channel 109a. The source / drain region 150a may be in-situ doped with dopant atoms during the epitaxial growth process. In an example where the lower transistor is a P-type transistor, the source / drain region 150a may be in-situ doped with P-type dopant atoms. The P-type dopant atoms may include boron or other P-type dopant atoms.

[0071] Figure 12 This is a cross-sectional view of wafer 101 according to some embodiments. Figure 12 The cross-sectional view corresponds to cutting line 5A, but it is in the process of further processing. Figure 12 In the middle, dielectric layer 148 has been removed. This exposes the sidewalls of channel 109b.

[0072] exist Figure 12 In this process, a contact etch stop layer (CESL) 154 has been deposited. CESL 154 is initially conformally deposited on all exposed surfaces. CESL 154 is deposited using CVD, ALD, PVD, or another suitable deposition process. CESL 154 comprises one or more of SiN, SiON, SiOCN, SiCN, or other suitable dielectric materials.

[0073] exist Figure 12 In this process, an interlayer dielectric layer 156 has been deposited. The interlayer dielectric layer 156 is deposited on CESL 154. The interlayer dielectric layer 156 is deposited by CVD, ALD, PVD or another suitable deposition process. The interlayer dielectric layer 156 comprises one or more of SiO, SiN, SiON, SiOCN, SiCN, FSG or other suitable dielectric materials.

[0074] exist Figure 12 In this process, a back-etching process has been implemented. The back-etching process recesses the top surfaces of CESL 158 and the interlayer dielectric layer 156 to a level below the lowest channel 109b. Therefore, the end portion of channel 109b remains exposed.

[0075] Figures 13A to 13C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 13A to 13C The cross-sectional view corresponds to cutting lines 5A-5C, but it is in the process of further processing.

[0076] exist Figure 13AIn some embodiments, a source / drain region 150b has been formed. The source / drain region 150b can be formed from the channel 109b during an epitaxial growth process. The source / drain region 150b comprises a semiconductor material. The semiconductor material can include the same semiconductor material as the channel 109. Alternatively, the semiconductor material of the source / drain region 150b can be different from the semiconductor material of the channel 109b. The source / drain region 150b can be in-situ doped with dopant atoms during the epitaxial growth process. In an example where the upper transistor is an N-type transistor, the source / drain region 150b can be in-situ doped with N-type dopant atoms. The dopant atoms can include phosphorus, arsenic, or other N-type dopant atoms. As previously described, in some embodiments, optionally, the lower transistor is an N-type transistor and the upper transistor is a P-type transistor.

[0077] Figure 13C It is shown that there is a CESL 154 and an interlayer dielectric layer 156 between the sacrificial gate structure 122 on the dielectric isolation structure 120.

[0078] Figures 14A to 14C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 14A to 14C The cross-sectional view corresponds to cutting lines 5A-5C, but it is in the process of further processing.

[0079] exist Figures 14A to 14C In this process, an interlayer dielectric layer 156 has been deposited. The interlayer dielectric layer 156 is deposited on CESL 154. The interlayer dielectric layer 156 is deposited by CVD, ALD, PVD or another suitable deposition process. The interlayer dielectric layer 156 comprises one or more of SiO, SiN, SiON, SiOCN, SiCN, FSG or other suitable dielectric materials.

[0080] exist Figures 14A to 14C In this process, CESL 158 has been deposited. CESL 158 is initially conformally deposited on all exposed surfaces. CESL 158 is deposited using CVD, ALD, PVD, or another suitable deposition process. CESL 158 comprises one or more of SiN, SiON, SiOCN, SiCN, or other suitable dielectric materials.

[0081] exist Figures 14A to 14C In this process, an interlayer dielectric layer 160 has been deposited. The interlayer dielectric layer 160 is deposited on a CESL 158. The interlayer dielectric layer 160 is deposited by CVD, ALD, PVD, or another suitable deposition process. The interlayer dielectric layer 160 comprises one or more of SiO, SiN, SiON, SiOCN, SiCN, FSG, or other suitable dielectric materials.

[0082] exist Figures 14A to 14CIn this process, CMP technology has been implemented. The CMP process planarizes the top surface of CESL 158, interlayer dielectric layer 160, gate spacer layer 130, and sacrificial gate structure 126. Dielectric layer 128 is removed by CMP process.

[0083] Figure 14A The CESL 158 is shown on the top surface of the source / drain region 150b. Figure 14C The diagram shows CESL 158 located on the top surface of CESL 154 and interlayer dielectric layer 156.

[0084] Figures 15A to 15C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 15A to 15C The cross-sectional view corresponds to cutting lines 5A-5C, but it is in the process of further processing.

[0085] exist Figures 15A to 15C In some embodiments, the sacrificial gate layer 126 has been removed. The sacrificial gate layer 126 can be removed by an etching process that selectively etches the material of the sacrificial gate layer 126 relative to adjacent materials, such as the gate spacer layer 130. The removal of the sacrificial gate layer 126 creates a gate trench 164 between the gate spacer layers 130.

[0086] refer to Figure 15A According to some embodiments, an etching process has been performed to remove the sacrificial semiconductor nanostructures 111a / 111b. The sacrificial semiconductor nanostructures 111a / 111b can be removed by a selective etching process using an etchant selective to the material of the channels 109a / 109b, thereby removing the sacrificial semiconductor nanostructures 111a / 111b without substantially etching the channels 109a / 109b. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, combinations thereof, etc. In some embodiments, the etching process rounds the sides of the channels 109a / 109b. The etching process also creates gaps between the channels 109a / 109b.

[0087] Figures 16A to 16C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 16A to 16C The cross-sectional view corresponds to cutting lines 5A-5C, but it is in the process of further processing.

[0088] exist Figures 16A to 16CIn some embodiments, a gate dielectric has been formed. The gate dielectric includes an interface gate dielectric layer 168 and a high-k gate dielectric layer 170. According to some embodiments, the interface gate dielectric layer 168 has been deposited on the exposed portions of the channels 109a / 109b. The interface gate dielectric layer 168 is formed directly on the exposed portions of the channels 109a / 109b. The high-k gate dielectric layer 170 is formed on the interface gate dielectric layer 168 and on other exposed surfaces, such as the exposed sidewalls of the gate spacer layer 130 and the internal spacer 142.

[0089] Interface gate dielectric layer 168 surrounds channels 109a / 109b. Interface gate dielectric layer 168 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. Interface gate dielectric layer 168 may include a low-k dielectric relative to a high-k dielectric such as hafnium oxide or other high-k dielectric materials that can be used in transistor gate dielectrics. High-k dielectrics may include dielectric materials having a dielectric constant higher than that of silicon oxide. Interface gate dielectric layer 168 may be formed by thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD). Interface gate dielectric layer 168 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for interface gate dielectric layer 168 without departing from the scope of embodiments of this disclosure.

[0090] A high-k gate dielectric layer 170 is deposited in a conformal deposition process. The conformal deposition process deposits the high-k gate dielectric layer 170 on the interface gate dielectric layer 168, the substrate 102a, the intermediate isolation structure 113, the dielectric isolation structure 120, and the gate spacer layer 130. The high-k gate dielectric layer 170 surrounds the channels 109a / 109b. The high-k gate dielectric layer 170 has a thickness between 1 nm and 3 nm. The high-k dielectric layer comprises one or more layers of dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k gate dielectric layer 170 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer 170 without departing from the scope of embodiments of this disclosure.

[0091] exist Figures 16A to 16CIn some embodiments, gate metal 172 has been deposited. Gate metal 172 is deposited to replace the sacrificial gate layer 126 and the sacrificial semiconductor nanostructures 111a / 111b. Therefore, gate metal 172 is positioned in a gate trench above each channel stack 109a / 109b. Gate metal 172 also encloses the channels 109a / 109b of each stack.

[0092] exist Figures 16A to 16C The diagram illustrates a single gate metal 172 as the gate electrode of transistor 101. However, in practice, gate metal 172 may comprise various gate metals. For example, gate metal 172 may comprise one or more pad layers, one or more function layers, and gate fill material filling the remaining space between gate spacer layers 130. Gate metal 172 may comprise one or more of Ti, TiN, Ta, TaN, Al, Cu, Co, Ru, W, Au, or other suitable conductive materials. Gate metal 172 may be deposited by PVD, ALD, or CVD. Gate metal 172 may also be referred to as the gate electrode.

[0093] As shown below Figure 17D To elaborate further, the gate metal has an inner gate length corresponding to the length of the gate metal 172 in the X-direction within the gap 166 between and around the channels 109a / 109b. The gate metal also has an outer gate length corresponding to the length of the gate metal 172 in the gate trench 164 above the channels 109a / 109b and corresponding to the side of the channel 109b in the Y-direction. Figure 17D As can be seen, the internal gate length is shorter than the lengths of other gates.

[0094] exist Figures 16A to 16C In this process, the processing of CFET 103 is nearing completion. CFET 103 includes a lower transistor 174a and an upper transistor 174b. In some embodiments, the upper transistor 174b is an NFET transistor, and the lower transistor 174a is a PFET transistor. Optionally, the lower transistor 174a is an NFET transistor, and the upper transistor 174b is a PFET transistor.

[0095] Transistor 174a includes a channel 109a extending in the X direction between source / drain regions 150a. A portion of gate metal 172 surrounding the channel 109a corresponds to the gate electrode of transistor 174a. When transistor 174a is turned on and current flows, the direction of the current is in the X direction between the channels 150a. In an example where transistor 174a is a PFET transistor and channel 109a is silicon, the crystal orientation of channel 109a is 110. This provides improved mobility for holes moving in the X direction. This further allows the vertical thickness of channel 109a to be relatively small without performance loss. In some embodiments, the vertical thickness of channel 109a is between 0.5 nm and 8 nm, but other thicknesses may be utilized. Other materials, thicknesses, and crystal orientations may be utilized without departing from the scope of embodiments of this disclosure.

[0096] Transistor 174b includes a channel 109b extending in the X direction between source / drain regions 150b. A portion of gate metal 172 surrounding the channel 109b corresponds to the gate electrode of transistor 174b. When transistor 174b is turned on and current flows, the direction of the current is in the X direction between the channels 150b. In an example where transistor 174b is an NFET transistor and channel 109b is silicon, the crystal orientation of channel 109b is 100. This provides improved mobility for electrons moving in the X direction. This further allows the vertical thickness of channel 109b to be relatively small without performance loss. In some embodiments, the vertical thickness of channel 109b is between 0.5 nm and 8 nm, but other thicknesses may be utilized. Other materials, thicknesses, and crystal orientations may be utilized without departing from the scope of embodiments of this disclosure.

[0097] Figures 17A to 17D This is a cross-sectional view of wafer 101 according to some embodiments. Figures 17A to 17C The cross-sectional view corresponds to cutting lines 5A-5C, but it is in the process of further processing. Figure 17D The cross-sectional view is along Figure 17A The cutting line was taken from 17D.

[0098] exist Figures 17A to 17D In this process, an interlayer dielectric layer 179 has been formed over the gate metal 172, the gate spacer 130, and other exposed structures on the top or front side of the wafer 101. The interlayer dielectric layer 179 comprises one or more of SiO, SiN, SiON, SiOCN, SiCN, FSG, or other suitable dielectric materials. The interlayer dielectric layer 179 can be formed by CVD, PVD, or other suitable deposition processes.

[0099] exist Figures 17A to 17DIn this process, photolithography and corresponding etching processes have been performed to etch portions of dielectric layers 179, 160, and CESL158 to expose the source / drain region 150b of transistor 174b of CFET 103. A silicide 180b has been formed on the exposed top surface of the source / drain region 150b. The silicide 180b may include titanium silicide, nickel silicide, or other types of silicides. After forming the silicide 180b, source / drain contacts 182b are formed in contact with the silicide 180b. The source / drain contacts 182b may include one or more of W, Ta, Ti, Ru, Co, TiN, TaN, WN, or other suitable conductive materials. A CMP process has been performed to remove excess material from the source / drain contacts 182b. The source / drain contacts 182b enable voltage to be applied to the source / drain region 150b.

[0100] Although Figures 17A to 17D Not shown, but after forming the source / drain contacts 182b, a dielectric layer stack is formed above the CFET 103. Multiple metal lines and conductive vias are formed in the dielectric layer stack to enable signals to be supplied to and from the CFET 103.

[0101] exist Figures 17A to 17D After forming the interconnect structure on CFET 103, wafer 101 is flipped to allow for back-side processing. In the back-side processing, semiconductor substrate 102a is removed. This can be achieved by performing an etching process that selectively etches the material of semiconductor substrate 102 relative to dielectric isolation structure 120. A dielectric layer 178 is then formed in place of semiconductor substrate 102a. Dielectric layer 178 comprises one or more of SiO, SiN, SiON, SiOCN, SiCN, FSG, or other suitable dielectric materials. Interlayer dielectric layer 178 can be formed by CVD, PVD, or other suitable deposition processes.

[0102] exist Figures 17A to 17DIn this process, photolithography and corresponding etching processes have been performed to etch portions of the dielectric layer 178 to expose the source / drain region 150a of the transistor 174a of the CFET 103 from the back side. A silicide 180a has been formed on the exposed surface of the source / drain region 150a. The silicide 180a may include titanium silicide, nickel silicide, or other types of silicides. After forming the silicide 180a, source / drain contacts 182a are formed in contact with the silicide 180a. The source / drain contacts 182a may include one or more of W, Ta, Ti, Ru, Co, TiN, TaN, WN, or other suitable conductive materials. A CMP process has been performed to remove excess material from the source / drain contacts 182a. The source / drain contacts 182a allow voltage to be applied to the source / drain region 150a.

[0103] Although Figures 17A to 17D Not shown, but after forming the source / drain contacts 182a, a dielectric layer stack is formed on the back side of the CFET 103. Multiple metal lines and conductive vias are formed in the dielectric layer stack to enable signals to be provided to and from the CFET 103.

[0104] Figure 17D The cross-sectional view shows that the gate metal 172 has an external gate length of dimension D1. The external gate length corresponds to the width of the gate metal 172 in the X direction in the location previously occupied by the sacrificial gate layer 126. Therefore, the gate metal 172 has dimension D1 in the gate trench 164 above the channel 109 and is laterally spaced from the channel 109 in the Y direction.

[0105] Figure 17D The cross-sectional view shows that the gate metal 172 has an internal gate length of dimension D2. The internal gate length corresponds to the width of the gate metal 172 in the X direction, in the position previously occupied by the sacrificial semiconductor nanostructures 111a / 111b. Figure 17D As can be seen, D2 is smaller than D1. In some embodiments, D1 is between 8 nm and 20 nm. In some embodiments, D2 is between 5 nm and 18 nm. In some embodiments, the difference between D1 and D2 is between 1 nm and 10 nm. Other dimensions may be used without departing from the scope of embodiments of this disclosure.

[0106] Figures 1A to 17D A single CFET 103 is shown according to some embodiments. In practice, multiple CFETs 103 are formed in each fin 116. Therefore, wafer 101 includes multiple CFETs. Wafer 101 will eventually be diced into multiple integrated circuits. Each integrated circuit includes multiple CFETs 103.

[0107] In some embodiments, a shorter internal gate length can increase drive current and reduce channel capacitance (caused by the metal gate and channel). This results in improved switching speed and overall device performance. By reducing only the internal gate length while keeping the external gate length constant, the process window can be improved, thereby minimizing challenges associated with gate replacement processes, such as Vt adjustment via work function material and the use of multiple metal gates. That is, because the external gate is larger than the internal gate, the gaps between channels (where the internal gate will form) can be filled well before the gate fill material merges at the upper portion (where the external gate will form), thus avoiding the formation of gaps or voids in the internal gate.

[0108] In some embodiments, the top channel 109b has an asymmetrical gate length because its top side contacts the outer gate (longer gate length D2), while its bottom side contacts the inner gate (shorter gate length D1).

[0109] Furthermore, by providing different wafer lattice orientations or materials for NFETs and PFETs, mobility can be maintained or the decrease in mobility caused by thin channel height can be reduced.

[0110] Figures 1A to 17D A single CFET 103 is shown according to some embodiments. In practice, multiple CFETs 103 are formed in each fin 116. Therefore, wafer 101 includes multiple CFETs. Wafer 101 will eventually be diced into multiple integrated circuits. Each integrated circuit includes multiple CFETs 103.

[0111] Figure 18 This is a cross-sectional view of a process for forming a CFET 103 in wafer 101 according to some embodiments. Figure 18 The processing stage shown has resulted in the formation of composite wafer 101, essentially as described above. Figures 1A to 3B As described. Wafers 100a and 100b have been placed together and a thermal annealing process has been performed to fuse wafers 100a and 100b into composite wafer 101.

[0112] exist Figure 18In this process, the semiconductor substrate 102B has been removed. The semiconductor substrate 102B can be removed via an etching process or a CMP process. A hard mask layer 184 has been formed on the top sacrificial semiconductor layer 110b. The hard mask layer 184 comprises one or more of SiO2, SiN, SiON, SiCN, SiOCN, SiOC, Al2O3, HfO2, ZrO2, SiC, or other suitable dielectric materials. The hard mask layer 184 has a thickness between 2 nm and 30 nm, but other thicknesses may be used without departing from the scope of embodiments of this disclosure. The hard mask layer 184 can be formed by CVD, ALD, PVD, or other suitable deposition processes.

[0113] Hard mask layer 184 corresponds to the gate protection hard mask layer, as will be described in more detail below. In some embodiments, the gate protection hard mask loss is minimal or nonexistent in the final structure. In some embodiments, the gate protection hard mask can be completely removed by CMP near the end of the process.

[0114] Figures 18 to 26B This is a cross-sectional view of wafer 101 at an intermediate stage of the process for forming CFET 103, according to some embodiments. Figure 18 The processing stage shown has resulted in the formation of composite wafer 101, essentially as described above. Figures 1A to 3B As described. Wafers 100a and 100b have been placed together and a thermal annealing process has been performed to fuse wafers 100a and 100b into composite wafer 101.

[0115] exist Figure 19 In some embodiments, a plurality of fins 116 have been formed from the stack 107. The fins 116 are formed as described above. Figure 4A and Figure 4B As described, in addition to each fin 116 including a hard mask layer 184 and a sacrificial semiconductor layer 110b present on the top semiconductor layer 110a, a dielectric isolation structure 120 has been formed, as previously described.

[0116] Figures 20A to 20C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 20A to 20C In some embodiments, a plurality of sacrificial gate structures 122 have been formed. The formation of the sacrificial gate structures 122 is essentially as described above. Figures 5A to 5D As described, except that the sacrificial gate structure 126 is formed on the hard mask layer 184.

[0117] Figures 21A to 21C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 21A to 21C In the middle, source / drain trenches 134 have been formed, as shown in the following... Figures 6A to 6CAs described. The formation of the source / drain trench 134 results in the formation of channels 109a / 109b, sacrificial semiconductor nanostructures 111a / 111b, and intermediate isolation structure 113, as described in... Figures 6A to 6C As described. The formation of the source / drain trench 134 also enables the formation of the hard mask nanostructure 185 from the hard mask layer 184.

[0118] Figures 22A to 22C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 22A to 22C In the middle, internal spacers 142, source / drain regions 150a / 150b, CESL 154, and dielectric layer 156 have been formed, basically as described above. Figures 7A to 13C The description includes the presence of a hard mask nanostructure 185.

[0119] Figures 23A to 23C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 23A to 23C In the process, CESL 158, interlayer dielectric layer 160, gate trench 164, and gap 166 have been formed, essentially as described above. Figures 14A to 15C The description includes the presence of a hard mask nanostructure 185.

[0120] Figures 24A to 24D This is a cross-sectional view of wafer 101 according to some embodiments. Figures 24A to 24D In the process, the sacrificial semiconductor nanostructures 111a / 111b have been removed, the interface gate dielectric layer 168 has been formed, the high-k gate dielectric layer 170 has been formed, and the gate metal 172 has been formed, essentially as described above. Figures 16A to 16C As described. A CMP process has been implemented to make the top surface of the gate metal 172 coplanar with the top surface of the hard mask nanostructure 185.

[0121] Figure 24D The cross-sectional view shows the short gate length D2 and the longer gate length D1, as previously discussed. Figure 17D As described.

[0122] In some embodiments, the hard mask nanostructure 185 has substantially the same dimensions as the channels 109a / 109b in the X and Y directions.

[0123] exist Figures 24A to 24D In this configuration, the gate length above the top channel 109b is the same as the gate length below the top channel 109b. In other words, the gate metal 172 has the same gate length D2 above and below the top channel 109b.

[0124] Figures 25A to 25C This is a cross-sectional view of wafer 101 according to some embodiments. Figures 25A to 25CIn the middle, dielectric layers 178 and 179, silicide 180a / 180b, and source / drain contacts 182a / 182b have been formed, basically as described above. Figures 17A to 17C As described.

[0125] Figure 26A and Figure 26B This is a cross-sectional view of wafer 101 according to some embodiments. According to some embodiments, Figure 26A and Figure 26B The wafer 101 is basically similar to Figures 24A to 24C The wafer 101, except that it has undergone CMP process to completely remove the hard mask nanostructure 185. The top surface of the gate metal 172 is coplanar with the top surface of the highest internal spacer 142.

[0126] Figures 27A to 29D This is a cross-sectional view of wafer 101 at an intermediate stage of the process for forming CFET 103, according to some embodiments.

[0127] Figures 27A to 27C It is wafer 101 corresponding to Figures 22A to 22C The cross-sectional view of the processing stage shown indicates that dielectric layers 158 and 160 have been formed. Figures 27A to 27C The processing stage shown has resulted in the formation of composite wafer 101, essentially as described above. Figures 1A to 3B As described. Wafers 100a and 100b have been placed together and a thermal annealing process has been performed to fuse wafers 100a and 100b into composite wafer 101.

[0128] exist Figures 28A to 28C In some embodiments, an etching process has been performed. According to some embodiments, the etching process removes the central portion of the hard mask nanostructure 185 that is not covered by the gate spacer layer 130. The etching process is a material anisotropic etching process that etches in a downward direction and selectively etches the hard mask nanostructure 185 relative to other exposed materials. After the etching process, a hard mask residue 187 remains on top of the highest inner spacer 142. A portion of the top surface of the highest inner spacer 142 is also exposed.

[0129] exist Figures 29A to 29D In the process, the sacrificial semiconductor nanostructures 111a / 111b have been removed, the interface gate dielectric layer 168 has been formed, the high-k gate dielectric layer 170 has been formed, and the gate metal 172 has been formed, essentially as described above. Figures 16A to 16C As described. Figure 29AThe T-shape of the gate metal 172 above the highest channel 109b is shown. Specifically, the upper portion of the gate metal 172 includes a first portion having a gate length dimension D2 above the highest channel 109b and a second portion having a gate length dimension D1 above the first portion. A hard mask residue 187 exists on the highest internal spacer 142. A CMP process has been performed to make the top surface of the gate metal 172 coplanar with the top surface of the hard mask residue 187.

[0130] Figure 30A and Figure 30B This is a cross-sectional view of wafer 101 according to some embodiments. Wafer 101 includes components substantially similar to those described above. Figure 26A and Figure 26B The CFET 103 shown is a CFET 103 except that the top portion of the high-K gate dielectric layer 170 adjacent to the highest internal spacer 142 was not removed by the CMP process.

[0131] Figure 31 This is a flowchart of a method 3100 for forming an integrated circuit according to some embodiments. Method 3100 can utilize... Figures 1A to 30B The system, process, components, and principles are described. In 3102, method 3100 includes a plurality of stacked first channels forming a first transistor of a CFET, the first channels extending in a first lateral direction between first source / drain region pairs of the first transistor. An example of a CFET is... Figure 17A The CFET 103. An example of the first transistor is... Figure 17A The transistor 174a. An example of a first-channel transistor is... Figure 17A The channel is 109a. An example of the first source / drain region is... Figure 17A The source / drain region 150a. In 3104, method 3100 includes a plurality of stacked channels forming a second transistor of a CFET over a first channel, the second channels extending in a second lateral direction between the second source / drain region pairs of the second transistor. An example of the second transistor is... Figure 17A The transistor 174b. An example of a second-channel transistor is... Figure 17A Channel 109b. An example of the second source / drain region is... Figure 17A The second source / drain region 150b. In 3106, method 3100 includes forming a gate trench between gate spacer layer pairs adjacent to the second channel. An example of a gate trench is... Figure 15A Gate trench 164. An example of a gate spacer layer is... Figure 15AThe gate spacer layer 130. In 3108, method 3100 includes forming gate metal in a gate trench and between second channels, wherein the gate metal has a first length in a first lateral direction in the gate trench and a second length in the first lateral direction between the second channels, wherein the first length is greater than the second length. An example of gate metal is... Figure 17A Gate metal 172. In 3110, method 3100 includes forming a first dielectric layer over the second source / drain region. An example of the first dielectric layer is dielectric layer 179. In 3112, method 3100 includes forming a silicide on one of the second source / drain regions. An example of a silicide is... Figure 17A The silicide 180b. In 3114, method 3100 includes forming source / drain contacts extending through a first dielectric layer to contact the silicide, wherein the source / drain contacts are surrounded by the first dielectric layer, and wherein the source / drain contacts are spaced apart from the first dielectric layer by a second dielectric layer having a higher dielectric constant than the first dielectric layer. An example of the second dielectric layer is... Figure 17A The dielectric layer is 158. An example of a source / drain contact is... Figure 17A Source / drain contact 182b.

[0132] Figure 32 This is a flowchart of a method 3200 for forming an integrated circuit according to some embodiments. Method 3200 can utilize... Figures 1A to 30B The system, process, components, and principles are described. In 3202, method 3200 includes an active region formed extending longitudinally in a first direction. An example of an active region is... Figure 4C The active region 116. In 3204, method 3200 includes forming an isolation structure that extends longitudinally in a first direction adjacent to the active region. An example of the isolation structure is... Figure 4C The isolation structure 120. In 3206, method 3200 includes a plurality of stacked first channels forming a first transistor of a CFET in the active region. An example of the first channel is... Figure 17A The channel is 109a. An example of a CFET is... Figure 17A The CFET 103. An example of the first transistor is... Figure 17A Transistor 174a. In 3208, method 3200 includes forming a first source / drain region pair of the first transistor, with a first channel extending between the first source / drain regions. An exemplary first source / drain region is... Figure 17A The source / drain region 150a. In 3210, method 3200 includes a plurality of stacked second channels forming a second transistor of a CFET over the first channel. An example of the second transistor is... Figure 17AThe transistor 174b. An example of a second-channel transistor is... Figure 17A The second channel 109b. In 3212, method 3200 includes forming a second source / drain region pair of the second transistor over the first source / drain region pair, the second channel extending between the second source / drain regions. An example of the second source / drain region is... Figure 17A The source / drain region 150b. In 3214, method 3200 includes forming an interface gate dielectric layer enclosing the second channel. An example of an interface gate dielectric layer is... Figure 17A The interface gate dielectric layer 168. In 3216, method 3200 includes forming a high-k gate dielectric layer on the interface gate dielectric layer. An example of a high-k gate dielectric layer is... Figure 17A A high-k gate dielectric layer 170. In 3218, method 3200 includes forming a gate metal enclosing a first channel and a second channel, wherein the first channel and the second channel have the same semiconductor material, wherein the first channel has a first crystal orientation, and the second channel has a second crystal orientation different from the first crystal orientation. An example of a gate metal is... Figure 17A Gate metal 172.

[0133] Embodiments of this disclosure provide integrated circuits including CFETs with improved electrical characteristics. A CFET includes NFET transistors and PFET transistors stacked together. Embodiments of this disclosure provide CFETs in which the inner gate length is shorter than the outer gate length, and in which the channel has a reduced vertical thickness. Embodiments of this disclosure also provide CFETs with different crystal orientations for the channels used in the PFET and NFET transistors.

[0134] The reduced internal gate length helps minimize undesirable short-channel effects. Different crystal orientations for the PFET and NFET channels help ensure strong carrier mobility in both NFET and PFET circuits. This further enables reduced vertical channel thickness, resulting in smaller stack heights. The result is integrated circuits with dense arrays of fully functional CFETs exhibiting good conduction and switching characteristics. This leads to better device implementation and higher wafer yields.

[0135] In some embodiments, the method includes forming a plurality of stacked first channels of a first transistor of a CFET. The first channels extend in a first lateral direction between first source / drain region pairs of the first transistor. The method includes forming a plurality of stacked channels of a second transistor of a CFET over the first channels. The second channels extend in a second lateral direction between second source / drain region pairs of the second transistor. The method includes forming a gate trench between pairs of gate spacer layers adjacent to the second channels; and forming gate metal in the gate trench and between the second channels. The gate metal has a first length in the gate trench in the first lateral direction and a second length in the second channels in the first lateral direction, wherein the first length is greater than the second length. The method includes forming a first dielectric layer over the second source / drain regions; forming a silicide on one of the second source / drain regions; and forming source / drain contacts extending through the first dielectric layer to contact the silicide. A portion of the source / drain contact is surrounded by the first dielectric layer. A portion of the source / drain contact is covered by a second dielectric layer.

[0136] In some embodiments, the method includes: forming an active region extending longitudinally in a first direction; forming an isolation structure extending longitudinally in the first direction adjacent to the active region; and forming a plurality of stacked first channels of a first transistor of a CFET in the active region. The method includes forming a first source / drain region pair of the first transistor. The first channel extends between the first source / drain regions. The method includes: forming a plurality of stacked second channels of a second transistor of a CFET over the first channel; and forming a second source / drain region pair of the second transistor over the first source / drain region pair. The second channel extends between the second source / drain regions. The method includes: forming an interface gate dielectric layer surrounding the second channel; forming a high-k gate dielectric layer on the interface gate dielectric layer; and forming a gate metal surrounding the first channel and the second channel. The first channel and the second channel have the same semiconductor material. The first channel has a first crystal orientation, and the second channel has a second crystal orientation different from the first crystal orientation.

[0137] In some embodiments, the device includes: a substrate; an active region disposed above the substrate and extending longitudinally along a first lateral direction; and an isolation structure disposed adjacent to the active region above the substrate. The device includes: a CFET located in the active region, including: a first transistor including a first source / drain region pair; and a plurality of stacked first channels extending in the first lateral direction between the first source / drain region pairs, such that the sidewalls of the first channels are in contact with the first source / drain regions. The CFET includes: a second transistor located above the first transistor and including: a second source / drain region pair; and a plurality of stacked second channels extending in the first lateral direction between the second source / drain region pairs. The device includes: a pair of gate spacer layers defining a gate trench adjacent to the second channels; and gate metal located in the gate trench and between the second channels. The gate metal has a first length in the gate trench in the first lateral direction and a second length in the first lateral direction between the second channels. The first length is greater than the second length.

[0138] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a plurality of stacked first channels of a first transistor of a complementary field-effect transistor, the first channels extending in a first lateral direction between first source / drain region pairs of the first transistor; forming a plurality of stacked second channels of a second transistor of the complementary field-effect transistor over the first channels, the second channels extending in a second lateral direction between second source / drain region pairs of the second transistor; forming a gate trench between gate spacer layer pairs adjacent to the second channels; and forming a gate metal in the gate trench and between the second channels. The gate metal has a first length in the first lateral direction in the gate trench and a second length in the first lateral direction between the second channels, wherein the first length is greater than the second length; a first dielectric layer is formed over the second source / drain regions; a silicide is formed on one of the source / drain regions in the second source / drain regions; and a source / drain contact is formed extending through the first dielectric layer to contact the silicide, wherein a portion of the source / drain contact is surrounded by the first dielectric layer, and wherein at least a portion of the source / drain contact is covered by a second dielectric layer.

[0139] In some embodiments, the method further includes: forming the gate spacer layer over the second channel; forming a recess by recessing a plurality of sacrificial semiconductor nanostructures between the second channels in the first direction; forming internal spacers in the recess; removing the sacrificial semiconductor nanostructures; and forming the gate metal in place of the sacrificial semiconductor nanostructures, wherein the second gate length depends on the distance between adjacent internal spacers in the first lateral direction. In some embodiments, after recessing the sacrificial semiconductor nanostructures, the width of the sacrificial semiconductor nanostructures in the first lateral direction is less than the distance between the gate spacer layers. In some embodiments, the gate metal has the first length on the top surface of the highest second channel of the plurality of second channels, wherein the gate metal has the second length on the bottom surface of the highest second channel. In some embodiments, the method further includes forming a hard mask nanostructure over the second channel, wherein forming the gate metal includes forming the gate metal between the hard mask nanostructure and the highest second channel of the plurality of second channels. In some embodiments, the gate metal has the first length on the top surface of the hard mask nanostructure, wherein the gate metal has the second length between the hard mask nanostructure and the highest second channel of the plurality of second channels. In some embodiments, the method further includes: removing a central portion of the hard mask nanostructure; and forming a gate metal between adjacent residual portions of the hard mask nanostructure above the highest second channel of the plurality of second channels. In some embodiments, the gate metal has a T-shape above the highest second channel. In some embodiments, the gate metal has a first length between the residual portions of the hard mask nanostructure, wherein the gate metal has the first length above the residual portions of the hard mask nanostructure. In some embodiments, the top surface of the gate metal is coplanar with the top surface of the residual portion of the hard mask structure. In some embodiments, the first channel and the second channel have the same semiconductor material, wherein the first channel has a first crystal orientation, and the second channel has a second crystal orientation different from the first crystal orientation.

[0140] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming an active region extending longitudinally in a first direction; forming an isolation structure extending longitudinally in the first direction adjacent to the active region; forming a plurality of stacked first channels of a first transistor of a complementary field-effect transistor in the active region; forming a first source / drain region pair of the first transistor, the first channel extending between the first source / drain regions; forming a plurality of stacked second channels of a second transistor of the complementary field-effect transistor over the first channel; forming a second source / drain region pair of the second transistor over the first source / drain region pair, the second channel extending between the second source / drain regions; forming an interface gate dielectric layer enclosing the second channel; forming a high-k gate dielectric layer on the interface gate dielectric layer; forming a gate metal enclosing the first channel and the second channel, wherein the first channel and the second channel have the same semiconductor material, wherein the first channel has a first crystal orientation, and the second channel has a second crystal orientation different from the first crystal orientation.

[0141] In some embodiments, the method further includes: forming a plurality of first semiconductor layers of the first material from a first semiconductor substrate of a first wafer having the first crystal orientation via an epitaxial growth process; forming a plurality of first semiconductor layers of the first material from a first semiconductor substrate of a second wafer having the first crystal orientation via an epitaxial growth process; forming a composite wafer by bonding the first wafer to the second wafer; forming a first channel from the first semiconductor layers in the active region; and forming a second channel from the second semiconductor layers in the active region. In some embodiments, the semiconductor material is silicon; the first transistor is a PFET; the first crystal orientation is 110; the second transistor is an NFET; and the second crystal orientation is 100. In some embodiments, the semiconductor material is silicon; the first transistor is an NFET; the first crystal orientation is 100; the second transistor is a PFET; and the second crystal orientation is 110.

[0142] Further embodiments of this application provide a semiconductor device comprising: a substrate; an active region disposed above the substrate and extending longitudinally along a first lateral direction; an isolation structure disposed adjacent to the active region above the substrate; a complementary field-effect transistor located in the active region, comprising: a first transistor including: a first source / drain region pair; and a plurality of stacked first channels extending in the first lateral direction between the first source / drain region pairs, such that the sidewalls of the first channels are in contact with the first source / drain regions; a second transistor located above the first transistor, including: a second source / drain region pair; and a plurality of stacked second channels extending in the first lateral direction between the second source / drain region pairs; a pair of gate spacer layers defining a gate trench adjacent to the second channel; and a gate metal located in the gate trench and between the second channel, wherein the gate metal has a first length in the gate trench in the first lateral direction and a second length in the first lateral direction between the second channels, wherein the first length is greater than the second length.

[0143] In some embodiments, the first channel and the second channel have the same semiconductor material, wherein the first channel has a first crystal orientation and the second channel has a second crystal orientation different from the first crystal orientation. In some embodiments, the gate metal has the first length on the top surface of the highest second channel of the plurality of second channels, wherein the gate metal has the second length on the bottom surface of the highest second channel. In some embodiments, the semiconductor device further includes a hard mask nanostructure located above the second channel, wherein the gate metal is located between the hard mask nanostructure and the highest second channel of the plurality of second channels, wherein the gate metal has the first length on the top surface of the hard mask nanostructure, and wherein the gate metal has the second length between the hard mask nanostructure and the highest second channel of the plurality of second channels. In some embodiments, the semiconductor device further includes: an inner spacer pair located on the highest second channel; and a corresponding hard mask residue located on each inner spacer below the corresponding gate spacer layer, wherein the gate metal is located between the hard mask residues and has a T-shape over the highest second channel, wherein the gate metal has a second length between the hard mask residues, and wherein the gate metal has a first length over the hard mask residues.

[0144] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method of forming a semiconductor device, comprising: forming a plurality of stacked first channels of a first transistor of a complementary field effect transistor, the first channels extending in a first lateral direction between pairs of first source / drain regions of the first transistor; forming a plurality of stacked second channels of a second transistor of the complementary field effect transistor over the first channels, the second channels extending in a second lateral direction between pairs of second source / drain regions of the second transistor; forming gate trenches between pairs of gate spacers adjacent the second channels; forming gate metal in the gate trenches and between the second channels, wherein the gate metal has a first length in the first lateral direction in the gate trenches and a second length in the first lateral direction between the second channels, wherein the first length is greater than the second length; forming a first dielectric layer over the second source / drain regions; forming a silicide on one of the source / drain regions; and forming a source / drain contact extending through the first dielectric layer to contact the silicide, wherein portions of the source / drain contact are surrounded by the first dielectric layer, wherein at least portions of the source / drain contact are covered by a second dielectric layer.

2. The method of claim 1, further comprising: forming the gate spacer layers over the second channels; forming grooves by recessing a plurality of sacrificial semiconductor nanostructures between the second channels in the first direction; forming inner spacers in the grooves; removing the sacrificial semiconductor nanostructures; and forming the gate metal in place of the sacrificial semiconductor nanostructures, wherein the second gate length depends on a distance between adjacent inner spacers in the first lateral direction. After recessing the sacrificial semiconductor nanostructures, the sacrificial semiconductor nanostructures have a width in the first lateral direction that is less than a distance between the gate spacer layers.

3. The method of claim 2, wherein, The gate metal has the first length on a top surface of an uppermost second channel of the plurality of second channels, wherein the gate metal has the second length on a bottom surface of the uppermost second channel.

4. The method of claim 1, wherein, Forming the gate metal includes forming the gate metal between the hardmask nanostructure and the uppermost second channel of the plurality of second channels.

5. The method of claim 1, further comprising forming a hard mask nanostructure over the second trench, wherein, The gate metal has the first length on a top surface of the hardmask nanostructure, wherein the gate metal has the second length between the hardmask nanostructure and the uppermost second channel of the plurality of second channels.

6. The method of claim 5, wherein, 7. The method of claim 5, further comprising: removing a central portion of the hardmask nanostructure; and forming the gate metal between adjacent remaining portions of the hardmask nanostructure over the uppermost second channel of the plurality of second channels. The gate metal has a T-shape over the uppermost second channel.

9. A method of forming a semiconductor device, comprising:

8. The method of claim 7, wherein, forming an active region extending longitudinally in a first direction; ​ ​ An isolation structure extending longitudinally in the first direction is formed adjacent to the active region; A first channel of a plurality of stacked first transistors forming a complementary field-effect transistor is formed in the active region; A first source / drain region pair is formed for the first transistor, and the first channel extends between the first source / drain regions; A plurality of stacked second channels are formed on top of the first channel for the second transistors of the complementary field-effect transistor; A second source / drain region pair of the second transistor is formed above the first source / drain region pair, and the second channel extends between the second source / drain regions; An interface gate dielectric layer is formed to enclose the second channel; A high-k gate dielectric layer is formed on the interface gate dielectric layer; A gate metal is formed to enclose the first channel and the second channel, wherein the first channel and the second channel have the same semiconductor material, wherein the first channel has a first crystal orientation, and the second channel has a second crystal orientation different from the first crystal orientation.

10. A semiconductor device, comprising: Substrate; An active region is disposed above the substrate and extends longitudinally along a first lateral direction; An isolation structure is disposed next to the active region above the substrate; A complementary field-effect transistor (CFPT) is located in the active region. The CFPT includes: a first transistor; and a second transistor located above the first transistor. The first transistor includes: a first source / drain region pair; and a plurality of stacked first channels extending in a first lateral direction between the first source / drain region pairs, such that the sidewalls of the first channels are in contact with the first source / drain regions. The second transistor includes: a second source / drain region pair; and a plurality of stacked second channels extending in the first lateral direction between the second source / drain region pairs. A pair of gate spacer layers defines a gate trench adjacent to the second channel; and A gate metal is located in the gate trench and between the second channel, wherein the gate metal has a first length in the first lateral direction in the gate trench and a second length in the first lateral direction between the second channels, wherein the first length is greater than the second length.

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