Pn integrated circuit device and method of manufacturing the same

Abstract

This invention discloses a pn integrated circuit device and its fabrication method. The embodiments of this invention utilize the negative polarization interface of nitrogen-polarized AlGaN / GaN to induce the generation of 2DHG, thereby forming p-GaN. This method abandons the traditional method of doping ionized holes, simplifying the epitaxial process and simultaneously obtaining high-mobility, high-density p-type and n-type channels.

Description

Technical Field

[0001] This invention specifically relates to a pn integrated circuit device and its fabrication method, belonging to the field of micro-nano manufacturing technology. Background Technology

[0002] Inverters are core components in integrated circuit products (such as microprocessors, CPUs and GPUs, logic and analog circuits, etc.). A schematic diagram of a typical Si-CMOS inverter is shown below. Figure 1a As shown, when the input voltage is high, the lower N-MOS is turned on and the upper P-MOS is turned off, so the output is low; when the input voltage is low, the lower N-MOS is turned off and the upper P-MOS is turned on, so the output is high, thus realizing the function of an inverter.

[0003] Because almost only one transistor is conducting during the entire operation of a CMOS inverter, static losses are significantly reduced. Compared to Si devices, electrons in GaN-HEMTs have higher mobility, meaning GaN-based devices will have faster switching speeds. Furthermore, GaN has a higher breakdown voltage, which allows for a larger operating voltage swing, effectively improving the driving capability of circuits. In addition, GaN exhibits high-temperature stability, effectively reducing circuit cooling costs and enabling operation in extreme environments such as high temperature and high pressure. Due to the superior physical properties of GaN compared to traditional Si materials, digital circuits based on GaN-HEMT devices will be one of the key research focuses for next-generation digital circuits.

[0004] However, during the epitaxial process, GaN exhibits n-GaN due to the unintentional incorporation of impurities such as O and Si. Furthermore, the two-dimensional charge carriers formed at the AlGaN / GaN heterojunction due to polarization effects are also electrons, allowing GaN HEMT devices to be realized without intentional doping. Therefore, most mainstream GaN devices are currently n-FET devices. Due to GaN's large bandgap, the intrinsic hole carrier concentration is very low. How to fabricate high-performance, high-stability GaN p-FETs is currently a key scientific problem. In gallium polar GaN, to realize p-FET devices, p-type dopants such as Mg are usually intentionally doped during GaN epitaxy to form p-GaN with a bulk hole carrier distribution, such as... Figure 1b As shown.

[0005] Currently, p-FET devices are fabricated using doping ionization to generate holes, resulting in low hole mobility and poor device performance because these holes are distributed within the GaN epitaxial material. Furthermore, Mg, the most commonly used p-type dopant in GaN, suffers from memory effects, numerous defect levels, and very low ionization efficiency (often below 1%), necessitating high Mg concentrations. However, excessive Mg doping can lead to a self-compensation effect, decreasing hole concentration, and some Mg diffuses into the underlying electron channel, reducing the 2DEG density on the n-FET side during pn integration and affecting overall circuit performance. Consequently, current p-FET devices exhibit poor stability and numerous reliability issues. Additionally, to prevent the 2DEG at the gallium-polar AlGaN / GaN heterojunction from affecting the p-GaN layer, a thinner AlGaN layer is used as a barrier in the epitaxial structure. For n-GaN, etching away the p-GaN region restores the 2DEG, but due to the thinner barrier, the 2DEG density is also lower, resulting in poor DC characteristics for the n-FET. Summary of the Invention

[0006] The main objective of this invention is to provide a pn integrated circuit device and its fabrication method. It innovatively utilizes the negative polarization interface in the nitrogen polar AlGaN / GaN heterojunction to intrinsically generate 2DHG (two-dimensional hole gas) without doping, which solves the problems of low mobility and poor stability of pFET caused by Mg doping p-GaN, improves the performance of p-FET devices, thereby improving the overall performance of pn integrated circuits and overcoming the shortcomings of the prior art.

[0007] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0008] A first aspect of the present invention provides a pn integrated circuit device, comprising:

[0009] The nitrogen-polar epitaxial structure includes an n-type heterostructure and a p-type heterostructure. The p-type heterostructure is disposed longitudinally on the n-type heterostructure. The n-type heterostructure contains a two-dimensional electron gas, and the p-type heterostructure contains a two-dimensional hole gas. The two-dimensional hole gas is induced by the negative polarization interface in the nitrogen-polar p-type heterostructure.

[0010] The first source, the first drain, and the first gate, together with the n-type heterostructure, form an n-FET device;

[0011] The second source, the second drain, and the second gate, together with the p-type heterostructure, form a p-FET device. The second gate is electrically connected to the first gate, and the second drain is electrically connected to the first drain.

[0012] A second aspect of this invention provides a method for fabricating a pn integrated circuit device, comprising:

[0013] A nitrogen-polar epitaxial structure is fabricated, comprising a first barrier layer, a first channel layer, a cap layer, a second channel layer, and a second barrier layer stacked sequentially along the longitudinal direction. The first barrier layer, the first channel layer, and the cap layer are combined to form an n-type heterostructure. A two-dimensional electron gas is formed at the interface between the first channel layer and the first barrier layer. The second channel layer and the second barrier layer are combined to form a p-type heterostructure. A two-dimensional hole gas is formed at the interface between the second channel layer and the second barrier layer. The two-dimensional hole gas is induced by the negative polarization interface between the second channel layer and the second barrier layer.

[0014] The epitaxial structure defines an n-FET device region and a p-FET device region, which are arranged laterally spaced.

[0015] Remove the second channel layer and the second barrier layer located in the n-FET device region;

[0016] An n-type heterostructure located in the n-FET device region is processed, and a first source, a first drain, and a first gate are fabricated in the n-FET device region. The first source, the first drain, and the first gate are then combined with the epitaxial structure to form an n-FET device. The first source and the first drain are electrically connected to the two-dimensional electron gas, and the first gate is disposed on the cap layer.

[0017] A p-type heterostructure located in the p-FET device region is processed, and a second source, a second drain, and a second gate are fabricated in the p-FET device region. The second source, the second drain, and the second gate are then combined with the epitaxial structure to form a p-FET device. The second source and the second drain are electrically connected to the two-dimensional hole gas, and the second gate is disposed on the second barrier layer.

[0018] An isolation structure is formed within the epitaxial structure, and the isolation structure is distributed around the n-FET device region and the p-FET device region.

[0019] The second gate is electrically connected to the first gate, and the second drain is electrically connected to the first drain.

[0020] Compared with the prior art, the advantages of the present invention include:

[0021] This invention innovatively utilizes the negative polarization interface in a nitrogen polar heterojunction to intrinsically generate 2DHG (two-dimensional hole gas), fundamentally changing the hole source in p-GaN;

[0022] Due to the presence of quantum wells, the hole carriers in 2DHG are subject to reduced scattering, resulting in higher mobility. The inverters formed by combining 2DHG with n-GaN will also have a faster response speed, thus making them applicable to high-speed circuits.

[0023] The hole carriers in this invention come from the polarization effect of the epitaxial structure itself, so doping is not required during the epitaxial process, which simplifies the epitaxial process and can also enhance the stability of the p-GaN channel layer.

[0024] The method provided by this invention does not require thinning of the barrier layer at the lower n-channel, thus the 2DEG density in the n-GaN channel layer is also higher. Attached Figure Description

[0025] Figure 1a This is a schematic diagram of the device-level structure of a traditional Si-CMOS inverter circuit;

[0026] Figure 1b This is a schematic diagram of a gallium-polar GaN-p-type doped p-FET epitaxial structure;

[0027] Figure 2 This is a schematic diagram of a heterojunction HEMT epitaxial structure based on nitrogen polar GaN provided in Embodiment 1 of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure after removing the second barrier layer and the second channel layer in the n-FET device region in Embodiment 1 of the present invention;

[0029] Figure 4 This is a schematic diagram of the structure after removing all the cap layers and part of the first channel layer of the ohmic region of the n-FET device region in Embodiment 1 of the present invention;

[0030] Figure 5 This is a schematic diagram of the structure after the first source and the first drain are formed in the n-FET device region in Embodiment 1 of the present invention;

[0031] Figure 6 This is a schematic diagram of the structure after the gate dielectric layer is deposited in Embodiment 1 of the present invention;

[0032] Figure 7 This is a schematic diagram of the structure after removing the dielectric layer, the second barrier layer, and part of the second channel layer from the ohmic region of the p-FET device region in Embodiment 1 of the present invention.

[0033] Figure 8This is a schematic diagram of the structure after the second source and second drain are formed in the p-FET device region and the first gate is formed in the n-FET device region in Embodiment 1 of the present invention;

[0034] Figure 9 This is a schematic diagram of the structure forming the isolation structure in Embodiment 1 of the present invention;

[0035] Figure 10 This is a schematic diagram of the structure after opening a window in the top gate dielectric layer of the first drain in the n-FET device region in Embodiment 1 of the present invention;

[0036] Figure 11 This is a schematic diagram of the pn integrated circuit device formed in Embodiment 1 of the present invention;

[0037] Figure 12 This is a schematic diagram of a heterojunction HEMT epitaxial structure based on nitrogen polar GaN provided in Embodiment 2 of the present invention;

[0038] Figure 13 This is a schematic diagram of the structure after removing the second barrier layer and the second channel layer in the n-FET device region in Embodiment 2 of the present invention;

[0039] Figure 14 This is a schematic diagram of the structure after removing the cap layer of the non-gate region of the n-FET device region in Embodiment 2 of the present invention;

[0040] Figure 15 This is a schematic diagram of the structure after removing the first channel layer of the ohmic region of the n-FET device region in Embodiment 2 of the present invention;

[0041] Figure 16 This is a schematic diagram of the structure after the first source and the first drain are formed in the n-FET device region in Embodiment 2 of the present invention;

[0042] Figure 17 This is a schematic diagram of the structure after the gate dielectric layer is deposited in Embodiment 2 of the present invention;

[0043] Figure 18 This is a schematic diagram of the structure after removing the dielectric layer and the n-doped second barrier layer from the non-gate region of the p-FET device region in Embodiment 2 of the present invention;

[0044] Figure 19 This is a schematic diagram of the structure after the second source and the second drain are formed in the p-FET device region and the first gate is formed in the n-FET device region in Embodiment 2 of the present invention;

[0045] Figure 20 This is a schematic diagram of the structure forming the isolation structure in Embodiment 2 of the present invention;

[0046] Figure 21This is a schematic diagram of the structure after opening a window in the top gate dielectric layer of the first drain in the n-FET device region in Embodiment 2 of the present invention;

[0047] Figure 22 This is a schematic diagram of the pn integrated circuit device formed in Embodiment 2 of the present invention. Detailed Implementation

[0048] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0049] A first aspect of the present invention provides a pn integrated circuit device, comprising:

[0050] The nitrogen-polar epitaxial structure includes an n-type heterostructure and a p-type heterostructure. The p-type heterostructure is disposed longitudinally on the n-type heterostructure. The n-type heterostructure contains a two-dimensional electron gas, and the p-type heterostructure contains a two-dimensional hole gas. The two-dimensional hole gas is induced by the negative polarization interface in the nitrogen-polar p-type heterostructure.

[0051] The first source, the first drain, and the first gate, together with the n-type heterostructure, form an n-FET device;

[0052] The second source, the second drain, and the second gate, together with the p-type heterostructure, form a p-FET device. The second gate is electrically connected to the first gate, and the second drain is electrically connected to the first drain.

[0053] Furthermore, the n-FET device is a depletion-type device or an enhancement-type device, and the p-FET device is a depletion-type device or an enhancement-type device.

[0054] Furthermore, the n-type heterostructure includes a first barrier layer, a first channel layer, and a cap layer stacked sequentially along the longitudinal direction. The two-dimensional electron gas is formed at the interface of the first channel layer near the first barrier layer. The first source and the first drain are electrically connected via the two-dimensional electron gas, and the first gate is disposed on the cap layer.

[0055] Furthermore, the material of the first channel layer includes GaN, but is not limited to this.

[0056] Furthermore, the first barrier layer and the first channel layer form a heterojunction. The material of the first barrier layer includes at least one or a combination of two or more of AlGaN, AlN, AlInN, and AlInGaN, but is not limited thereto. That is, the first barrier layer can be a single-layer structure of a single material, or a composite structure formed by two or more material layers.

[0057] Furthermore, the cap layer is used to reduce gate leakage current of the n-FET device. The material of the cap layer includes at least one or a combination of two or more of AlN, AlGaN, AlInN-based, and AlInGaN, but is not limited thereto. That is, the cap layer can be a single-layer structure formed by a single material, or a composite structure formed by two or more material layers.

[0058] Furthermore, the p-type heterostructure includes a second channel layer and a second barrier layer stacked sequentially along the longitudinal direction. The two-dimensional hole gas is formed at the interface of the second channel layer near the second barrier layer. The second source and the second drain are electrically connected through the two-dimensional hole gas, and the second gate is disposed on the second barrier layer.

[0059] Furthermore, the material of the second channel layer includes GaN, but is not limited to this.

[0060] Furthermore, the second barrier layer and the second channel layer form a heterojunction. The material of the second barrier layer includes at least one or a combination of two or more of AlGaN, AlN, AlInN, and AlInGaN, but is not limited thereto. That is, the second barrier layer can be a single-layer structure of a single material, or a composite structure formed by two or more material layers.

[0061] Furthermore, the second channel layer is stacked on the cap layer.

[0062] Furthermore, if the p-FET device is an enhancement-mode device, the second barrier layer includes a first sub-barrier layer and a second sub-barrier layer sequentially stacked on the second channel layer, wherein the second sub-barrier layer is n-type doped, and the second gate is disposed on the second sub-barrier layer.

[0063] Furthermore, the epitaxial structure includes an n-FET device region and a p-FET device region arranged laterally, a portion of the n-type heterostructure is located in the n-FET device region and another portion is located in the p-FET device region, the p-type heterostructure is completely located in the p-FET device region, and an isolation structure is also formed within the epitaxial structure, the isolation structure being distributed around the n-FET device region and the p-FET device region.

[0064] Furthermore, the epitaxial structure also includes a substrate and a buffer layer, the buffer layer being stacked on the substrate, the first barrier layer being stacked on the buffer layer, and the isolation structure extending longitudinally into the buffer layer along the epitaxial structure.

[0065] Furthermore, the buffer layer includes a doped high-resistivity layer and an undoped layer stacked together. The specific thickness and structure of the doped high-resistivity layer and the undoped layer can be adjusted according to actual needs. This buffer layer can improve the performance of p-FET and n-FET devices.

[0066] Furthermore, the material of the doped high-resistivity layer includes either GaN-based or AlGaN-based materials, and the doping atoms of the doped high-resistivity layer include Fe atoms and / or C atoms, with a doping concentration of 1e*18 to 2e*19. The material of the undoped layer includes GaN, and the thickness of the undoped layer is 50 nm to 200 nm. It should be noted that the undoped layer is used to separate the doped high-resistivity layer from the first barrier layer above it, preventing doping atoms (such as Fe) in the doped high-resistivity layer from diffusing into the channel due to the memory effect during epitaxy, thus affecting device performance. If there is no doped high-resistivity layer, the undoped layer is not required. In addition, it should be noted that this buffer layer is not necessary depending on the epitaxial growth conditions.

[0067] Furthermore, the substrate includes a silicon substrate, a sapphire substrate, a silicon carbide substrate, or a composite substrate formed from two or more of silicon substrate, sapphire, and silicon carbide, but is not limited thereto.

[0068] In a more specific implementation, the epitaxial structure further includes an n-type doped layer, on which the first barrier layer is stacked. The n-type doped layer is used at least to adjust the band structure near the nitrogen-polarized AlGaN / GaN heterojunction, so that the Fermi level is far away from the valence band, thereby avoiding the influence of hole traps near the valence band and ensuring the output of the device.

[0069] Furthermore, the n-type doped layer is stacked on the buffer layer.

[0070] Furthermore, the n-type doped layer includes a first n-type doped layer and a second n-type doped layer stacked together, and the n-type heterostructure is disposed on the second n-type doped layer, wherein the Al composition in the second n-type doped layer is gradually distributed. Even further, the Al composition content in the second n-type doped layer gradually increases from the first n-type doped layer towards the n-type heterostructure. This gradual distribution of Al composition can reduce the required n-type doping concentration and avoid excessive doping leading to parasitic channels. Even further, the material of the first n-type doped layer includes GaN, but is not limited to this, and the material of the second n-type doped layer includes AlGaN, but is not limited to this. For example, the dopant in the n-type doped layer can be an impurity containing Si, or other n-type dopant impurities. For example, the n-type doped layer consists of a GaN doped layer and a graded AlGaN doped layer. The Si doping concentration of both the GaN doped layer and the graded AlGaN doped layer is (3~5)*e18. The thickness of the GaN doped layer is about 10 nm, and the thickness of the graded AlGaN doped layer is about 20 nm. The Al content in the graded AlGaN doped layer gradually changes from 0.05 to 0.3 from the side closest to the GaN doped layer.

[0071] Furthermore, the isolation structure not only isolates the n-FET device and the p-FET device, but also separates the PN integrated device from external devices to prevent mutual interference. Even further, the isolation structure is an ion-implanted region formed by ion implantation of the epitaxial structure, or an isolation trench formed by etching away a portion of the epitaxial structure.

[0072] A second aspect of this invention provides a method for fabricating a pn integrated circuit device, comprising:

[0073] A nitrogen-polar epitaxial structure is fabricated, comprising a first barrier layer, a first channel layer, a cap layer, a second channel layer, and a second barrier layer stacked sequentially along the longitudinal direction. The first barrier layer, the first channel layer, and the cap layer are combined to form an n-type heterostructure. A two-dimensional electron gas is formed at the interface between the first channel layer and the first barrier layer. The second channel layer and the second barrier layer are combined to form a p-type heterostructure. A two-dimensional hole gas is formed at the interface between the second channel layer and the second barrier layer. The two-dimensional hole gas is induced by the negative polarization interface between the second channel layer and the second barrier layer.

[0074] The epitaxial structure defines an n-FET device region and a p-FET device region, which are arranged laterally spaced.

[0075] Remove the second channel layer and the second barrier layer located in the n-FET device region;

[0076] An n-type heterostructure located in the n-FET device region is processed, and a first source, a first drain, and a first gate are fabricated in the n-FET device region. The first source, the first drain, and the first gate are then combined with the epitaxial structure to form an n-FET device. The first source and the first drain are electrically connected to the two-dimensional electron gas, and the first gate is disposed on the cap layer.

[0077] A p-type heterostructure located in the p-FET device region is processed, and a second source, a second drain, and a second gate are fabricated in the p-FET device region. The second source, the second drain, and the second gate are then combined with the epitaxial structure to form a p-FET device. The second source and the second drain are electrically connected to the two-dimensional hole gas, and the second gate is disposed on the second barrier layer.

[0078] An isolation structure is formed within the epitaxial structure, and the isolation structure is distributed around the n-FET device region and the p-FET device region.

[0079] The second gate is electrically connected to the first gate, and the second drain is electrically connected to the first drain.

[0080] Furthermore, the n-FET device is a depletion-type device or an enhancement-type device, and the p-FET device is a depletion-type device or an enhancement-type device.

[0081] Furthermore, the material of the first channel layer includes GaN, but is not limited to this.

[0082] Furthermore, the first barrier layer and the first channel layer form a heterojunction. The material of the first barrier layer includes at least one or a combination of two or more of AlGaN, AlN, AlInN, and AlInGaN, but is not limited thereto. That is, the first barrier layer can be a single-layer structure of a single material, or a composite structure formed by two or more material layers.

[0083] Furthermore, the cap layer is used to reduce gate leakage current of the n-FET device. The material of the cap layer includes at least one or a combination of two or more of AlN, AlGaN, AlInN-based, and AlInGaN, but is not limited thereto. That is, the cap layer can be a single-layer structure formed by a single material, or a composite structure formed by two or more material layers.

[0084] Furthermore, the material of the second channel layer includes GaN, but is not limited to this.

[0085] Furthermore, the second barrier layer and the second channel layer form a heterojunction. The material of the second barrier layer includes at least one or a combination of two or more of AlGaN, AlN, AlInN, and AlInGaN, but is not limited thereto. That is, the second barrier layer can be a single-layer structure of a single material, or a composite structure formed by two or more material layers.

[0086] Furthermore, the second channel layer is stacked on the cap layer.

[0087] Furthermore, if the p-FET device is an enhancement-mode device, the second barrier layer includes a first sub-barrier layer and a second sub-barrier layer sequentially stacked on the second channel layer, wherein the second sub-barrier layer is n-type doped, and the second gate is disposed on the second sub-barrier layer.

[0088] Furthermore, the epitaxial structure also includes a substrate and a buffer layer, wherein the buffer layer is stacked on the substrate and the first barrier layer is stacked on the buffer layer.

[0089] Furthermore, the buffer layer includes a doped high-resistivity layer and an undoped layer stacked together. The specific thickness and structure of the doped high-resistivity layer and the undoped layer can be adjusted according to actual needs. This buffer layer can improve the performance of p-FET and n-FET devices.

[0090] Furthermore, the substrate includes a silicon substrate, a sapphire substrate, a silicon carbide substrate, or a composite substrate formed from two or more of silicon substrate, sapphire, and silicon carbide, but is not limited thereto.

[0091] In a more specific embodiment, the epitaxial structure further includes an n-type doped layer, which is stacked on a buffer layer, and the first barrier layer is stacked on the n-type doped layer. The n-type doped layer is used at least to adjust the band structure near the nitrogen-polarized AlGaN / GaN heterostructure, so that the Fermi level is far away from the valence band, thereby avoiding the influence of hole traps near the valence band and ensuring the output of the device.

[0092] Furthermore, the n-type doped layer is stacked on the buffer layer.

[0093] Furthermore, the n-type doped layer includes a first n-type doped layer and a second n-type doped layer stacked together, and the n-type heterostructure is disposed on the second n-type doped layer, wherein the Al composition in the second n-type doped layer is gradually distributed. Even further, the Al composition content in the second n-type doped layer gradually increases from the first n-type doped layer towards the n-type heterostructure. This gradual distribution of Al composition can reduce the required n-type doping concentration and avoid excessive doping leading to parasitic channels. Even further, the material of the first n-type doped layer includes GaN, but is not limited to this, and the material of the second n-type doped layer includes AlGaN, but is not limited to this. For example, the dopant in the n-type doped layer can be an impurity containing Si, or other n-type dopant impurities. For example, the n-type doped layer consists of a GaN doped layer and a graded AlGaN doped layer. The Si doping concentration of both the GaN doped layer and the graded AlGaN doped layer is (3~5)*e18. The thickness of the GaN doped layer is about 10 nm, and the thickness of the graded AlGaN doped layer is about 20 nm. The Al content in the graded AlGaN doped layer gradually changes from 0.05 to 0.3 from the side closest to the GaN doped layer.

[0094] Furthermore, the isolation structure not only isolates the n-FET device and the p-FET device, but also separates the PN integrated device from external devices to prevent mutual interference. Even further, the isolation structure is an ion-implanted region formed by ion implantation of the epitaxial structure, or an isolation trench formed by etching away a portion of the epitaxial structure.

[0095] This invention proposes a method for fabricating a nitrogen-polar GaN heterojunction epitaxial structure that integrates GaN-pn devices on the same wafer. The key to this invention lies in the epitaxial structure designed based on the unique polarization direction of nitrogen-polar GaN. This epitaxial structure includes a top AlGaN / GaN heterojunction that generates 2DHG, an AlGaN heavily doped Si layer that realizes enhanced p-GaN, and an AlN / GaN / AlGaN heterojunction that realizes enhanced n-GaN.

[0096] This invention proposes to utilize the negative polarization interface of nitrogen-polar AlGaN / GaN to induce the generation of 2DHG, thereby forming p-GaN. This method abandons the traditional method of doping ionized holes, which not only simplifies the epitaxial process but also allows for the simultaneous acquisition of p-type and n-type channels with high mobility and high density.

[0097] The following explanation uses nitrogen-polar HEMT as an example, along with accompanying drawings and specific implementation examples, to further illustrate the technical solution, its implementation process, and principles. Unless otherwise specified, the epitaxial growth, etching, ion implantation, and other equipment and processes used in the embodiments of this invention are all known in the art and will not be specifically described here.

[0098] Example 1

[0099] A method for fabricating a PN double depletion type integrated circuit device based on a nitrogen-polar AlGaN / GaN negative polarization interface includes the following steps:

[0100] 1) Heterojunction HEMT epitaxial structures oriented towards nitrogen-polar GaN-pn double depletion type integration are epitaxially grown using MOCVD (organic metal chemical vapor deposition) technology, such as... Figure 2 As shown.

[0101] The heterojunction HEMT epitaxial structure includes a substrate, a buffer layer, a first barrier layer, a first channel layer, a cap layer, a second channel layer, and a second barrier layer stacked sequentially along its own longitudinal direction. The interface between the second channel layer and the second barrier layer has a two-dimensional hole gas, and the interface between the first channel layer and the first barrier layer has a two-dimensional electron gas.

[0102] The first barrier layer is an AlGaN barrier layer with an Al content of 0.3% and a thickness of 10 nm to 30 nm; the first channel layer is a GaN channel layer with a thickness of 20 nm to 40 nm; the cap layer is an AlGaN cap layer with a thickness of approximately 3 nm to 5 nm and an Al content of 0.4%; the second channel layer is a GaN channel layer with a thickness of approximately 20 nm to 50 nm; the second barrier layer is an AlGaN barrier layer with a thickness of approximately 10 nm to 30 nm and an Al content of 0.6%.

[0103] 2) Define n-FET and p-FET device regions in the heterojunction HEMT epitaxial structure, with the n-FET and p-FET device regions spaced laterally along the HEMT epitaxial structure; using AZ5214 photoresist (or other types of photoresist) with a thickness of 1μm to 2μm as a mask, etch away the second barrier layer and second channel layer of the n-FET device region using ICP (inductively coupled plasma etching). Figure 3 As shown.

[0104] 3) Using AZ5214 photoresist with a thickness of 1μm to 2μm (or other types of photoresist) as a mask, etch away the cap layer in the source and drain ohmic regions of the n-FET device region and the first channel layer with a thickness of 0nm to 10nm using ICP slow etching. Figure 4 As shown.

[0105] 4) Fabrication of the first source and first drain of the n-FET device: Ohmic metals Ti / Al / Ni / Au are formed in the source and drain ohmic regions of the n-FET device using electron beam evaporation technology. The thicknesses of Ti / Al / Ni / Au are 20nm / 100nm / 50nm / 50nm. Subsequently, the first source and first drain are formed by high-temperature annealing at 810℃~890℃ for 15s~60s using an RTP (Rapid Retardation Processing) furnace. The first source and first drain are then electrically connected to a two-dimensional electron gas, such as... Figure 5 As shown.

[0106] 5) Deposited gate dielectric layer: An Al2O3 layer is deposited on the top surface of the epitaxial structure using ALD (Atom Layer Deposition) technology. The thickness of the Al2O3 layer is 2nm to 50nm. Figure 6 As shown. Further, post-annealing is performed in an N2 atmosphere at a temperature of 300°C to 500°C for a time of 1 min to 20 min, preferably 1 min to 3 min, to reduce the interface states at the dielectric-semiconductor interface, thereby improving the dynamic characteristics of the device.

[0107] 6) Using AZ5214 photoresist with a thickness of 1μm to 2μm (or other types of photoresist), ICP etching is performed on the gate dielectric layer, second barrier layer, and part of the second channel layer in the ohmic region of the p-FET device area, such as... Figure 7 As shown.

[0108] 7) Fabrication of the second source and second drain of the p-FET device, and fabrication of the first gate of the n-FET device: Electron beam evaporation is used to deposit Ni / Au metal in the ohmic region of the p-FET device region and the gate region of the n-FET device region. The Ni / Au thickness is 50nm / 100nm. Subsequently, it is annealed at a medium temperature of 400℃~600℃ for 2min~4min using an RTP (Rapid Retardation Processing) furnace, thereby forming the second source and second drain in the ohmic region of the p-FET device region, and the first gate in the gate region of the n-FET device region. The first gate is disposed above the cap layer. The second source and second drain are electrically connected to the two-dimensional hole gas, such as... Figure 8 As shown.

[0109] 8) Active region isolation and p-FET / n-FET device region isolation: N-ion implantation technology is used to implant ions into the epitaxial structure located between the p-FET and n-FET device regions and between different pn integrated devices. The ion implantation energy is 20 keV to 400 keV, and the implantation ion dose is 10. 12 / cm2 ~10 14 / cm 2 The injection depth is approximately 50nm to 250nm beyond the buffer layer, thereby forming an isolation structure, such as... Figure 9 As shown.

[0110] 9) First drain dielectric windowing of n-FET: Using AZ5214 photoresist with a thickness of 1μm to 2μm (or other types of photoresist) as a mask, ICP plasma etching is used to etch the Al2O3 dielectric layer covering the first drain to achieve ohmic contact windowing at the n-FET drain terminal, as shown below. Figure 10 As shown.

[0111] 10) Fabricating the second gate of the p-FET device, and performing pn-FET drain and gate interconnects: Electron beam evaporation is used to deposit Ti / Au metal in the gate region of the p-FET device area. The thickness of the Ti / Au is 20nm / 100nm, thus forming the second gate. The second gate is positioned above the second barrier layer. Simultaneously, the first drain is interconnected with the second drain, and the first gate and second gate are interconnected, as shown below. Figure 11 As shown.

[0112] Example 2

[0113] A method for fabricating a PN dual-enhancement integrated circuit device based on a nitrogen-polar AlGaN / GaN negative polarization interface includes the following steps:

[0114] 1) A heterojunction HEMT epitaxial structure oriented towards nitrogen-polar GaN-pn dual-enhancement integration is epitaxially grown using MOCVD technology, such as... Figure 12 As shown.

[0115] The heterojunction HEMT epitaxial structure includes a substrate, a buffer layer, a first barrier layer, a first channel layer, a cap layer, a second channel layer, and a second barrier layer stacked sequentially along its own longitudinal direction. A two-dimensional electron gas is present at the interface between the first channel layer and the first barrier layer.

[0116] The first barrier layer is an AlGaN barrier layer with an Al composition of 0.3 and a thickness of approximately 10–30 nm. The first channel layer is a GaN channel layer with a thickness of 10–30 nm. The cap layer is an AlN cap layer with a thickness of approximately 3–5 nm. The second channel layer is a GaN channel layer with a thickness of 30–50 nm. The second barrier layer includes a Si-doped AlGaN sub-barrier layer and a non-Si-doped AlGaN sub-barrier layer stacked sequentially. The Si-doped AlGaN sub-barrier layer has a thickness of approximately 10–20 nm and a Si doping concentration of (1–3) × 10⁻⁶. 20 cm -3The Al content is 0.3%, the thickness of the non-Si-doped AlGaN sub-barrier layer is 3nm to 5nm, and the Al content is 0.6%.

[0117] 2) Define n-FET and p-FET device regions in the heterojunction HEMT epitaxial structure, with the n-FET and p-FET device regions spaced laterally along the HEMT epitaxial structure; using AZ5214 photoresist (or other types of photoresist) with a thickness of 1μm to 2μm as a mask, etch away the second barrier layer and second channel layer of the n-FET device region using ICP etching, as shown. Figure 13 As shown.

[0118] 3) Using AZ5214 photoresist with a thickness of 1μm to 2μm (or other types of photoresist) as a mask, the cap layer of the non-gate region of the n-FET device is etched away using ICP etching, thereby recovering the underlying two-dimensional electron gas (2DEG), such as... Figure 14 As shown. It should be noted that the cap layer of the non-gate region within the n-FET device area is not limited to full etching; its etching depth is adjustable, as long as the underlying two-dimensional electron gas can be recovered.

[0119] 4) Using AZ5214 photoresist with a thickness of 1μm to 2μm (or other types of photoresist) as a mask, etch away part of the first channel layer in the ohmic region of the n-FET device area using ICP etching, such as... Figure 15 As shown.

[0120] 5) Fabrication of the first source and first drain of the n-FET device: Using electron beam evaporation, ohmic metals Ti / Al / Ni / Au are formed in the source and drain ohmic regions of the n-FET device, with thicknesses of 20nm / 100nm / 50nm / 50nm respectively. Subsequently, the first source and first drain are formed by high-temperature annealing at 810℃~890℃ for 15s~60s using an RTP (Rapid Retardation Processing) furnace. The first source and first drain are then electrically connected to a two-dimensional electron gas, such as... Figure 16 As shown.

[0121] 6) Gate dielectric layer deposition: Al2O3 is deposited as the gate dielectric layer on the top surface of the epitaxial structure using ALD (Atom Layer Deposition) technology. The thickness of the Al2O3 layer is 2nm to 50nm. Figure 17 As shown. Further, post-annealing is performed in an N2 atmosphere at a temperature of 300°C to 500°C for a time of 1 min to 20 min, preferably 1 min to 3 min, to reduce the interface states at the dielectric-semiconductor interface, thereby improving the dynamic characteristics of the device.

[0122] 7) Using AZ5214 photoresist with a thickness of 1μm to 2μm (or other types of photoresist) as a mask, ICP etching is used to remove the dielectric layer and Si-doped AlGaN barrier layer between the non-gate regions of the p-FET device, thereby recovering the underlying two-dimensional hole gas (2DHG). Figure 18 As shown.

[0123] 8) Fabricate the second source and second drain of the p-FET device, and the first gate of the n-FET device. Electron beam evaporation is used to deposit Ni / Au metal in the ohmic region of the p-FET device region and the gate region of the n-FET device region. The Ni / Au thickness is 50nm / 100nm. Subsequently, annealing is performed at a medium temperature of 400–600℃ for 2–4 minutes using an RTP (Rapid Retardation Processing) furnace to form the second source and second drain of the p-FET device and the first gate of the n-FET device. The second source and second drain are disposed on a non-Si-doped AlGaN cap layer and are electrically connected to a two-dimensional hole gas. The first gate is disposed above the cap layer. Figure 19 As shown.

[0124] 9) Active region isolation and p-FET / n-FET device region isolation: N-ion implantation technology is used to implant ions into the epitaxial structure located between the p-FET and n-FET device regions and between different pn integrated devices. The ion implantation energy is 20 keV to 400 keV, and the implantation ion dose is 10. 12 / cm 2 ~10 14 / cm 2 The injection depth is approximately 50nm to 250nm beyond the buffer layer, thereby forming an isolation structure, such as... Figure 20 As shown.

[0125] 10) First drain dielectric windowing of n-FET: Using AZ5214 photoresist with a thickness of 1μm to 2μm (or other types of photoresist) as a mask, the Al2O3 dielectric layer covering the first drain is etched by ICP plasma etching to realize the ohmic contact windowing of the n-FET drain terminal, such as... Figure 21 As shown.

[0126] 11) Fabricating the second gate of the p-FET device, and performing pn-FET drain and gate interconnects: Electron beam evaporation is used to deposit Ti / Au metal in the gate region of the p-FET device area. The Ti / Au thickness is 20nm / 100nm, thus forming the second gate. The second gate is positioned above the Si-doped AlGaN cap layer. Simultaneously, the first drain and the second drain are interconnected, and the first gate and the second gate are interconnected, as shown below. Figure 22 As shown.

[0127] It should be noted that the pn integrated circuit device in the embodiments of the present invention is applicable to any integrated circuit based on pn devices. The pn devices include any integrated combination of pn type devices such as double depletion pn devices, double enhancement pn devices, p-depletion and n-enhancement devices, and p-enhancement and n-depletion devices.

[0128] The epitaxial growth method in this embodiment is not limited to MOCVD; other epitaxial growth methods such as MBE and HVPE can also be used. In this example, the nitrogen-polar GaN is prepared by direct epitaxial growth, but a method of first growing a gallium-polar substrate and then flipping it to obtain nitrogen polarity can also be used. The drain and source ohmic contacts in this embodiment can be achieved using alloy high-temperature annealing, secondary epitaxial n+ technology, or ion implantation of Si ions. Any technique for achieving GaN ohmic contacts is included within the scope of this invention. The drain and source ohmic metals in this embodiment can be not only Ti / Al / Ni / Au, but also other metal systems that can form ohmic contacts with GaN, such as Ti / Al / Ti / Au, Ti / Al / Pt / Au, etc., and the thickness of each metal layer can also be adjusted. The gate metal is not limited to Ni / Au; it can also be Ni / Pt / Au, Ni / Pt, or other metal systems that can form Schottky contacts with GaN, and its thickness can also be adjusted. The gate dielectric layer in this embodiment can also be made of SiN, SiO2, HfO2, La2O3, etc., and the deposition method is not limited to ALD, but can also be PECVD, LPCVD, MOCVD, etc. The gate in this embodiment uses a MIS structure, but a Schottky structure can also be used. The order of the gate dielectric deposition and ion implantation isolation processes in this embodiment can be interchanged. The active region isolation technology in this embodiment is not limited to ion implantation; it can also be achieved by etching away the epitaxial layer outside the active region. The ions used for implantation isolation in this embodiment are not limited to N ions; other ions that can achieve GaN device isolation are included within the scope of protection of this invention. The dielectric windowing process in this embodiment is not limited to ICP dry etching; other processes such as wet etching can also be used for dielectric removal. The photoresist used in this embodiment is not limited to AZ5214; other photoresist types can also be used.

[0129] The process steps for realizing this structure device given in the embodiments of the present invention are not limited to the process steps described in the embodiments, but also include other process steps that can realize this structure. The specific device process in the embodiments of the present invention is not limited to the process described in the embodiments. The present invention may also include other possible process steps, such as forming a thickened passivation layer, a field plate structure, a thickened interconnect electrode, etc.

[0130] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A pn ​​integrated circuit device, characterized in that, include: The nitrogen-polar epitaxial structure includes an n-type heterostructure and a p-type heterostructure. The p-type heterostructure is disposed longitudinally on the n-type heterostructure. The n-type heterostructure contains a two-dimensional electron gas, and the p-type heterostructure contains a two-dimensional hole gas. The two-dimensional hole gas is induced by the negative polarization interface in the nitrogen-polar p-type heterostructure. The first source, the first drain, and the first gate, together with the n-type heterostructure, form an n-FET device; The second source, the second drain, and the second gate, together with the p-type heterostructure, form a p-FET device. The second gate is electrically connected to the first gate, and the second drain is electrically connected to the first drain.

2. The pn integrated circuit device according to claim 1, characterized in that: The n-FET device is a depletion-type device or an enhancement-type device, and the p-FET device is a depletion-type device or an enhancement-type device.

3. The pn integrated circuit device according to claim 1 or 2, characterized in that: The n-type heterostructure includes a first barrier layer, a first channel layer, and a cap layer stacked sequentially along the longitudinal direction. The two-dimensional electron gas is formed at the interface of the first channel layer near the first barrier layer. The first source and the first drain are electrically connected through the two-dimensional electron gas, and the first gate is disposed on the cap layer. Preferably, the material of the first channel layer includes GaN, the material of the first barrier layer includes at least one or a combination of two or more of AlGaN, AlN, AlInN, and AlInGaN, and the material of the cap layer includes at least one or a combination of two or more of AlN, AlGaN, AlInN-based, and AlInGaN.

4. The pn integrated circuit device according to claim 1 or 2, characterized in that: The p-type heterostructure includes a second channel layer and a second barrier layer stacked sequentially along the longitudinal direction. The two-dimensional hole gas is formed at the interface of the second channel layer near the second barrier layer. The second source and the second drain are electrically connected through the two-dimensional hole gas, and the second gate is disposed on the second barrier layer. Preferably, the material of the second channel layer includes GaN, and the material of the second barrier layer includes at least one or a combination of two or more of AlGaN, AlN, AlInN, and AlInGaN.

5. The pn integrated circuit device according to claim 1, characterized in that: The epitaxial structure includes an n-FET device region and a p-FET device region spaced laterally. A portion of the n-type heterostructure is located in the n-FET device region, and another portion is located in the p-FET device region. The p-type heterostructure is completely located in the p-FET device region. Furthermore, an isolation structure is formed within the epitaxial structure, and the isolation structure is distributed around the n-FET device region and the p-FET device region. Preferably, the epitaxial structure further includes a substrate and a buffer layer, the buffer layer is stacked on the substrate, the first barrier layer is stacked on the buffer layer, and the isolation structure extends longitudinally into the buffer layer along the epitaxial structure; Preferably, the substrate includes any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate, or the substrate is a composite substrate formed of two or more of a silicon substrate, sapphire, and silicon carbide. Preferably, the isolation structure is an ion implantation region formed by ion implantation of the epitaxial structure, or the isolation structure is an isolation trench formed by etching away a portion of the epitaxial structure.

6. A method for fabricating a pn integrated circuit device, characterized in that, include: A nitrogen-polar epitaxial structure is fabricated, comprising a first barrier layer, a first channel layer, a cap layer, a second channel layer, and a second barrier layer stacked sequentially along the longitudinal direction. The first barrier layer, the first channel layer, and the cap layer are combined to form an n-type heterostructure. A two-dimensional electron gas is formed at the interface between the first channel layer and the first barrier layer. The second channel layer and the second barrier layer are combined to form a p-type heterostructure. A two-dimensional hole gas is formed at the interface between the second channel layer and the second barrier layer. The two-dimensional hole gas is induced by the negative polarization interface between the second channel layer and the second barrier layer. The epitaxial structure defines an n-FET device region and a p-FET device region, which are arranged laterally spaced. Remove the second channel layer and the second barrier layer located in the n-FET device region; An n-type heterostructure located in the n-FET device region is processed, and a first source, a first drain, and a first gate are fabricated in the n-FET device region. The first source, the first drain, and the first gate are then combined with the epitaxial structure to form an n-FET device. The first source and the first drain are electrically connected to the two-dimensional electron gas, and the first gate is disposed on the cap layer. A p-type heterostructure located in the p-FET device region is processed, and a second source, a second drain, and a second gate are fabricated in the p-FET device region. The second source, the second drain, and the second gate are then combined with the epitaxial structure to form a p-FET device. The second source and the second drain are electrically connected to the two-dimensional hole gas, and the second gate is disposed on the second barrier layer. An isolation structure is formed within the epitaxial structure, and the isolation structure is distributed around the n-FET device region and the p-FET device region. The second gate is electrically connected to the first gate, and the second drain is electrically connected to the first drain.

7. The method for fabricating the pn integrated circuit device according to claim 6, characterized in that: The n-FET device is a depletion-type device or an enhancement-type device, and the p-FET device is a depletion-type device or an enhancement-type device.

8. The method for fabricating the pn integrated circuit device according to claim 6, characterized in that: The material of the first channel layer includes GaN, the material of the first barrier layer includes at least one or a combination of two or more of AlGaN, AlN, AlInN, and AlInGaN, and the material of the cap layer includes at least one or a combination of two or more of AlN, AlGaN, AlInN-based, and AlInGaN.

9. The method for fabricating the pn integrated circuit device according to claim 6, characterized in that: The material of the second channel layer includes GaN, and the material of the second barrier layer includes at least one or a combination of two or more of AlGaN, AlN, AlInN, and AlInGaN.

10. The method for fabricating the pn integrated circuit device according to claim 6, characterized in that: The epitaxial structure further includes a substrate and a buffer layer, wherein the buffer layer is stacked on the substrate and the first barrier layer is stacked on the buffer layer; Preferably, the isolation structure is an ion implantation region formed by ion implantation of the epitaxial structure, or the isolation structure is an isolation trench formed by etching away a portion of the epitaxial structure.

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