Semiconductor device and image sensor

Abstract

This application provides a semiconductor device and an image sensor. The semiconductor device includes a substrate and a device unit. The device unit includes: a first doped region, a second doped region, and an isolation region disposed within the substrate; and a first gate disposed on the substrate. The second doped region is spaced apart from the first doped region, with one end of the second doped region protruding towards the first doped region. The isolation region is located between the first and second doped regions. The first gate is located above the isolation region, and its orthogonal projection onto the substrate surrounds a portion of the first doped region and covers at least a portion of the end of the second doped region protruding towards the first doped region. This semiconductor device is used to improve fabrication yield and performance.

Description

Technical Field

[0001] This application relates to semiconductors, and more particularly to a semiconductor device and an image sensor. Background Technology

[0002] An image sensor is a device that converts light signals into electrical signals. With the continuous development of semiconductor technology, complementary metal-oxide-semiconductor (CMOS) image sensors are widely used in various electronic devices, such as digital cameras, camcorders, tablet computers, and smartphones, due to their advantages of high sensitivity and low power consumption.

[0003] CMOS image sensors integrate image acquisition and signal processing units onto a single chip using CMOS technology. The image acquisition unit includes a photoelectric structure to convert incident photons into electron-hole pairs, thereby generating an electrical signal. The image acquisition unit also includes an anti-corona structure adjacent to the photoelectric structure to transfer or remove excess charge (e.g., electrons) generated in the photoelectric structure before saturation. However, existing image sensors struggle to fully utilize full-well charge and swing amplitude, resulting in poor performance. Summary of the Invention

[0004] This application provides semiconductor devices and image sensors to fully utilize full-well charge and swing amplitude, thereby improving the performance of the image sensor.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, including a substrate and a device unit, wherein the device unit includes: a first doped region, a second doped region, and an isolation region disposed within the substrate, and a first gate disposed on the substrate;

[0006] The second doped region is spaced apart from the first doped region, and one end of the second doped region protrudes toward the first doped region;

[0007] The isolation region is located between the first doped region and the second doped region;

[0008] The first gate is located above the isolation region, and the orthographic projection of the first gate on the substrate surrounds a portion of the first doped region and covers at least a portion of the second doped region protruding toward one end of the first doped region.

[0009] In some possible implementations, the second doped region forms a protruding angle at one end protruding toward the first doped region.

[0010] In some possible implementations, the device unit further includes: a third doped region, a fourth doped region, and a fifth doped region disposed within the substrate, and a second gate disposed on the substrate;

[0011] The third doped region is adjacent to the second doped region;

[0012] The fourth doped region is located on the side of the third doped region away from the second doped region and is adjacent to the third doped region;

[0013] The fifth doped region is located on the side of the fourth doped region away from the third doped region and is spaced apart from the fourth doped region. An isolation region is also provided between the fifth doped region and the fourth doped region.

[0014] The second gate is located above the isolation region between the fourth doped region and the fifth doped region.

[0015] In some possible implementations, the third doped region and the second doped region are an integral structure, and the isolation region surrounds the second doped region, the third doped region and the fourth doped region.

[0016] In some possible implementations, the device unit has at least two;

[0017] The at least two device units are arranged radially, and the first doped regions of the at least two device units are adjacent to form an integral structure, and the first gates of the at least two device units are adjacent to form an integral structure.

[0018] In some possible implementations, the device unit has at least two;

[0019] The at least two device units are arranged radially, and the fifth doped regions of the at least two device units are adjacent to each other to form an integral structure.

[0020] In some possible implementations, there are four device units, each rectangular in shape, and the isolation regions of the four device units are adjacent to form an integral structure.

[0021] In some possible implementations, the vertex of the first doped region is adjacent to the vertex of the protruding angle.

[0022] In some possible implementations, the first gate is offset from the vertex of the first doped region, and the vertex of the protrusion angle is collinear with the vertex of the first doped region.

[0023] In some possible implementations, the first doped region is rectangular, the first gate is L-shaped, and the orthographic projection of the first gate on the substrate surrounds and is adjacent to two adjacent sides of the first doped region, the intersection of the two adjacent sides forming the vertex of the first doped region.

[0024] In some possible implementations, the convex angle is greater than or equal to 30 degrees and less than or equal to 120 degrees.

[0025] In some possible implementations, the distance between the vertex of the protruding angle and the vertex of the first gate away from the first doped region is greater than or equal to 0.3 μm and less than or equal to 1 μm.

[0026] In some possible implementations, the distance between the vertex of the first gate away from the first doped region and the vertex of the first gate facing the first doped region is greater than or equal to 1 μm and less than or equal to 1.3 μm.

[0027] In some possible implementations, the first doped region, the second doped region, the third doped region, the fourth doped region, and the fifth doped region have the same conductivity type, and the conductivity type is opposite to that of the isolation region;

[0028] The doping concentration of the fourth doped region is greater than that of the third doped region and the second doped region.

[0029] In some possible implementations, the device unit further includes a passivation region located at least on the surface of the second doped region, the third doped region, and the fourth doped region between the first gate and the second gate along the thickness direction of the substrate.

[0030] Secondly, embodiments of this application provide an image sensor, including the semiconductor device described above.

[0031] In the semiconductor device and image sensor provided in this application embodiment, a second doped region is spaced apart from a first doped region, with one end of the second doped region protruding towards the first doped region. An isolation region is disposed between the first and second doped regions. A first gate is located above the isolation region, and the orthogonal projection of the first gate onto the substrate surrounds the first doped region and covers at least a portion of the area of ​​the second doped region protruding towards the first doped region. Thus, the first doped region, the second doped region, the isolation region, and the first gate can form an anti-corona transistor to prevent charge overflow. Furthermore, the fact that one end of the second doped region protrudes towards the first doped region, is adjacent to the first doped region, and overlaps with the first gate increases process redundancy, provides greater process flexibility, and improves the yield and performance of the semiconductor device. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0033] Figure 1 A planar layout diagram of a semiconductor device;

[0034] Figure 2 A schematic diagram of the device unit provided in this application;

[0035] Figure 3 A partial enlarged view of the device unit provided in this application;

[0036] Figure 4 This is a layout diagram of the device units provided in this application;

[0037] Figure 5 Another layout diagram of the device units provided in this application;

[0038] Figure 6 for Figure 5 Sectional view at point P.

[0039] Explanation of reference numerals in the attached figures:

[0040] 10 - Device Unit;

[0041] 11 - First doped region;

[0042] 12 - Second doped region;

[0043] 13 - Third doped region;

[0044] 14 - Fourth doped region;

[0045] 15 - Fifth doped region;

[0046] 16 - First gate;

[0047] 17 - Second gate;

[0048] 18-Isolation Zone;

[0049] 19-Protruding angle;

[0050] 20-substrate;

[0051] 21-Passivation region;

[0052] 31-N type lightly doped region;

[0053] 32-Floating drain;

[0054] 33-Anti-nausea structure;

[0055] 34-Gate. Detailed Implementation

[0056] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0057] Figure 1 This is a planar layout diagram of a semiconductor device. For example... Figure 1 As shown, the semiconductor device includes a substrate, and a P-type heavily doped region and an N-type lightly doped region 31 are formed in a direction perpendicular to the substrate. The P-type doped region serves as a photosensitive region. The N-type lightly doped region 31 is slightly smaller than the pixel unit in a direction parallel to the substrate surface, and the doping concentration of the N-type lightly doped region 31 is 1×10⁻⁶. 15 cm -3 Magnitude.

[0058] When the photosensitive region is large, the donors of the lightly doped N-type region 31 participate almost exclusively in the electric field perpendicular to the substrate surface, and the reset speed of the pixel unit is mainly limited by electron diffusion. For example, the reset time of a 40-micrometer pixel unit is approximately 4 microseconds. In the pixel unit, the floating drain 32 is typically placed in the center to improve the reset speed.

[0059] Due to power consumption limitations, the applied voltage is restricted, and the application scenario requires a long linear segment of the response curve, meaning a large potential swing at the floating drain 32. This necessitates reducing the highest voltage within the photosensitive region during reset; for example, it can be reduced to the applied voltage minus the swing and then by approximately 0.3V. To shorten the reset time, a drift electric field is added, pointing from the floating drain 32 towards the center of the photosensitive region. The maximum permissible potential within the photosensitive region far from the floating drain 32 during reset (e.g., near the center of the photosensitive region) will be further reduced.

[0060] like Figure 1 As shown, the semiconductor device also includes an anti-corona structure 33, for example, the anti-corona structure 33 is located at the four corners of the pixel unit, or at the middle of the edge of the pixel unit. The full-well charge of the photosensitive area is the integral of its own capacitance between the highest and lowest potentials. However, the capacitance-voltage curve is not linear, and the capacitance near the lowest potential is larger than the capacitance near the highest potential. The design of the full-well charge and the anti-corona structure 33 are closely related.

[0061] The anti-corona structure 33 typically uses a metal-oxide-semiconductor field-effect transistor (MOSFET) as the electron overflow channel. The anti-corona structure 33 generally suffers from the following problems: the overlap length window between the N-type lightly doped region 31 and the gate 34 of the anti-corona structure 33 is limited. A large overlap length results in significant full-well charge loss, making it difficult for the semiconductor device to meet higher performance requirements. A small overlap length renders the anti-corona structure 33 ineffective, and the anti-corona structure 33 is significantly affected by process alignment, leading to large fluctuations in full-well charge between pixel cells and poor semiconductor device performance.

[0062] In the semiconductor device provided in this application, one end of the second doped region protrudes toward the first doped region, and the orthogonal projection of the first gate onto the substrate covers at least a portion of the area of ​​the second doped region protruding toward the first doped region. This can improve the stacking length of the first gate and the second doped region, increase process redundancy, provide greater process flexibility, and improve the on-chip uniformity and performance of the semiconductor device.

[0063] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0064] See Figures 2 to 6 This application provides an image sensor, which is a CMOS image sensor. The image sensor includes a semiconductor device, which includes a substrate 20 and at least one device unit 10, such as a pixel unit having a photoelectric structure. The pixel unit has a size greater than 20 μm, meaning the pixel unit of the CMOS image sensor is a large pixel. The substrate 20 provides support for the structures within and on it, and the substrate 20 is, for example, a semiconductor substrate. The substrate 20 can be a doped substrate, such as a P-type substrate, to form a photodiode in conjunction with at least a third doped region 13.

[0065] like Figure 2 and Figure 6As shown, the device unit 10 includes a first doped region 11, a second doped region 12, an isolation region 18, and a first gate 16. The first doped region 11, the second doped region 12, and the isolation region 18 are disposed within the substrate 20. The second doped region 12 is spaced apart from the first doped region 11 and one end protrudes toward the first doped region 11. The isolation region 18 is disposed between the first doped region 11 and the second doped region 12. The first gate 16 is disposed on the substrate 20, specifically above the isolation region 18. The orthogonal projection of the first gate 16 onto the substrate 20 surrounds the first doped region 11 and covers at least a portion of the area of ​​the second doped region 12 protruding toward the first doped region 11.

[0066] In this way, the first doped region 11, the second doped region 12, the isolation region 18, and the first gate 16 can form an anti-corona transistor to prevent charge overflow. Specifically, the first doped region 11 forms the drain of the anti-corona transistor, the second doped region 12 forms the source of the anti-corona transistor, the isolation region 18 forms the channel of the anti-corona transistor, and the first gate 16 forms the gate of the anti-corona transistor.

[0067] Continue reading Figure 2 and Figure 6 The first doped region 11 and the second doped region 12 are spaced apart, for example, arranged diagonally along the device unit 10 and spaced apart. An isolation region 18 is disposed between the first doped region 11 and the second doped region 12. For example, the isolation region 18 is adjacent to both the first doped region 11 and the second doped region 12, and the isolation region 18 is used to isolate the first doped region 11 and the second doped region 12.

[0068] In some possible implementations, the first doped region 11 and the second doped region 12 have the same conductivity type, but different conductivity type from the isolation region 18. For example, both the first doped region 11 and the second doped region 12 are N-type, but with different doping concentrations.

[0069] For example, the first doped region 11 is a heavily doped region, and the second doped region 12 is a lightly doped region. The isolation region 18 has a P-type conductivity, for example, the isolation region 18 is a P-type doped region. The first doped region 11, the second doped region 12, and the isolation region 18 are formed, for example, by ion implantation. For example, the first doped region 11 is formed by high-energy, high-dose implantation, the second doped region 12 is formed by high-energy, low-dose implantation, and the isolation region 18 is formed by high-energy, medium-dose implantation.

[0070] In device cells 10 with a diameter greater than 20 μm, the doping concentration of the second doped region 12 is 1 × 10⁻⁶. 15 cm -3 With 5×10 15 cm -3The potential difference between the second doped region 12 and the isolation region 18 is approximately one-tenth of that between the two regions and is essentially constant. The doping concentration of the second doped region 12 is approximately one-tenth of that of the surrounding isolation region 18, which means that the potential difference between the second doped region 12 and the isolation region 18 is mainly determined by the area and shape of the second doped region 12.

[0071] In this way, the second doped region 12 can be regarded as a region with a fixed potential, which is almost unaffected by the number of electrons stored in other structures (such as the third doped region 13), thus improving the linearity of the response curve. The second doped region 12 can also be fully depleted, so its relative barrier height is only affected by its shape, and the barrier height can be easily adjusted to bring the full-well charge to a suitable level.

[0072] like Figure 2 As shown, one end of the second doped region 12 protrudes towards the first doped region 11, and this end of the second doped region 12 can be arc-shaped or angular. For example, the end of the second doped region 12 protruding towards the first doped region 11 forms a protruding arc. Another example is that the end of the second doped region 12 protruding towards the first doped region 11 forms a protruding angle 19, that is, the second doped region 12 has a sharp angle, and the sharp angle is opposite to the first doped region 11.

[0073] In some possible examples, the second doped region 12 is triangular in shape, with one corner of the triangle opposite to the first doped region 11. For example, the second doped region 12 is an isosceles triangle with a convex angle 19 at its apex, which is opposite to the first doped region 11. The shape of the second doped region 12 can be specifically defined by the isolation region 18, for example, by adjusting the shape of the mask used for implantation in the isolation region 18. With this configuration, the semiconductor device in this embodiment does not require an additional mask based on the CMOS image sensor process.

[0074] In some possible examples, the angle of the protrusion angle 19 is greater than or equal to 30 degrees and less than or equal to 120 degrees. The protrusion angle 19 partially overlaps with the first gate 16. The larger the angle of the protrusion angle 19, the greater the full-well charge loss due to the anti-corona transistor setup; the smaller the angle of the protrusion angle 19, the weaker the anti-corona transistor overflow capability. The angle of the protrusion angle 19 ( Figure 3 As shown in Figure A, the temperature range of 30 to 120 degrees can balance anti-dizziness effect and full-well charge.

[0075] In some possible implementations, the vertex of the first doped region 11 is positioned opposite to the vertex of the protrusion angle 19, such that the inner angles of the first doped region 11 and the second doped region 12 are opposite each other, thereby reducing the area occupied by the anti-corona transistor. The end of the first doped region 11 facing the protrusion angle 19 is a sharp angle, and the vertex of this sharp angle forms the vertex of the first doped region 11.

[0076] For example, the first doped region 11 is rectangular, such as a square, with one interior corner of the rectangle opposite the vertex of the protruding corner 19. The vertex of the protruding corner 19 of the second doped region 12 may lie on the extension of the diagonal of the first doped region 11. Furthermore, the angle bisector of the second doped region 12 and the diagonal of the first doped region 11 may be collinear.

[0077] The area of ​​the first doped region 11 is smaller than the area of ​​the second doped region 12. The smaller area of ​​the first doped region 11 can reduce the amount of charge controlled by the first doped region 11 in the channel, reduce the short-channel effect of the anti-corona transistor, improve the uniformity of the full-well charge distribution among the device units 10, and increase the length of the linear segment of the response curve.

[0078] Continue reading Figure 2 and Figure 6 The first gate 16 is specifically located above the isolation region 18. The orthogonal projection of the first gate 16 on the substrate 20 surrounds a portion of the first doped region 11. For example, the orthogonal projection of the first gate 16 on the substrate 20 partially surrounds the first doped region 11 and is located on the side of the first doped region 11 facing the second doped region 12.

[0079] The orthogonal projection of the first gate 16 onto the substrate 20 also covers at least a portion of the area of ​​the second doped region 12 protruding towards the first doped region 11, such that the first gate 16 and the second doped region 12 are partially stacked to ensure the anti-corona effect of the anti-corona transistor. For example, the orthogonal projection of the first gate 16 onto the substrate 20 covers a portion of the isolation region 18, the vertex of the protrusion angle 19 of the second doped region 12, and a portion of the second doped region 12 adjacent to that vertex. The first gate 16 may be a polysilicon gate.

[0080] In this configuration, the first doped region 11 is rectangular, and the first gate 16 is L-shaped. The orthographic projection of the first gate 16 onto the substrate 20 surrounds and is adjacent to two adjacent sides of the first doped region 11, and the intersection of these two sides forms the vertex of the first doped region 11. With this configuration, the shape of the first gate 16 is adapted to the shape of the first doped region 11, allowing the first gate 16 to partially surround the first doped region 11, which facilitates the arrangement of multiple device units 10.

[0081] like Figure 3 As shown, the first side of the first gate 16 surrounds the first doped region 11, and a portion of the second side of the first gate 16 is located on the second doped region 12. The first side of the first gate 16 is the side facing the first doped region 11, as shown. Figure 3 As shown at point D1, the second side of the first gate 16 is the side facing the second doped region 12, as shown... Figure 3 As shown at point D2 in the middle.

[0082] See Figure 2 and Figure 3 The first gate 16 is offset from the vertex of the first doped region 11, and the vertex of the protrusion angle 19 is collinear with the vertex of the first doped region 11. In this way, the electron overflow channel formed by the anti-corona transistor is located near the diagonal of the first gate 16, so as to shorten the length of the first gate 16 and thereby reduce the impact of the anti-corona transistor on the effective photosensitive area.

[0083] Among them, the first gate 16 is away from the vertex of the first doped region 11 ( Figure 3 M (as shown) is located on the second doped region 12, and the first gate 16 faces the vertex of the first doped region 11. Figure 3 The N shown is located on the first doped region 11, for example, coinciding with the vertex of the first doped region 11. The first gate 16 is diagonally opposite to the vertex of the first doped region 11 and the first gate 16 facing the vertex of the first doped region 11.

[0084] See some possible examples. Figure 3 The distance between the vertex of the protrusion angle 19 and the vertex of the first gate 16 that is away from the first doped region 11 is greater than or equal to 0.3 μm and less than or equal to 1 μm. This distance is as follows: Figure 3 As shown in Figure a, the larger the distance, the more full-well charge is lost; the smaller the distance, the weaker the overflow capability and the more sensitive it is to process fluctuations.

[0085] The overlap length of the diagonal between the second doped region 12 and the first gate 16 is between 0.3 μm and 1 μm, for example, 0.7 μm. This allows for increased process redundancy while maintaining anti-corona performance. Numerical simulations show that a deviation of 0.05 μm results in approximately 4% difference in full-well charge. In contrast, numerical simulations of existing anti-corona transistors show that a deviation of 0.025 μm results in approximately 5% difference in full-well charge. Therefore, the anti-corona transistor in this embodiment exhibits reduced process sensitivity and improved on-chip uniformity.

[0086] See Figure 3 The distance between the vertex of the first gate 16 facing away from the first doped region 11 and the vertex of the first gate 16 facing the first doped region 11 is between 0.6 μm and 1.7 μm. More specifically, the distance between the vertex of the first gate 16 facing away from the first doped region 11 and the vertex of the first gate 16 facing the first doped region 11 is greater than or equal to 1 μm and less than or equal to 1.3 μm. Wherein, the distance between the vertex of the first gate 16 facing the first doped region 11 and the vertex of the protrusion angle is greater than 0.3 μm.

[0087] The distance between the vertex of the first gate 16 away from the first doped region 11 and the vertex of the first gate 16 facing the first doped region 11 is as follows: Figure 3As shown in Figure b, the smaller the distance, the more full-well charge is lost, and the more significant the short-channel effect becomes. The more uneven the distribution of full-well charge between device cells 10 within the wafer, and the lower the tolerance for process alignment. The larger the distance, the greater the loss of effective photosensitive area. The distance between the vertex of the first gate 16 facing the second doped region 12 and the vertex of the first gate 16 facing the first doped region 11 is between 1 μm and 1.3 μm, that is, the length of the diagonal direction of the first gate 16 is between 1 μm and 1.3 μm, which can balance full-well charge and effective photosensitive area.

[0088] Continue reading Figures 2 to 6 The device unit 10 also includes a third doped region 13, a fourth doped region 14, a fifth doped region 15, and a second gate 17. The third doped region 13, the fourth doped region 14, and the fifth doped region 15 are located within the substrate 20, and the second gate 17 is located on the substrate 20.

[0089] Specifically, the third doped region 13 is adjacent to the second doped region 12, and the fourth doped region 14 is located on the side of the third doped region 13 away from the second doped region 12 and is adjacent to the third doped region 13. The fifth doped region 15 is located on the side of the fourth doped region 14 away from the third doped region 13 and is spaced apart from the fourth doped region 14. An isolation region 18 is also provided between the fifth doped region 15 and the fourth doped region 14. The second gate 17 is located above the isolation region 18 between the fourth doped region 14 and the fifth doped region 15.

[0090] In this configuration, along a direction away from the first doped region 11, the second doped region 12, the third doped region 13, the fourth doped region 14, and the fifth doped region 15 are sequentially arranged, with the second doped region 12, the third doped region 13, and the fourth doped region 14 being adjacent to each other. An isolation region 18 is provided between the fourth doped region 14 and the fifth doped region 15. Thus, the fourth doped region 14, the fifth doped region 15, the isolation region 18 located between the fourth doped region 14 and the fifth doped region 15, and the second gate 17 form a transmission transistor for transmitting signals.

[0091] In some possible examples, isolation region 18 surrounds the second doped region 12, the third doped region 13, and the fourth doped region 14. For example, isolation region 18 surrounds the second doped region 12, the third doped region 13, and the fourth doped region 14 for a full circumference, that is, isolation region 18 is fitted around the outer periphery of the second doped region 12, the third doped region 13, and the fourth doped region 14 to isolate the doped regions of adjacent device cells 10.

[0092] The second doped region 12 and the third doped region 13 are a single structure, with the same conductivity type and doping concentration. Thus, the second doped region 12 also serves to store electrons, and the second doped region 12 and the third doped region 13 can be fabricated together, for example, by synchronously forming them through ion implantation on the substrate 20 using a mask for the doped region. The second doped region 12 is formed by the combined use of a mask for the isolation region 18 and a mask for the doped region.

[0093] In conventional anti-corona transistors (such as...) Figure 1 As shown, the potential of the source region of the transistor is modulated only by the pixel isolation region below the gate of the transistor, the passivation injection layer on the surface, and the electron storage level of the N-type lightly doped region 31 of the optoelectronic structure 33. The electron storage level modulation by the N-type lightly doped region 31 causes the response curve of the transistor to deteriorate linearly when the signal is large.

[0094] In the aforementioned conventional anti-corona transistor, the overlap between the source region and gate 34 should not be too long. Simulations show that even a 0.2μm overlap can cause a potential difference loss of approximately 0.35V and a full-well charge loss of over 40% during device operation. Furthermore, the N-type lightly doped region 31 and the pixel isolation region of the optoelectronic structure 33 are both formed through high-energy implantation, requiring photoresist of at least 3μm. Alignment deviations can easily exceed 0.13μm. Without the overlap portion, the passivation implantation layer and the pixel isolation region may connect, potentially rendering the anti-corona transistor ineffective or only minimally effective.

[0095] Compared to the conventional anti-corona transistor described above, the second doped region 12 in this embodiment can be divided into a region covered by the first gate 16 and a region not covered by the first gate 16. The potential of the region not covered by the anti-corona transistor gate is an electron barrier valley compared to the isolation region 18, and a higher electron barrier plateau compared to the third doped region 13. Under full depletion, the barrier difference between this region and the isolation region 18 and the third doped region 13 is essentially fixed, largely unaffected by the charge quantity of the third doped region 13, and entirely determined by its shape and size.

[0096] Furthermore, one end of the second doped region 12 is connected to the third doped region 13, and the other end is stacked with the first gate 16. When the third doped region 13 is filled with photogenerated electrons to a certain level, the potential drops to about 0.2 volts higher than the potential of the second doped region 12, and begins to overflow from the second doped region 12 to the drain of the anti-corona transistor (i.e., the first doped region 11).

[0097] Continue reading Figure 2 and Figure 6The first doped region 11, the second doped region 12, the third doped region 13, the fourth doped region 14, and the fifth doped region 15 have the same conductivity type, which is opposite to that of the isolation region 18. The doping concentration of the fourth doped region 14 is greater than that of the third doped region 13 and the second doped region 12. By providing the fourth doped region 14, an electron transfer channel from the third doped region 13 to below the second gate 17 can be provided.

[0098] The fifth doped region 15 is, for example, formed in a triangle, and the second gate 17 is, for example, formed in a trapezoidal shape. The upper base of the second gate 17 is aligned with the long side of the fifth doped region 15, and the lower base of the second gate 17 can be located above the fourth doped region 14. Figure 2 and Figure 6 As shown, the orthogonal projection of the second gate 17 onto the substrate 20 covers a portion of the isolation region 18 between the fourth doped region 14 and the fifth doped region 15, and also covers a portion of the fourth doped region 14. The second gate 17 is, for example, a polysilicon gate, but this embodiment is not limited to it.

[0099] The first doped region 11 and the fifth doped region 15 can be located within the isolation region 18. For example, the first doped region 11 and the fifth doped region 15 are formed by ion implantation onto a portion of the surface of the isolation region 18. The depths of the first doped region 11 and the fifth doped region 15 are both lower than the depth of the isolation region 18. The fourth doped region 14 can be located at one end of the third doped region 13. For example, the fourth doped region 14 is formed by ion implantation onto a portion of the surface of the third doped region 13. The depth of the fourth doped region 14 is lower than the depth of the third doped region 13.

[0100] Device cell 10 also includes a passivation region 21. Along a direction perpendicular to substrate 20, passivation region 21 is located at least on the surface of the second doped region 12, the third doped region 13, and the fourth doped region 14, and may extend to the surface of isolation region 18. By providing passivation region 21, dark current can be reduced. Passivation region 21 is offset from the regions below the first gate 16 and the second gate 17, and is formed by ion implantation onto the surfaces of the second doped region 12, the third doped region 13, and the fourth doped region 14. The depth of passivation region 21 is less than the depth of the fourth doped region 14. The conductivity type of passivation region 21 is different from that of the second doped region 12, the third doped region 13, and the fourth doped region 14.

[0101] In some possible implementations, see [reference] Figure 4The device unit 10 has at least two units; the at least two device units 10 are arranged radially, and the first doped regions 11 of the at least two device units 10 are adjacent to form an integral structure, and the first gate 16 is adjacent to form an integral structure. In this way, multiple device units 10 can share a larger first gate 16 and first doped region 11, which improves the compactness of the device unit arrangement and improves the performance of the device unit 10.

[0102] For example, there are four device cells 10. The device cells 10 are rectangular, and the isolation regions 18 of the four device cells 10 are adjacent to form a single structure. The four device cells 10 are arranged radially, and the first doped regions 11 of the four device cells 10 are adjacent to form a single rectangular structure. The first gates 16 of the four device cells 10 are adjacent to form a single structure in a U-shape. The anti-corona transistors of the four device cells 10 share a common gate and drain.

[0103] In other examples, there are two device cells 10, each rectangular in shape, with their isolation regions 18 adjacent to each other to form a single structure. The two device cells 10 are arranged radially, specifically, adjacent to each other. The first doped regions 11 of the two device cells 10 are adjacent to each other to form a single rectangular structure. The first gates 16 of the two device cells 10 are adjacent to each other to form a single, U-shaped structure, or the first gates 16 of the two device cells 10 are adjacent to each other to form a single, U-shaped structure. The anti-corona transistors of the two device cells 10 share a common gate and drain.

[0104] In other possible implementations, see [reference] Figure 5 The device unit 10 has at least two units; the at least two device units 10 are arranged radially, and the fifth doped regions 15 of the at least two device units 10 are adjacent to each other to form an integral structure. In this way, multiple device units 10 can share a larger fifth doped region 15, which improves the compactness of the arrangement of device units 10 and improves the performance of device units 10.

[0105] For example, there are four device cells 10, each rectangular in shape, with isolation regions 18 of the four device cells 10 adjacent to form a single structure. The four device cells 10 are arranged radially, with fifth doped regions 15 of the four device cells 10 adjacent to form a single rectangular structure. The anti-corona transistors of the four device cells 10 are independent of each other.

[0106] In other examples, there are six device cells 10 arranged in a triangular shape, with the isolation regions 18 of the six device cells 10 adjacent to each other to form a single structure. Four device cells 10 are arranged radially, with the fifth doped regions 15 of the four device cells 10 adjacent to each other to form a single hexagonal structure. The anti-corona transistors of the four device cells 10 are independent of each other.

[0107] The semiconductor device in the embodiments of this application can be formed by the following process:

[0108] See Figure 6 The process involves providing a substrate 20 to form shallow trench isolation (STI); implanting isolation region 18, second doped region 12, and third doped region 13 on the first surface of substrate 20; performing CMOS process well implantation and well annealing; forming a first gate 16 and a second gate 17; implanting a fourth doped region 14 in the third doped region 13; forming sidewalls on the first gate 16 and the second gate 17; implanting passivation region 21 in the portion outside the first gate 16 and the second gate 17; performing CMOS process source / drain implantation and annealing to form a first doped region 11 and a fifth doped region 15; performing CMOS process metallization; thinning the second surface of substrate 20, with the second surface opposite to the first surface along the thickness direction of substrate 20; and performing multilayer dielectric deposition and metal grid processes on the second surface of substrate 20.

[0109] The semiconductor device in this embodiment includes a substrate 20 and a device unit 10. The device unit 10 includes a first doped region 11, a second doped region 12, an isolation region 18, and a first gate 16. The second doped region 12 is spaced apart from the first doped region 11, with one end of the second doped region 12 protruding towards the first doped region 11. The isolation region 18 is disposed between the first doped region 11 and the second doped region 12. The first gate 16 is located above the isolation region 18, and its orthogonal projection onto the substrate 20 surrounds the first doped region 11 and covers at least a portion of the area of ​​the end of the second doped region 12 protruding towards the first doped region 11. Thus, the first doped region 11, the second doped region 12, the isolation region 18, and the first gate 16 can form an anti-corona transistor to prevent charge overflow. Furthermore, the fact that one end of the second doped region 12 protrudes towards the first doped region 11, is adjacent to the first doped region 11, and overlaps with the first gate 16 increases process redundancy, provides greater process flexibility, and improves the yield and performance of the semiconductor device.

[0110] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that, The device includes a substrate and a device unit, wherein the device unit includes: a first doped region, a second doped region, and an isolation region disposed within the substrate, and a first gate disposed on the substrate; The second doped region is spaced apart from the first doped region, and one end of the second doped region protrudes toward the first doped region; The isolation region is located between the first doped region and the second doped region; The first gate is located above the isolation region, and the orthographic projection of the first gate on the substrate surrounds a portion of the first doped region and covers at least a portion of the second doped region protruding toward one end of the first doped region.

2. The semiconductor device according to claim 1, characterized in that, The second doped region protrudes towards the end of the first doped region, forming a protruding angle.

3. The semiconductor device according to claim 1, characterized in that, The device unit further includes: a third doped region, a fourth doped region, and a fifth doped region disposed in the substrate, and a second gate disposed on the substrate; The third doped region is adjacent to the second doped region; The fourth doped region is located on the side of the third doped region away from the second doped region and is adjacent to the third doped region; The fifth doped region is located on the side of the fourth doped region away from the third doped region and is spaced apart from the fourth doped region. An isolation region is also provided between the fifth doped region and the fourth doped region. The second gate is located above the isolation region between the fourth doped region and the fifth doped region.

4. The semiconductor device according to claim 3, characterized in that, The third doped region and the second doped region are an integral structure, and the isolation region surrounds the second doped region, the third doped region and the fourth doped region.

5. The semiconductor device according to claim 3, characterized in that, The device unit has at least two; The at least two device units are arranged radially, and the first doped regions of the at least two device units are adjacent to form an integral structure, and the first gates of the at least two device units are adjacent to form an integral structure.

6. The semiconductor device according to claim 3, characterized in that, The device unit has at least two; The at least two device units are arranged radially, and the fifth doped regions of the at least two device units are adjacent to each other to form an integral structure.

7. The semiconductor device according to claim 5 or 6, characterized in that, The device unit has four units, each unit is rectangular, and the isolation areas of the four device units are adjacent to each other to form an integral structure.

8. The semiconductor device according to any one of claims 2-6, characterized in that, The vertex of the first doped region is adjacent to the vertex of the protruding angle.

9. The semiconductor device according to claim 8, characterized in that, The first gate is collinear with the vertex of the first doped region, the vertex of the protrusion angle, and the vertex of the first doped region.

10. The semiconductor device according to claim 9, characterized in that, The first doped region is rectangular, the first gate is L-shaped, and the orthographic projection of the first gate on the substrate surrounds and is adjacent to two adjacent sides of the first doped region. The intersection of the two adjacent sides forms the vertex of the first doped region.

11. The semiconductor device according to any one of claims 2-6, characterized in that, The angle of the protrusion is greater than or equal to 30 degrees and less than or equal to 120 degrees.

12. The semiconductor device according to any one of claims 1-6, characterized in that, The distance between the vertex of the protruding angle and the vertex of the first gate that is away from the first doped region is greater than or equal to 0.3 μm and less than or equal to 1 μm.

13. The semiconductor device according to any one of claims 1-6, characterized in that, The distance between the vertex of the first gate away from the first doped region and the vertex of the first gate facing the first doped region is greater than or equal to 1 μm and less than or equal to 1.3 μm.

14. The semiconductor device according to any one of claims 3-6, characterized in that, The first doped region, the second doped region, the third doped region, the fourth doped region, and the fifth doped region have the same conductivity type, and the conductivity type is opposite to that of the isolation region; The doping concentration of the fourth doped region is greater than that of the third doped region and the second doped region.

15. The semiconductor device according to any one of claims 3-6, characterized in that, The device unit further includes a passivation region, which is located at least on the surface of the second doped region, the third doped region, and the fourth doped region between the first gate and the second gate along the thickness direction of the substrate.

16. An image sensor, characterized in that, Includes the semiconductor device according to any one of claims 1-15.

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