Method for manufacturing p-type polysilicon layer, method for manufacturing tbc cell, and tbc cell

Abstract

This invention provides a method for preparing a P-type polycrystalline silicon layer, a method for preparing a TBC (Transient Carbon Fiber) cell, and a TBC cell, specifically relating to the field of solar cell fabrication technology. The method for preparing the P-type polycrystalline silicon layer involves first preparing a polycrystalline silicon-amorphous silicon stack on an N-type crystalline silicon substrate with a first tunneling oxide layer on the back side, followed by boron diffusion to obtain a P-type polycrystalline silicon layer and a BSG (Bipolar Solid State Geographic Array) layer. The polycrystalline silicon-amorphous silicon stack includes a first polycrystalline silicon layer, a second polycrystalline silicon layer, a third polycrystalline silicon layer, and an amorphous silicon layer arranged sequentially. The polycrystalline silicon-amorphous silicon stack is prepared using a stepped cooling and boosting LPCVD (Liquid Crystallization-Voltage Continuous Chemical Deposition) process. This structure effectively alleviates the accumulation of interfacial thermal stress caused by thermal expansion mismatch, suppresses wafer warping and localized bonding during post-reaction cooling, significantly reduces the risk of mechanical scratches and fragmentation caused by inter-wafer contact in subsequent material feeding and wafer separation processes, and improves the process consistency and production line yield of the P-type polycrystalline silicon layer structure.

Description

Technical Field

[0001] This invention relates to the field of solar cell fabrication technology, and in particular to a method for fabricating a P-type polycrystalline silicon layer, a method for fabricating a TBC cell, and a TBC cell. Background Technology

[0002] Currently, TBC (Tunneling Oxide Passivated Contact) cells, as a new generation of high-efficiency crystalline silicon photovoltaic devices, generally employ low-pressure chemical vapor deposition (LPCVD) to construct tunneling oxide / polycrystalline silicon structures on both sides of an N-type crystalline silicon substrate. In existing technologies, LPCVD often uses single-layer or simple bilayer amorphous silicon / microcrystalline silicon structures, maintaining isothermal and isobaric conditions during the deposition process to balance deposition rate and film uniformity.

[0003] However, this conventional process suffers from significant thermodynamic mismatch: the coefficient of thermal expansion of the N-type crystalline silicon substrate is approximately 2.6 × 10⁻⁶. -6 / K, while the coefficient of thermal expansion of amorphous silicon thin films is only about 2.0×10. -6 / K, the two differ significantly; during the natural cooling process to room temperature after high-temperature deposition, interfacial thermal stress mismatch leads to micron-level warping or localized bonding of the silicon wafer. Especially in the dual-insertion boat loading and unloading process, warped silicon wafers are prone to abnormal contact and slippage between the back film layer and the boat / guide rail during mechanical clamping, transportation and dicing, causing irreversible physical scratches and edge microcracks, ultimately leading to increased breakage rate and decreased electrical performance yield.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a method for preparing a P-type polycrystalline silicon layer, a method for preparing a TBC cell, and a TBC cell, aiming to solve at least one of the above-mentioned technical problems in the prior art.

[0006] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: A first aspect of the present invention provides a polycrystalline silicon-amorphous silicon stack, comprising a first polycrystalline silicon layer, a second polycrystalline silicon layer, a third polycrystalline silicon layer, and an amorphous silicon layer stacked sequentially.

[0007] The second aspect of the present invention provides a method for preparing a P-type polycrystalline silicon layer, wherein a polycrystalline silicon-amorphous silicon stack is prepared on an N-type crystalline silicon back surface having a first tunneling oxide layer, and then doped to obtain a P-type polycrystalline silicon layer and a BSG layer; wherein the polycrystalline silicon-amorphous silicon stack comprises a first polycrystalline silicon layer, a second polycrystalline silicon layer, a third polycrystalline silicon layer, and an amorphous silicon layer stacked sequentially in a direction away from the N-type crystalline silicon; the polycrystalline silicon-amorphous silicon stack is prepared using a stepped cooling and boosting LPCVD process.

[0008] Furthermore, the stepped cooling and boosting LPCVD process includes: during LPCVD deposition, the deposition temperature is gradually decreased and the deposition pressure is gradually increased in the direction away from N-type crystalline silicon.

[0009] Furthermore, the deposition temperature of the first polycrystalline silicon layer is 630~650℃, and the deposition pressure is 80~120mtorr.

[0010] Preferably, the deposition temperature of the second polycrystalline silicon layer is 610~630℃, and the deposition pressure is 120~250 mtorr.

[0011] Preferably, the deposition temperature of the third polycrystalline silicon layer is 585~610℃, and the deposition pressure is 250~350 mtorr.

[0012] Preferably, the deposition temperature of the amorphous silicon layer is 550~585℃, and the deposition pressure is 350~450 mtorr.

[0013] Furthermore, the thickness of the first polycrystalline silicon layer is 5~10nm.

[0014] Preferably, the deposition time of the first polycrystalline silicon layer is 20~100s.

[0015] Preferably, the thickness of the second polycrystalline silicon layer is 10~20nm.

[0016] Preferably, the deposition time of the second polycrystalline silicon layer is 20~100s.

[0017] Preferably, the thickness of the third polycrystalline silicon layer is 10~20nm.

[0018] Preferably, the deposition time of the third polycrystalline silicon layer is 20~100s.

[0019] Preferably, the thickness of the amorphous silicon layer is 250~350nm.

[0020] Preferably, the deposition time of the amorphous silicon layer is 60~120 min.

[0021] Furthermore, the thickness of the tunneling oxide layer is 1.0~2.5 nm.

[0022] Preferably, the tunneling oxide layer is prepared using LPCVD process, wherein the deposition temperature is 580~650℃ and the deposition time is 20~80min.

[0023] Preferably, the doping includes boron diffusion.

[0024] Preferably, the boron diffusion uses a mixed gas of BCl3, O2, and N2.

[0025] Preferably, the flow rate of the BCl3 is 200~400 sccm.

[0026] Preferably, the flow rate of the O2 is 700~1000 sccm.

[0027] Preferably, the flow rate of N2 is 2500~3000 sccm.

[0028] Preferably, the deposition temperature for boron diffusion is 800~1000℃, and the deposition time is 1~2h.

[0029] Preferably, the sheet resistance of the P-type polycrystalline silicon layer is 100~200Ω / □.

[0030] A third aspect of this invention provides a method for preparing a TBC battery, comprising: S1. Pattern the back side of the N-type crystalline silicon semi-finished product, and then remove the first tunneling oxide layer and the P-type polycrystalline silicon layer in the patterned area. S2. Continue to deposit the second tunneling oxide layer, the N-type polycrystalline silicon layer, and the PSG layer on the back side; then remove the PSG layer outside the patterned area, retain the second tunneling oxide layer and the N-type polycrystalline silicon layer in the N region on the back side, retain the first tunneling oxide layer and the P-type polycrystalline silicon layer in the P region, and finally texturize both sides, prepare passivation layers on both sides, and prepare electrodes on the back side to obtain the TBC battery. The N-type crystalline silicon semi-finished product is an N-type crystalline silicon with a first tunneling oxide layer, a P-type polycrystalline silicon layer and a BSG layer on the back side; the P-type polycrystalline silicon layer is prepared by the preparation method described in the first aspect.

[0031] Furthermore, the specific steps of the patterning are as follows: a picosecond laser is used to form a patterned groove on the BSG layer on the back side.

[0032] Preferably, the depth of the patterned groove is 35~90nm and the width is 400~600μm.

[0033] Preferably, a grooved polishing method is used to remove the first tunneling oxide layer and the P-type polysilicon layer in the patterned area.

[0034] Preferably, after the groove polishing, the depth of the patterned groove is 2~3μm.

[0035] Preferably, the thickness of the second tunneling oxide layer is 1.0~2.5 nm, the deposition temperature is 500~650℃, and the deposition time is 20~80 min.

[0036] Preferably, the thickness of the N-type polycrystalline silicon layer is 100~300nm, the deposition temperature is 500~650℃, and the deposition time is 50~100min.

[0037] Furthermore, a PSG layer is formed by phosphorus diffusion, and the PSG layer has a thickness of 30~80nm.

[0038] Preferably, the phosphorus diffusion uses a mixture of POCl3, O2, and N2 gas.

[0039] Preferably, the flow rate of POCl3 is 1000~2000 sccm.

[0040] Preferably, the flow rate of the O2 is 500~1000 sccm.

[0041] Preferably, the flow rate of N2 is 500~1500 sccm.

[0042] Preferably, the deposition temperature for phosphorus diffusion is 800~1000℃, and the deposition time is 1~3h.

[0043] Preferably, the sheet resistance of the PSG layer is 20~80Ω / □.

[0044] Furthermore, the passivation layer on the front side sequentially includes an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer in the direction away from N-type crystalline silicon.

[0045] Preferably, the passivation layer on the back side comprises, in sequence, an aluminum oxide layer and a silicon oxide layer in the direction away from N-type crystalline silicon.

[0046] The fourth aspect of this invention provides a TBC battery, which is prepared using the preparation method described in the second aspect.

[0047] Compared with the prior art, the present invention has at least the following beneficial effects: The P-type polycrystalline silicon layer provided by this invention constructs a multi-level buffer structure with a continuous transition in thermal expansion coefficient between the silicon substrate and amorphous silicon with a significantly lower thermal expansion coefficient. This structure effectively alleviates the accumulation of interfacial thermal stress caused by thermal expansion mismatch, suppresses the overall warping and local bonding of the silicon wafer during the cooling process after the reaction, significantly reduces the risk of mechanical scratches and fragmentation caused by inter-wafer contact in subsequent material feeding and wafer splitting processes, and improves the process consistency and production line yield of the P-type polycrystalline silicon layer structure.

[0048] The method for preparing a P-type polycrystalline silicon layer provided by this invention involves sequentially depositing three layers of polycrystalline silicon with gradient thermal expansion characteristics and a top amorphous silicon layer on the back side of an N-type crystalline silicon substrate and on top of a first tunneling oxide layer. The preparation is carried out using a stepped cooling and boosting LPCVD process, which gradually decreases the deposition temperature and increases the reaction pressure of each layer. This creates a multi-level buffer structure with a continuously transitioning thermal expansion coefficient between the silicon substrate and the amorphous silicon, which has a significantly lower thermal expansion coefficient. This structure effectively alleviates the accumulation of interfacial thermal stress caused by thermal expansion mismatch, suppresses overall warping and localized adhesion of the silicon wafer during the cooling process after the reaction, and significantly reduces the risk of mechanical scratches and fragmentation caused by inter-wafer contact in subsequent material handling and wafer separation processes. This improves the process consistency and production line yield of the P-type polycrystalline silicon layer structure.

[0049] The TBC battery fabrication method provided by this invention involves the precise removal of the first tunneling oxide layer and P-type polycrystalline silicon layer in the patterned region in step S1, exposing the silicon substrate and creating a clean and controllable interface for the subsequent formation of the N-type doped region. In step S2, while retaining the original structure of the P-region, a second tunneling oxide layer and an N-type polycrystalline silicon layer are redeposited in the N-region, and spatial isolation of the N / P double-sided doped regions is achieved through PSG layer patterning. Finally, a double-sided passivated contact structure with physical isolation, electrical independence, and interface matching is constructed through double-sided texturing and passivation. This process path fully utilizes the excellent morphological stability and interlayer adhesion of the P-type polycrystalline silicon layer prepared in the first step due to thermal stress relief, ensuring the integrity and edge steepness of the back structure during patterning and polishing, and avoiding the risks of interface damage, lateral diffusion, or layer peeling caused by traditional full-back stacking and re-etching, thereby achieving high-fidelity integration of double-sided heterogeneous doped structures.

[0050] The TBC battery provided by this invention benefits from the low residual stress, high interface uniformity, and excellent interlayer bonding force of the P-type polycrystalline silicon layer produced by the stepped cooling and voltage boosting process in the first aspect. The passivated contact in the P-region maintains stable morphology, without warping or microcracks, during high-temperature boron diffusion and subsequent heat treatment, significantly reducing the back recombination rate. At the same time, a high-quality tunneling oxide interface is also formed between the newly deposited N-type polycrystalline silicon layer in the N-region and the silicon substrate. Combined with PSG-assisted phosphorus diffusion, low sheet resistance, high doping activation rate, and dense passivation are achieved. Ultimately, the battery significantly improves the open-circuit voltage and fill factor while maintaining a high short-circuit current, possessing the dual advantages of high photoelectric performance and high manufacturing yield. Attached Figure Description

[0051] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the structure of a P-type polycrystalline silicon layer; Figure 2 This is a schematic diagram of the structure of an N-type crystalline silicon semi-finished product; Figure 3 This is a schematic diagram of the process for preparing a TBC battery.

[0053] Explanation of key component symbols: 100 - N-type crystalline silicon; 200 - First tunneling oxide layer; 320 - First polycrystalline silicon layer; 340 - Second polycrystalline silicon layer; 360 - Third polycrystalline silicon layer; 380 - Amorphous silicon layer; 300 - P-type polycrystalline silicon layer; 400 - BSG layer; 500 - Second tunneling oxide layer; 600 - N-type polycrystalline silicon layer; 700 - PSG layer. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0055] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0056] A first aspect of the present invention provides a polycrystalline silicon-amorphous silicon stack, comprising a first polycrystalline silicon layer, a second polycrystalline silicon layer, a third polycrystalline silicon layer, and an amorphous silicon layer stacked sequentially.

[0057] The P-type polycrystalline silicon layer provided by this invention constructs a multi-level buffer structure with a continuous transition in thermal expansion coefficient between the silicon substrate and amorphous silicon with a significantly lower thermal expansion coefficient. This structure effectively alleviates the accumulation of interfacial thermal stress caused by thermal expansion mismatch, suppresses the overall warping and local bonding of the silicon wafer during the cooling process after the reaction, significantly reduces the risk of mechanical scratches and fragmentation caused by inter-wafer contact in subsequent material feeding and wafer splitting processes, and improves the process consistency and production line yield of the P-type polycrystalline silicon layer structure.

[0058] A second aspect of the present invention provides a method for preparing a P-type polycrystalline silicon layer 300, comprising preparing a polycrystalline silicon-amorphous silicon stack on an N-type crystalline silicon 100 on the back side having a first tunneling oxide layer 200, followed by doping to obtain a P-type polycrystalline silicon layer 300 and a BSG layer 400; wherein the polycrystalline silicon-amorphous silicon stack, as shown in the figure... Figure 1 As shown, in the direction away from N-type crystalline silicon 100, there are a first polycrystalline silicon layer 320, a second polycrystalline silicon layer 340, a third polycrystalline silicon layer 360 and an amorphous silicon layer 380 stacked sequentially; the polycrystalline silicon-amorphous silicon stack is prepared by a stepped cooling and boosting LPCVD process.

[0059] The method for preparing the P-type polycrystalline silicon layer 300 provided by this invention involves sequentially depositing three polycrystalline silicon layers with gradient thermal expansion characteristics and a top amorphous silicon layer 380 on the back side of an N-type crystalline silicon 100 substrate and on top of a first tunneling oxide layer 200. The preparation is carried out using a stepped cooling and boosting LPCVD process, which gradually decreases the deposition temperature and increases the reaction pressure of each layer. This creates a multi-level buffer structure with a continuous transition in thermal expansion coefficient between the silicon substrate and the amorphous silicon with a significantly lower thermal expansion coefficient. This structure effectively alleviates the accumulation of interfacial thermal stress caused by thermal expansion mismatch, suppresses the overall warping and local adhesion of the silicon wafer during the cooling process after the reaction, and significantly reduces the risk of mechanical scratches and fragmentation caused by inter-wafer contact in subsequent blanking and slitting processes. This improves the process consistency and production line yield of the P-type polycrystalline silicon layer 300 structure.

[0060] Furthermore, the stepped cooling and boosting LPCVD process includes: during LPCVD deposition, the deposition temperature is gradually decreased and the deposition pressure is gradually increased in a direction away from N-type crystalline silicon 100.

[0061] Furthermore, the deposition temperature of the first polycrystalline silicon layer 320 is 630~650℃, and the deposition pressure is 80~120mtorr.

[0062] Typically, but not limitingly, the deposition temperature of the first polysilicon layer 320 can be, for example, 630°C, 635°C, 640°C, 645°C, or 650°C, or any value within the range of 630°C to 650°C; the deposition pressure of the first polysilicon layer 320 can be, for example, 80 mtorr, 90 mtorr, 100 mtorr, 110 mtorr, or 120 mtorr, or any value within the range of 80 to 120 mtorr.

[0063] Preferably, the deposition temperature of the second polycrystalline silicon layer 340 is 610~630℃, and the deposition pressure is 120~250 mtorr.

[0064] Typically, but not limitingly, the deposition temperature of the second polysilicon layer 340 can be, for example, 610°C, 615°C, 620°C, 625°C, or 630°C, or any value within the range of 610°C to 630°C; the deposition pressure of the second polysilicon layer 340 can be, for example, 120 mtorr, 150 mtorr, 180 mtorr, 210 mtorr, 240 mtorr, or 250 mtorr, or any value within the range of 120 to 250 mtorr.

[0065] Preferably, the deposition temperature of the third polycrystalline silicon layer 360 is 585~610℃, and the deposition pressure is 250~350 mtorr.

[0066] Typically, but not limitingly, the deposition temperature of the third polysilicon layer 360 can be, for example, 585°C, 590°C, 595°C, 600°C, 605°C, or 610°C, or any value within the range of 585°C to 610°C; the deposition pressure of the third polysilicon layer 360 can be, for example, 250 mtorr, 270 mtorr, 290 mtorr, 310 mtorr, 330 mtorr, or 350 mtorr, or any value within the range of 250 to 350 mtorr.

[0067] Preferably, the deposition temperature of the amorphous silicon layer 380 is 550~585℃, and the deposition pressure is 350~450mtorr.

[0068] Typically, but not limitingly, the deposition temperature of the amorphous silicon layer 380 can be, for example, 550°C, 560°C, 570°C, 580°C, or 585°C, or any value within the range of 550°C to 585°C; the deposition pressure of the amorphous silicon layer 380 can be, for example, 350 mtorr, 370 mtorr, 390 mtorr, 410 mtorr, 430 mtorr, or 450 mtorr, or any value within the range of 350 to 450 mtorr.

[0069] Furthermore, the thickness of the first polycrystalline silicon layer 320 is 5~10nm.

[0070] Typically, but not limitingly, the thickness of the first polysilicon layer 320 can be, for example, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, or any value in the range of 5 to 10 nm.

[0071] Preferably, the deposition time of the first polycrystalline silicon layer 320 is 20~100s.

[0072] Typically, but not limitingly, the deposition time of the first polysilicon layer 320 can be, for example, 20s, 40s, 60s, 80s, or 100s, or any value in the range of 20 to 100s.

[0073] Preferably, the thickness of the second polycrystalline silicon layer 340 is 10~20nm.

[0074] Typically, but not limitingly, the thickness of the second polysilicon layer 340 can be, for example, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm or 20 nm, or any value in the range of 10 to 20 nm.

[0075] Preferably, the deposition time of the second polycrystalline silicon layer 340 is 20~100s.

[0076] Typically, but not limitingly, the deposition time of the second polysilicon layer 340 can be, for example, 20s, 40s, 60s, 80s, or 100s, or any value in the range of 20 to 100s.

[0077] Preferably, the thickness of the third polycrystalline silicon layer 360 is 10~20nm.

[0078] Typically, but not limitingly, the thickness of the third polysilicon layer 360 can be, for example, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm or 20 nm, or any value in the range of 10 to 20 nm.

[0079] Preferably, the deposition time of the third polycrystalline silicon layer 360 is 20~100s.

[0080] Typically, but not limitingly, the deposition time of the third polycrystalline silicon layer 360 can be, for example, 20s, 40s, 60s, 80s or 100s, or any value in the range of 20 to 100s.

[0081] Preferably, the thickness of the amorphous silicon layer 380 is 250~350nm.

[0082] Typically, but not limitingly, the thickness of the amorphous silicon layer 380 can be, for example, 250 nm, 270 nm, 290 nm, 310 nm, 330 nm or 350 nm, or any value in the range of 250 to 350 nm.

[0083] Preferably, the deposition time of the amorphous silicon layer 380 is 60~120 min.

[0084] Typically, but not limitingly, the deposition time of the amorphous silicon layer 380 can be, for example, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, or 120 min, or any value in the range of 60 to 120 min.

[0085] Furthermore, the thickness of the tunneling oxide layer is 1.0~2.5 nm.

[0086] Typically, but not limitingly, the thickness of the tunneling oxide layer can be, for example, 1.0 nm, 1.5 nm, 2.0 nm or 2.5 nm, or any value in the range of 1.0 to 2.5 nm.

[0087] Preferably, the tunneling oxide layer is prepared using LPCVD process, wherein the deposition temperature is 580~650℃ and the deposition time is 20~80min.

[0088] The tunneling oxide layer is prepared using an LPCVD process. Typically, but not limitingly, the deposition temperature can be, for example, 580°C, 590°C, 600°C, 610°C, 620°C, 630°C, 640°C, or 650°C, or any value within the range of 580°C to 650°C. The deposition time can be, for example, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, or 80 min, or any value within the range of 20 to 80 min.

[0089] Preferably, the doping includes boron diffusion.

[0090] Preferably, the boron diffusion uses a mixed gas of BCl3, O2, and N2.

[0091] Preferably, the flow rate of the BCl3 is 200~400 sccm.

[0092] Typically, but not limitingly, the flow rate of the BC13 can be, for example, 200 sccm, 250 sccm, 300 sccm, 350 sccm or 400 sccm, or any value in the range of 200 to 400 sccm.

[0093] Preferably, the flow rate of the O2 is 700~1000 sccm.

[0094] Typically, but not limitingly, the flow rate of O2 can be, for example, 700 sccm, 750 sccm, 800 sccm, 850 sccm, 900 sccm, 950 sccm or 1000 sccm, or any value in the range of 700 to 1000 sccm.

[0095] Preferably, the flow rate of N2 is 2500~3000 sccm.

[0096] Typically, but not limitingly, the flow rate of N2 can be, for example, 2500 sccm, 2600 sccm, 2700 sccm, 2800 sccm, 2900 sccm or 3000 sccm, or any value in the range of 2500 to 3000 sccm.

[0097] Preferably, the deposition temperature for boron diffusion is 800~1000℃, and the deposition time is 1~2h.

[0098] Typically, but not limitingly, the deposition temperature for boron diffusion can be, for example, 800°C, 850°C, 900°C, 950°C, or 1000°C, or any value within the range of 800°C to 1000°C; the deposition time can be, for example, 1h, 1.2h, 1.4h, 1.6h, 1.8h, or 2h, or any value within the range of 1h to 2h.

[0099] Preferably, the sheet resistance of the P-type polycrystalline silicon layer 300 is 100~200Ω / □.

[0100] Typically, but not limitingly, the sheet resistance of the P-type polycrystalline silicon layer 300 can be, for example, 100Ω / □, 120Ω / □, 140Ω / □, 160Ω / □, 180Ω / □, or 200Ω / □, or any value in the range of 100~200Ω / □.

[0101] A third aspect of this invention provides a method for preparing a TBC battery, comprising: S1. In the N-type crystalline silicon semi-finished product (its structural schematic diagram is shown below) Figure 2 The back side of the (shown) is patterned, and then the first tunneling oxide layer 200 and the P-type polysilicon layer 300 of the patterned area are removed. S2. Continue to deposit the second tunneling oxide layer 500, the N-type polycrystalline silicon layer 600, and the PSG layer 700 on the back side; then remove the PSG layer 700 outside the patterned area, retain the second tunneling oxide layer 500 and the N-type polycrystalline silicon layer 600 in the N region on the back side, retain the first tunneling oxide layer 200 and the P-type polycrystalline silicon layer 300 in the P region, and finally perform double-sided texturing, double-sided passivation layer fabrication, and back-side electrode fabrication to obtain the TBC battery. The N-type crystalline silicon semi-finished product is an N-type crystalline silicon with a first tunneling oxide layer 200, a P-type polycrystalline silicon layer 300 and a BSG layer 400 on the back side; the P-type polycrystalline silicon layer 300 is prepared by the preparation method described in the second aspect.

[0102] The TBC battery fabrication method provided by this invention involves the precise removal of the first tunneling oxide layer 200 and the P-type polycrystalline silicon layer 300 in the patterned region in step S1, exposing the silicon substrate and creating a clean and controllable interface for the subsequent formation of the N-type doped region. In step S2, while retaining the original structure of the P-region, a second tunneling oxide layer 500 and an N-type polycrystalline silicon layer 600 are redeposited in the N-region, and spatial isolation of the N / P double-sided doped regions is achieved through patterning of the PSG layer 700. Finally, a double-sided passivated contact structure with physical isolation, electrical independence, and interface matching is constructed through double-sided texturing and passivation. This process path fully utilizes the excellent morphological stability and interlayer adhesion of the P-type polycrystalline silicon layer 300 prepared in the first step due to thermal stress relief, ensuring the integrity and edge steepness of the back structure during patterning and polishing, and avoiding the risks of interface damage, lateral diffusion, or layer peeling caused by traditional full-back stacking and re-etching, thereby achieving high-fidelity integration of double-sided heterogeneous doped structures.

[0103] Furthermore, the specific steps of the patterning are as follows: a picosecond laser is used to form a patterned groove on the BSG layer 400 on the back side.

[0104] Preferably, the depth of the patterned groove is 35~90nm and the width is 400~600μm.

[0105] Typically, but not limitingly, the depth of the patterned groove can be, for example, 35nm, 45nm, 55nm, 65nm, 75nm, 85nm, or 90nm, or any value within the range of 35 to 90nm; the width can be, for example, 400μm, 440μm, 480μm, 520μm, 560μm, or 600μm, or any value within the range of 400 to 600μm.

[0106] Preferably, a grooved polishing method is used to remove the first tunneling oxide layer and the P-type polysilicon layer in the patterned area.

[0107] Preferably, after the groove polishing, the depth of the patterned groove is 2~3μm.

[0108] Typically, but not limitingly, after groove polishing, the depth of the patterned groove can be, for example, 2μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm or 3μm, or any value in the range of 2 to 3μm.

[0109] Preferably, the thickness of the second tunneling oxide layer 500 is 1.0~2.5 nm, the deposition temperature is 500~650℃, and the deposition time is 20~80 min.

[0110] Typically, but not limitingly, the thickness of the second tunneling oxide layer 500 can be, for example, 1.0 nm, 1.5 nm, 2.0 nm, or 2.5 nm, or any value in the range of 1.0 to 2.5 nm; the deposition temperature can be, for example, 500 °C, 530 °C, 560 °C, 590 °C, 620 °C, or 650 °C, or any value in the range of 500 to 650 °C; the deposition time can be, for example, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, or 80 min, or any value in the range of 20 to 80 min.

[0111] Preferably, the thickness of the N-type polycrystalline silicon layer 600 is 100~300nm, the deposition temperature is 500~650℃, and the deposition time is 50~100min.

[0112] Typically, but not limitingly, the thickness of the N-type polycrystalline silicon layer 600 can be, for example, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm, or any value within the range of 100 to 300 nm; the deposition temperature can be, for example, 500 °C, 530 °C, 560 °C, 590 °C, 620 °C, or 650 °C, or any value within the range of 500 to 650 °C; the deposition time can be, for example, 50 min, 60 min, 70 min, 80 min, 90 min, or 100 min, or any value within the range of 50 to 100 min.

[0113] Furthermore, a PSG layer 700 is formed by phosphorus diffusion, the PSG layer 700 having a thickness of 30~80nm.

[0114] The PSG layer 700 is formed by phosphorus diffusion. Typically, but not limitingly, the thickness of the PSG layer 700 can be, for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm or 80 nm, or any value in the range of 30 to 80 nm.

[0115] Preferably, the phosphorus diffusion uses a mixture of POCl3, O2, and N2 gas.

[0116] Preferably, the flow rate of POCl3 is 1000~2000 sccm.

[0117] Typically, but not limitingly, the flow rate of the POCl3 can be, for example, 1000 sccm, 1200 sccm, 1400 sccm, 1600 sccm, 1800 sccm or 2000 sccm, or any value in the range of 1000 to 2000 sccm.

[0118] Preferably, the flow rate of the O2 is 500~1000 sccm.

[0119] Typically, but not limitingly, the flow rate of O2 can be, for example, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm or 1000 sccm, or any value in the range of 500 to 1000 sccm.

[0120] Preferably, the flow rate of N2 is 500~1500 sccm.

[0121] Typically, but not limitingly, the flow rate of N2 can be, for example, 500 sccm, 700 sccm, 900 sccm, 1100 sccm, 1300 sccm or 1500 sccm, or any value in the range of 500 to 1500 sccm.

[0122] Preferably, the deposition temperature for phosphorus diffusion is 800~1000℃, and the deposition time is 1~3h.

[0123] Typically, but not limitingly, the deposition temperature for phosphorus diffusion can be, for example, 800°C, 850°C, 900°C, 950°C, or 1000°C, or any value within the range of 800°C to 1000°C; the deposition time can be, for example, 1h, 1.5h, 2h, 2.5h, or 3h, or any value within the range of 1h to 3h.

[0124] Preferably, the sheet resistance of the PSG layer 700 is 20~80Ω / □.

[0125] Typically, but not limitingly, the sheet resistance of the PSG layer 700 can be, for example, 20Ω / □, 30Ω / □, 40Ω / □, 50Ω / □, 60Ω / □, 70Ω / □, or 80Ω / □, or any value in the range of 20 to 80Ω / □.

[0126] Furthermore, the passivation layer on the front side sequentially includes an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer in the direction away from the N-type crystalline silicon 100.

[0127] Preferably, the passivation layer on the back side comprises, in sequence, an aluminum oxide layer and a silicon oxide layer in a direction away from the N-type crystalline silicon 100.

[0128] The fourth aspect of this invention provides a TBC battery, which is prepared using the preparation method described in the second aspect.

[0129] The TBC battery provided by this invention benefits from the low residual stress, high interface uniformity, and excellent interlayer bonding force of the P-type polycrystalline silicon layer 300 fabricated by the stepped cooling and voltage boosting process in the first aspect. The passivated contact in the P-region maintains stable morphology, without warping or microcracks, during high-temperature boron diffusion and subsequent heat treatment, significantly reducing the back recombination rate. At the same time, a high-quality tunneling oxide interface is also formed between the newly deposited N-type polycrystalline silicon layer 600 in the N-region and the silicon substrate. Combined with PSG-assisted phosphorus diffusion, low sheet resistance, high doping activation rate, and dense passivation are achieved. Ultimately, the battery maintains a high short-circuit current while significantly improving the open-circuit voltage and fill factor, possessing the dual advantages of high photoelectric performance and high manufacturing yield.

[0130] The present invention is further illustrated below with specific embodiments and comparative examples. However, it should be understood that these embodiments are merely for illustrative purposes and should not be construed as limiting the invention in any way. Unless otherwise specified, the raw materials used in the embodiments and comparative examples of the present invention were carried out under conventional conditions or conditions recommended by the manufacturer. Reagents or instruments used, unless otherwise specified, are all commercially available conventional products.

[0131] Example 1 This embodiment provides a method for preparing a TBC battery, such as... Figure 3 As shown, the specific steps are as follows: 1. Select a double-sided polished N-type crystal substrate, and use LPCVD to deposit the first tunneling oxide layer 200 on the back side of the silicon wafer. The tunneling oxide layer is a silicon dioxide layer with a thickness of 1.5 nm, the deposition temperature is 600℃, and the deposition time is 50 min.

[0132] 2. A polycrystalline silicon-amorphous silicon stack is deposited on the surface of the first tunneling oxide layer 200, in the following order from the side closest to the tunneling oxide layer outwards: First polycrystalline silicon layer 320: thickness 8nm, deposition temperature 640℃, deposition time 60s, deposition pressure 100mtorr.

[0133] Second polycrystalline silicon layer 340: thickness 15nm, deposition temperature 620℃, deposition time 60s, deposition pressure 200mtorr.

[0134] The third polycrystalline silicon layer 360: thickness 15nm, deposition temperature 600℃, deposition time 60s, deposition pressure 300mtorr.

[0135] Amorphous silicon layer 380: thickness 300nm, deposition temperature 570℃, deposition time 90min, deposition pressure 400mtorr.

[0136] 3. The silicon wafer is subjected to boron diffusion treatment by introducing a mixed gas of BCl3, O2, and N2. The flow rate of BCl3 is 300 sccm, the flow rate of O2 is 850 sccm, the flow rate of N2 is 2750 sccm, the diffusion temperature is 900℃, and the diffusion time is 1.5h. After diffusion, the sheet resistance of the silicon wafer is 150Ω / □, and a BSG layer of 400 is formed on the surface of the silicon wafer.

[0137] 4. Picosecond laser is used to remove the BSG layer 400 corresponding to the pre-set gap area and N-type area on the back of the silicon wafer, forming a patterned groove with a depth of 60nm and a width of 500μm. A chain-type wet process is used to remove the BSG wrap-around coating on the front of the silicon wafer. A tank-type alkaline polishing process (KOH solution, mass fraction 10%, temperature 80℃) is used to remove the doped wrap-around coating on the front of the silicon wafer, as well as the P-type polysilicon layer 300 and tunneling oxide layer in the patterned groove area on the back. After processing, the depth of the patterned groove increases to 2.5μm.

[0138] 5. A second tunneling oxide layer 500 and an intrinsic polycrystalline silicon layer were sequentially deposited on both sides of the silicon wafer using the LPCVD method. The thickness of the tunneling oxide layer was 1.5 nm, the deposition temperature was 580 °C, and the deposition time was 50 min. The thickness of the intrinsic polycrystalline silicon layer was 200 nm, the deposition temperature was 580 °C, and the deposition time was 75 min.

[0139] 6. A mixed gas of POCl3, O2, and N2 is introduced. The flow rate of POCl3 is 1500 sccm, the flow rate of O2 is 750 sccm, the flow rate of N2 is 1000 sccm, the diffusion temperature is 900℃, the diffusion time is 2h, the sheet resistance of the silicon wafer after diffusion is 50Ω / □, and the PSG layer formed on the surface of the silicon wafer is 700 with a thickness of 50nm.

[0140] 7. Use a picosecond laser to remove the PSG layer 700 in the remaining areas of the back side of the silicon wafer, excluding the preset N-type region, while retaining the PSG layer 700 corresponding to the N-type region. Remove the excess PSG layer 700 by HF acid etching, retaining the N-type doped polysilicon layer and tunnel oxide layer in the N-type region and the P-type doped polysilicon layer and tunnel oxide layer in the P-type region on the back side of the silicon wafer. Use an alkaline texturing process to texture the remaining areas on both sides of the silicon wafer to form a pyramid textured structure.

[0141] 8. First, use the ALD process to deposit an aluminum oxide passivation layer with a thickness of 5nm on both sides of the silicon wafer; then use the PECVD process to deposit a silicon nitride passivation layer with a thickness of 80nm on the back side of the silicon wafer; then use the PECVD process to deposit a silicon nitride passivation layer (70nm thick) and a silicon oxide passivation layer (10nm thick) on the front side of the silicon wafer in sequence.

[0142] 9. Silver electrodes are printed on the P-type and N-type regions on the back of the battery using screen printing technology. After sintering, ohmic contacts are formed to produce a TBC battery.

[0143] Example 2 This embodiment provides a method for preparing a TBC battery, which differs from Embodiment 1 only in the process parameters of step 2, as follows: The parameters for the stepped cooling and boosting polycrystalline silicon-amorphous silicon stack are as follows: First polycrystalline silicon layer 320: thickness 5nm, deposition temperature 630℃, deposition time 100s, deposition pressure 80mtorr.

[0144] Second polycrystalline silicon layer 340: thickness 10nm, deposition temperature 610℃, deposition time 100s, deposition pressure 120mtorr.

[0145] The third polycrystalline silicon layer 360: thickness 10nm, deposition temperature 585℃, deposition time 100s, deposition pressure 250mtorr.

[0146] Amorphous silicon layer 380: thickness 250nm, deposition temperature 550℃, deposition time 120min, deposition pressure 350mtorr.

[0147] The remaining steps and parameters are the same as in Example 1, and a TBC battery is obtained.

[0148] Example 3 This embodiment provides a method for preparing a TBC battery, which differs from Embodiment 1 only in the process parameters of step 2, as follows: The parameters for the stepped cooling and boosting polycrystalline silicon-amorphous silicon stack are as follows: First polycrystalline silicon layer 320: thickness 10nm, deposition temperature 650℃, deposition time 20s, deposition pressure 120mtorr.

[0149] Second polycrystalline silicon layer 340: thickness 20nm, deposition temperature 630℃, deposition time 20s, deposition pressure 250mtorr.

[0150] The third polycrystalline silicon layer 360: thickness 20nm, deposition temperature 610℃, deposition time 20s, deposition pressure 350mtorr.

[0151] Amorphous silicon layer 380: thickness 350nm, deposition temperature 585℃, deposition time 60min, deposition pressure 450mtorr.

[0152] The remaining steps and parameters are the same as in Example 1, and a TBC battery is obtained.

[0153] Comparative Example 1 This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that in step 1, a single-step LPCVD process is used to deposit a polycrystalline silicon layer instead of a stepped cooling and boosting polycrystalline silicon-amorphous silicon stack. The specific parameters are: polycrystalline silicon layer thickness 338 nm, deposition temperature 570 °C, deposition time 90 min, and deposition pressure 400 mtorr. The remaining steps and parameters are the same as in Example 1, and a TBC battery is obtained.

[0154] Comparative Example 2 This comparative example provides a method for preparing a TBC battery, which differs from Example 1 only in the process parameters of step 2, as follows: The parameters for the stepped cooling and boosting polycrystalline silicon-amorphous silicon stack are as follows: First polycrystalline silicon layer 320: thickness 15nm, deposition temperature 600℃, deposition time 60s, deposition pressure 300mtorr.

[0155] Second polycrystalline silicon layer 340: thickness 15nm, deposition temperature 620℃, deposition time 60s, deposition pressure 200mtorr.

[0156] The third polycrystalline silicon layer 360: thickness 8nm, deposition temperature 640℃, deposition time 60s, deposition pressure 100mtorr.

[0157] Amorphous silicon layer 380: thickness 300nm, deposition temperature 650℃, deposition time 90min, deposition pressure 80mtorr.

[0158] The remaining steps and parameters are the same as in Example 1, and a TBC battery is obtained.

[0159] Comparative Example 3 This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that the first polycrystalline silicon layer 320 is removed. All other steps and parameters are the same as in Example 1, and a TBC battery is obtained.

[0160] Comparative Example 4 This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that the second polycrystalline silicon layer 340 is removed. All other steps and parameters are the same as in Example 1, and a TBC battery is obtained.

[0161] Comparative Example 5 This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that the third polycrystalline silicon layer 360 is removed. All other steps and parameters are the same as in Example 1, and a TBC battery is obtained.

[0162] Comparative Example 6 This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that the second polycrystalline silicon layer 340 and the third polycrystalline silicon layer 360 are omitted. All other steps and parameters are the same as in Example 1, and a TBC battery is obtained.

[0163] Test Example 1 The photoelectric performance of the TBC cells prepared in Examples 1-3 and Comparative Examples 1-6 was tested, and the test results are shown in Table 1 below: Table 1. Battery performance test results of each embodiment and comparative example.

[0164] As can be seen from Table 1, Examples 1-3 are significantly better than all comparative examples, especially in terms of conversion efficiency (Eff) and production line yield, which show a systematic advantage. Example 1 ranks first with the highest efficiency of 26.77% and the best yield of 97.65%, followed closely by Examples 2 and 3 in terms of efficiency and yield. The fluctuations of the three are minimal, indicating that the gradient stacked structure has good process consistency.

[0165] All comparative examples showed efficiencies below 26.48%, with yields dropping significantly to 86.52-90.87%. Comparative example 1, with an efficiency of only 26.48% and a yield of 90.87%, directly confirmed that conventional single-layer deposition cannot alleviate thermal stress mismatch. Comparative example 2 had the worst performance, indicating that the directionality of stepped cooling and pressurization is the core technology. The gradual cooling and pressurization must be coordinated to match the decreasing trend of the coefficient of thermal expansion, which cannot be reversed. Comparative examples 3-6 showed a stepwise decrease in efficiency and yield, and the more layers missing, the worse the performance. This confirmed that the thermal expansion gradient buffer chain composed of three polycrystalline silicon layers has an irreplaceable structural integrity requirement, and the removal of a single layer would destroy the stress relief path.

[0166] Example 4 This embodiment provides a method for preparing a TBC battery. The difference from Embodiment 1 is that the thickness of the first polycrystalline silicon layer 320 is 3 nm. The remaining steps are the same as in Embodiment 1 and will not be repeated here.

[0167] Example 5 This embodiment provides a method for preparing a TBC battery. The difference from Embodiment 1 is that the thickness of the first polycrystalline silicon layer 320 is 15 nm. The remaining steps are the same as in Embodiment 1 and will not be repeated here.

[0168] Example 6 This embodiment provides a method for preparing a TBC battery. The difference from Embodiment 1 is that the thickness of the second polycrystalline silicon layer 340 is 8 nm. The remaining steps are the same as in Embodiment 1 and will not be repeated here.

[0169] Example 7 This embodiment provides a method for preparing a TBC battery. The difference from Embodiment 1 is that the thickness of the second polycrystalline silicon layer 340 is 25 nm. The remaining steps are the same as in Embodiment 1 and will not be repeated here.

[0170] Example 8 This embodiment provides a method for preparing a TBC battery. The difference from Embodiment 1 is that the thickness of the third polycrystalline silicon layer 360 is 8 nm. The remaining steps are the same as in Embodiment 1 and will not be repeated here.

[0171] Example 9 This embodiment provides a method for preparing a TBC battery. The difference from Embodiment 1 is that the thickness of the third polycrystalline silicon layer 360 is 25 nm. The remaining steps are the same as in Embodiment 1 and will not be repeated here.

[0172] Example 10 This embodiment provides a method for preparing a TBC battery. The difference from Embodiment 1 is that the thickness of the amorphous silicon layer 380 is 200 nm. The remaining steps are the same as in Embodiment 1 and will not be repeated here.

[0173] Example 11 This embodiment provides a method for preparing a TBC battery. The difference from Embodiment 1 is that the thickness of the amorphous silicon layer 380 is 380 nm. The remaining steps are the same as in Embodiment 1 and will not be repeated here.

[0174] Test Example 2 The photoelectric performance of the TBC cells prepared in Examples 4-11 above was tested, and the test results are shown in Table 2 below: Table 2 Battery performance test results for each embodiment

[0175] As can be seen from Table 2, in Example 4, the first layer was too thin, and the FF dropped to 86.15%. In Example 5, the first layer was too thick, and the Voc dropped to 0.732 V. In Examples 10-11, the yield of the amorphous silicon layer was too thin / too thick, and the yield dropped to 92.63% and 92.32%, respectively.

[0176] When the thickness of the first polycrystalline silicon layer in Example 4 is ≤3 nm or the thickness of the first polycrystalline silicon layer in Example 5 is ≥15 nm, the yield drops by 2 to 3.5 percentage points; when the amorphous silicon layer in Example 10 is less than 250 nm or the thickness in Example 11 is greater than 350 nm, not only does the yield drop below 93%, but the Isc also decreases slightly, indicating that the interface passivation quality or carrier collection ability is impaired.

[0177] This indicates that the thickness of each layer is not only an independent process parameter, but also constitutes a dynamic coupling system in the transmission of thermal stress gradient, the uniformity of boron diffusion, the shape preservation of BSG / PSG patterning, and the stability of subsequent high-temperature treatment. If it is too thin, the buffer is insufficient and it is easy to crack; if it is too thick, the internal stress accumulates and the risk of warping increases.

[0178] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A polycrystalline silicon-amorphous silicon stack, characterized in that, It includes a first polycrystalline silicon layer, a second polycrystalline silicon layer, a third polycrystalline silicon layer and an amorphous silicon layer stacked in sequence.

2. A method for preparing a P-type polycrystalline silicon layer, characterized in that, On an N-type crystalline silicon with a first tunneling oxide layer on the back side, a polycrystalline silicon-amorphous silicon stack as described in claim 1 is further prepared on the back side and then doped to obtain a P-type polycrystalline silicon layer and a BSG layer. The polycrystalline silicon-amorphous silicon stack, arranged in a direction away from N-type crystalline silicon, includes a first polycrystalline silicon layer, a second polycrystalline silicon layer, a third polycrystalline silicon layer, and an amorphous silicon layer stacked sequentially.

3. The preparation method according to claim 2, characterized in that, The polycrystalline silicon-amorphous silicon stack is prepared using a stepped cooling and boosting LPCVD process; Preferably, the stepped cooling and pressurizing LPCVD process includes: During LPCVD deposition, the deposition temperature decreases layer by layer while the deposition pressure increases layer by layer, moving away from N-type crystalline silicon.

4. The preparation method according to claim 2, characterized in that, The deposition temperature of the first polycrystalline silicon layer is 630~650℃; the deposition pressure is 80~120 mtorr. Preferably, the deposition temperature of the second polycrystalline silicon layer is 610~630℃; the deposition pressure is 120~250 mtorr. Preferably, the deposition temperature of the third polycrystalline silicon layer is 585~610℃; the deposition pressure is 250~350 mtorr. Preferably, the deposition temperature of the amorphous silicon layer is 550~585℃; the deposition pressure is 350~450 mtorr. Preferably, the thickness of the first polycrystalline silicon layer is 5~10 nm; Preferably, the deposition time of the first polycrystalline silicon layer is 20~100s; Preferably, the thickness of the second polycrystalline silicon layer is 10~20 nm; Preferably, the deposition time of the second polycrystalline silicon layer is 20~100s; Preferably, the thickness of the third polycrystalline silicon layer is 10~20nm; Preferably, the deposition time of the third polycrystalline silicon layer is 20~100s; Preferably, the thickness of the amorphous silicon layer is 250~350nm; Preferably, the deposition time of the amorphous silicon layer is 60~120 min.

5. The preparation method according to claim 2 or 3, characterized in that, The thickness of the tunneling oxide layer is 1.0~2.5 nm; Preferably, the tunneling oxide layer is prepared using LPCVD process, wherein the deposition temperature is 580~650℃ and the deposition time is 20~80min; Preferably, the doping includes boron diffusion; Preferably, the boron diffusion uses a mixed gas of BCl3, O2, and N2; Preferably, the flow rate of the BCl3 is 200~400 sccm; Preferably, the flow rate of the O2 is 700~1000 sccm; Preferably, the flow rate of N2 is 2500~3000 sccm; Preferably, the deposition temperature for boron diffusion is 800~1000℃; the deposition time is 1~2h. Preferably, the sheet resistance of the P-type polycrystalline silicon layer is 100~200Ω / □.

6. A method for preparing a TBC battery, characterized in that, include: S1. Pattern the back side of the N-type crystalline silicon semi-finished product, and then remove the first tunneling oxide layer and the P-type polycrystalline silicon layer in the patterned area. S2. Continue to deposit the second tunneling oxide layer, the N-type polycrystalline silicon layer, and the PSG layer on the back side; then remove the PSG layer outside the patterned area, retain the second tunneling oxide layer and the N-type polycrystalline silicon layer in the N region on the back side, retain the first tunneling oxide layer and the P-type polycrystalline silicon layer in the P region, and finally texturize both sides, prepare passivation layers on both sides, and prepare electrodes on the back side to obtain the TBC battery. The N-type crystalline silicon semi-finished product is an N-type crystalline silicon with a first tunneling oxide layer, a P-type polycrystalline silicon layer and a BSG layer on the back side; The P-type polycrystalline silicon layer is prepared by the preparation method described in any one of claims 2 to 5.

7. The preparation method according to claim 6, characterized in that, The specific steps of the patterning are as follows: a picosecond laser is used to form a patterned groove on the BSG layer on the back side; Preferably, the depth of the patterned groove is 35~90nm; the width is 400~600μm. Preferably, a grooved polishing method is used to remove the first tunneling oxide layer and the P-type polysilicon layer in the patterned area; Preferably, after the groove polishing, the depth of the patterned groove is 2~3μm; Preferably, the thickness of the second tunneling oxide layer is 1.0~2.5 nm; the deposition temperature is 500~650℃; and the deposition time is 20~80 min. Preferably, the thickness of the N-type polycrystalline silicon layer is 100~300nm; the deposition temperature is 500~650℃; and the deposition time is 50~100min.

8. The preparation method according to claim 6, characterized in that, A PSG layer is formed by phosphorus diffusion; the thickness of the PSG layer is 30~80 nm. Preferably, the phosphorus diffusion uses a mixed gas of POCl3, O2, and N2; Preferably, the flow rate of POCl3 is 1000~2000 sccm; Preferably, the flow rate of the O2 is 500~1000 sccm; Preferably, the flow rate of N2 is 500~1500 sccm; Preferably, the deposition temperature for phosphorus diffusion is 800~1000℃, and the deposition time is 1~3h; Preferably, the sheet resistance of the PSG layer is 20~80Ω / □.

9. The preparation method according to any one of claims 6 to 8, characterized in that, The passivation layer on the front side consists of an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer in sequence, away from the N-type crystalline silicon. Preferably, the passivation layer on the back side comprises, in sequence, an aluminum oxide layer and a silicon oxide layer in the direction away from N-type crystalline silicon.

10. A TBC battery, characterized in that, It is prepared by the preparation method according to any one of claims 6 to 9.

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