Interface engineering method and structure of a high-stability graphene transistor

Abstract

This invention relates to an interface engineering method and structure for high-stability graphene transistors, belonging to the field of two-dimensional material optoelectronic device manufacturing. The method first involves transferring graphene prepared by chemical vapor deposition to an insulating substrate with pre-defined electrodes and etching the channel. Subsequently, vacuum low-temperature annealing is performed in the chamber of a thin-film deposition system to remove impurity molecules adsorbed on the graphene surface. Then, without disrupting the vacuum, metal oxide nanolayers of varying thicknesses are deposited in situ for encapsulation. Through the synergistic effect of "vacuum annealing-encapsulation," the Dirac point of the graphene transistor can be brought back from heavily p-type doped to near zero, achieving its intrinsic characteristic of high carrier mobility at room temperature and pressure. Furthermore, after 60 days of storage in an atmospheric environment, the carrier mobility of graphene treated with "vacuum annealing-in-situ encapsulation" interface engineering decreases by less than 4%. This invention provides effective process guidance for the large-scale fabrication of high-performance, high-stability graphene-based optoelectronic devices.

Description

Technical Field

[0001] This invention belongs to the field of two-dimensional material optoelectronic device manufacturing, and relates to an interface engineering method and structure of a high-stability graphene transistor. Background Technology

[0002] Graphene, as the first discovered two-dimensional material, has become a research focus in condensed matter physics, materials science, and optoelectronics due to its unique electronic structure, ultra-high carrier mobility, and ultrafast carrier relaxation dynamics. Its excellent properties give it an ultra-wide spectral response covering the ultraviolet to terahertz band, demonstrating enormous application potential in high-performance optoelectronic devices. Among existing fabrication techniques, chemical vapor deposition (CVD) is considered the most promising method for achieving large-scale preparation of high-quality graphene.

[0003] However, in practical applications, the performance of graphene transistors often falls far short of theoretical expectations. As a material with a single atomic layer thickness, graphene's electrical properties exhibit extremely high sensitivity to environmental impacts. The main challenges are: Environmental doping and interface defects: Water molecules, oxygen and organic pollutants in the environment are easily adsorbed on the graphene surface, inducing significant p-type doping, causing a severe shift in the Dirac point and a significant deterioration in carrier mobility.

[0004] Insufficient stability: The fabricated devices are prone to performance degradation under environmental conditions, making it difficult to meet the long-term stability requirements of applications.

[0005] Limitations of existing packaging technologies: Although hexagonal boron nitride is an excellent packaging material, its transfer process is complex and prone to introducing dangling bonds and interface impurities, making it unsuitable for large-scale production. While traditional alumina packaging has the potential for large-scale production, systematic process solutions are still lacking for issues such as the impact of deposition thickness on the electrical properties of graphene, interface quality, and how to synergistically eliminate existing dopants.

[0006] Therefore, how to maintain the intrinsic high mobility of graphene under normal temperature and pressure conditions and achieve long-term environmental stability is a key technical bottleneck to promote the transformation of graphene devices from laboratory research to practical applications. Summary of the Invention

[0007] In view of this, the purpose of this invention is to provide an interface engineering method and structure for a high-stability graphene transistor. This invention aims to solve the performance degradation problem of existing graphene transistors caused by interface defect states and environmental doping. Specifically, because graphene is extremely sensitive to the environment, the adsorption of impurities such as water molecules and oxygen can induce severe p-type doping, leading to a significant shift in the Dirac point, a decrease in carrier mobility, and insufficient long-term device stability. Furthermore, existing packaging processes (such as hexagonal boron nitride packaging) have limitations such as process complexity and difficulty in scaling up.

[0008] To achieve the above objectives, the present invention provides the following technical solution: An interface engineering method for highly stable graphene transistors includes the following steps: Step 1: Transfer graphene onto an insulating substrate with a preset electrode pattern, or grow graphene directly on the substrate, and perform channel etching on the graphene using patterning technology to obtain a graphene field-effect transistor. Step 2: Perform low-voltage vacuum annealing on the graphene field-effect transistor to remove adsorbed impurities on the graphene surface; Step 3: Under vacuum or protective atmosphere conditions, a protective layer is deposited in situ on the surface of the heat-treated graphene channel using a thin film deposition process to form an encapsulation structure; wherein, the material of the protective layer is selected from at least one of metal oxides, metal nitrides or two-dimensional layered materials; the thin film deposition process is selected from any one of atomic layer deposition, chemical vapor deposition, physical vapor deposition or magnetron sputtering.

[0009] Furthermore, in step 1, the graphene comprises graphene prepared by low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, high-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, microwave chemical vapor deposition, or mechanical exfoliation; the graphene transfer methods include wet transfer, dry transfer, roll-to-roll transfer, in-situ transfer, and electrochemical bubble transfer.

[0010] Furthermore, the devices formed in step 1 include top-gate devices, bottom-gate devices, dual-gate devices, van der Waals heterojunction devices, Schottky junction devices, and flexible substrate devices.

[0011] Furthermore, in step 2, the temperature of the vacuum heat treatment is 50°C to 1000°C, the time is 10 minutes to 300 minutes, and the vacuum degree is less than 10 Torr.

[0012] Furthermore, in step 3, the protective layer is a dense, continuous thin film with a thickness at the nanometer level.

[0013] Furthermore, in step 3, the precursor is selected based on the type of protective layer material.

[0014] A highly stable graphene transistor structure, comprising: Substrate; including insulating substrate and electrodes; A graphene channel is located on an insulating substrate and electrically connected to the electrode; And a protective layer that covers the surface of the graphene channels.

[0015] The beneficial effects of this invention are as follows: through the synergistic effect of vacuum heat treatment and in-situ deposition of a protective layer, the influence of environmental doping on the electrical properties of graphene surface is effectively eliminated, causing its Dirac point to return to near its intrinsic position. The dense and continuous protective layer provides a long-lasting physicochemical barrier for graphene, significantly improving the long-term stability of the device under environmental conditions. This method has strong process compatibility and is applicable to graphene materials with different crystalline states, showing good prospects for large-scale application.

[0016] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 The diagram shows the structure of the graphene device before and after packaging. Figure 2 The back gate voltage-channel resistance characteristic curves of graphene transistor devices before and after "vacuum annealing-packaging" are shown. Figure 3 The bar chart shows the carrier mobility of graphene devices with different coating thicknesses after "vacuum annealing-encapsulation". Figure 4 The bar chart shows the carrier mobility changes of graphene devices after "vacuum annealing-encapsulation" and those without the treatment over 60 days of storage. Figure 5 This is a bar chart showing the carrier mobility of a polycrystalline graphene device after "vacuum annealing-encapsulation". Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0019] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0020] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0021] Figure 1 To determine whether aluminum oxide is present or absent Al 2 O 3. Schematic diagram of the structure of the graphene field-effect transistor device with encapsulation.

[0022] Example 1: This embodiment uses single-crystal graphene prepared by chemical vapor deposition as an example to illustrate the effectiveness of the present invention in improving the electrical performance of graphene transistors. The specific process is as follows: 1. Graphene film preparation Graphene growth: Chemical vapor deposition was employed. A 46 μm thick, 99.95% pure single-crystal copper foil was placed in the high-temperature zone of a tube furnace and annealed for 30 minutes at 1015 °C in a mixed atmosphere of 500 sccm argon and 100 sccm hydrogen to remove impurities from the copper foil surface. Subsequently, the atmosphere was switched to a mixed atmosphere of 5 sccm methane and 15 sccm hydrogen, and growth was carried out for 30 minutes at 950 °C–1070 °C under conditions below 20 Pa. After completion, the growth was allowed to cool naturally to room temperature.

[0023] Graphene transfer: Graphene is transferred from copper foil to a silicon substrate with pre-prepared electrodes using a 15% (w / w) ammonium persulfate aqueous solution via a wet transfer process.

[0024] 2. Substrate preparation Substrate cleaning: The silicon wafer with a 300nm thick SiO2 layer was cut into 10 mm × 10 mm square substrates, which were then ultrasonically cleaned in plasma aqueous solution, acetone, and anhydrous ethanol in sequence and dried with nitrogen gas.

[0025] Photolithography process: LOR 5A photoresist (heated at 170 °C for 10 minutes) and S1805 photoresist (heated at 100 °C for 10 minutes) were spin-coated sequentially. The electrode pattern was exposed using a binary exposure machine and developed in AZ300 developer.

[0026] Electrode deposition and stripping: A 5 nm thick chromium adhesion layer and a 50 nm thick gold conductive layer were sequentially deposited using a magnetron sputtering system. Subsequently, the electrode was ultrasonically stripped in acetone for 1 minute, followed by immersion in AZ300 developer for 1 minute to remove residual photoresist.

[0027] 3. Construction of graphene field-effect transistors Channel definition: Immerse the transferred sample in acetone for 2 hours to completely remove the PMMA auxiliary transfer layer. Repeat the spin coating, exposure, and development steps described above to form the channel pattern.

[0028] Plasma etching: A plasma etching machine was used for 4 minutes to completely remove the graphene in the unprotected areas. After etching, residual adhesive was removed by acetone treatment for 3 minutes and immersion in AZ300 developer for 1 minute to obtain a complete channel structure.

[0029] 4. "Annealing-Encapsulation" Collaborative Interface Engineering The core steps of this invention are completed in a thin film deposition system. This embodiment takes an atomic layer deposition system as an example: Collaborative environment: The pressure in the reaction chamber is controlled below 1 Torr.

[0030] Vacuum low-temperature annealing: In the ALD chamber, the sample is annealed under vacuum at 100 °C to 300 °C for 45 minutes to promote the desorption of adsorbed water molecules and remove difficult-to-desorb adsorbates.

[0031] In-situ Al2O3 coating: After annealing, the vacuum is not destroyed, and Al2O3 layers of three different thicknesses of 5nm, 10nm and 15nm are directly deposited in-situ.

[0032] 5. Electrical performance testing Transfer characteristic curves were obtained using a semiconductor parameter analyzer. For example... Figure 2 As shown, the uncoated device exhibits significant p-type doping, with the Dirac point located at 60 V; after 10 nm... Al 2 O After coating, the Dirac point returns to near 0 V, and the curve exhibits a clear symmetrical distribution. This indicates that the vacuum annealing and in-situ deposition process used in this invention can effectively eliminate environmental doping and restore the intrinsic electrical properties of graphene.

[0033] The electrical properties of graphene transistors exhibit a dependence on the thickness of the Al2O3 protective layer. Figure 3 It can be seen that the mobility exhibits a non-linear relationship with the coating layer thickness. The performance improvement of graphene is optimal after coating with a 10nm Al₂O₃ protective layer. The Dirac point of single-crystal graphene is located near 0 V. Its average hole mobility is 23798.02 cm⁻¹. 2 / (V·s), average electron mobility is 20122.22 cm⁻¹ 2 / (V·s).

[0034] 6. Stability Verification The 10nm Al2O3-coated device was tested in an environment of 25 °C and 70% relative humidity. Stability metrics: During a 60-day testing period, the carrier mobility of the coated device decreases by less than 4%.

[0035] Control group: Under the same conditions, the mobility of uncoated devices decreased by more than 50% after 60 days.

[0036] 7. Results Analysis The effectiveness of the interface engineering was verified by comparing the transfer characteristic curves before and after the wrapping process. Doping elimination: Uncoated devices exhibit severe p-type doping with a Dirac point at 65 V; after the "vacuum annealing-packaging" process of this invention, the Dirac point returns to near 0 V, exhibiting its intrinsic characteristics.

[0037] Mobility jump: After coating, the hole mobility and electron mobility of single-crystal graphene both reach over 20,000 cm² / (V·s).

[0038] Stability metrics: From Figure 4 It is evident that, within 60 days of storage in a normal environment, the carrier mobility of the "annealed-encapsulated" device decreases by less than 4%, while the untreated device, under the same conditions, experiences a mobility decrease of more than 50% after 60 days. This fully demonstrates that the dense and continuous protective layer formed by this invention can provide a long-lasting and stable physicochemical barrier for graphene.

[0039] Example 2: This embodiment is basically the same as Embodiment 1, except that in step 4, a magnetron sputtering system is used instead of an atomic layer deposition system to deposit the protective layer. After vacuum annealing, without breaking the vacuum, a 10 nm thick alumina layer is directly deposited by magnetron sputtering. Testing showed that the Dirac point of the fabricated graphene transistor is located near 0 V, and after 60 days of storage at room temperature, the carrier mobility decay is less than 5%, demonstrating good environmental stability.

[0040] Example 3: This embodiment is basically the same as Embodiment 1, except that in step 4, the protective layer material is hafnium oxide, prepared by atomic layer deposition at a deposition temperature of 200 °C, and the precursor is tetramethylaminohafnium and water. Testing showed that the Dirac point of the obtained graphene transistor was near 0 V, and the carrier mobility decayed by less than 5% after 60 days of storage at room temperature, thus achieving both environmental doping elimination and improved long-term stability.

[0041] Example 4: This embodiment is basically the same as Embodiment 1, except that the graphene used in step 1 is polycrystalline graphene prepared by CVD. Figure 5 The results show that in the polycrystalline graphene system, the 10nm coating layer also achieved the best mobility improvement effect, confirming that the method of the present invention has good universality and is applicable to graphene materials with different crystal states. Tests showed that the average hole mobility of the 10nm coated graphene transistor was improved by 237.18% and 342.77% compared to the 5nm and 15nm packages, respectively, and the average electron mobility was improved by 237.24% and 313.38% compared to the 5nm and 15nm packages, respectively.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method of interface engineering of high-stability graphene transistors, characterized by: Includes the following steps: Step 1: Transfer graphene onto an insulating substrate with a preset electrode pattern, or grow graphene directly on the substrate, and perform channel etching on the graphene using patterning technology to obtain a graphene field-effect transistor. Step 2: Vacuum anneal the graphene field-effect transistor to remove adsorbed impurities from the graphene surface; Step 3: Under vacuum or protective atmosphere conditions, a protective layer is deposited in situ on the surface of the heat-treated graphene channel using a thin film deposition process to form an encapsulation structure; wherein, the material of the protective layer is selected from at least one of metal oxides, metal nitrides or two-dimensional layered materials; the thin film deposition process is selected from any one of atomic layer deposition, chemical vapor deposition, physical vapor deposition or magnetron sputtering.

2. The interface engineering method of a high-stability graphene transistor according to claim 1, characterized in that: In step 1, the graphene includes graphene prepared by low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, high-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, microwave chemical vapor deposition, or mechanical exfoliation; the graphene transfer methods include wet transfer, dry transfer, roll-to-roll transfer, in-situ transfer, and electrochemical bubble transfer.

3. The interface engineering method of a high-stability graphene transistor according to claim 1, characterized in that: The devices formed in step 1 include top-gate devices, bottom-gate devices, dual-gate devices, van der Waals heterojunction devices, Schottky junction devices, and flexible substrate devices.

4. The interface engineering method of a high-stability graphene transistor according to claim 1, characterized in that: In step 2, the temperature of the vacuum heat treatment is 50°C to 1000°C, the time is 10 minutes to 300 minutes, and the vacuum degree is less than 10 Torr.

5. The interface engineering method of a high-stability graphene transistor according to claim 1, wherein: In step 3, the protective layer is a dense, continuous thin film with a thickness at the nanometer level.

6. The interface engineering method of a high-stability graphene transistor according to claim 1, wherein: In step 3, the precursor is selected based on the type of protective layer material.

7. A highly stable graphene transistor structure, characterized in that: include: Substrate; including insulating substrate and electrodes; A graphene channel is located on an insulating substrate and electrically connected to the electrode; And a protective layer that covers the surface of the graphene channels.

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