Shift register, drive circuit, drive method, and display device

Abstract

A shift register, driving circuit, driving method, and display device are disclosed, relating to the field of display technology. The shift register includes a first control circuit (110) configured to control the potential of a first node (N1) using the input signal (INPUT) and a first power supply voltage (VGH) of a first power supply, and to control the potential of a second node (N2) using the first power supply voltage (VGH) and the second power supply voltage (LVGL1) of a second power supply; and a first output circuit (120) configured to, under the control of the potentials of the first node (N1) and the second node (N2),... Based on the first clock signal (CLK1) at the first clock terminal and the third power supply voltage (VGL) of the third power supply, a first output signal (OUT1) is output; the second output circuit (130) is configured to output a second output signal (OUT2) based on the second clock signal (CLK2) at the second clock terminal and the second power supply voltage (LVGL1) under the control of the potential of the first node (N1) and the potential of the second node (N2); the voltage of the first level of the first clock signal (CLK1) is greater than or equal to the voltage of the first level of the second clock signal (CLK2).

Description

Shift registers, driving circuits, driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, and a display device. Background Technology

[0002] In the pixel circuits of some display products, the gate drive circuit needs to output a scan signal with a relatively high voltage to drive the transistors to turn on and off. However, this forces the transistors in the gate drive circuit to withstand a large voltage surge, which can damage the device.

[0003] Summary of the Invention

[0004] To address the aforementioned problems, this disclosure provides a shift register, a driving circuit, a driving method, and a display device.

[0005] According to a first aspect, this disclosure provides a shift register, comprising: a first control circuit configured to control the potential of a first node using an input signal from an input terminal and a first power supply voltage from a first power supply, and to control the potential of a second node using the first power supply voltage and the second power supply voltage; a first output circuit configured to output a first output signal via a first output terminal based on a first clock signal from a first clock terminal and a third power supply voltage from a third power supply, under the control of the potentials of the first and second nodes; and a second output circuit configured to output a second output signal via a second output terminal based on a second clock signal from a second clock terminal and a second power supply voltage, under the control of the potentials of the first and second nodes; wherein the voltage of a first level of the first clock signal is greater than or equal to the voltage of a first level of the second clock signal.

[0006] According to a second aspect, this disclosure provides a driving circuit including M cascaded shift registers provided in embodiments of this disclosure, where M is an integer greater than 1.

[0007] According to a third aspect, this disclosure provides a display device including a driving circuit as provided in the embodiments of this disclosure.

[0008] According to a fourth aspect, this disclosure provides a driving method applied to a shift register provided in an embodiment of this disclosure, comprising: controlling the potential of a first node using an input signal from an input terminal and a first power supply voltage from a first power supply, and controlling the potential of a second node using the first power supply voltage and the second power supply voltage; outputting a first output signal via a first output terminal based on a first clock signal from a first clock terminal and a third power supply voltage from a third power supply under the control of the potentials of the first and second nodes; and outputting a second output signal via a second output terminal based on a second clock signal from a second clock terminal and a second power supply voltage under the control of the potentials of the first and second nodes; wherein the voltage of a first level of the first clock signal is greater than or equal to the voltage of a first level of the second clock signal. Attached Figure Description

[0009] Figure 1 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure;

[0010] Figure 2 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0011] Figure 3A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0012] Figure 3B is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0013] Figure 4A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0014] Figure 4B is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0015] Figure 5 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0016] Figure 6A is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0017] Figure 6B is a schematic diagram of voltage and current in a shift register according to an embodiment of the present disclosure;

[0018] Figure 6C is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0019] Figure 7A is a schematic diagram of the voltage of a first clock signal according to an embodiment of the present disclosure;

[0020] Figure 7B is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0021] Figure 7C is a schematic diagram of the current in a shift register according to another embodiment of the present disclosure;

[0022] Figure 8 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0023] Figure 9 is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0024] Figure 10 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0025] Figure 11 is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0026] Figure 12 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0027] Figure 13 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0028] Figure 14 is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0029] Figure 15 is a schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure;

[0030] Figure 16 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure; and

[0031] Figure 17 is a flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0034] Furthermore, in the description of the embodiments disclosed herein, the terms "connected" or "connected to" can refer to two components being directly connected, or to two components being connected via one or more other components. Additionally, these two components can be connected or coupled via wired or wireless means.

[0035] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to their function, the gate can be called the control electrode, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode.

[0036] Furthermore, in the description of the embodiments of this disclosure, the terms "first power supply voltage" and "second power supply voltage" are used only to distinguish the different amplitudes of the two power supply voltages. For example, the following description uses "first power supply voltage" as a relatively high voltage and "second power supply voltage," "third power supply voltage," and "fourth power supply voltage" as relatively low voltages. Those skilled in the art will understand that this disclosure is not limited thereto.

[0037] It should be noted that, in the description of the embodiments of this disclosure, INPUT can represent an input signal terminal, an input signal provided by the input terminal, or the level of the input signal. Similarly, the symbol CLK1 can represent a first clock terminal, a first clock signal provided by the first clock terminal, or the level of the first clock signal. OUT1 can represent a first output terminal, a first output signal output by the first output terminal, or the level of the first output signal. VGH and VGL can represent power supply terminals or power supply voltages provided by the power supply terminals. For example, power supply VGH can provide a high-level voltage, and power supply VGL can provide a low-level voltage. The following embodiments are the same and will not be described again.

[0038] Figure 1 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0039] As shown in Figure 1, the shift register 100 includes a first control circuit 110, a first output circuit 120, and a second output circuit 130.

[0040] In this embodiment, the first control circuit 110 is electrically connected to the input terminal INPUT, the first power supply VGH, and the second power supply LVGL1. Under the control of the input signal INPUT from the input terminal INPUT and the first power supply voltage VGH of the first power supply VGH, the first control circuit 110 controls the potential of the first node N1 using the input signal INPUT and the second power supply voltage LVGL1 of the second power supply LVGL1. Under the control of the input signal INPUT and the first power supply voltage VGH, the first control circuit 110 also controls the potential of the second node N2 using the first power supply voltage VGH and the second power supply voltage LVGL1.

[0041] For example, the input signal INPUT can control the connection between the input terminal INPUT and the first node N1. At this time, the first control circuit 110 writes the input signal INPUT into the first node N1. The first power supply voltage VGH can control the connection between the first power supply VGH and the second node N2. At this time, the first control circuit 110 writes the first power supply voltage VGH into the second node N2, pulling up the potential of the second node N2.

[0042] For example, at least one of the input signal INPUT and the potential of the first node N1 can control the connection between the second power supply LVGL1 and the second node N2. In this case, the first control circuit 110 can write the second power supply voltage LVGL1 into the second node N2. The potential of the second node N2 can control the connection between the second power supply LVGL1 and the first node N1. In this case, the first control circuit 110 can write the second power supply voltage LVGL1 into the first node N1, thus pulling down the potential of the first node N1.

[0043] In this embodiment, the first output circuit 120 is electrically connected to the third power supply VGL, the first node N1, the second node N2, the first clock terminal CLK1, and the first output terminal OUT1. Under the control of the potential of the first node N1 and the potential of the second node N2, the first output circuit 120 outputs the first output signal OUT1 via the first output terminal OUT1 based on the first clock signal CLK1 from the first clock terminal CLK1 and the third power supply voltage VGL from the third power supply VGL.

[0044] For example, the potential of the first node N1 can control whether the first clock terminal CLK1 and the first output terminal OUT1 are in a connected or disconnected state. When the first clock terminal CLK1 and the first output terminal OUT1 are in a connected state, the first output circuit 120 provides the first clock signal CLK1 to the first output terminal OUT1, and the first output signal OUT1 output by the first output terminal OUT1 has the same level as the first clock signal CLK1.

[0045] For example, the potential of the second node N2 can control whether the third power supply VGL and the first output terminal OUT1 are in a connected or disconnected state. When the third power supply VGL and the first output terminal OUT1 are in a connected state, the first output circuit 120 provides the third power supply voltage VGL to the first output terminal OUT1, and the first output signal OUT1 output by the first output terminal OUT1 is a low-level signal.

[0046] In this embodiment, the second output circuit 130 is electrically connected to the second power supply LVGL1, the first node N1, the second node N2, the second clock terminal CLK2, and the second output terminal OUT2. Under the control of the potential of the first node N1 and the potential of the second node N2, the second output circuit 130 outputs the second output signal OUT2 via the second output terminal OUT2 based on the second clock signal CLK2 from the second clock terminal CLK2 and the second power supply voltage LVGL1.

[0047] For example, the potential of the first node N1 can control whether the second clock terminal CLK2 and the second output terminal OUT2 are in a connected or disconnected state. When the second clock terminal CLK2 and the second output terminal OUT2 are in a connected state, the second output circuit 130 provides the second clock signal CLK2 to the second output terminal OUT2, and the second output signal OUT2 output by the second output terminal OUT2 has the same level as the second clock signal CLK2.

[0048] For example, the potential of the second node N2 can control whether the second power supply LVGL1 and the second output terminal OUT2 are in a connected or disconnected state. When the second power supply LVGL1 and the second output terminal OUT2 are in a connected state, the second output circuit 130 provides the second power supply voltage LVGL1 to the second output terminal OUT2, and the second output signal OUT2 output by the second output terminal OUT2 is a low-level signal.

[0049] In this embodiment of the disclosure, the first input signal OUT1 can be a scan signal used to control the on and off states of the transistors in the pixel circuit. For example, when the level of the first input signal OUT1 is low, the P-type transistor is turned on and the N-type transistor is turned off. When the level of the first input signal OUT1 is high, the P-type transistor is turned off and the N-type transistor is turned on.

[0050] In this embodiment of the disclosure, a plurality of cascaded shift registers 100 can drive a plurality of pixel rows in a pixel array. For example, the second output signal OUT2 output by the previous stage shift register in the plurality of cascaded shift registers 100 can be the input signal INPUT received by the next stage shift register.

[0051] In this embodiment of the disclosure, the voltage of the first level of the first clock signal CLK1 is greater than or equal to the voltage of the first level of the second clock signal CLK2. For example, the first level is a high level. The high level voltage of the first output signal OUT1 is the same as the high level voltage of the first clock signal CLK1. The high level voltage of the second output signal OUT2 is the same as the high level voltage of the second clock signal CLK2.

[0052] In this embodiment of the disclosure, the high-level voltage of the first output signal OUT1 can be controlled by controlling the high-level voltage of the first clock signal CLK1. Therefore, by controlling the first clock signal CLK1 to have a higher high-level voltage, it can be ensured that the high level of the first output signal OUT1 drives the transistors of the pixel circuit to be fully turned on or completely turned off, thereby improving the driving effect of the pixel circuit.

[0053] In this embodiment, the high-level voltage of the second output signal OUT2 can be controlled by controlling the high-level voltage of the second clock signal CLK2. Therefore, the high-level voltage of the input signal INPUT of the next-stage shift register can be controlled by controlling the high-level voltage of the input signal INPUT. The high level of the input signal INPUT can pull up the potential of the first node N1, so the voltage across the first control circuit 110 can be controlled by controlling the high-level voltage of the input signal INPUT.

[0054] When the voltage difference between the high-level voltage of the second clock signal CLK2 and the second power supply voltage LVGL1 is low, it can be ensured that the voltage difference between the high and low voltages applied to the first control circuit 110 is small, thereby ensuring that the source-drain voltage difference of the transistor in the first control circuit 110 is also small. When the transistor in the first control circuit 110 is turned on, it can be ensured that the current flowing through the transistor is small, avoiding damage to the device.

[0055] In this embodiment, the high-level voltage of the first clock signal CLK1 can be greater than the high-level voltage of the second clock signal CKL2. The first output signal OUT1, with a relatively high high-level voltage based on the first clock signal CKL1, can meet the driving requirements of the pixel circuit. The second output signal OUT2, with a relatively low high-level voltage based on the second clock signal CKL2, can protect the transistors in the first control circuit 110, thereby meeting the driving requirements of the cascaded multiple shift registers.

[0056] In this embodiment, the high-level voltage of the first clock signal CLK1 can be equal to the high-level voltage of the second clock signal CKL2, ensuring that a first output signal OUT1 with a relatively high high-level voltage can be output based on the first clock signal CKL1 to meet the driving requirements of the pixel circuit. In this case, a higher power supply voltage relative to the second power supply voltage LVGL1 can be provided to the shift register, thereby increasing the low voltage supplied to the first control circuit 110 and reducing the voltage drop across the first control circuit 110.

[0057] The shift register provided in this disclosure can output two output signals with different high-level voltages by setting two clock signals with different high-level voltages. This allows the two output signals to respectively meet the driving requirements of the pixel circuit and the requirements of the shift register. The first output signal OUT1 is output using the first clock signal CLK1 with a higher high-level voltage, enabling the complete on / off switching of the transistors in the pixel circuit. The second output signal OUT2 is output using the second clock signal CLK2 with a lower high-level voltage, protecting the transistors in the shift register and preventing excessive heat from burning them out.

[0058] Figure 2 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0059] As shown in Figure 2, the shift register 200 includes a first control circuit 210, a first output circuit 220, a second output circuit 230, and a second control circuit 240. The first control circuit 210, the first output circuit 220, and the second output circuit 230 can be referred to in the preceding description of the first control circuit 110, the first output circuit 120, and the second output circuit 130. For the sake of simplicity, similar parts will not be described again.

[0060] In this embodiment of the disclosure, the second control circuit 240 is electrically connected to the second power supply LVGL1, the fourth power supply LVGL2, the first node N1, and the second node N2. The second control circuit 240 is also electrically connected to the third node N3, along with the first control circuit 210 and the second output circuit 230.

[0061] In this embodiment of the present disclosure, under the control of the potential of the first node N1, the second control circuit 240 controls the potential of the third node N3 using the fourth power supply voltage LVGL2 of the fourth power supply LVGL2. Under the control of the potential of the second node N2, the second control circuit 240 also controls the potential of the third node N3 using the second power supply voltage LVGL1.

[0062] For example, the potential of the first node N1 can control the connection between the fourth power supply LVGL2 and the third node N3, at which time the second control circuit 240 writes the fourth power supply voltage LVGL2 into the third node N3. The potential of the second node N2 can control the connection between the second power supply voltage LVGL1 and the third node N3, at which time the second control circuit 240 writes the second power supply voltage LVGL1 into the third node N3.

[0063] In this embodiment, the fourth power supply voltage LVGL2 is greater than or equal to the second power supply voltage LVGL1. The voltage of the first level of the first clock signal is greater than both the second and fourth power supply voltages, and the voltage of the first level of the second clock signal is also greater than both the second and fourth power supply voltages. For example, the first level is a high level. The high level voltage of the second output signal OUT2 is the same as the high level voltage of the second clock signal CLK2. The low level voltage of the second output signal OUT2 is the same as the fourth power supply voltage LVGL2.

[0064] In this embodiment of the disclosure, by controlling the low-voltage power supply electrically connected to the second output circuit 230 and the first control circuit 210, the low-level voltage of the second output signal OUT2 and the voltage across the first control circuit 210 can be controlled.

[0065] In this embodiment, when the voltage difference between the high-level voltage of the second clock signal CLK2 and the fourth power supply voltage LVGL2 is small, it can be ensured that the voltage difference between the high and low voltages applied to the first control circuit 210 is small, thereby ensuring that the source-drain voltage difference of the transistor in the first control circuit 210 is also small. When the transistor in the first control circuit 210 is turned on, it can be ensured that the current flowing through the transistor is small, avoiding damage to the transistor.

[0066] In this embodiment, the high-level voltage of the first clock signal CLK1 can be equal to the high-level voltage of the second clock signal CLK2, and the fourth power supply voltage LVGL2 is greater than the second power supply voltage LVGL1. For example, based on the first clock signal CLK1, the first output circuit 220 can output a first output signal OUT with a higher high-level voltage that satisfies the pixel circuit requirements. At the same time, based on the second clock signal CLK2, the second output circuit 230 also outputs a second input signal OUT2 with a higher high-level voltage. By using the fourth power supply voltage LVGL2 and the second clock signal CLK2 to output the second output signal OUT2, the low-level voltage of the second output signal OUT2 can be increased by controlling the voltage value of the fourth power supply voltage LVGL2, thereby keeping the voltage difference between the high and low levels of the second output signal OUT2 in a small state.

[0067] Since the fourth power supply voltage LVGL2 is greater than the second power supply voltage LVGL1, the low-level voltage of the second output signal OUT2 output by the second output circuit 230 based on the fourth power supply voltage LVGL2 is greater than the low-level voltage of the second output signal OUT2 output based on the second power supply voltage LVGL1. While keeping the high-level voltage of the second output signal OUT2 constant, increasing the low-level voltage can reduce the voltage difference between the high and low levels of the second output signal OUT2, thereby reducing the voltage difference between the high and low voltages applied to the first control circuit 210.

[0068] In this embodiment of the disclosure, the high-level voltage of the first clock signal CLK1 can be greater than the high-level voltage of the second clock signal CLK2, and the fourth power supply voltage LVGL2 is greater than the second power supply voltage LVGL1. For example, based on the first clock signal CLK1, the first output circuit 220 can output a first output signal OUT with a higher high-level voltage that satisfies the pixel circuit requirements. At this time, based on the second clock signal CLK2, the second output circuit 230 can output a second input signal OUT2 with a lower high-level voltage.

[0069] Based on the fourth power supply voltage LVGL2 and the second clock signal CKL2, the second output signal OUT2 is output. The second output circuit 230 can output a second input signal OUT2 with a lower high-level voltage and a higher low-level voltage. By reducing the high-level voltage of the second output signal OUT2 and increasing the low-level voltage of the second output signal OUT2, the voltage difference between the high and low levels of the second output signal OUT2 is controlled to be small.

[0070] In this embodiment of the disclosure, when the high-level voltage of the first clock signal CLK1 is greater than the high-level voltage of the second clock signal CLK2, the fourth power supply voltage LVGL2 can also be equal to the second power supply voltage LVGL1. Based on the fourth power supply voltage LVGL2 and the second clock signal CLK2, the second output signal OUT2 output by the second output circuit 230 can have a higher high-level voltage and a higher low-level voltage, thereby controlling the voltage difference between the high and low levels of the second output signal OUT2 to be small by reducing the high-level voltage of the second output signal OUT2.

[0071] In this embodiment of the present disclosure, when the high-level voltage of the first clock signal CLK1 is equal to the high-level voltage of the second clock signal CLK2, and the first clock signal CLK1 has a higher high-level voltage, the first control circuit 210 and the second output circuit 220 can be electrically connected to the first clock terminal CLK1. In this case, the first output circuit 210 and the second output circuit 220 each output a first output signal OUT1 and a second output signal OUT2 based on the first clock signal CLK1. When the fourth power supply voltage LVGL2 is equal to the second power supply voltage LVGL1, and the second power supply voltage LVGL1 is lower, the first control circuit 210 and the second output circuit 220 can be electrically connected to the second power supply voltage LVGL1. In this case, the second output circuit 220 outputs a second output signal OUT2 based on the second power supply voltage LVGL1.

[0072] In this embodiment of the disclosure, when the voltage difference between the high and low levels of the second output signal OUT2 is small, it can be ensured that the voltage difference between the high and low voltages applied to the first control circuit 210 is also small. When the transistor in the first control circuit 210 is turned on, it can be ensured that the current flowing through the transistor is small, thus avoiding damage to the transistor.

[0073] In some embodiments, the first control circuit 210 controls the potential of the first node N1 using the input signal INPUT and the fourth power supply voltage LVGL2, and the first control circuit 210 controls the potential of the second node N2 using the first power supply voltage VGH and the fourth power supply voltage LVGL2. Under the control of the potentials of the first node N1 and the second node N2, the second output circuit 230 outputs a second output signal OUT2 via the second output terminal OUT2 based on the second clock signal CLK2 and the fourth power supply voltage LVGL2.

[0074] In this embodiment, during the output of the second output signal OUT2 by the second output circuit 230, the second control circuit 240, under the potential control of the first node N1, writes the fourth power supply voltage LVGL2 into the third node N3. At this time, the potential of the third node N3 is pulled down to the fourth power supply voltage LVGL2. The potential of the first node N1 is controlled using the potential of the third node N3 and the input signal INPUT, and the potential of the second node N2 is controlled using the first power supply voltage VGH and the potential of the third node N3. In this case, under the control of the potentials of the first node N1 and the second node N2, the second output circuit 230 outputs the second output signal OUT2 via the second output terminal OUT2 based on the second clock signal CLK2 and the potential of the third node N2.

[0075] In this embodiment, after the second output terminal OUT2 outputs the second output signal OUT2, the second output terminal OUT2 can be reset using the second power supply voltage LVGL1, thereby pulling down the potential of the second output terminal OUT2. Under the control of the potential of the second node N2, the second control circuit 240 writes the second power supply voltage LVGL1 into the third node N3, at which time the potential of the third node N3 is pulled down to the second power supply voltage LVGL1. The first control circuit 210 and the second output circuit 230 pull down the potential of the second output terminal OUT2 based on the potential of the third node N3.

[0076] In this embodiment, since the fourth power supply voltage LVGL2 is greater than the second power supply voltage LVGL1, the second output signal OUT2 output using the fourth power supply voltage LVGL2 can meet the voltage requirements of the next-stage shift register. By using the second power supply voltage LVGL1 to pull down the potential of the second output terminal OUT2, the potential of the second output terminal OUT2 can be reduced and reset as much as possible, and the operating stability of the circuit can be improved.

[0077] Figure 3A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0078] As shown in Figure 3A, the shift register 300a includes a first control circuit 310, a first output circuit 320, and a second output circuit 330.

[0079] In this embodiment of the disclosure, the first control circuit 310, the first output circuit 320 and the second output circuit 330 can refer to the first control circuit 110, the first output circuit 120 and the second output circuit 130 described above. For the sake of brevity, similar parts will not be described again.

[0080] In this embodiment, the first control circuit 310 is also electrically connected to the reset terminal RST. Under the control of the reset signal RST from the reset terminal RST, the potential of the first node N1 is controlled by the second power supply voltage LVGL1.

[0081] For example, the reset signal RST can control the second power supply LVGL1 to be in a connected state with the first node N1. At this time, the first control circuit 310 writes the second power supply voltage LVGL1 into the first node N1, pulls down the potential of the first node N1, and realizes the potential reset of the first node N1.

[0082] In this embodiment, under the control of the low level of the first node N1, the first output circuit 320 controls the first clock terminal CLK1 and the first output terminal OUT1 to be in a disconnected state. At this time, the potential of the second node N2 can control the first output terminal OUT to be in a connected state with the third power supply VGL, and the first output signal OUT1 output by the first output terminal OUT1 is a continuous low-level signal, thereby pausing the scanning of the pixel circuit.

[0083] In this embodiment, the first output circuit 320 is also electrically connected to the reset terminal RST. Under the control of the reset signal RST, the first output circuit 320 uses the third power supply voltage VGL to control the potential of the first output terminal OUT1.

[0084] For example, the reset signal RST can control the connection between the third power supply VGL and the first output terminal OUT1. At this time, the first output circuit 320 writes the third power supply voltage VGL into the first output terminal OUT1, pulls down the potential of the first output terminal OUT1, and realizes the potential reset of the first output terminal OUT1.

[0085] In this embodiment, when the potential of the second node N2 cannot control the first output terminal OUT to be fully connected with the third power supply VGL, the first output circuit 320 cannot fully pull down the potential of the first output terminal OUT1 using the third power supply voltage VGL. The reset signal RST can be used to control the third power supply VGL to be fully connected with the first output terminal OUT1, thereby allowing the first output circuit 320 to fully pull down the potential of the first output terminal OUT1 using the third power supply voltage VGL.

[0086] In this embodiment, under the control of the low level of the first node N1, the second output circuit 330 controls the second clock terminal CLK2 and the second output terminal OUT2 to be in a disconnected state. At this time, the second output signal OUT2 output by the second output terminal OUT2 is also a continuous low level signal, so the second output signal OUT2 cannot be written to the next stage shift register.

[0087] In this embodiment of the disclosure, after resetting the potential of the first node N1 and the potential of the first output terminal OUT1, the shift register 300a can output the first output signal OUT1 and the second output signal OUT2 for the next frame.

[0088] Figure 3B is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0089] As shown in Figure 3B, the shift register 300b includes a first control circuit 310, a first output circuit 320, a second output circuit 330, and a second control circuit 340. The first control circuit 310, the first output circuit 320, the second output circuit 330, and the second control circuit 340 can be referenced to the first control circuit 210, the first output circuit 220, the second output circuit 230, and the second control circuit 240 described above. For simplicity, similar parts will not be repeated.

[0090] In this embodiment of the disclosure, the first control circuit 310 is also electrically connected to the reset terminal RST. Under the control of the reset signal RST from the reset terminal RST, the potential of the first node N1 is controlled by the potential of the third node N3.

[0091] For example, the reset signal RST can control the third node N3 to be in a connected state with the first node N1. At this time, the first control circuit 310 writes the third node N3 into the first node N1, pulls down the potential of the first node N1, and realizes the potential reset of the first node N1.

[0092] In this embodiment, under the control of the low level of the first node N1, the first output circuit 320 controls the first clock terminal CLK1 to be in a disconnected state with the first output terminal OUT1. At this time, the high potential of the second node N2 can control the second power supply LVGL1 to be in a connected state with the third node N3, and the third node N3 is written with the second power supply voltage LVGL1. The potential of the third node N3 can be used to pull down the potential of the first node N1. At this time, the high potential of the second node N2 can also control the third node N3 to be in a connected state with the second output terminal OUT2, and the second output circuit 430 writes the potential of the third node N3 to the second output terminal OUT2, thereby using the second power supply voltage LVGL1 to pull down the potential of the second output terminal OUT2.

[0093] Since the second power supply voltage LVGL1 is less than the fourth power supply voltage LVGL2, the second power supply voltage LVGL1 can be used to completely pull down the potential of the first node N1 and the potential of the second output terminal OUT2.

[0094] Figure 4A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0095] As shown in Figure 4A, the shift register 400a includes a first control circuit 410, a first output circuit 420, a second output circuit 430, and a third output circuit 450.

[0096] In the embodiments disclosed herein, the first control circuit 410, the first output circuit 420, and the second output circuit 430 can refer to the first control circuit 110, the first output circuit 120, and the second output circuit 130. For the sake of brevity, similar parts will not be described again.

[0097] In this embodiment of the disclosure, the third output circuit 450 is electrically connected to the third clock terminal CLK3, the third power supply VGL, and the first output terminal OUT1.

[0098] In this embodiment of the disclosure, under the control of the potential of the first node N1 and the potential of the second node N2, the first output circuit 420 controls the potential of the first output terminal OUT1 using the first clock signal CLK1 and the third power supply voltage VGL. Under the control of the potential of the first output terminal OUT1, the third output circuit 450 controls the potential of the first output terminal OUT1 based on the third power supply voltage VGL and the third clock signal CLK3 from the third clock terminal CLK3, and outputs the first output signal OUT1 via the first output terminal OUT1.

[0099] For example, the potential of the first node N1 can control whether the first clock terminal CLK1 and the first output terminal OUT1 are in a connected or disconnected state. When the first clock terminal CLK1 and the first output terminal OUT1 are in a connected state, the first output circuit 420 provides the first clock signal CLK1 to the first output terminal OUT1.

[0100] Under the control of the potential of the first output terminal OUT1, the potential of the first output terminal OUT1 is pulled up by the third clock signal CLK3 and the third power supply voltage VGL, so that the high level potential of the first output signal OUT1 output by the first output terminal OUT1 is increased.

[0101] In this embodiment of the disclosure, the first clock signal CLK1 may have a low high-level voltage. After the first clock signal CLK1 is provided to the first output terminal OUT1, the high level of the first output signal OUT1 output from the first output terminal OUT1 is increased by the third clock signal CLK3 and the third power supply voltage VGL, so that the first output signal OUT1 has a high high-level voltage.

[0102] In this embodiment of the disclosure, the first clock signal CLK1 and the second clock signal CLK2 can both have a low high-level voltage, which allows the second output signal OUT2 to have a low high-level voltage and the first output signal OUT1 to have a high high-level voltage.

[0103] In this embodiment of the disclosure, when the high-level voltage of the first clock signal CLK1 is equal to the high-level voltage of the second clock signal CLK2, and the second clock signal CLK2 has a lower high-level voltage, the first control circuit 410, the first output circuit 420, and the second output circuit 430 can be electrically connected to the second clock terminal CLK2. At this time, the first output circuit 410 and the third output circuit 450 output a first output signal OUT1 with a higher high-level voltage based on the second clock signal CLK2 and the third clock signal CLK3. The second output circuit 430 outputs a second output signal OUT2 with a lower high-level voltage based on the second clock signal CLK2.

[0104] In the shift register provided in this disclosure, a first output signal OUT1 and a second output signal OUT2 are output using a clock signal with a relatively low high-level voltage. A third clock signal CLK3 amplifies the high-level voltage of the first output signal OUT1, resulting in a higher high-level voltage for the first output signal OUT1 supplied to the pixel circuit. This allows the first output signal OUT1 to completely turn on and off the transistors in the pixel circuit, while the second output signal OUT2 protects the transistors in the shift register, preventing excessive heat from burning them out due to the current flowing through them.

[0105] Figure 4B is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0106] As shown in Figure 4B, the shift register 400b includes a first control circuit 410, a first output circuit 420, a second output circuit 430, a second control circuit 440, and a third output circuit 450.

[0107] In the embodiments disclosed herein, the first control circuit 410, the first output circuit 420, the second output circuit 430 and the third output circuit 450 can be referred to the previous description of FIG4A, and the second control circuit 440 can be referred to the previous second control circuit 240. For the sake of brevity, similar parts will not be described again.

[0108] In this embodiment, the high and low level voltages of the first clock signal CLK1 and the second clock signal CLK2 can be the same, both having a lower high level voltage. The fourth power supply voltage LVGL2 is greater than the second power supply voltage LVGL1. A second output signal OUT2 is output based on the second clock signal CLK2 and the fourth power supply voltage LVGL2. The high level voltage of the second output signal OUT2 is the same as the high level voltage of the second clock signal CLK2, and the low level voltage of the second output signal OUT2 is the same as the fourth power supply voltage LVGL2. In this case, the voltage difference between the high and low voltages experienced by the next-stage shift register is the voltage difference between the high level voltage of the second clock signal CLK2 and the fourth power supply voltage LVGL2, which makes the voltage difference experienced by the shift register smaller. After outputting the second output signal OUT2, the second output terminal OUT2 is reset using the second power supply voltage LVGL1, which can completely pull down the potential of the second output terminal OUT2.

[0109] The first output signal OUT1 is output based on the first clock signal CLK1, the third clock signal CKL3, and the third power supply voltage VGL. The high-level voltage of the first output signal OUT1 is determined by the high-level voltages of the first clock signal CLK1 and the third clock signal CKL3, while the low-level voltage of the first output signal OUT1 is determined by the third power supply voltage VGL. In this case, the high level of the third clock signal CLK3 is used to amplify the high-level voltage of the first output signal OUT1, resulting in a higher high-level voltage for OUT1, thus meeting the driving requirements of the pixel circuit.

[0110] In some existing examples, a first output signal OUT1 and a second output signal OUT2 are output based on the same clock signal. If the clock signal has a high voltage level, the second output signal OUT2 will subject the next-stage shift register to a large voltage surge, causing transistors to burn out. If the clock signal has a low high voltage level, the high voltage level of the first output signal OUT1 cannot fully drive the transistors in the pixel circuit.

[0111] In this embodiment of the disclosure, a first clock signal CLK1 and a second clock signal CLK2 with different high-level voltages are used to output a first output signal OUT1 and a second output signal OUT2 with different high-level voltages to meet different driving requirements.

[0112] When both the first clock signal CLK1 and the second clock signal CLK2 have high-level voltages, the second power supply LVGL1 and the fourth power supply LVGL2 with different voltages are set to realize the output of the second output signal OUT2 and the reset of the second output terminal OUT2, respectively, so as to increase the low-level voltage of the second output signal OUT2 and thus avoid the voltage difference between the high and low levels of the second output signal OUT2 being too large.

[0113] When both the first clock signal CLK1 and the second clock signal CLK2 have low high-level voltages, a third clock terminal CLK3 is set, and the high-level voltage of the first output signal OUT1 is increased by the third clock signal CLK3 to meet the driving requirements of the pixel circuit.

[0114] Figure 5 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0115] In this embodiment of the disclosure, the shift register 500 includes a first control circuit 510, a first output circuit 520, and a second output circuit 530.

[0116] In this embodiment, the first control circuit 510 includes transistors T5 to T15; the first output circuit 520 includes transistors T19 to T22 and a second capacitor C2; and the second output circuit 530 includes transistors T16 to T18. The first power supply VGH includes a first sub-power supply VDDO and a second sub-power supply VDDE. The second node N2 includes a first sub-node N2-1 and a second sub-node N2-2.

[0117] The control electrode and the first electrode of the fifth transistor T5 are electrically connected to the input terminal INPUT, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1.

[0118] The control electrode of the sixth transistor T6 is electrically connected to the reset terminal RST, the first electrode of the sixth transistor T6 is electrically connected to the first node N1, and the second electrode of the sixth transistor T6 is electrically connected to the second power supply LVGL1.

[0119] The control electrode of the seventh transistor T7 is connected to the total reset terminal STV0, the first electrode of the seventh transistor T7 is connected to the first node N1, and the second electrode of the seventh transistor T7 is connected to the second power supply LVGL1.

[0120] The control electrode of the eighth transistor T8 is electrically connected to the first sub-node N2-1, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the second power supply LVGL1.

[0121] The control electrode of the ninth transistor T9 is electrically connected to the second sub-node N2-2, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the second power supply LVGL1.

[0122] The control electrode of the tenth transistor T10 is electrically connected to the first node N1, the first electrode of the tenth transistor T10 is electrically connected to the first sub-node N2-1, and the second electrode of the tenth transistor T10 is electrically connected to the second power supply LVGL1.

[0123] The control electrode of the eleventh transistor T11 is electrically connected to the first node N1, the first electrode of the eleventh transistor T11 is electrically connected to the second sub-node N2-2, and the second electrode of the eleventh transistor T11 is electrically connected to the second power supply LVGL1.

[0124] The control electrode of the twelfth transistor T12 is electrically connected to the first node N1, the first electrode of the twelfth transistor T12 is electrically connected to the first sub-node N2-1, and the second electrode of the twelfth transistor T12 is electrically connected to the second power supply LVGL1.

[0125] The control electrode of the thirteenth transistor T13 is connected to the first node N1, the first electrode of the thirteenth transistor T13 is connected to the second sub-node N2-2, and the second electrode of the thirteenth transistor T13 is connected to the second power supply LVGL1.

[0126] The control electrode and first electrode of the fourteenth transistor T14 are electrically connected to the first sub-power supply VDDO, and the second electrode of the fourteenth transistor T14 is electrically connected to the first sub-node N2-1.

[0127] The control electrode and the first electrode of the fifteenth transistor T15 are electrically connected to the second sub-power supply VDDE, and the second electrode of the fifteenth transistor T15 is electrically connected to the second sub-node N2-2.

[0128] The control electrode of the sixteenth transistor T16 is electrically connected to the second sub-node N2-2, the first electrode of the sixteenth transistor T16 is electrically connected to the second output terminal OUT2, and the second electrode of the sixteenth transistor T16 is electrically connected to the second power supply LVGL1.

[0129] The control electrode of the seventeenth transistor T17 is electrically connected to the first sub-node N2-1, the first electrode of the seventeenth transistor T17 is electrically connected to the second output terminal OUT2, and the second electrode of the seventeenth transistor T17 is electrically connected to the second power supply LVGL1.

[0130] The control electrode of the eighteenth transistor T18 is connected to the first node N1, the first electrode of the eighteenth transistor T18 is connected to the second clock terminal CLK2, and the second electrode of the eighteenth transistor T18 is connected to the second output terminal OUT2.

[0131] The control electrode of the nineteenth transistor T19 is electrically connected to the second sub-node N2-2, the first electrode of the nineteenth transistor T19 is electrically connected to the first output terminal OUT1, and the second electrode of the nineteenth transistor T19 is electrically connected to the third power supply VGL.

[0132] The control electrode of the twentieth transistor T20 is electrically connected to the first sub-node N2-1, the first electrode of the twentieth transistor T20 is electrically connected to the first output terminal OUT1, and the second electrode of the twentieth transistor T20 is electrically connected to the third power supply VGL.

[0133] The control electrode of the 21st transistor T21 is connected to the first node N1, the first electrode of the 21st transistor T21 is connected to the first clock terminal CLK1, and the second electrode of the 21st transistor T21 is connected to the first output terminal OUT1.

[0134] The control electrode of the 22nd transistor T22 is connected to the reset terminal RST, the first electrode of the 22nd transistor T22 is connected to the first output terminal OUT1, and the second electrode of the 22nd transistor T22 is connected to the third power supply VGL.

[0135] The first terminal of the second capacitor C2 is connected to the first node N1, and the second terminal of the second capacitor C2 is connected to the first output terminal OUT1.

[0136] In the embodiments of this disclosure, the fifth transistor T5 to the twenty-second transistor T22 are N-type TFT transistors. For example, thin-film transistors with an active layer of indium gallium zinc oxide (IGZO). Those skilled in the art will understand that the first transistor T1 to the twenty-second transistor T22 in this disclosure can also be P-type TFT transistors, such as thin-film transistors with an active layer of low-temperature doped polysilicon (LTPS), by correspondingly changing the level of the gate conduction signal of each transistor.

[0137] Furthermore, those skilled in the art will understand that the storage capacitor can be implemented as a single capacitor or multiple capacitor units connected in parallel or series, as long as it can achieve its corresponding function.

[0138] In the description of the embodiments of this disclosure, the first node N1, the first child node N2-1, and the second child node N2-2 do not represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0139] Figure 6A is a signal timing diagram of a shift register according to an embodiment of the present disclosure. Figure 6A shows the signal timing of a first clock signal CLK1, a second time signal CLK2, a first sub-supply voltage VDDO, and a second sub-supply voltage VDDE.

[0140] As shown in Figure 6A, the high-level voltage H1 of the first clock signal CLK1 is greater than the high-level voltage H2 of the second clock signal CLK2. At this time, the high-level voltage of the first output signal OUT1 is the same as the high-level voltage H1, and the high-level voltage of the second output signal OUT2 is the same as the high-level voltage H2. Therefore, the high-level voltage of the first output signal OUT1 is greater than the high-level voltage of the second output signal OUT2. The higher high-level voltage of the first output signal OUT1 ensures the normal switching on and off of the transistors in the pixel circuit, while the lower high-level voltage of the second output signal OUT2 reduces the voltage drop across the shift register.

[0141] In this embodiment, the first sub-power supply voltage VDDO controls the fourteenth transistor T14 to turn on, and the first sub-power supply voltage VDDO is written to the first sub-node N2-1 through the fourteenth transistor T14. When the input signal INPUT controls the tenth transistor T10 to turn on, the second power supply voltage LVGL1 is written to the first sub-node N2-1 through the tenth transistor T10. At this time, the source-drain voltage difference of the fourteenth transistor T14 and the source-drain voltage difference of the tenth transistor T10 can be the voltage difference between the first sub-power supply voltage VDDO and the second power supply voltage LVGL1. Similarly, the second sub-power supply voltage VDDE controls the fifteenth transistor T15 to turn on, and the second sub-power supply voltage VDDE is written to the second sub-node N2-2 through the fifteenth transistor T15. When the input signal INPUT controls the eleventh transistor T11 to turn on, the second power supply voltage LVGL1 is written to the second sub-node N2-2 through the eleventh transistor T11. At this time, the source-drain voltage difference of the fifteenth transistor T15 and the source-drain voltage difference of the eleventh transistor T11 can be the voltage difference between the second sub-supply voltage VDDE and the second supply voltage LVGL1.

[0142] In this embodiment of the disclosure, the voltage of the high level H1 of the first clock signal CLK1 is greater than the first power supply voltage. The first power supply voltage includes a first sub-power supply voltage VDDO and a second sub-power supply voltage VDDE. The voltage of the high level H1 of the first clock signal CLK1 is greater than the first sub-power supply voltage VDDO and the second sub-power supply voltage VDDE. For example, the first sub-power supply voltage VDDO and the second sub-power supply voltage VDDE can be the same as the voltage of the high level H2 of the second clock signal CLK2. At this time, the lower first sub-power supply voltage VDDO and the lower second sub-power supply voltage VDDE can reduce the voltage across the tenth transistor T10, the eleventh transistor T11, the fourteenth transistor T14, and the fifteenth transistor T15. When the tenth transistor T10, the eleventh transistor T11, the fourteenth transistor T14, and the fifteenth transistor T15 are turned on, it can prevent the current flowing through the tenth transistor T10, the eleventh transistor T11, the fourteenth transistor T14, and the fifteenth transistor T15 from burning out the tenth transistor T10, the eleventh transistor T11, the fourteenth transistor T14, and the fifteenth transistor T15.

[0143] Figure 6B is a schematic diagram of voltage and current in a shift register according to an embodiment of the present disclosure.

[0144] As shown in Figure 6B, the solid lines represent the voltage and current values ​​before adjustment, and the dashed lines represent the voltage and current values ​​after adjustment. For example, the voltage and current values ​​before adjustment can be one example. The voltage and current values ​​after adjustment can be the voltage and current values ​​in the shift register 500 shown in Figure 5.

[0145] Based on the circuit structure of shift register 500 shown in Figure 5, the current flowing through the fourteenth transistor T14, taking the first sub-power supply voltage VDDO and the voltage of the first sub-node N2-1 as an example, will be used for illustrative explanation.

[0146] For example, in this embodiment of the present disclosure, the first sub-power supply voltage VDDO is less than the example first sub-power supply voltage VDDO, which causes the potential of the first sub-node N2-1 to be pulled high after the first sub-power supply voltage VDDO is written to the first sub-node N2-1. After the second power supply voltage LVGL1 is written to the first sub-node N2-1 through the tenth transistor 10, it pulls the potential of the first sub-node N2-1 low.

[0147] At this time, the voltage of the first child node N2-1 in this embodiment is less than the voltage of the first child node N2-1 in the example. In this case, the fourteenth transistor T14 and the tenth transistor T10 are turned on. The source-drain voltage difference of the fourteenth transistor T14 in this embodiment is less than the source-drain voltage difference of the fourteenth transistor T14 in the example, and the source-drain voltage difference of the tenth transistor T10 in this embodiment is less than the source-drain voltage difference of the tenth transistor T10 in the example. The current flowing through the fourteenth transistor T14 and the tenth transistor T10 in this embodiment is less than the current flowing through the fourteenth transistor T14 and the tenth transistor T10 in the example.

[0148] In this embodiment of the disclosure, by setting a first sub-supply voltage VDDO and a second sub-supply voltage VDDE with lower voltages, the source-drain voltage difference of the tenth transistor T10, the eleventh transistor T11, the fourteenth transistor T14, and the fifteenth transistor T15 can be reduced, as can the gate-source voltage difference between the tenth transistor T10 and the eleventh transistor T11. This reduces the current flowing through the tenth transistor T10, the eleventh transistor T11, the fourteenth transistor T14, and the fifteenth transistor T15, thus preventing the tenth transistor T10, the eleventh transistor T11, the fourteenth transistor T14, and the fifteenth transistor T15 from burning out.

[0149] Figure 6C is a signal timing diagram of a shift register according to another embodiment of the present disclosure.

[0150] The following description uses the structure of shift register 500 shown in Figure 5 as an example, combined with the signal timing diagram shown in Figure 6C, to illustrate the operation of the shift register provided in this embodiment. The operation of shift register 500 is divided into three time periods.

[0151] During the first time period P1, the first clock signal CLK1 is at a low level, the second clock signal CLK2 is at a low level, and the input signal INPUT is at a high level.

[0152] Under the control of the high level of the input signal INPUT, the fifth transistor T5, the tenth transistor T10, and the eleventh transistor T11 are turned on. The input signal INPUT is written to the first node N1 through the fifth transistor T5, and the potential of the first node N1 is pulled high. The second power supply voltage LVGL1 is written to the first child node N2-1 through the tenth transistor T10, and to the second node N2-2 through the eleventh transistor T11, and the potentials of the first child node N2-1 and the second node N2-2 are pulled low.

[0153] At this time, under the control of the high potential of the first node N1, transistors T12, T13, T18, and T21 are turned on. Under the control of the low potential of the first sub-node N2-1 and the second node N2-2, transistors T8, T9, T16, T17, T19, and T20 are turned off.

[0154] In this configuration, the first clock signal CLK1 is written to the first output terminal OUT1 via the twenty-first transistor T21, causing OUT1 to output a low-level signal. The first clock signal CLK1 charges the second capacitor C2, causing C2 to store a high-level signal. The second clock signal CLK2 is written to the second output terminal OUT2 via the eighteenth transistor T18, causing OUT2 to output a low-level signal.

[0155] The first sub-power supply voltage VDDO and the second sub-power supply voltage VDDE control the conduction of the fourteenth transistor T14 and the fifteenth transistor T115. The first sub-power supply voltage VDDO is written to the first sub-node N2-1 and the second sub-power supply voltage VDDE through the fourteenth transistor T14. The second power supply voltage LVGL1 is written to the first sub-node N2-1 through the tenth transistor T10 and to the second node N2-2 through the eleventh transistor T11. The potentials of the first sub-node N2-1 and the second node N2-2 are pulled low.

[0156] During the first time period P1, the reset signal RST is low, and the sixth transistor T6 and the twenty-second transistor T22 are turned off. The total reset signal STV0 is at a low level, and the seventh transistor T7 is turned off. The total reset signal received at the total reset terminal can be the frame start signal, which is used to achieve a total reset of each shift register unit.

[0157] During the second time period P2, the first clock signal CLK1 is at a high level, the second clock signal CLK2 is at a high level, and the input signal INPUT is at a low level.

[0158] Under the control of the low level of the input signal INPUT, transistors 5 (T5), 10 (T10), and 11 (T11) are turned off. Since transistors 6 (T6), 7 (T7), 8 (T8), and 9 (T9) are turned off, node N1 maintains the high potential of the previous stage, therefore transistors T12 (T12), T13 (T13), T18 (T18), and T21 (T21) are turned on. Under the discharge of the second capacitor C2, the potential of node N1 is pulled high again.

[0159] At this time, under the control of the high potential of the first node N1, transistors T12, T13, T18, and T21 remain on. The second power supply voltage LVGL1, through transistors T12 and T13, pulls down the potential of the first sub-node N2-1 and the second node N2-2 again. At this time, transistors T16, T17, T19, and T20 are turned off.

[0160] In this configuration, the first clock signal CLK1 is written to the first output terminal OUT1 via the twenty-first transistor T21, and the first output terminal OUT1 outputs a high-level signal. The second clock signal CLK2 is written to the second output terminal OUT2 via the eighteenth transistor T18, and the second output terminal OUT2 outputs a high-level signal.

[0161] During the third time period P3, the first clock signal CLK1 is at a low level, the second clock signal CLK2 is at a low level, and the input signal INPUT is at a low level.

[0162] After the first output signal OUT1 with a high level is output at the first output terminal OUT1, the reset signal RST is a high level signal to reset the shift register 500.

[0163] Under the control of a low level input signal INPUT, transistors T5, T10, and T11 are turned off. Under the control of a high level reset signal RST, transistors T6 and T22 are turned on. The second power supply voltage LVGL1 is written to the first node N1 through transistor T6, pulling down the potential of the first node N1. The third power supply voltage VGL is written to the first output terminal OUT1 through transistor T22, pulling down the potential of the first output terminal OUT1.

[0164] Under the control of the low potential of the first node N1, the twelfth transistor T12, the thirteenth transistor T13, the eighteenth transistor T18, and the twenty-first transistor T21 are turned off. Since the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are all turned off, the first sub-power supply voltage VDDO and the second sub-power supply voltage VDDE are pulled up by the fourteenth transistor T14 and the fifteenth transistor T15 to raise the potential of the first sub-node N2-1 and the potential of the second sub-node N2-2.

[0165] Under the control of the potential of the first sub-node N2-1 and the high potential of the second sub-node N2-2, the eighth transistor T8, the ninth transistor T9, the sixteenth transistor T16, the seventeenth transistor T17, the nineteenth transistor T19, and the twentieth transistor T20 are turned on.

[0166] In this configuration, the third power supply voltage VGL is written to the first output terminal OUT1 via the nineteenth transistor T19 and the twentieth transistor T20, resulting in a low-level signal at OUT1. The second power supply voltage LVGL1 is written to the second output terminal OUT2 via the sixteenth transistor T16 and the seventeenth transistor T17, resulting in a low-level signal at OUT2.

[0167] In this embodiment, the high-level voltage of the first output signal OUT1 is consistent with the high-level voltage of the first clock signal CLK1. When the first clock signal CLK1 has a high-level voltage, the high-level voltage of the first output signal OUT1 can satisfy the driving of the pixel circuit. The high-level voltage of the second output signal OUT2 is consistent with the high-level voltage of the second clock signal CLK2. When the second clock signal CLK2 has a low-level voltage, when the second output signal OUT2 is provided to the next-stage shift register, the voltage drop across the shift register can be reduced.

[0168] In some embodiments, the first clock signal CLK1 has a stepped waveform. The first level of the first clock signal CLK1 is the highest level of the stepped waveform, and the second level of the first clock signal CLK1 is the lowest level of the stepped waveform.

[0169] Figure 7A is a schematic diagram of the voltage of the first clock signal according to an embodiment of the present disclosure. The timing of the first clock signal CLK1 is schematically illustrated with reference to Figure 7A.

[0170] As shown in Figure 7A, the solid line represents the signal voltage variation trend of the first clock signal before adjustment, and the dashed line represents the signal voltage variation trend of the first clock signal after adjustment. For example, the signal voltage variation trend of the first clock signal before adjustment can be a signal voltage variation trend of a conventional example. The signal voltage variation trend of the first clock signal after adjustment can be the signal voltage variation trend of the first clock signal provided to the shift register 500 shown in Figure 5.

[0171] In one existing example, the low-level voltage of the first clock signal is V2, and the high-level voltage is V1. During the rise of the voltage level, the voltage of the first clock signal is raised directly from the low-level voltage V2 to the high-level voltage V1 after one rise. During the fall of the voltage level, the voltage of the first clock signal is raised directly from the high-level voltage V1 to the low-level voltage V2 after one fall.

[0172] In this embodiment, the low-level voltage of the first clock signal is V2, and the high-level voltage is V1. During the rise of the voltage level, the voltage of the first clock signal rises from the low-level voltage V2 to voltage V3 after a first rise, and then rises from voltage V3 to the high-level voltage V1 after a second rise. During the fall of the voltage level, the voltage of the first clock signal falls from the high-level voltage V1 to voltage V3 after a first fall, and then rises from voltage V3 to the low-level voltage V2 after a second fall.

[0173] In this embodiment, the high-level voltage V1 is greater than the voltage V3, and the voltage V3 is greater than the low-level voltage V2. In this embodiment, the high-level voltage of the first clock signal is obtained by repeatedly raising the low-level voltage, and the low-level voltage of the first clock signal is obtained by repeatedly lowering the high-level voltage; therefore, the first clock signal has a stepped waveform.

[0174] In this embodiment of the disclosure, while ensuring that signal level voltages can be distinguished, the interval between two adjacent rises of the first clock signal can be set to a short duration as much as possible. For example, after detecting that the level of the first clock signal has been raised to voltage V3 and the duration has reached a preset duration, the level of the first clock signal is raised a second time. The preset duration can be approximately 3 to 5 μs. For example, the level of the first clock signal can be raised a second time after a plateau with a duration of the preset duration is detected in the timing diagram of the first clock signal.

[0175] The circuit structure of shift register 500 shown in Figure 5 and the signal timing shown in Figure 7B are illustrated schematically.

[0176] The timing variations of the input signal INPUT1, the second clock signal CLK2, the potential of the first node N1, the potential of the first child node N2-1, the potential of the second child node N2-2, the second output signal OUT2, and the third power supply voltage VGL shown in Figure 7B can be referenced in Figure 6C. For simplicity, similar parts will not be described again.

[0177] In this embodiment of the present disclosure, during the second time period P2, the first clock signal CKL1 is raised from a low level to a high level through a double boost, and then lowered from a high level to a low level through a double debuff. Correspondingly, the level of the first output signal OUT1 during the second time period P2 is also raised from a low level to a high level through a double boost, and then lowered from a high level to a low level through a double debuff.

[0178] In this embodiment, during the second time period P2, the twenty-first transistor T21 is turned on. The first clock signal CLK1 is written to the first output terminal OUT1 through the twenty-first transistor T21. During the rise or fall of the level of the first clock signal, a transient current is generated in the twenty-first transistor T21, and the magnitude of the transient current is related to the source-drain voltage difference of the transistor. For example, each rise of the first clock signal CLK1 will generate a transient current in the twenty-first transistor T21. Since the voltage difference between the highest and lowest level voltages of the first clock signal CLK1 remains constant, the voltage difference generated by each level rise after multiple level rises is less than the voltage difference generated by only one level rise. Therefore, the current value of the transient current generated by each level rise after multiple level rises is less than the transient current generated by only one level rise.

[0179] Therefore, compared to the case where the high-level voltage is simply a low-level voltage that has been raised once, the high-level voltage, which is the first clock signal obtained by raising the low-level voltage multiple times, can reduce the instantaneous current in the 21st transistor T21, thereby reducing the risk of the 21st transistor T21 being burned out.

[0180] Figure 7C is a schematic diagram of the current in a shift register according to another embodiment of the present disclosure.

[0181] As shown in Figure 7C, the solid line represents the current change trend generated by the first clock signal represented by the solid line in Figure 7A, and the dashed line represents the current change trend generated by the first clock signal represented by the dashed line in Figure 7A. For example, the current change trend shown by the solid line can be a current change trend of a conventional example. The current change trend shown by the dashed line can be the current change trend provided to the twenty-first transistor T21 in the shift register 500 shown in Figure 5.

[0182] In one existing example, during the rise of the first clock signal level, the maximum current (instantaneous current) in the current change trend is I1. During the fall of the first clock signal level, the maximum current (instantaneous current) in the current change trend is I3 (absolute value).

[0183] In this embodiment of the disclosure, during the rise of the first clock signal level, the current change trend shows two large instantaneous currents, with current values ​​of approximately I2. During the fall of the first clock signal level, the current change trend shows two large instantaneous currents, with current values ​​of approximately I4 (absolute value).

[0184] For example, the high-level voltage V1 of the first clock signal CLK1 is 38V, and the low-level voltage V2 is -38V. The instantaneous voltage difference generated by a single level rise from low voltage V2 to high voltage V1 is 76V. The instantaneous voltage difference generated by two level rises from low voltage V2 to voltage V3 (0V), and then from voltage V3 to high voltage V1, is 38V each time. The instantaneous current generated by a single level rise can be 76 / R, and the instantaneous current generated by two level rises is 38 / R, where R can be the resistance value of the twenty-first transistor T21.

[0185] According to the heat formula Q = I 2 According to Rt and the formula Q = IUt, reducing the current flowing through the transistor can effectively reduce the heat generated in the transistor. Reducing the source-drain voltage difference of the transistor can also reduce the current flowing through it.

[0186] For example, the time it takes for the current to pass through the transistor during a single voltage level rise is t1, and the time it takes for the current to pass through the transistor during two voltage level rises is t2. For example, the current value I1 can be 2a, the current value I2 can be a, the time t2 can be 2b, and the time t1 can be b. According to the heat formula, the heat generated by a single voltage level rise is Q1 = (I1) 2 Rtl = 4a 2 Rb, the heat generated by the two level increases is Q2 = (I2). 2 Rt2=2a 2 Rb. Therefore, compared to the heat generated by the transistor during a single level rise, the heat generated by the transistor during two level rises is reduced by 1 / 2.

[0187] When the level switching process of the first clock signal CLK1 includes n rises or falls, the heat generated in the transistor is Qn = I. 2 Rt = a 2 Rb / n. Therefore, the heat generated by n level rises or falls is 1 / n of the heat generated by a single level rise or fall. Thus, by setting the timing of the first clock signal CLK1 to have a stepped waveform, the level switching process of the first clock signal includes multiple rises or falls, thereby reducing the heat generated when the first clock signal CLK1 passes through the transistor and preventing transistor burnout. Similarly, the second clock signal CLK2 can also have a stepped waveform, and the level switching process is similar to that of the first clock signal CLK1.

[0188] Figure 8 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0189] As shown in Figure 8, the shift register 800 includes a first control circuit 810, a first output circuit 820, a second output circuit 830, and a second control circuit 840.

[0190] In this embodiment, the first control circuit 810, the first output circuit 820, and the second output circuit 830 can refer to the first control circuit 510, the first output circuit 520, and the second output circuit 530 described above. For the sake of brevity, similar parts will not be described again.

[0191] In this embodiment of the disclosure, the second control circuit 840 includes a first transistor T1 and a second transistor T2.

[0192] The control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply LVGL2, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0193] The control electrode of the second transistor T2 is electrically connected to the second node N2, the first electrode of the second transistor T2 is electrically connected to the second power supply LVGL1, and the second electrode of the second transistor T2 is electrically connected to the third node N3.

[0194] The first terminal of the eighteenth transistor T18 is electrically connected to the first clock terminal CKL1. The second terminals of the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the sixteenth transistor T16, and the seventeenth transistor T17 are all electrically connected to the third node N3.

[0195] In the embodiments of this disclosure, the first transistor T1 and the second transistor T2 are N-type TFT transistors. Those skilled in the art will understand that the first transistor T1 and the second transistor T2 in this disclosure can also be P-type TFT transistors, by correspondingly changing the level of the gate conduction signal of each transistor.

[0196] In the description of the embodiments of this disclosure, the third node N3 does not represent an actual existing component, but rather represents the junction point of related circuit connections in the circuit diagram.

[0197] Figure 9 is a signal timing diagram of a shift register according to an embodiment of the present disclosure.

[0198] The following description uses the structure of shift register 800 shown in Figure 8 as an example, combined with the signal timing diagram shown in Figure 9, to describe the operation of the shift register provided in this embodiment. The operation of shift register 800 is divided into three time periods. The on and off states of the transistors in shift register 800 during the first time period P1, the second time period P2, and the third time period P3 can be referred to the on and off states of the transistors in shift register 500 described above. For simplicity, similar parts will not be repeated.

[0199] In embodiments of this disclosure, the first clock signal CLK1 has a high-level voltage, and the high-level voltage of the input signal IPNUT can be consistent with the high-level voltage of the first clock signal CLK1.

[0200] During the first time period P1, the high potential of the first node N1 controls the first transistor T1 to turn on, and the fourth power supply voltage LVGL2 is written to the third node N3, pulling the potential of the third node N3 low. The high-level voltage of the input signal INPUT is written to the first node N1.

[0201] In the first time period P1 and the second time period P2, the voltage across the first control circuit 810 is the voltage difference between the high-level voltage of the input signal INPUT and the fourth power supply voltage LVGL2, and the voltage across the second output circuit 830 is the voltage difference between the high-level voltage of the first clock signal CLK1 and the fourth power supply voltage LVGL2.

[0202] In the third time period P3, the high potential of the second node N2 controls the second transistor T2 to turn on, and the second power supply voltage LVGL1 is written to the third node N3, pulling down the potential of the third node N3. The second power supply voltage LVGL1 is used to pull down the potential of the first node N1 and the potential of the second output terminal OUT2.

[0203] Since the fourth power supply voltage LVGL2 is greater than the second power supply voltage LVGL1, the voltage across the first control circuit 810 and the second output circuit 830 during the first time period P1 and the second time period P2 is relatively small. During the third time period P3, the second power supply voltage LVGL1 can be used to fully pull down the potential of the first node N1 and the potential of the second output terminal OUT2.

[0204] Furthermore, before the second power supply voltage LVGL1 is written to the third node N3, the potential of the first node N1 and the potential of the second output terminal OUT2 are pulled down to the fourth power supply voltage LVGL2 using the fourth power supply voltage LVGL2 of the third node N3. After the second power supply voltage LVGL1 is written to the third node N3, the potential of the first node N1 and the potential of the second output terminal OUT2 are pulled down from the fourth power supply voltage LVGL2 to the second power supply voltage LVGL1 using the second power supply voltage LVGL1 of the third node N3. In this case, the potential of the first node N1 and the potential of the second output terminal OUT2 can be pulled down twice, thereby reducing the instantaneous current of the transistors electrically connected to the first node N1 and the second output terminal OUT2, reducing the heat generated by the instantaneous current, and preventing the transistors from burning out.

[0205] Figure 10 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0206] As shown in Figure 10, the shift register 1000 includes a first control circuit 1010, a first output circuit 1020, a second output circuit 1030, and a third output circuit 1050.

[0207] In this embodiment, the first control circuit 1010, the first output circuit 1020, and the second output circuit 1030 can refer to the first control circuit 510, the first output circuit 520, and the second output circuit 530 described above. For the sake of brevity, similar parts will not be described again.

[0208] In this embodiment of the disclosure, the third output circuit 1050 includes a third transistor T3, a fourth transistor T4, and a first capacitor C1.

[0209] The control electrode of the third transistor T3 is connected to the first output terminal OUT1, the first electrode of the third transistor T3 is connected to the third clock terminal CLK3, and the second electrode of the third transistor T3 is connected to the fourth node N4.

[0210] The control electrode of the fourth transistor T4 is electrically connected to the reset terminal RST, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected to the third power supply VGL.

[0211] The first terminal of the first capacitor C1 is connected to the first output terminal OUT1, and the second terminal of the first capacitor C1 is connected to the fourth node N4.

[0212] The first terminal of the twenty-first transistor T21 is electrically connected to the second clock terminal CLK2.

[0213] In the embodiments of this disclosure, the third transistor T3 and the fourth transistor T4 are N-type TFT transistors. Those skilled in the art will understand that the third transistor T3 and the fourth transistor T4 in this disclosure can also be P-type TFT transistors, by correspondingly changing the level of the gate conduction signal of each transistor.

[0214] In the description of the embodiments of this disclosure, the fourth node N4 does not represent an actual existing component, but rather represents the junction point of related circuit connections in the circuit diagram.

[0215] Figure 11 is a signal timing diagram of a shift register according to an embodiment of the present disclosure.

[0216] The following description uses the structure of shift register 1000 shown in Figure 10 as an example, combined with the signal timing diagram shown in Figure 11, to describe the operation of the shift register provided in this embodiment. The operation of shift register 1000 is divided into three time periods. The on and off states of the transistors in shift register 1000 during the first time period P1, the second time period P2, and the third time period P3 can be referred to the on and off states of the transistors in shift register 500 described above. For simplicity, similar parts will not be repeated.

[0217] In embodiments of this disclosure, the second clock signal CLK2 has a lower high-level voltage, and the high-level voltage of the input signal IPNUT can be consistent with the high-level voltage of the second clock signal CLK2.

[0218] During the second time period P2, the eighteenth transistor T18 and the twenty-first transistor T21 are turned on. The second clock signal CLK2 is written to the second output terminal OUT2 through the eighteenth transistor T18, and the second output terminal OUT2 outputs a high-level signal. The high-level voltage of the second output signal OUT2 is the same as the high-level voltage of the second clock signal CLK2.

[0219] The second clock signal CLK2 is written to the first output terminal OUT1 through the twenty-first transistor T21, and the first output terminal OUT1 outputs a high-level signal. At this time, the high-level voltage of the first output signal OUT1 is the same as the high-level voltage of the second clock signal CLK2.

[0220] Under the control of the high potential of the first output terminal OUT1, the third transistor T3 is turned on. The third clock signal CLK3 is written to the fourth node N4 through the third transistor T3. The potential of the second terminal of the first capacitor C1 is increased to the high-level voltage of the third clock signal CLK3. Under the bootstrap effect of the first capacitor C1, the potential of the first terminal of the first capacitor C1 is also increased by a corresponding voltage, thereby increasing the high-level voltage of the second output signal OUT2.

[0221] For example, during the first time period P1, the third transistor T3 is turned on, and the low level of the third clock signal CLK3 is written to the fourth node N4, pulling the potential of the fourth node N4 down to the low level voltage of the third clock signal CLK3. During the second time period P2, the potential of the first terminal of the first capacitor C1 is consistent with the high level voltage of the second clock signal CLK2, and the potential of the second terminal of the first capacitor C1 is the low level voltage of the third clock signal CLK3. When the high level of the third clock signal CLK3 is written to the fourth node N4, pulling the potential of the fourth node N4 up to the high level voltage of the third clock signal CLK3, due to the bootstrap effect of the first capacitor C1, when the potential of the second terminal of the first capacitor C1 is pulled up from the low level voltage of the third clock signal CLK3 to the high level voltage of the third clock signal CLK3, the potential of the second terminal of the first capacitor C1 is also increased by the voltage, that is, the high level voltage of the second clock signal CLK2 + the high level voltage of the third clock signal CLK3 - the low level voltage of the third clock signal CLK3, thereby increasing the high level voltage of the first output signal OUT1.

[0222] In this embodiment, a second output signal OUT2 is output using a second clock signal CLK2 with a lower high-level voltage, thereby reducing the voltage drop across the next-stage shift register. After outputting the first output signal OUT1 based on the second clock signal CLK2, the bootstrap effect of the first capacitor C1 is used to increase the high-level voltage of the first output signal OUT1 based on the high-level voltage of the third clock signal CLK3, so that the high-level voltage of the first output signal OUT1 meets the high-level driving requirements of the pixel circuit.

[0223] During the third time period P3, under the action of the high level of the reset signal RST, the fourth transistor T4 is turned on, and the third power supply voltage VGL is written to the fourth node N4 through the fourth transistor T4, and the potential of the fourth node N4 is pulled down.

[0224] Figure 12 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0225] As shown in Figure 12, the shift register 1200 includes a first control circuit 1210, a first output circuit 1220, a second output circuit 1230, and a second control circuit 1240.

[0226] In this embodiment, the first control circuit 1210, the first output circuit 1220, and the second output circuit 1230 can refer to the first control circuit 510, the first output circuit 520, and the second output circuit 530 described above. The second control circuit 1240 can refer to the second control circuit 840 described above. For simplicity, similar parts will not be described again.

[0227] In this embodiment, the on / off states of the fifth transistor T5 to the twenty-second transistor T22 in the shift register 1200 during the first time period P1, the second time period P2, and the third time period P3, as well as the potential changes of the first node N1, the first sub-node N2-1, and the second sub-node N2-2, can be referenced to the shift register 500 described above. The on / off states of the first transistor T1, the second transistor T2, and the potential changes of the third node N1 in the shift register 1200 during the first time period P1, the second time period P2, and the third time period P3 can be referenced to the shift register 800 described above. For simplicity, similar details will not be repeated.

[0228] In this embodiment, the first clock signal CLK1 has a higher high-level voltage, and the second clock signal CLK2 has a lower high-level voltage. The high-level voltage of the input signal IPNUT can be the same as the high-level voltage of the second clock signal CLK2.

[0229] In the first time period P1 and the second time period P2, the voltage across the first control circuit 1210 is the voltage difference between the high-level voltage of the input signal INPUT and the fourth power supply voltage LVGL2, and the voltage across the second output circuit 1230 is the voltage difference between the high-level voltage of the second clock signal CLK2 and the fourth power supply voltage LVGL2.

[0230] In this embodiment, the high-level voltage of the first output signal OUT1 is consistent with the high-level voltage of the first clock signal CLK1, ensuring that the high-level voltage of the first output signal OUT1 meets the high-level driving requirements of the pixel circuit. The high-level voltage of the second output signal OUT2 is consistent with the high-level voltage of the second clock signal CLK2, ensuring that the input signal INPUT, which provides the value to the next-stage shift register, has a lower high-level voltage. Since the fourth power supply voltage LVGL2 is relatively higher than the second power supply voltage LVGL1, the fourth power supply voltage LVGL1 and the second output signal OUT2 are provided to the first control circuit 1210 and the second output circuit 1230, resulting in a smaller voltage drop across the first control circuit 1210 and the second output circuit 1230.

[0231] In addition, during the third time period P3, the potential of the first node N1 and the potential of the second output terminal OUT2 are pulled down by the second power supply voltage LVGL1, so as to fully reset the potential of the first node N1 and the potential of the second output terminal OUT2.

[0232] Figure 13 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0233] As shown in Figure 13, the shift register 1300 includes a first control circuit 1310, a first output circuit 1320, a second output circuit 1330, a second control circuit 1340, and a third output circuit 1350.

[0234] In this embodiment, the first control circuit 1310, the first output circuit 1320, the second output circuit 1330, and the third output circuit 1350 can be referred to as the first control circuit 1010, the first output circuit 1020, the second output circuit 1030, and the third output circuit 1050 described above. The second control circuit 1340 can be referred to as the second control circuit 840 described above. For simplicity, similar parts will not be described again.

[0235] In this embodiment, the on / off states of the third transistor T3 to the twenty-second transistor T22 in the shift register 1300 during the first time period P1, the second time period P2, and the third time period P3, as well as the potential changes of the first node N1, the first child node N2-1, and the second child node N2-2, can be referenced to the shift register 1000 described above. The on / off states of the first transistor T1, the second transistor T2, and the potential changes of the third node N1 in the shift register 1300 during the first time period P1, the second time period P2, and the third time period P3 can be referenced to the shift register 800 described above. For simplicity, similar parts will not be repeated.

[0236] In this embodiment of the disclosure, the second clock signal CLK2 has a lower high-level voltage. The high-level voltage of the input signal IPNUT can be the same as the high-level voltage of the second clock signal CLK2.

[0237] During the first time period P1 and the second time period P2, the voltage difference between the high-level voltage of the input signal INPUT and the fourth power supply voltage LVGL2 is the voltage difference between the first control circuit 1310 and the second output circuit 1330. Since the fourth power supply voltage LVGL2 is relatively higher than the second power supply voltage LVGL1, and the second clock signal CLK2 has a lower high-level voltage, the voltage difference between the first control circuit 1310 and the second output circuit 1330 is smaller, thus preventing transistor burnout.

[0238] In this embodiment of the disclosure, for the second time period P2, before the high-level voltage of the third clock signal CLK3 is written to the fourth node N4, the high-level voltage of the first output signal OUT1 is consistent with the high-level voltage of the second clock signal CLK2. After the high-level voltage of the third clock signal CLK3 is written to the fourth node N4, the high-level voltage of the first output signal OUT1 is pulled high by the high-level voltage of the third clock signal CLK3, so that the high-level voltage of the first output signal OUT1 meets the high-level driving requirements of the pixel circuit.

[0239] In the shift register described in the above embodiments, the timing change of the first clock signal CLK1 provided to the shift register can be the timing of the first clock signal shown in FIG7B. The first sub-power supply voltage VDDO and the second sub-power supply voltage VDDE provided to the shift register can be the first sub-power supply voltage VDDO and the second sub-power supply voltage VDDE shown in FIG6A. The voltage relationship between the first clock signal CLK1 and the second clock signal CLK2 provided to the shift register can also refer to the voltage relationship between the first clock signal CLK1 and the second clock signal CLK2 shown in FIG6A.

[0240] In the shift register described in the above embodiment, the twenty-first transistor T21 has a significant impact on the voltage level of the first output signal OUT1, and the instantaneous current it withstands is also relatively large. To ensure that the first output signal OUT1 can drive the pixel circuit normally, the twenty-second transistor T22 resets the first output terminal OUT1 based on the reset signal RST, and the instantaneous current it withstands is also relatively large. Therefore, compared to the other transistors in the shift register, the twenty-first transistor T21 and the twenty-second transistor T22 have larger dimensions. For example, the size of the twenty-first transistor T21 can be at least four times the size of the other transistors, and the size of the twenty-first transistor T22 can be at least twice the size of the other transistors.

[0241] Figure 14 is a schematic diagram of the structure of a drive circuit according to an embodiment of the present disclosure.

[0242] As shown in Figure 14, the driving circuit 1400 includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include the first-stage shift register ST1, ..., the m-th-stage shift register STm, ..., and the M-th-stage shift register STM.

[0243] In an embodiment of the present disclosure, the shift register ST1 can be any one of the foregoing shift registers 100, 200, 300a, 300b, 400a, 400b, 500, 800, 1000, 1200, and 1300. For example, the M shift registers are all shift register 500. For example, the M shift registers are all shift register 800. Details are not described herein again.

[0244] In an embodiment of the present disclosure, among the M cascaded shift registers, the input signal INPUT at the input terminal INPUT of the first-stage shift register ST1 is the start signal GSTV.

[0245] In an embodiment of the present disclosure, the input terminal INPUT of the m-stage shift register STm is electrically connected to the second output terminal OUT2 of the (m - x)-stage shift register, where x < m ≤ M, and x and m are integers. For example, x can be 1, 2, 3,.... The m-stage shift register STm uses the second output signal OUT2 of the previous-stage shift register as the input signal INPUT to drive the m-stage shift register STm.

[0246] In an embodiment of the present disclosure, the reset terminal RST of the m-stage shift register STm is electrically connected to the second output OUT2 of the (m + y)-stage shift register, where 1 < m ≤ M - y, and y and m are integers. For example, y can be 1, 2, 3,.... The m-stage shift register STm uses the second output signal OUT2 of the subsequent-stage shift register as the reset signal RST to reset the m-stage shift register STm.

[0247] In an embodiment of the present disclosure, the first-stage shift register ST1,..., the m-stage shift register STm,..., the M-stage shift register STM respectively output first output signals OUT1(1),..., OUT1(m),..., OUT1(M) based on their respective first output terminals OUT, so as to drive the pixel array in the display panel.

[0248] FIG. 15 is a schematic structural diagram of a driving circuit according to another embodiment of the present disclosure.

[0249] As shown in FIG. 15, the driving circuit 1500 includes a plurality of cascaded shift registers. The connection relationship of the cascaded plurality of shift registers can refer to the driving circuit 1400.

[0250] In this embodiment of the disclosure, x = 4, y = 4, the input terminal INPUT of the m-th stage shift register STm is electrically connected to the second output terminal OUT2 of the (m-4)-th stage shift register, and the reset terminal RST of the m-th stage shift register STm is electrically connected to the second output terminal OUT2 of the (m+4)-th stage shift register.

[0251] For example, the input terminal INPUT of the 6th stage shift register ST6 is electrically connected to the second output terminal OUT2 of the 2nd stage shift register, and the reset terminal RST of the 2nd stage shift register STm is electrically connected to the second output terminal OUT2 of the 6th stage shift register.

[0252] In this embodiment, the first clock terminals CLK1 of multiple shift registers can be electrically connected to clock signal lines ck1, ..., ck8, ... respectively, and the second clock terminals CLK2 of multiple shift registers can be electrically connected to clock signal lines cb1, ..., cb8, ... respectively. For example, the first clock terminals CLK1 of the first-stage shift register ST1 to the first clock terminals CLK1 of the eighth-stage shift register ST8 can be electrically connected to clock signal lines ck1 to ck8 in sequence, and the second clock terminals CLK2 of the first-stage shift register ST1 and the second clock terminal CLK2 of the eighth-stage shift register ST8 can be electrically connected to clock signal lines cb1 to cb8 in sequence.

[0253] The driving circuit described in this disclosure can be used to drive electronic paper. Electronic paper is a new type of display device, mainly used for displays in electronic tags, billboards, e-readers, etc., and has advantages such as repeated rewriting, low power consumption, and wide viewing angle. The display principle of electronic paper is based on electrophoresis or other similar technologies, which changes the reflective properties of the screen by controlling the position of charged particles in the display unit, thereby presenting images and text.

[0254] Using cascaded shift registers to drive electronic paper reduces the amount of wiring in the paper, which helps to narrow the bezel. Furthermore, it reduces the number of IC circuits and the materials used in the module, significantly lowering costs and increasing profits. Since transistors in electronic paper require relatively high voltages to turn on and off, the driving circuit described in this disclosure can also meet the product requirements of electronic paper, outputting a scanning signal with a high-level voltage to turn the transistors in the electronic paper on and off.

[0255] Figure 16 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0256] As shown in Figure 16, the display device 1600 may include a driving circuit 1610.

[0257] In this embodiment, the driving circuit 1610 can be any one of the driving circuits 1400 and 1500 described above, and will not be repeated here.

[0258] Figure 17 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0259] As shown in Figure 17, the driving method may include operations S1710 to S1730.

[0260] In operation S1710, under the control of the input signal from the input terminal and the first power supply voltage of the first power supply, the potential of the first node is controlled by the input signal and the second power supply voltage of the second power supply, and the potential of the second node is controlled by the first power supply voltage and the second power supply voltage.

[0261] In operation S1720, under the control of the potential of the first node and the potential of the second node, a first output signal is output via the first output terminal based on the first clock signal from the first clock terminal and the third power supply voltage of the third power supply.

[0262] In operation S1730, under the control of the potential of the first node and the potential of the second node, a second output signal is output via the second output terminal based on the second clock signal from the second clock terminal and the second power supply voltage.

[0263] In this embodiment of the disclosure, operations S1710 to S1730 are similar to the operations performed by the shift register 500 described above, and will not be repeated here.

[0264] In this embodiment of the disclosure, the driving method further includes: controlling the potential of the third node using a fourth power supply voltage under the control of the potential of the first node; and controlling the potential of the third node using a second power supply voltage under the control of the potential of the second node; wherein the fourth power supply voltage is greater than or equal to the second power supply voltage, and the voltage of the first level of the first clock signal and the voltage of the first level of the second clock signal are both greater than the second power supply voltage and the fourth power supply voltage.

[0265] In this embodiment of the disclosure, the driving method further includes: controlling the potential of a first node using an input signal and a fourth power supply voltage, and controlling the potential of a second node using a first power supply voltage and a fourth power supply voltage; and under the control of the potentials of the first node and the second node, outputting a second output signal via a second output terminal based on a second clock signal and a fourth power supply voltage.

[0266] In this embodiment of the disclosure, the driving method further includes: controlling the potential of the first node using a second power supply voltage under the control of a reset signal from the reset terminal; and controlling the potential of the first input terminal using a third power supply voltage under the control of the reset signal.

[0267] In this embodiment of the disclosure, the driving method further includes: controlling the potential of the first output terminal based on a first clock signal and a third power supply voltage under the control of the potential of the first node and the potential of the second node; controlling the potential of the first output terminal using the third power supply voltage and a third clock signal from the third clock terminal under the control of the potential of the first output terminal, and outputting a first output signal via the first output terminal.

[0268] In this embodiment of the disclosure, the voltage of the first level of the first clock signal is greater than or equal to the first power supply voltage.

[0269] In this embodiment of the disclosure, during a first time period, the input signal is at a first level, the first clock signal is at a second level, and the second clock signal is at a second level; during a second time period, the input signal is at a second level, the first clock signal is at a first level, and the second clock signal is at a first level; and during a third time period, the input signal is at a second level, the first clock signal is at a second level, and the second clock signal is at a second level.

[0270] In this embodiment of the disclosure, during the second time period, the first clock signal has a stepped waveform, wherein the first level of the first clock signal is the highest level of the stepped waveform, and the second level of the first clock signal is the lowest level of the stepped waveform.

[0271] In this embodiment of the present disclosure, during a first time period, the third clock signal is at a second level; during a second time period, the third clock signal changes from the second level to the first level; and during a third time period, the third clock signal is at the second level.

[0272] In this embodiment, the first voltage level is high and the second voltage level is low. Those skilled in the art can also set the first voltage level to low and the second voltage level to high, and correspondingly set the voltage values ​​of the first, second, third, and fourth power supplies, based on the type of transistor in the shift register.

[0273] In this embodiment of the disclosure, the operation of the first time period is similar to that of the first time period P1 shown in FIG. 6C, the second time period includes the operation of the second time period P2 shown in FIG. 6C, and the operation of the third time period is similar to that of the third time period P3 shown in FIG. 6C. For the sake of simplicity, the same parts will not be described again in this disclosure.

[0274] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0275] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0276] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A shift register, comprising: The first control circuit is configured to control the potential of a first node using the input signal from the input terminal and the first power supply voltage of a first power supply, and to control the potential of a second node using the first power supply voltage and the second power supply voltage, under the control of the input signal from the input terminal and the first power supply voltage of the first power supply. The first output circuit is configured to output a first output signal via a first output terminal, under the control of the potential of the first node and the potential of the second node, based on a first clock signal from a first clock terminal and a third power supply voltage from a third power supply. as well as The second output circuit is configured to output a second output signal via a second output terminal, based on a second clock signal from a second clock terminal and a second power supply voltage, under the control of the potential of the first node and the potential of the second node. Wherein, the voltage of the first level of the first clock signal is greater than or equal to the voltage of the first level of the second clock signal.

2. The shift register according to claim 1, wherein, It also includes a second control circuit, which is electrically connected to the second power supply, the fourth power supply, the first node, the second node, and is electrically connected to the third node in conjunction with the first control circuit and the second output circuit; The second control circuit is further configured to control the potential of the third node using the fourth power supply voltage of the fourth power supply under the control of the potential of the first node; And under the potential control of the second node, the potential of the third node is controlled by the second power supply voltage; Wherein, the fourth power supply voltage is greater than or equal to the second power supply voltage, and the voltage of the first level of the first clock signal and the voltage of the first level of the second clock signal are both greater than the second power supply voltage and the fourth power supply voltage.

3. The shift register according to claim 2, wherein, The first control circuit is further configured to control the potential of the first node using the input signal and the fourth power supply voltage, and to control the potential of the second node using the first power supply voltage and the fourth power supply voltage. as well as The second output circuit is further configured to, under the control of the potentials of the first node and the second node, output the first [node name] via the second output terminal based on the second clock signal and the fourth power supply voltage. Two output signals.

4. The shift register according to claim 1 or 2, wherein, The first control circuit is also electrically connected to the reset terminal, and the first control circuit is further configured to control the potential of the first node using the second power supply voltage under the control of the reset signal from the reset terminal. The first output circuit is also electrically connected to the reset terminal, and the first output circuit is further configured to control the potential of the first output terminal using the third power supply voltage under the control of the reset signal.

5. The shift register according to claim 1 or 2 further includes a third output circuit electrically connected to the third clock terminal, the third power supply, and the first output terminal; The first output circuit is further configured to control the potential of the first output terminal using the first clock signal and the third power supply voltage, under the control of the potential of the first node and the potential of the second node. The third output circuit is configured to control the potential of the first output terminal under the control of the potential of the first output terminal, using the third power supply voltage and the third clock signal from the third clock terminal, and output the first output signal via the first output terminal.

6. The shift register according to any one of claims 1 to 5, wherein, The voltage of the first level of the first clock signal is greater than or equal to the voltage of the first power supply.

7. The shift register according to any one of claims 1 to 6, wherein, The first clock signal has a stepped waveform, the first level of the first clock signal is the highest level of the stepped waveform, and the second level of the first clock signal is the lowest level of the stepped waveform.

8. The shift register according to claim 2, wherein, The second control circuit includes a first transistor and a second transistor; Wherein, the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth power supply, and the second electrode of the first transistor is electrically connected to the third node; and The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the second power supply, and the second electrode of the second transistor is electrically connected to the third node.

9. The shift register according to claim 5, wherein, The third output circuit includes a third transistor, a fourth transistor, and a first capacitor; The control electrode of the third transistor is electrically connected to the first output terminal, the first electrode of the third transistor is electrically connected to the third clock terminal, and the second electrode of the third transistor is electrically connected to the fourth node. The control electrode of the fourth transistor is electrically connected to the reset terminal, the first electrode of the fourth transistor is electrically connected to the fourth node, and the second electrode of the fourth transistor is electrically connected to the third power supply; and The first terminal of the first capacitor is connected to the first output terminal, and the second terminal of the first capacitor is connected to the fourth node.

10. A driving circuit comprising M cascaded shift registers as described in any one of claims 1-9, where M is an integer greater than 1.

11. The driving circuit according to claim 10, wherein, The input terminal of the m-th stage shift register is electrically connected to the second output terminal of the mx-th stage shift register, where x < m ≤ M, and x and m are integers.

12. The driving circuit according to claim 10, wherein, The reset terminal of the m-th shift register is electrically connected to the second output terminal of the (m+y)-th shift register, where 1 < m ≤ My, and y and m are integers.

13. A display device, comprising: The driving circuit as described in any one of claims 10 to 12.

14. A driving method applied to a shift register as described in any one of claims 1-9, comprising: Under the control of the input signal from the input terminal and the first power supply voltage of the first power supply, the potential of the first node is controlled by the input signal and the second power supply voltage of the second power supply, and the potential of the second node is controlled by the first power supply voltage and the second power supply voltage. Under the control of the potential of the first node and the potential of the second node, based on the first clock signal from the first clock terminal and the third power supply voltage of the third power supply, a first output signal is output via the first output terminal. as well as Under the control of the potentials of the first node and the second node, based on the voltage from the second clock terminal... The second clock signal and the second power supply voltage are used to output a second output signal via the second output terminal; Wherein, the voltage of the first level of the first clock signal is greater than or equal to the voltage of the first level of the second clock signal.

15. The driving method according to claim 14, further comprising: Under the control of the potential of the first node, the potential of the third node is controlled by the fourth power supply voltage; as well as Under the control of the potential of the second node, the potential of the third node is controlled by the second power supply voltage; Wherein, the fourth power supply voltage is greater than or equal to the second power supply voltage, and the voltage of the first level of the first clock signal and the voltage of the first level of the second clock signal are both greater than the second power supply voltage and the fourth power supply voltage.

16. The driving method according to claim 15, further comprising: The potential of the first node is controlled using the input signal and the fourth power supply voltage, and the potential of the second node is controlled using the first power supply voltage and the fourth power supply voltage. as well as Under the control of the potential of the first node and the potential of the second node, the second output signal is output via the second output terminal based on the second clock signal and the fourth power supply voltage.

17. The driving method according to claim 14 or 15, further comprising: Under the control of the reset signal from the reset terminal, the potential of the first node is controlled by the second power supply voltage; Under the control of the reset signal, the potential of the first input terminal is controlled by the third power supply voltage.

18. The driving method according to claim 14 or 15, further comprising: Under the control of the potential of the first node and the potential of the second node, the potential of the first output terminal is controlled based on the first clock signal and the third power supply voltage; Under the control of the potential of the first output terminal, the potential of the first output terminal is controlled by the third power supply voltage and the third clock signal from the third clock terminal, and the first output signal is output through the first output terminal.

19. The driving method according to any one of claims 14 to 18, wherein, The voltage of the first level of the first clock signal is greater than or equal to the voltage of the first power supply.

20. The driving method according to any one of claims 14 to 19, wherein, During the first time period, the input signal is at a first level, the first clock signal is at a second level, and the second clock signal is at a second level. During the second time period, the input signal is at a second level, the first clock signal is at a first level, and the second clock signal is at a first level. as well as During the third time period, the input signal is at the second level, the first clock signal is at the second level, and the second clock signal is at the second level.

21. The driving method according to claim 20, wherein, In the second time period, the first clock signal has a stepped waveform, wherein the first level of the first clock signal is the highest level of the stepped waveform, and the second level of the first clock signal is the lowest level of the stepped waveform.

22. The driving method according to claim 20, wherein, During the first time period, the third clock signal is at the second level; During the second time period, the third clock signal transitions from the second level to the first level. In the third time period, the third clock signal is at the second level.

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