Method and apparatus for programming voltage management in memory systems

Abstract

This disclosure relates to programming voltage management in storage devices and systems. An example method for programming memory cells of a storage device is provided. The method includes increasing the voltage of a first word line of the storage device from a first voltage to a second voltage during a first time period. The method further includes increasing the voltage of the first word line from the second voltage to a target programming voltage during a second time period. The method also includes increasing the voltage of a second word line of the storage device from a third voltage to a fourth voltage. The second word line is adjacent to the first word line. After the voltage of the first word line reaches the voltage of the second word line, the voltage of the second word line increases starting from the third voltage.

Description

Technical Field

[0001] This disclosure relates generally to storage devices and memory systems, and more specifically to the management of programming voltages in storage devices and systems. Background Technology

[0002] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose data when power is off. Non-volatile memory devices can retain stored data when power is not connected. Flash memory is a low-cost, high-density non-volatile memory device, including NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as reading, programming (writing), and erasing. Summary of the Invention

[0003] This disclosure describes techniques for managing programming voltages in storage devices and systems.

[0004] One aspect of this disclosure is characterized by a method for programming memory cells of a memory device. The method includes increasing the voltage of a first word line of the memory device from a first voltage to a second voltage during a first time period. The method further includes increasing the voltage of the first word line from the second voltage to a target programming voltage during a second time period. The method also includes increasing the voltage of a second word line of the memory device from a third voltage to a fourth voltage. The second word line is adjacent to the first word line. The voltage of the second word line begins to increase from the third voltage after the voltage of the first word line reaches the second voltage and before the voltage of the first word line reaches the target programming voltage.

[0005] In some implementations, the voltage of the first word line begins to increase from the second voltage, and at the same time, the voltage of the second word line begins to increase from the third voltage.

[0006] In some implementations, at the beginning of the second time period, the voltage of the first word line begins to increase from the second voltage, and the voltage of the second word line begins to increase from the third voltage.

[0007] In some implementations, the method further includes increasing the voltage of a third word line of the storage device from a first voltage to a fourth voltage during a first time period. The third word line is adjacent to the first word line.

[0008] In some implementations, the memory cell coupled to the first word line is being programmed in the current programming operation, the memory cell coupled to the second word line has not yet been programmed in the current programming operation, and the memory cell coupled to the third word line has been programmed in the current programming operation.

[0009] In some implementations, the method further includes increasing the voltage of the second word line from the fourth voltage to the first pass voltage during a second time period, and increasing the voltage of the third word line from the fourth voltage to the second pass voltage during the second time period. The first pass voltage is higher than the second pass voltage.

[0010] In some implementations, the voltage of the second word line and the voltage of the third word line simultaneously begin to increase from the fourth voltage.

[0011] In some implementations, after the voltage of the third word line reaches the fourth voltage, the voltage of the second word line begins to increase from the third voltage.

[0012] In some implementations, during the first time period, the voltage of the second word line is maintained at a third voltage, and the third voltage is lower than the first voltage.

[0013] In some implementations, the third voltage is less than or equal to 0 volts (V).

[0014] Another feature of this disclosure is a storage device. The storage device includes: a memory block including a first word line and a second word line adjacent to the first word line; and peripheral circuitry including a voltage generator and a string driver. The peripheral circuitry is configured to: increase the voltage of the first word line from a first voltage to a second voltage during a first time period; increase the voltage of the first word line from the second voltage to a target programming voltage during a second time period; and increase the voltage of the second word line from a third voltage to a fourth voltage. After the voltage of the first word line reaches the second voltage and before the voltage of the first word line reaches the target programming voltage, the voltage of the second word line begins to increase from the third voltage.

[0015] In some implementations, at the beginning of the second time period, the voltage of the first word line begins to increase from the second voltage, and the voltage of the second word line begins to increase from the third voltage.

[0016] In some implementations, the memory block also includes a third word line adjacent to the first word line. The peripheral circuitry is also configured to increase the voltage of the third word line from a first voltage to a fourth voltage during a first time period.

[0017] In some implementations, the memory cell coupled to the first word line is being programmed in the current programming operation, the memory cell coupled to the second word line has not yet been programmed in the current programming operation, and the memory cell coupled to the third word line has been programmed in the current programming operation.

[0018] In some implementations, the peripheral circuitry is also configured to: increase the voltage of the second word line from the fourth voltage to the first pass voltage during the second time period; and increase the voltage of the third word line from the fourth voltage to the second pass voltage during the second time period.

[0019] In some implementations, the voltage of the second word line and the voltage of the third word line simultaneously begin to increase from the fourth voltage.

[0020] In some implementations, after the voltage of the third word line reaches the fourth voltage, the voltage of the second word line begins to increase from the third voltage.

[0021] In some implementations, the third voltage is less than or equal to 0V.

[0022] In some implementations, during the first time period, the voltage of the second word line is maintained at a third voltage, and the third voltage is less than or equal to the first voltage.

[0023] Another aspect of this disclosure is characterized by a memory system. The memory system includes a memory device and a memory controller configured to control the memory device. The memory device includes: a memory block including a first word line and a second word line adjacent to the first word line; and peripheral circuitry including a voltage generator and a string driver. The peripheral circuitry is configured to: increase the voltage of the first word line from a first voltage to a second voltage during a first time period; increase the voltage of the first word line from the second voltage to a target programming voltage during a second time period; and increase the voltage of the second word line from a third voltage to a fourth voltage. After the voltage of the first word line reaches the second voltage and before the voltage of the first word line reaches the target programming voltage, the voltage of the second word line begins to increase from the third voltage.

[0024] Details of one or more implementations of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0025] Figure 1 An example of a schematic diagram of a storage device including peripheral circuitry is shown.

[0026] Figure 2 An example of a side view showing a cross-section of a memory cell array including NAND memory strings.

[0027] Figure 3 Examples of schematic diagrams of some peripheral circuits are shown.

[0028] Figure 4 An example circuit for performing programming operations is shown.

[0029] Figure 5 A schematic diagram of an example voltage transmission circuit is shown.

[0030] Figure 6 This is a timing diagram showing the voltage waveforms at various locations during an example programming operation for a selected word line.

[0031] Figure 7 This is a timing diagram showing the voltage waveforms at various locations in another example programming operation for a selected word line.

[0032] Figures 8A-8B This shows a timing diagram illustrating the voltage waveforms at various locations during another example programming operation for a selected word line.

[0033] Figure 9 A flowchart is shown for an example method used to perform programming operations.

[0034] Figure 10 A block diagram of an example system with storage devices is shown.

[0035] Figure 11A A diagram showing a memory card with storage devices is shown.

[0036] Figure 11B A diagram showing a solid-state drive (SSD) with storage devices is shown.

[0037] Similar reference numerals and names in the various figures indicate similar elements. It should also be understood that the various exemplary implementations shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0038] Due to the demand for cheaper and higher-density memory devices, memory devices (e.g., 3D NAND flash memory) can be formed with multiple stacks, and each stack can have a large number of layers. The large number of layers and high aspect ratio of such memory devices can pose challenges to the manufacturing process. As the die size of memory devices continues to shrink, the string driver, which occupies a portion of the memory device, also faces increasing pressure to reduce its size. Faster programming times (tProg) are expected in memory devices such as TLC (three-layer cell) devices. However, after the rise and fall ramp cycles during erase / program operations, the string driver may suffer from hot carrier injection (HCI) issues, which can cause threshold voltage shifts in the transistors of the string driver and a reduction in subsequent ramp speeds. Therefore, reducing performance degradation and ensuring that the memory device remains functional at the end of its lifespan without increasing the size of the string driver has become a common challenge across the industry.

[0039] In one or more implementations of this disclosure, an example method for programming memory cells of a memory device is provided. By utilizing coupling between adjacent word lines, the voltage at a word line adjacent to a selected word line can be controlled to help ramp up the voltage at the selected word line during programming operations. Implementations of this disclosure may provide one or more of the following technical advantages and / or benefits. In some implementations, no hardware modification is required because the described techniques can be implemented in firmware changes to the memory controller or control circuitry. HCI problems of the serial driver can be mitigated. Test results show that, in some implementations, improvements to tProg can result in a 2 microsecond (μs) saving per page without increasing the die size of the memory device. Test results also show that, in some instances, the HCI problem of the serial driver at the end of the memory device's lifespan can be improved by 0.4 pulses.

[0040] The technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory devices (NVMs) (e.g., NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc.). The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-layer cell) devices, MLC (multi-layer cell) devices (e.g., 2-layer cell devices), TLC (three-layer cell) devices, QLC (four-layer cell) devices, or PLC (five-layer cell) devices. Alternatively or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0041] Figure 1Example of a schematic circuit diagram of a memory device 100 including peripheral circuitry according to some aspects of this disclosure. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein memory cells 106 are provided in the form of an array of memory strings 108 (e.g., NAND memory strings), each memory string 108 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0042] In some implementations, each memory cell 106 is a single-level cell (SLC) having two possible memory states and thus capable of storing one data bit. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 106 is a multi-level cell (MLC) capable of storing more than a single data bit in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, then the MLC can be programmed by writing one of the three possible nominal storage values ​​to the cell to restore the MLC from an erase state to one of the three possible programming levels. A fourth nominal storage value can be used for the erase state.

[0043] like Figure 1As shown, each NAND flash memory string 108 may include a source select gate (SSG) 110 at its source end and a drain select gate (DSG) 112 at its drain end. SSG 110 may be referred to as a bottom select gate (BSG), and DSG 112 may be referred to as a top select gate (TSG). BSG 110 and TSG 112 may be configured to activate the selected NAND flash memory string 108 (column of the array) during read and program operations. In some implementations, the sources of the NAND flash memory strings 108 in the same block 104 are coupled via the same source line (SL) 114 (e.g., common SL). In other words, according to some implementations, the NAND flash memory strings 108 in the same block 104 have an array common source (ACS). According to some implementations, the TSG 112 of each NAND flash memory string 108 is coupled to a corresponding bit line 116 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having TSG 112) or a deselect voltage (e.g., 0V) to the corresponding TSG 112 via one or more TSG lines 113, and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having BSG 110) or a deselect voltage (e.g., 0V) to the corresponding BSG 110 via one or more BSG lines 115. In some implementations, the NAND memory string 108 includes bottom memory cells adjacent to BSG 110 and top memory cells adjacent to TSG 112, wherein the bottom memory cells are coupled to bottom word lines, e.g. Figure 1 The WL5 shown is used, and the top memory cell is coupled to the top word line, for example, Figure 1 WL0 is shown.

[0044] like Figure 1As shown, NAND storage strings 108 can be organized into multiple blocks 104, each of which can have a common source line 114, for example, coupled to the ACS. In some implementations, each block 104 is the basic data unit for an erase operation, i.e., all storage cells 106 on the same block 104 are erased simultaneously. To erase storage cells 106 in a selected block 104, the source line 114 coupled to the selected block 104 and unselected blocks 104 in the same plane as the selected block 104 can be biased using an erase voltage (Verase) (e.g., a high positive voltage (e.g., 20V or higher)). In some examples, the erase operation can be performed at a half-block level, a quarter-block level, or a level with any suitable number of blocks or any suitable fraction of blocks. Storage cells 106 of adjacent NAND storage strings 108 can be coupled via word lines 118, which select which row of storage cells 106 is affected by read and programming operations. Figure 1 The example word lines shown include top word lines WL0, WL1, WL2, WL3, WL4 and bottom word line WL5 located between one or more TSG lines 113 and one or more BSG lines 115.

[0045] Figure 2 An example of a cross-sectional side view of a memory cell array 101 including NAND memory strings 108 is shown, according to some aspects of this disclosure. (See example...) Figure 2 As shown, the NAND memory string 108 can extend vertically through the memory stack 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0046] The memory stack 204 may include staggered gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, TSG 112, or BSG 110, and may extend laterally as a TSG line 113 at the top of the memory stack 204, a BSG line 115 at the bottom of the memory stack 204, or a word line 118 between TSG line 113 and BSG line 115.

[0047] like Figure 2 As shown, the NAND memory string 108 includes a channel 210 extending vertically through the memory stack 204. In some implementations, the channel 210 includes multiple layers, each formed of a different material (e.g., a semiconductor material or a dielectric material).

[0048] Figure 3 Some example peripheral circuitry according to certain aspects of this disclosure is shown. The example peripheral circuitry includes a page buffer / sensor amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface 316, and a data bus. In some examples, it may also include... Figure 3 Additional peripheral circuitry, not shown. Peripheral circuitry 102 can be accessed via... Figure 1 The bit line 116, word line 118, source line 114, BSG line 115, and TSG line 113 are coupled to the memory cell array 101. The peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 106 via the bit line 116, word line 118, source line 114, BSG line 115, and TSG line 113, and for sensing voltage and / or current signals from each target memory cell 106, to facilitate the operation of the memory cell array 101. The peripheral circuitry 102 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0049] Page buffer / sensor amplifier 304 can be configured to read data from memory cell array 101 and program (write) data to memory cell array 101 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store a page of programming data (write data) to be programmed into a page of memory cell array 101. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from bit line 116 representing data bits stored in memory cell 106 and amplify small voltage swings to a recognizable logic level during read operations. Column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from voltage generator 310.

[0050] The line decoder / word line driver 308 can be configured to be controlled by control logic 312 and select / deselect block 104 of memory cell array 101 and select / deselect word line 118 of block 104. The line decoder / word line driver 308 can also be configured to drive word line 118 using word line voltage generated from voltage generator 310. In some implementations, the line decoder / word line driver 308 can also select / deselect and drive BSG line 115 and TSG line 113. As described in detail below, the line decoder / word line driver 308 is configured to apply a read voltage to the selected word line 118 during read operations on memory cells 106 coupled to the selected word line 118.

[0051] Voltage generator 310 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 101.

[0052] Control logic 312 can be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. As described in detail below, the status register of register 314 may include one or more registers configured to store open block information indicating open blocks of all blocks 104 in the memory cell array 101. In some implementations, the open block information also indicates the last programmed page of each open block.

[0053] Interface 316 can be coupled to control logic 312 and used as a control buffer to buffer and relay control commands received from the host (not shown) to control logic 312, and to buffer and relay status information received from control logic 312 to the host. Interface 316 can also be coupled to column decoder / bit line driver 306 via a data bus and used as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 101.

[0054] Figure 4 An example circuit 400 for performing programming operations is shown, according to some aspects of this disclosure. Circuit 400 can be... Figure 1 The storage device 100 in the middle. For example... Figure 4 As shown, circuit 400 includes a row decoder / word line driver 308 and is coupled to at least one memory string 108 (e.g., a NAND memory string). Circuit 400 may be peripheral circuitry of the memory device (e.g., Figure 1 Peripheral circuit 102 or Figure 3 The peripheral circuit shown is a portion of the circuit. In some implementations, circuit 400 also includes a voltage generator (e.g., Figure 3 The voltage generator 310, the voltage generator 310 in Figure 4 (Not shown in the image), the memory string 108 includes a series-coupled TSG 112, memory cells 416-424, and BSG 110. TSG 112 is coupled to bit line 116, and BSG 110 is coupled to source line 114. The transistors and memory cells in the memory string 108 are coupled to the row decoder / word line driver 308 via WL0-WL31 and are configured to receive control voltages from the row decoder / word line driver 308. The row decoder / word line driver 308 includes a string driver 402, a decoder 403, and drivers 405-415. The decoder 403 is configured to select and control the transistors of the string driver 402 and is coupled to a voltage generator (e.g., ...). Figure 3 The voltage generator 310). Driver 405 may be referred to as a TSG driver, and driver 405 is configured to provide a control voltage to TSG 112. Driver 415 may be referred to as a BSG driver, and driver 415 is configured to provide a control voltage to BSG 110. Drivers 407-413 are word line drivers, and drivers 407-413 are configured to provide control voltages to WL1-WL30. In some implementations, word line drivers 407-413 are coupled to a voltage generator (e.g., Figure 3A voltage generator 310 is positioned between WL1-WL30 and is configured to supply voltage from the voltage generator to WL1-WL30. String driver 402 includes drive transistors 404-414 coupled in parallel through their gates. Controlled by voltage from decoder 403, each of drive transistors 404-414 is configured to pass voltage from one of drivers 405-415 to a corresponding transistor in the memory string 108. In some implementations, each drive transistor 404-414 may include a suitable semiconductor transistor, such as a bipolar junction transistor (BJT) or a field-effect transistor (FET). In some implementations, each drive transistor 404-414 may be a metal-oxide-semiconductor field-effect transistor (MOSFET), such as an n-channel MOSFET.

[0055] Figure 5 A schematic diagram of an example voltage transfer circuit 500 is shown. The voltage transfer circuit 500 may include lines coupled to different word lines (e.g., such as...). Figure 5 The line decoder / word line driver 502 shown is for word lines 503a, 503b, and 503c. The line decoder / word line driver 502 can be... Figure 3 and Figure 4 The implementation of the line decoder / word line driver 308 is described below. Circuit 504a represents the equivalent circuitry of a memory cell coupled to word line 503a (e.g., within the same memory page). Circuit 504a may include two capacitors connected in parallel and a resistor connected in series with one of the capacitors. Similarly, circuits 504b and 504c may represent the equivalent circuitry of memory cells coupled to word lines 503b and 503c, respectively. In some implementations, word lines 503a, 503b, and 503c may belong to different memory blocks. For example, word line 503a may belong to memory block 0, word line 503b to memory block 1, and word line 503c to memory block 2. The line decoder / word line driver 502 may include driving transistors M0, M1, and M2. Each of M0, M1, and M2 may be... Figure 4 An example of a driving transistor among driving transistors 406-412, and which can be coupled to a corresponding word line. The line decoder / word line driver 502 can be configured to deliver a voltage (e.g., provided by voltage generator 310) to a selected word line. In some implementations, the line decoder / word line driver 502 can be configured to deliver a voltage (e.g., provided by voltage generator 310) according to a control signal (e.g., provided by voltage generator 310). Figure 3 (Control logic 312 sends) Select memory block, global word line (gwl, gwl in) Figure 5(Not shown in the diagram) A local word line (lwl) 501, or one of word lines 503a, 503b, and 503c. Gate selection voltages (e.g., Vxd0, Vxd1, and Vxd2) can be applied to the gates of driving transistors (e.g., M0, M1, and M2) according to a control signal. The voltage at a near-word line node (e.g., nodes 506a, 506b, and 506c) represents the actual voltage applied to the selected word line. When the driving transistor is turned on by the gate selection voltage, the voltage at the corresponding near-word line node can follow the voltage from the local word line (e.g., provided by a voltage generator).

[0056] Figure 6 This is a timing diagram 600 illustrating voltage waveforms at various locations in an example programming operation for selecting a word line, according to some implementations of this disclosure. In this example, the word line in memory block 0 (e.g., word line 503a) is selected, while memory blocks 1 and 2 are not selected. The programming operation may include multiple stages, such as a channel preparation stage, a channel boost stage, a programming pulse stage, and a programming recovery stage.

[0057] During the channel preparation phase, the voltage generator can generate the voltages required in later stages, such as the gate voltages applied to various transistors and the channel boost voltage. When memory block 1 and memory block 2 are not selected, drive transistors M1 and M2 can be turned off. Therefore, gate selection voltages Vxd1 and Vxd2 can be maintained at a low level (e.g., as shown in the image). Figure 6 The -0.5V shown, and Vwl_near_blk1 and Vwl_near_blk2 representing the voltages at near word line nodes 506b and 506c, can be maintained at Vdd. The gate selection voltage Vxd0 increases from Vss to a higher level (e.g., as shown in the figure). Figure 6 The 15V shown is used to turn on the drive transistor M0. The local word line voltage Vlwl (e.g., Figure 5 The voltage at the local word line 501 decreases from Vdd to Vss. When the driving transistor M0 is turned on, the selected word line voltage Vselwl (e.g., the voltage at the selected word line 503a or near the word line node 506a) also decreases from Vdd to Vss.

[0058] During the channel boost phase, Vlwl can be increased from Vss to the channel boost voltage (e.g., as...). Figure 6(As shown in the 6.5V example). Vxd0 increases from 15V to a higher voltage to keep M0 on. For example, the higher voltage could be the target programming voltage Vpe plus a value greater than the threshold voltage of M0 (e.g., ΔV). Vselwl follows Vlwl and also increases from Vss to the channel boost voltage. When Vselwl increases more slowly than Vlwl, the drain-to-source voltage Vds of M0 is high. In some implementations, a high gate voltage (e.g., Vxd0) and a high drain-to-source voltage (e.g., Vds) of M0 can cause hot carrier injection (HCI), which refers to the injection of high-energy charge carriers (electrons or holes) into the gate oxide of M0, thereby shifting the threshold voltage of M0 and affecting the reliability of M0. In some instances, due to HCI, Vselwl may slow down the ramp rate after several erase / programming cycles.

[0059] During the programming pulse phase, Vxd0 remains at Vpe + ΔV. Vlwl can be increased from the channel boost voltage to the target programming voltage Vpe. Vselwl follows Vlwl and is also increased from the channel boost voltage to Vpe. During the programming recovery phase, Vxd0, Vlwl, and Vselwl can ramp down to their respective lower voltages.

[0060] Figure 7 This is a timing diagram 700 illustrating voltage waveforms at various locations in another example programming operation for selecting a word line according to some embodiments of the present disclosure. In this example, the index of the selected word line is n. By utilizing the coupling between adjacent word lines, the voltage at word lines adjacent to the selected word line can be controlled to help ramp up the voltage at the selected word line. In the programming operation, the voltages Vunseltsg at the unselected TSG (e.g., TSGs in an unselected memory string) and Vbsg at the BSG are maintained at Vss.

[0061] During the channel preparation phase of the programming operation, the voltage Vseltsg at the selected TSG (e.g., the selected TSG in the memory string) is maintained at Vss. The voltage at the word lines (including selected word lines and unselected word lines) is also Vss.

[0062] During the channel boost phase of the programming operation, the selected word line voltage Vselwl is increased from Vss to the channel boost voltage. The channel boost voltage can be in the range of 6V and 10V. For example, the channel boost voltage can be 6.5V. Figure 7 The gate selection voltage Vxd0 and local word line voltage Vlwl, not shown in the figure, can be compared with the above regarding... Figure 6 Those described are the same or similar. In some implementations ( Figure 7(Not shown in the image), the voltage at the unselected word line can also be increased from Vss to the channel boost voltage. In some other implementations, such as Figure 7 As shown, the voltages (e.g., Vwl(n-1) and Vwl(n+1)) at word lines adjacent to the selected word line n (e.g., word lines n-1 and n+1) can be increased to a value less than the channel boost voltage (e.g., 3V), while the voltage Vwl(k) at other word lines (e.g., word lines k, k ≠ n-1, n, and n+1) rises to the channel boost voltage. Vseltsg can be increased from Vss to 3V, such that the bit lines coupled to the selected TSG (e.g., ... Figure 1 Lower voltages (e.g., Vss) at bit line 116 can pass through, while higher voltages (e.g., Vdd) at bit lines may be blocked.

[0063] During the programming pulse phase of the programming operation, Vselwl can be increased from the channel boost voltage to the target programming voltage Vpe. In some implementations, Vwl(n+1) and Vwl(n-1) can be controlled to increase (e.g., from 3V to a higher level 3V+ΔV1 or 3V+ΔV2) before Vselwl reaches Vpe. Coupling capacitors can be present between adjacent word lines. Therefore, due to the coupling between adjacent word lines n-1, n, and n+1, Vselwl can follow Vwl(n-1) and Vwl(n+1) as Vwl(n-1) and Vwl(n+1) increase, and thus can ramp up more quickly. Although in Figure 7 Not shown in the diagram, but the gate select voltage Vxd0 and local word line voltage Vlwl during the programming pulse phase can be compared with the above regarding... Figure 6 Those described are the same or similar. Therefore, for similar reasons, Figure 7 The programming operation can also induce HCI during the programming pulse phase. During the programming recovery phase of the programming operation, Vseltsg and voltage at different word lines can be ramped down to correspondingly lower voltages.

[0064] Figures 8A-8B Timing diagram 800 shows voltage waveforms at various locations in another example programming operation for a selected word line, illustrating some implementations of this disclosure. In this example, the word line in memory block 0 (e.g., Figure 5 Word line 503a) is selected, and memory blocks 1 and 2 are not selected. The index of the selected word line is n. The programming operation may include multiple stages, such as a channel preparation stage, a channel boost stage, a programming pulse stage, and a programming recovery stage. Figure 8B As shown, during programming operations, the voltages Vunseltsg at the unselected TSG and Vbsg at the BSG can be maintained at Vss. Additionally, during programming operations, for unselected memory blocks (e.g., ...), Figure 8B The gate selection voltages of Vxd1 and Vxd2 in ) can be maintained at a lower level (e.g., -0.5V), and the voltages at the near word line nodes (e.g., Vwl_near_blk1 at node 506b and Vwl_near_blk2 at node 506c) can be maintained at Vdd (e.g., as shown in Figure 8B ).

[0065] The channel preparation stage starts at time T0 and ends at time T1. The gate selection voltage Vxd0 can increase from Vss to a higher level (e.g., 15V as shown in Figure 8A ) to turn on the drive transistor (e.g., M0) coupled to the selected word line before the channel preparation stage, and can be maintained at the higher level during the channel preparation stage. The local word line voltage Vlwl can decrease from Vdd to a voltage V1 (e.g., Vss) before the channel preparation stage, and can be maintained at V1 during the channel preparation stage. The selected word line voltage Vselwl (e.g., the voltage at the selected word line n) also decreases from Vdd to V1 before the channel preparation stage, and is maintained at V1 during the channel preparation stage because the drive transistor M0 is turned on.

[0066] In this example, each word line is programmed one by one according to the ascending order of the word line index. That is, the memory cells coupled to the selected word line n are programmed in the current programming operation. Additionally, the memory cells coupled to the word line i (i > n) are not programmed in the current programming operation and will be programmed, and the memory cells coupled to the word line (j < n) have been programmed in the current programming operation. It should be understood that although this example is for illustrative purposes and is not intended to be construed in a limiting sense, in some implementations, each word line can be programmed one by one according to the descending order of the word line index. For example, the memory cells coupled to the word line i (i > n) may have been programmed in the current programming operation, and the memory cells coupled to the word line (j < n) may not have been programmed in the current programming operation and will be programmed.

[0067] In this example, word line n - 1 and word line n + 1 are adjacent to the selected word line n in the memory string. As Figure 8AAs shown, the voltage Vwl(n+1) at word line n+1 can be V1 at the beginning of the channel preparation phase and can decrease to voltage V3 at some point in the channel preparation phase (e.g., between T0 and T1). In some implementations, V3 can be lower than or equal to V1. In some instances, V3 can be lower than V1. For example, V1 can be Vss (e.g., 0V), and V3 can be -0.5V. During the channel preparation phase, the voltage Vwl(n-1) at word line n-1 can be V1. During the channel preparation phase, the voltage Vwl(k) at other word lines (e.g., word lines k, k≠n-1, n, and n+1) also remains at V1. It should be understood that... Figures 8A-8B The various voltages shown (e.g., word line voltages, Vseltsg, and Vbsg during the channel preparation phase between T0 and T1) are for illustrative purposes only and are not intended to be interpreted in a limiting sense. In practice, voltage values ​​or voltage schedules can be adjusted according to specific circumstances. For example, any suitable voltage schedule used for the channel preparation phase can be applied. The same concepts are applied throughout this disclosure to describe voltages.

[0068] The channel boost phase begins at time T1 and ends at time T2. At some point during the channel boost phase, Vlwl can be increased from V1 to voltage V2 (also known as the channel boost voltage). For example, as... Figure 8A As shown, the channel boost voltage V2 can be in the range of 6V and 10V. In some instances, V2 can be 6.5V. Vxd0 increases from 15V to a higher voltage to keep M0 on. For example, the higher voltage can be the target programming voltage Vpe plus a value greater than the threshold voltage of M0 (e.g., ΔV). Vselwl follows Vlwl and increases from V1 to the channel boost voltage V2. Figure 8A As shown, Vwl(k) (k ≠ n-1, n, and n+1) increases from V1 to V2 at some point during the channel boost phase. At some point during the channel boost phase, Vwl(n-1) can increase from V1 to a voltage V4 (e.g., 3V) that is less than the channel boost voltage V2. During the channel boost phase, Vwl(n+1) can remain at V3. Figure 8B As shown, during the channel boost phase, Vseltsg can be increased from Vss to 3V, allowing lower voltages (e.g., Vss) coupled to the bit line of the selected TSG to pass through, while higher voltages (e.g., Vdd) at the bit line can be blocked.

[0069] The programming pulse phase begins at time T2 and ends at time T3. During the programming pulse phase, Vxd0 remains at Vpe + ΔV. At T2, Vlwl begins to increase from the channel boost voltage V2. Vlwl reaches the target programming voltage Vpe sometime between T2 and T3 and remains at Vpe until T3. Vselwl follows Vlwl and also begins to increase from the channel boost voltage V2 at T2. Due to coupling between adjacent word lines n-1, n, and n+1, the ramp-up of Vselwl can be boosted by changing Vwl(n-1) and Vwl(n+1). Vwl(n-1) and Vwl(n+1) can be configured to increase during the programming pulse phase. In some implementations, Vwl(n+1) increases from V3 at T2. Sometime between T2 and T3, Vwl(n+1) reaches V4. At a slightly later point in the programming pulse phase (e.g., time T5), Vwl(n-1) and Vwl(n+1) begin to increase from V4 (e.g., 3V). Vwl(n+1) can increase from V4 to the first pass voltage Vpass1 (e.g., 3V + ΔV1), and Vwl(n-1) can increase from V4 to the second pass voltage Vpass2 (e.g., 3V + ΔV2). Therefore, as Figure 8A As shown, Vselwl follows Vlwl and also increases from the channel boost voltage V2 to Vpe. The ramp of Vselwl becomes faster as at least one of Vwl(n-1) and Vwl(n+1) increases.

[0070] The programming recovery phase begins at T3 and ends at T4. During the programming recovery phase, as... Figure 8A As shown, Vxd0, Vlwl, Vselwl, and Vwl(k) (k≠n) can be ramped down to the corresponding lower voltage.

[0071] Figure 7 The waveforms of Vwl(n+1) and Vselwl in the data are as follows: Figure 8A The line in the middle is now represented as a dashed line. (And...) Figure 7 Compared to the examples in, Figure 8A In the example, Vselwl increases more rapidly because Vwl(n+1) increases from V3 to V4 at the start of the programming pulse phase. Since Vselwl is the voltage at the source of the driving transistor M0, the faster ramp-up of Vselwl helps reduce the drain-to-source voltage Vds and gate-to-source voltage Vgs of M0, thereby mitigating the HCI problem during the programming pulse phase.

[0072] In some implementations, the memory cells coupled to word line n-1 have been programmed, while the memory cells coupled to word line n+1 have not been programmed (e.g., they are in an erased state). Therefore, Vpass2 can be configured to be lower than Vpass1, because a higher Vpass2 can affect the distribution of the threshold voltages of the memory cells coupled to word line n-1 and can corrupt the data programmed into these memory cells.

[0073] In some implementations, Vselwl starts increasing from V2, and Vwl(n+1) starts simultaneously (e.g., in...). Figure 8A The programming pulse phase T2 shown begins with V3. In some other implementations, the increase of Vselwl from V2 and the increase of Vwl(n+1) from V3 may not occur at the same time. For example, Vwl(n+1) may begin increasing from V3 after Vselwl reaches V2 (e.g., at time T6) and before Vselwl reaches Vpe (e.g., at time T7). In other words, in some implementations, Vwl(n+1) may begin increasing at any suitable point between T6 and T7.

[0074] In some implementations, a voltage similar to Vwl(n+1) can be provided to more than one word line adjacent to the selected word line n that has not yet been programmed in the current programming operation (e.g., word lines n+2 and n+3). In this way, more neighboring word lines can be utilized to help ramp up the selected word line voltage Vselwl. However, allowing more neighboring word lines to have lower voltages during the channel boost phase can reduce the overall potential of the memory string. Therefore, in practice, a suitable number of neighboring word lines can be selected and configured to have a voltage similar to Vwl(n+1). Figure 8A The voltage change of Vwl(n+1). In some implementations, the appropriate amount can be determined based on experimental results.

[0075] It should be understood that Figures 8A-8B The values ​​of V2, V3, and V4 in the examples are for illustrative purposes and are not intended to be interpreted in a limiting sense. In practice, any suitable values ​​can be applied to these voltages. In some implementations, incremental step pulse programming (ISPP) can be applied to the programming operation, and therefore for each ISPP programming cycle, V2 and V4 can become higher than V2 and V4 in the previous ISPP programming cycle.

[0076] Figure 9 A flowchart illustrating an example method 900 for performing programming operations according to some aspects of this disclosure is shown. Method 900 can be performed by any suitable device or circuit disclosed herein.

[0077] like Figure 9 As shown, in operation 902, the voltage (e.g., selected word line n) of the first word line of the memory device is... Figure 8A The voltage (Vselwl) increases from a first voltage (e.g., V1) to a second voltage (e.g., V2) during a first time period (e.g., between T1 and T2).

[0078] In operation 904, during a second time period (e.g., between T2 and T3), the voltage of the first word line is increased from the second voltage to the target programming voltage (e.g., Vpe).

[0079] In operation 906, the second word line of the storage device (e.g., as per [reference]) Figures 8A-8B The voltage of the described word line (n+1) (e.g., Vwl(n+1)) increases from a third voltage (e.g., V3) to a fourth voltage (e.g., V4). The second word line is adjacent to the first word line. After the voltage of the first word line reaches the second voltage (e.g., at T6) and before the voltage of the first word line reaches the target programming voltage (e.g., at T7), the voltage of the second word line begins to increase from the third voltage.

[0080] In some implementations, the voltage of the first word line begins to increase from the second voltage, and the voltage of the second word line simultaneously (e.g., at T2) begins to increase from the third voltage.

[0081] In some implementations, at the beginning of the second time period (e.g., Figures 8A-8B (At the start of the channel boost phase), the voltage of the first word line begins to increase from the second voltage, and the voltage of the second word line begins to increase from the third voltage.

[0082] In some implementations, method 900 further includes storing the third word line of the storage device (e.g., as per the context of...) within a first time period. Figures 8A-8B The voltage of the described word line (n-1) (e.g., Vwl(n-1)) increases from a first voltage to a fourth voltage (e.g., V4). The third word line is adjacent to the first word line.

[0083] In some implementations, the memory cell coupled to the first word line is being programmed in the current programming operation, the memory cell coupled to the second word line has not yet been programmed in the current programming operation, and the memory cell coupled to the third word line has been programmed in the current programming operation.

[0084] In some implementations, method 900 further includes increasing the voltage of the second word line from the fourth voltage to the first pass voltage during a second time period (e.g., between T2 and T3). Figure 8AVpass1). Method 900 further includes increasing the voltage of the third word line from the fourth voltage to the second pass voltage (e.g., Vpass1) during the second time period. Figure 8A (Vpass2). The first pass voltage can be higher than the second pass voltage.

[0085] In some implementations, the voltages of the second and third word lines simultaneously begin to increase from the fourth voltage (e.g., in...). Figure 8A (at point T5).

[0086] In some implementations, after the voltage of the third word line reaches the fourth voltage (at some point between T1 and T2), the voltage of the second word line begins to increase from the third voltage (e.g., at T2).

[0087] In some implementations, the voltage of the second word line is maintained at a third voltage during the first time period, and the third voltage (e.g., V3) is less than the first voltage (e.g., Vss).

[0088] In some implementations, the third voltage is less than or equal to 0V (e.g., -0.5V).

[0089] Figure 10 An example block diagram of a system 1000 having storage devices according to some aspects of this disclosure is shown. System 1000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage devices therein. Figure 10 As shown, system 1000 may include a host 1008 and a memory system 1002 having one or more memory devices 1004 and a memory controller 1006. The host 1008 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 1008 may be configured to send data to or receive data from the memory devices 1004.

[0090] Storage device 1004 can be any storage device disclosed herein. According to some implementations, memory controller 1006 is coupled to storage device 1004 and host 1008 and configured to control storage device 1004. Memory controller 1006 can manage data stored in storage device 1004 and communicate with host 1008. In some implementations, memory controller 1006 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash Memory (CF) cards, Universal Serial Bus (USB) flash memory drives, or other media for electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 1006 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 1006 can be configured to control the operation of storage device 1004, such as read, erase, and program operations. The memory controller 1006 can also be configured to manage various functions relating to data stored or to be stored in the storage device 1004, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 1006 is also configured to process error correction codes (ECC) relative to data read from or written to the storage device 1004. The memory controller 1006 can also perform any other suitable function, such as formatting the storage device 1004.

[0091] The memory controller 1006 can communicate with an external device (e.g., the host 1008) according to a specific communication protocol. For example, the memory controller 1006 can communicate with the external device through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Mini-Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0092] The memory controller 1006 and one or more memory devices 1004 can be integrated into various types of storage devices, such as within the same package, like a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 1002 can be implemented and packaged into different types of end electronic products. Figure 11AIn one example shown, the memory controller 1006 and a single storage device 1004 may be integrated into a memory card 1102. The memory card 1102 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1102 may also include a connection between the memory card 1102 and a host computer (e.g., Figure 10 The memory card connector 1104 is coupled to the host 1008. In such a... Figure 11B In another example shown, the memory controller 1006 and multiple storage devices 1004 can be integrated into the SSD 1106. The SSD 1106 may also include a connection between the SSD 1106 and a host (e.g., Figure 10 The SSD connector 1108 is coupled to the host 1008. In some implementations, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102.

[0093] The subjects, actions, and operations described in this disclosure can be implemented in digital electronic circuit systems, tangible embedded computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their equivalents), or in combinations thereof. The subjects described in this disclosure can also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer program carrier for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. The carrier can be a tangible, non-transitory computer storage medium. Alternatively, the carrier can be artificially generated propagation signals (e.g., machine-generated electrical, optical, or electromagnetic signals) generated to encode information for transmission to a suitable receiving device for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination thereof. The computer storage medium is not a propagation signal.

[0094] Note that references to "an embodiment," "an embodiment," "an example embodiment," "some implementations," "some implementations," etc., in this disclosure indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, its effect in conjunction with other implementations on such feature, structure, or characteristic will be within the knowledge of those skilled in the art, whether explicitly described or not.

[0095] Generally, terms can be understood, at least in part, based on their use in context. For example, the term "one or more," as used herein, depends at least in part on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" can also be understood to convey either singular or plural use, depending at least in part on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0096] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes the meaning of something “on” and an intermediate feature or layer thereof. Furthermore, “above” or “above” means not only “above” or “above” something, but can also include the meaning of something “above” or “above” without any intermediate feature or layer (i.e., directly on something).

[0097] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., are used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.

[0098] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of an N+ conductive material such as glass, plastic, or sapphire wafer.

[0099] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between or at any set of horizontal planes between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and / or vertical interconnect pathways (VIAs) are formed) and one or more dielectric layers.

[0100] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10%–30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0101] In this disclosure, the terms “horizontal / horizontal / lateral / lateral” refer to a side surface parallel to the substrate, and the terms “vertical” or “perpendicular” refer to a side surface perpendicular to the substrate.

[0102] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in the vertical direction relative to the substrate.

[0103] This disclosure provides numerous different implementations or examples for achieving various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on top of a second component can include implementations in which the first and second components can be in direct contact, and can also include implementations in which an additional component can be formed between the first and second components, such that the first and second components do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not, in itself, prescribe a relationship between the various implementations and / or configurations discussed.

[0104] The foregoing description of a particular implementation can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementation.

[0105] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features specific to particular implementations of a particular invention. Specific features described in the context of different implementations in this disclosure may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single embodiment may be implemented separately in multiple implementations or in any suitable sub-combination. Furthermore, although the foregoing features may be described as functioning in certain combinations, and even initially claimed in this way, in some cases one or more features in the claimed combination may be removed from the combination, and the claims may be directed to sub-combinations or variations thereof.

[0106] Similarly, although the operations are depicted and described in a specific order in the accompanying drawings and claims, this should not be construed as requiring these operations to be performed in the specific order or sequence shown, or to perform all of the operations shown, to achieve the desired effect. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system modules and components in the implementations described above should not be construed as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products.

[0107] Specific implementations of the subject matter have been described. Other implementations are also within the scope of the appended claims. For example, the actions listed in the claims can be performed in a different order and still achieve the desired result. As an example, the processes depicted in the figures do not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0108] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for programming a storage cell of a storage device, wherein, The method includes: During a first time period, the voltage of the first word line of the storage device is increased from a first voltage to a second voltage; During the second time period, the voltage of the first word line is increased from the second voltage to the target programming voltage; and The voltage of the second word line of the memory device is increased from a third voltage to a fourth voltage, wherein the second word line is adjacent to the first word line, and the voltage of the second word line begins to increase from the third voltage after the voltage of the first word line reaches the second voltage and before the voltage of the first word line reaches the target programming voltage.

2. The method according to claim 1, wherein, The voltage of the first word line begins to increase from the second voltage, and simultaneously, the voltage of the second word line begins to increase from the third voltage.

3. The method according to claim 1 or 2, wherein, At the beginning of the second time period, the voltage of the first word line begins to increase from the second voltage, and the voltage of the second word line begins to increase from the third voltage.

4. The method according to any one of claims 1-3, further comprising: During the first time period, the voltage of the third word line of the storage device is increased from the first voltage to the fourth voltage, wherein the third word line is adjacent to the first word line.

5. The method according to claim 4, wherein, The memory cell coupled to the first word line is being programmed in the current programming operation, the memory cell coupled to the second word line has not yet been programmed in the current programming operation, and the memory cell coupled to the third word line has been programmed in the current programming operation.

6. The method according to claim 4, further comprising: During the second time period, the voltage of the second word line is increased from the fourth voltage to the first pass voltage; as well as During the second time period, the voltage of the third word line is increased from the fourth voltage to the second pass voltage, wherein the first pass voltage is higher than the second pass voltage.

7. The method according to claim 6, wherein, The voltage of the second word line and the voltage of the third word line simultaneously begin to increase from the fourth voltage.

8. The method according to claim 4, wherein, After the voltage of the third word line reaches the fourth voltage, the voltage of the second word line begins to increase from the third voltage.

9. The method according to any one of claims 1-8, wherein, During the first time period, the voltage of the second word line is maintained at the third voltage, and the third voltage is less than the first voltage.

10. The method according to any one of claims 1-9, wherein, The third voltage is less than or equal to 0 volts (V).

11. A storage device comprising: A storage block, the storage block including a first word line and a second word line adjacent to the first word line; as well as The peripheral circuitry includes a voltage generator and a string driver, wherein the peripheral circuitry is configured as follows: During the first time period, the voltage of the first word line is increased from the first voltage to the second voltage; During the second time period, the voltage of the first word line is increased from the second voltage to the target programming voltage; and The voltage of the second word line is increased from the third voltage to the fourth voltage, wherein the voltage of the second word line begins to increase from the third voltage after the voltage of the first word line reaches the second voltage and before the voltage of the first word line reaches the target programming voltage.

12. The storage device according to claim 11, wherein, At the beginning of the second time period, the voltage of the first word line begins to increase from the second voltage, and the voltage of the second word line begins to increase from the third voltage.

13. The storage device according to claim 11 or 12, wherein, The memory block further includes a third word line adjacent to the first word line, and wherein the peripheral circuitry is further configured as follows: During the first time period, the voltage of the third word line is increased from the first voltage to the fourth voltage.

14. The storage device according to claim 13, wherein, The memory cell coupled to the first word line is being programmed in the current programming operation, the memory cell coupled to the second word line has not yet been programmed in the current programming operation, and the memory cell coupled to the third word line has been programmed in the current programming operation.

15. The storage device according to claim 13, wherein, The peripheral circuit is also configured to: During the second time period, the voltage of the second word line is increased from the fourth voltage to the first pass voltage; and During the second time period, the voltage of the third word line is increased from the fourth voltage to the second pass voltage.

16. The storage device according to claim 15, wherein, The voltage of the second word line and the voltage of the third word line simultaneously begin to increase from the fourth voltage.

17. The storage device according to claim 13, wherein, After the voltage of the third word line reaches the fourth voltage, the voltage of the second word line begins to increase from the third voltage.

18. The storage device according to any one of claims 11-17, wherein, The third voltage is less than or equal to 0 volts (V).

19. The storage device according to any one of claims 11-18, wherein, During the first time period, the voltage of the second word line is maintained at the third voltage, and the third voltage is less than or equal to the first voltage.

20. A memory system comprising a memory device and a memory controller, the memory controller being configured to control the memory device, wherein, The storage device includes: A storage block, the storage block including a first word line and a second word line adjacent to the first word line; and The peripheral circuitry includes a voltage generator and a string driver, wherein the peripheral circuitry is configured as follows: During the first time period, the voltage of the first word line is increased from the first voltage to the second voltage; During the second time period, the voltage of the first word line is increased from the second voltage to the target programming voltage; and The voltage of the second word line is increased from the third voltage to the fourth voltage, wherein the voltage of the second word line begins to increase from the third voltage after the voltage of the first word line reaches the second voltage and before the voltage of the first word line reaches the target programming voltage.

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