A high gain high linearity amplification circuit

Abstract

This invention proposes a high-gain, high-linearity amplifier circuit, mainly comprising an input circuit and an output circuit. The input circuit has high gain, converting the received input voltage into current and amplifying it. The input circuit transmits the amplified current to the output circuit. The output circuit generates an output voltage and reduces the input impedance of the input circuit through its included feedback loop. The feedback loop in the output circuit also stabilizes the gain of the entire circuit system and optimizes the system linearity. This invention significantly improves the system gain through the amplifier circuit structure and the back-gate coupled circuit structure, and optimizes the system linearity by setting passive and active feedback loops. This invention achieves both high gain and high linearity.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically, to a high-gain, high-linearity amplifier circuit. Background Technology

[0002] In integrated circuits used for signal transmission, amplifier circuits play a crucial role, amplifying weak signals into strong signals that meet the requirements of subsequent circuits. With the continuous development of electronic technology, there are increasing demands for lower power consumption in amplifier circuits while simultaneously requiring higher gain and linearity. In traditional amplifier circuits, increasing the system gain often leads to a significant decrease in linearity, while increasing linearity increases system power consumption and reduces system gain. This difficulty in achieving both high gain and high linearity in traditional amplifier circuits greatly limits their application in integrated circuit systems. Summary of the Invention

[0003] The problem addressed by this invention is to propose a high-gain, high-linearity amplifier circuit. By significantly improving the system gain through the amplifier circuit structure and back-gate coupling circuit structure, and by setting passive and active feedback loops to reduce the system's input impedance, the system gain is stabilized, while simultaneously optimizing the system linearity. Thus, this invention achieves both high gain and high linearity.

[0004] To address the aforementioned problems, this invention proposes a high-gain, high-linearity amplifier circuit comprising an input circuit and an output circuit.

[0005] The input circuit is connected to the output circuit. The input circuit has a high gain, converting the received input voltage into current and amplifying it. The input circuit then transmits the amplified current to the output circuit.

[0006] The output circuit generates an output voltage and reduces the input impedance of the input circuit through its included feedback loop. The feedback loop in the output circuit also stabilizes the gain of the entire circuit system and optimizes the system linearity.

[0007] The input circuit includes ports VB1, VA1, VSP1, VSN1, VN1, ITN1, ITP1, NOD1, NUE1, SFP1, SFN1, BN1, BP1, FN1, and FP1.

[0008] The output circuit includes ports ITN2, ITP2, NOD2, NUE2, SFP2, SFN2, BN2, BP2, FN2, FP2, VON, and VOP.

[0009] Port VB1 is used to receive the first bias voltage Vb. Port VA1 is used to receive the second bias voltage Va. Port VSP1 is used to receive the first input voltage Vs+. Port VSN1 is used to receive the second input voltage Vs-. Port VN1 is used to receive the third bias voltage Vn. Ports ITN1 and ITN2 are connected to transmit the first current component In1. Ports ITP1 and ITP2 are connected to transmit the second current component Ip1.

[0010] Connecting ports NOD1 and NOD2 connects the first active feedback loop to input circuit mod1. Connecting ports NUE1 and NUE2 connects the second active feedback loop to input circuit mod1. Connecting ports SFP1 and SFP2 connects the third passive feedback loop to input circuit mod1. Connecting ports SFN1 and SFN2 connects the sixth passive feedback loop to input circuit mod1.

[0011] Ports BN1 and BN2 are connected to connect the second passive feedback loop to the input circuit mod1. Ports BP1 and BP2 are connected to connect the fifth passive feedback loop to the input circuit mod1. Ports FN1 and FN2 are connected to connect the first passive feedback loop to the input circuit mod1. Ports FP1 and FP2 are connected to connect the fourth passive feedback loop to the input circuit mod1. Port VON is used to output the first output voltage Vo-. Port VOP is used to output the second output voltage Vo+.

[0012] The input circuit includes a gain circuit and a coupling circuit.

[0013] The gain circuit is connected to the coupling circuit. The coupling circuit provides the bias voltage transmission path, the AC signal transmission path, and the coupling path for the gain circuit, enabling the gain circuit to operate normally and have good frequency response characteristics.

[0014] The gain circuit significantly improves the gain of the circuit system of the present invention through the cascaded amplifier circuit structure and the back gate coupling circuit structure, and reduces the power consumption of the circuit system of the present invention through the bias current multiplexing circuit structure.

[0015] The output circuit includes a load circuit and a feedback circuit.

[0016] The load circuit is connected to the feedback circuit. The load circuit generates an output voltage, and the feedback circuit feeds this output voltage back to the input circuit.

[0017] The load circuit's structure makes the output impedance of the circuit system independent of the resistance increment of the input circuit. The load circuit further increases the gain of the circuit system and generates its output voltage, which is then output to the subsequent circuitry via a port.

[0018] The feedback circuit includes both passive and active feedback loops, which are connected to the input circuit respectively. The passive feedback loop in the feedback circuit effectively reduces the input impedance of the circuit system of this invention, stabilizes the system gain, and optimizes the system linearity.

[0019] The active feedback loop in the feedback circuit further reduces the input impedance of the circuit system without sacrificing the output impedance of the circuit system of the present invention, and significantly reduces the correlation between the system noise figure and the system impedance.

[0020] Compared with existing technologies, the advantages of this invention are as follows: This invention proposes a high-gain, high-linearity amplifier circuit, including an input circuit and an output circuit. By incorporating a gain circuit in the input circuit, the system gain of this invention is greatly increased. By incorporating a coupling circuit in the input circuit, this invention possesses a complete AC feedback path and exhibits good frequency response characteristics. By incorporating a feedback circuit in the output circuit, this invention has low output impedance and high linearity. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the system structure of the present invention; Figure 2 This is a schematic diagram of the input circuit of the present invention. Figure 3 This is a schematic diagram of the output circuit of the present invention.

[0022] Explanation of reference numerals in the attached figures: mod1 - Input circuit; mod2 - Output circuit; mod1.1 - Gain circuit; mod1.2 - Coupling circuit; mod2.1 - Load circuit; mod2.2 - Feedback circuit. Detailed Implementation

[0023] like Figure 1 As shown, a high-gain, high-linearity amplifier circuit includes an input circuit mod1 and an output circuit mod2.

[0024] Input circuit mod1 is connected to output circuit mod2. Input circuit mod1 has a high gain, converting the received input voltage into current and amplifying it. Input circuit mod1 then transmits the amplified current to output circuit mod2. Output circuit mod2 generates an output voltage and reduces the input impedance of input circuit mod1 through its included feedback loop. The feedback loop in output circuit mod2 also stabilizes the gain of the entire circuit system and optimizes the system linearity.

[0025] The input circuit mod1 includes ports VB1, VA1, VSP1, VSN1, VN1, ITN1, ITP1, NOD1, NUE1, SFP1, SFN1, BN1, BP1, FN1, and FP1.

[0026] The output circuit mod2 includes ports ITN2, ITP2, NOD2, NUE2, SFP2, SFN2, BN2, BP2, FN2, FP2, VON, and VOP.

[0027] Port VB1 is used to receive the first bias voltage Vb. Port VA1 is used to receive the second bias voltage Va. Port VSP1 is used to receive the first input voltage Vs+. Port VSN1 is used to receive the second input voltage Vs-. Port VN1 is used to receive the third bias voltage Vn. Ports ITN1 and ITN2 are connected to transmit the first current component In1. Ports ITP1 and ITP2 are connected to transmit the second current component Ip1.

[0028] Connecting ports NOD1 and NOD2 connects the first active feedback loop to input circuit mod1. Connecting ports NUE1 and NUE2 connects the second active feedback loop to input circuit mod1. Connecting ports SFP1 and SFP2 connects the third passive feedback loop to input circuit mod1. Connecting ports SFN1 and SFN2 connects the sixth passive feedback loop to input circuit mod1.

[0029] Ports BN1 and BN2 are connected to connect the second passive feedback loop to the input circuit mod1. Ports BP1 and BP2 are connected to connect the fifth passive feedback loop to the input circuit mod1. Ports FN1 and FN2 are connected to connect the first passive feedback loop to the input circuit mod1. Ports FP1 and FP2 are connected to connect the fourth passive feedback loop to the input circuit mod1. Port VON is used to output the first output voltage Vo-. Port VOP is used to output the second output voltage Vo+.

[0030] like Figure 1 As shown, the input circuit mod1 includes a gain circuit mod1.1 and a coupling circuit mod1.2.

[0031] Gain circuit mod1.1 is connected to coupling circuit mod1.2. Coupling circuit mod1.2 provides a bias voltage transmission path, a signal transmission AC path, and a coupling path for gain circuit mod1.1, enabling gain circuit mod1.1 to operate normally and exhibit good frequency response characteristics. Gain circuit mod1.1 significantly improves the gain of the circuit system of the present invention through cascaded amplifier circuit structure and back-gate coupling circuit structure, and reduces the power consumption of the circuit system of the present invention through bias current multiplexing circuit structure.

[0032] like Figure 1 As shown, the output circuit mod2 includes the load circuit mod2.1 and the feedback circuit mod2.2.

[0033] Load circuit mod2.1 is connected to feedback circuit mod2.2. Load circuit mod2.1 generates an output voltage, while feedback circuit mod2.2 feeds this output voltage back to input circuit mod1. The circuit structure of load circuit mod2.1 ensures that the output impedance of the circuit system of this invention is independent of the resistance increment of input circuit mod1. Load circuit mod2.1 further increases the gain of the circuit system of this invention and generates the output voltage of the circuit system of this invention, which is output to the subsequent circuit through the port.

[0034] Feedback circuit mod2.2 includes both passive and active feedback loops, which are connected to input circuit mod1 respectively. The passive feedback loop in feedback circuit mod2.2 effectively reduces the input impedance of the circuit system, stabilizes the system gain, and optimizes the system linearity. The active feedback loop in feedback circuit mod2.2 further reduces the input impedance of the circuit system without sacrificing its output impedance and significantly reduces the correlation between the system noise figure and the system impedance.

[0035] like Figure 2 As shown, the gain circuit mod1.1 includes field-effect transistors MF1, MF2, MF3, MF4, MF5, MF6, MF7, MF8, port VB1, port FP1, port FN1, port BP1, port BN1, port VTN1, and port VTP1.

[0036] The source of MOSFET MF1 is connected to power supply VDD, the gate of MOSFET MF1 is connected to port VB1, and the drain of MOSFET MF1 is connected to the source of MOSFET MF2. The source of MOSFET MF2 is connected to port FP1, the gate of MOSFET MF2 is connected to the upper end of capacitor C1, the drain of MOSFET MF2 is connected to the drain of MOSFET MF3, and the substrate of MOSFET MF2 is connected to the source of MOSFET MF6. The drain of MOSFET MF3 is connected to port ITN1, the gate of MOSFET MF3 is connected to the right end of capacitor C2, the source of MOSFET MF3 is connected to the drain of MOSFET MF4, and the substrate of MOSFET MF3 is connected to the source of MOSFET MF7. The drain of MOSFET MF4 is connected to port BP1, the gate of MOSFET MF4 is connected to port VA1, and the source of MOSFET MF4 is grounded.

[0037] The source of MOSFET MF5 is connected to the source of MOSFET MF1, the gate of MOSFET MF5 is connected to the gate of MOSFET MF1, and the drain of MOSFET MF5 is connected to the source of MOSFET MF6. The source of MOSFET MF6 is connected to port FN1, the gate of MOSFET MF6 is connected to the upper end of capacitor C3, the drain of MOSFET MF6 is connected to the drain of MOSFET MF7, and the substrate of MOSFET MF6 is connected to the source of MOSFET MF2. The drain of MOSFET MF7 is connected to port ITP1, the gate of MOSFET MF7 is connected to the left end of capacitor C4, the source of MOSFET MF7 is connected to the drain of MOSFET MF8, and the substrate of MOSFET MF7 is connected to the source of MOSFET MF3. The drain of MOSFET MF8 is connected to port BN1, the gate of MOSFET MF8 is connected to the gate of MOSFET MF4, and the source of MOSFET MF8 is grounded.

[0038] The gate of field-effect transistor MF3 is connected to port VSP1 via capacitor C2, receiving the first input voltage Vs+. Based on its common-source amplification structure, the first input voltage Vs+ is converted into the drain current Idmf3 of field-effect transistor MF3. The gate of field-effect transistor MF7 is connected to port VSN1 via capacitor C4, receiving the second input voltage Vs-. Based on its common-source amplification structure, the second input voltage Vs- is converted into the drain current Idmf7 of field-effect transistor MF7. The first input voltage Vs+ and the second input voltage Vs- form a differential input voltage pair.

[0039] The drain of MOSFET MF2 is connected to the drain of MOSFET MF3, achieving bias current multiplexing. Based on its common-gate amplification structure, this reduces the power consumption of the input circuit mod1 system while improving its output impedance and gain. The drain of MOSFET MF6 is connected to the drain of MOSFET MF7, achieving bias current multiplexing. Based on its common-gate amplification structure, this reduces the power consumption of the input circuit mod1 system while improving its output impedance and gain.

[0040] The substrate of MOSFET MF3 is connected to the source of MOSFET MF7, and the substrate of MOSFET MF7 is connected to the source of MOSFET MF3. The substrate of MOSFET MF2 is connected to the source of MOSFET MF6, and the substrate of MOSFET MF6 is connected to the source of MOSFET MF2. MOSFETs MF3, MF7, MF2, and MF6, along with capacitors C1, C2, C3, and C4, are interconnected to form a back-gate coupled structure. This back-gate modulation effect introduces an additional signal path, increasing the transconductance of the input circuit mod1 system, thereby improving the system gain. Simultaneously, it suppresses nonlinear distortion caused by the nonlinear characteristics of the MOSFETs through positive feedback enhancement.

[0041] The drain of MOSFET MF1 is connected to the source of MOSFET MF2, sharing the same bias current. This reduces system power consumption, further improves system gain, and optimizes system noise performance. Similarly, the drain of MOSFET MF5 is connected to the source of MOSFET MF6, sharing the same bias current. This reduces system power consumption, further improves system gain, and optimizes system noise performance.

[0042] Field-effect transistors MF4 and MF3 are connected to provide a stable bias current for MF3, MF2, and MF1, enabling them to operate normally. Field-effect transistors MF8 and MF7 are connected to provide a stable bias current for MF7, MF6, and MF5, enabling them to operate normally.

[0043] The drain of MOSFET MF3 is connected to port ITN1. The first current component In1 of the drain-source branch of MOSFET MF3 is output to the output circuit mod2 through port ITN1. The drain of MOSFET MF7 is connected to port ITP1. The second current component Ip1 of the drain-source branch of MOSFET MF7 is output to the output circuit mod2 through port ITP1.

[0044] like Figure 2As shown, the coupling circuit mod1.2 includes resistors R1, R2, R3, and R4, capacitors C1, C2, C3, and C4, and ports VA1, VSP1, NOD1, SFP1, VN1, NUE1, VSN1, and SFN1.

[0045] The left end of resistor R1 is connected to port VA1, and the right end of resistor R1 is connected to the gate of MOSFET MF2. The upper end of capacitor C1 is connected to the gate of MOSFET MF2, and the lower end of capacitor C1 is connected to the gate of MOSFET MF3. The left end of capacitor C2 is connected to port VSP1, port NOD1, and port SFP1, and the right end of capacitor C2 is connected to the gate of MOSFET MF3. The left end of resistor R2 is connected to port VN1, and the right end of resistor R2 is connected to the lower end of capacitor C1.

[0046] The left end of resistor R3 is connected to the left end of resistor R1, and the right end of resistor R3 is connected to the gate of MOSFET MF6. The upper end of capacitor C3 is connected to the gate of MOSFET MF6, and the lower end of capacitor C3 is connected to the gate of MOSFET MF7. The right end of capacitor C4 is connected to port VSN1, port NUE1, and port SFN1, and the left end of capacitor C4 is connected to the gate of MOSFET MF7. The left end of resistor R4 is connected to the left end of resistor R2, and the right end of resistor R4 is connected to the lower end of capacitor C3.

[0047] Port VA1 provides bias voltage to MOSFET MF2 through resistor R1. Port VA1 provides bias voltage to MOSFET MF6 through resistor R3. Port VA1 also provides bias voltage to MOSFETs MF4 and MF8. The first input voltage Vs+ is input to input circuit mod1 through port VSP1. The second input voltage Vs- is input to input circuit mod1 through port VSN1. Port VN1 provides bias voltage to MOSFET MF3 through resistor R2. Port VN1 also provides bias voltage to MOSFET MF7 through resistor R4.

[0048] Capacitor C2 is connected to the gate of MOSFET MF3, forming an AC signal path between MOSFET MF3 and ports VSP1, NOD1, and SFP1. Capacitor C4 is connected to the gate of MOSFET MF7, forming an AC signal path between MOSFET MF7 and ports NUE1, VSN1, and SFN1. Capacitor C1 is connected to the gates of MOSFETs MF2 and MF3 respectively, forming a coupling path to optimize the high-frequency response characteristics of input circuit mod1.

[0049] like Figure 3As shown, the load circuit mod2.1 includes MOSFET MS1, MOSFET MS2, resistor R7, resistor R8, port ITN2, port ITP2, port VON, and port VOP.

[0050] The upper end of resistor R7 is connected to the power supply VDD, and the lower end of resistor R7 is connected to the drain of MOSFET MS1. The drain of MOSFET MS1 is connected to port VON, the gate of MOSFET MS1 is connected to the power supply VHG, and the source of MOSFET MS1 is connected to port ITN2. The upper end of resistor R8 is connected to the upper end of resistor R7, and the lower end of resistor R8 is connected to the drain of MOSFET MS2. The drain of MOSFET MS2 is connected to port VOP, the gate of MOSFET MS2 is connected to the power supply VHG, and the source of MOSFET MS2 is connected to port ITP2.

[0051] The gates of field-effect transistors MS1 and MS2 are connected to the power supply VHG to obtain a bias voltage, and the power supply VHG voltage is greater than the power supply VDD voltage. The connection structure of field-effect transistors MS1 and MS2 further increases the system gain and participates in the optimization of system linearity. The source of field-effect transistor MS1 is connected to port ITN2, receiving the first current component In1 output from input circuit mod1, and through its drain, the first current component In1 flows into resistor R7. The source of field-effect transistor MS2 is connected to port ITP2, receiving the second current component Ip1 output from input circuit mod1, and through its drain, the second current component Ip1 flows into resistor R8.

[0052] The circuit structure formed by interconnecting MOSFETs MS1 and MS2, resistors R7 and R8 ensures that the output impedance of the circuit system of this invention is independent of the incremental resistances of MOSFETs MF2, MF3, MF6, and MF7. The lower end of resistor R7 is connected to port VON, acting as a load resistor. The current in its branch is converted into the first output voltage Vo-, which is output through port VON. The lower end of resistor R8 is connected to port VOP, acting as a load resistor. The current in its branch is converted into the second output voltage Vo+, which is output through port VOP. The circuit system of this invention has a dual-ended output, with the output voltage Vo = Vo+ - Vo-.

[0053] like Figure 3 As shown, the feedback circuit mod2.2 includes field-effect transistors MT1, MT2, MT3, and MT4, resistors R5, R6, R9, and R10, capacitors C5, C6, C7, C8, C9, and C10, and ports NOD2, SFP2, BN2, FN2, NUE2, SFN2, BP2, and FP2.

[0054] The upper end of resistor R5 is connected to power supply VHG, and the lower end of resistor R5 is connected to the gate of MOSFET MT1. The drain of MOSFET MT1 is connected to power supply VDD, the gate of MOSFET MT1 is connected to the left end of capacitor C6, and the source of MOSFET MT1 is connected to the drain of MOSFET MT2. The drain of MOSFET MT2 is connected to port NOD2, the gate of MOSFET MT2 is connected to the drain of MOSFET MT2, and the source of MOSFET MT2 is grounded. The left end of capacitor C6 is connected to the lower end of resistor R5, and the right end of capacitor C6 is connected to the lower end of resistor R7. The upper end of capacitor C5 is connected to port SFP2, and the lower end of capacitor C5 is connected to port BN2. The upper end of capacitor C7 is connected to port SFP2, and the lower end of capacitor C7 is connected to port FN2. The left end of resistor R6 is connected to port SFP2, and the right end of resistor R6 is connected to the lower end of resistor R7.

[0055] The upper end of resistor R10 is connected to the upper end of resistor R5, and the lower end of resistor R10 is connected to the gate of MOSFET MT3. The drain of MOSFET MT3 is connected to power supply VDD, the gate of MOSFET MT3 is connected to the left end of capacitor C8, and the source of MOSFET MT3 is connected to the drain of MOSFET MT4. The drain of MOSFET MT4 is connected to port NUE2, the gate of MOSFET MT4 is connected to the drain of MOSFET MT4, and the source of MOSFET MT4 is grounded. The left end of capacitor C8 is connected to the lower end of resistor R8, and the right end of capacitor C8 is connected to the lower end of resistor R10. The upper end of capacitor C10 is connected to port SFN2, and the lower end of capacitor C10 is connected to port BP2. The upper end of capacitor C9 is connected to the upper end of capacitor C10, and the lower end of capacitor C9 is connected to port FP2. The right end of resistor R9 is connected to the upper end of capacitor C9, and the left end of resistor R9 is connected to the lower end of resistor R8.

[0056] Port VON is connected to resistor R6, which in turn connects to capacitor C7. Capacitor C7 is connected to port FN2, and port FN2 is connected to port FN1 of input circuit mod1, thus forming the first passive feedback loop. Port VON is also connected to resistor R6, which in turn connects to capacitor C5. Capacitor C5 is connected to port BN2, and port BN2 is connected to port BN1 of input circuit mod1, thus forming the second passive feedback loop. Finally, port VON is connected to resistor R6, which in turn connects to port SFP2. Port SFP2 is connected to port SFP1 of input circuit mod1, thus forming the third passive feedback loop.

[0057] Port VOP is connected to resistor R9, which in turn is connected to capacitor C9. Capacitor C9 is connected to port FP2, and port FP2 is connected to port FP1 of input circuit mod1, thus forming the fourth passive feedback loop. Port VOP is connected to resistor R9, which in turn is connected to capacitor C10. Capacitor C10 is connected to port BP2, and port BP2 is connected to port BP1 of input circuit mod1, thus forming the fifth passive feedback loop. Port VOP is connected to resistor R9, which in turn is connected to port SFN2, and port SFN2 is connected to port SFN1 of input circuit mod1, thus forming the sixth passive feedback loop. The above first to sixth passive feedback loops can effectively reduce the input impedance of the circuit system of the present invention, stabilize the system gain, optimize the system linearity, and suppress third-order intermodulation distortion.

[0058] The power supply VHG is connected to the gate of the field-effect transistor MT1 through resistor R5, providing a bias voltage for MT1. The output terminal VON is connected to capacitor C6, which is connected to the gate of MT1. The source of MT1 is connected to the drain of MT2, and the source of MT1 is connected to port NOD2. Port NOD2 is connected to port NOD1 of the input circuit mod1, thus forming the first active feedback loop.

[0059] The power supply VHG is connected to the gate of MOSFET MT3 via resistor R10, providing a bias voltage for MOSFET MT3. The output terminal VOP is connected to capacitor C8, which is connected to the gate of MOSFET MT3. The source of MOSFET MT3 is connected to the drain of MOSFET MT4, and the source of MOSFET MT3 is connected to port NUE2. Port NUE2 is connected to port NUE1 of the input circuit mod1, thus forming a second active feedback loop.

[0060] The first and second active feedback loops utilize their active feedback characteristics to further reduce the input impedance of the circuit system without sacrificing its output impedance. Furthermore, the active devices in the first and second active feedback loops exhibit low device noise, significantly reducing the correlation between the system noise figure and system impedance.

[0061] like Figure 2 and Figure 3 As shown, field-effect transistors MF1, MF2, MF3, and MF4 are connected to form the first input branch. Based on the port connections, the first input branch is connected to the third, fourth, and fifth passive feedback loops, respectively. Under the influence of the passive feedback loops and the first input voltage Vs+, the current Iz flowing through the first input branch is expressed as shown in equations (1) and (2).

[0062] (1); (2); In the formula, Vz is the voltage value of the first input voltage Vs+, r7 is the resistance value of resistor R7, r6 is the resistance value of resistor R6, gf3 is the transconductance of field-effect transistor MF3, gbf3 is the transconductance introduced by the body effect of field-effect transistor MF3, gf2 is the transconductance of field-effect transistor MF2, and gbf2 is the transconductance introduced by the body effect of field-effect transistor MF2.

[0063] Based on formulas (1) and (2), the input impedance Zp of the first input branch under the action of the passive feedback loop can be further obtained. The expression of the input impedance Zp is shown in formula (3).

[0064] (3); In formula (3), Vz is the voltage value of the first input voltage Vs+, Iz is the current flowing through the first input branch, r7 is the resistance value of resistor R7, r6 is the resistance value of resistor R6, and Gz is the sum of the transconductance of the field-effect transistor.

[0065] like Figure 2 and Figure 3 As shown, the first active feedback loop is connected to the first input branch through the connection of port NOD1 and port NOD2, and an impedance Zps is introduced into the first input branch. The expression of the impedance Zps is shown in formula (4).

[0066] (4); In the formula, gt1 is the transconductance of MT1, and Af3 is the gain of the amplifier circuit composed of MF3.

[0067] like Figure 2 and Figure 3 As shown, the input impedance Z1 of the circuit system of the present invention as seen from port VSP1 is the parallel value of the input impedance Zp and the impedance Zps. The expression of the input impedance Z1 is shown in formula (5).

[0068] ; In the formula, r7 is the resistance value of resistor R7, r6 is the resistance value of resistor R6, Gz is the sum of the transconductances of the field-effect transistors, gt1 is the transconductance of field-effect transistor MT1, and Af3 is the gain of the amplifier circuit section composed of field-effect transistor MF3.

[0069] As can be seen from the expression for the input impedance Z1, under the action of the active feedback loop and the passive feedback loop in the circuit system of the present invention, the input impedance Z1 of the circuit system of the present invention is significantly reduced compared with the input impedance of the single-sided input port of the traditional dual-input dual-output amplifier circuit.

[0070] like Figure 2 and Figure 3 As shown, the circuit structure of the circuit system of the present invention significantly improves the gain of the system. Taking into full account the noise source, the expression of the gain Au of the circuit system of the present invention is shown in formula (6).

[0071] (6); In the formula, Vo is the voltage value of the first output voltage Vo-, Vz is the voltage value of the first input voltage Vs+, Rs is the parallel resistance value of resistors R6 and R7, Gz is the sum of the transconductances of the field-effect transistors (Gz=gf3+gbf3+gf2+gbf2), r6 is the resistance value of resistor R6, cl is the parasitic capacitance value of output circuit mod2 at the output terminal, s is the complex frequency variable, Cms1 is the gate-source parasitic capacitance value of field-effect transistor MS1, and gs1 is the transconductance of field-effect transistor MS1.

[0072] like Figure 2 and Figure 3 As shown, the circuit configuration of gain circuit mod1.1, coupling circuit mod1.2, and feedback circuit 2.2 in the circuit system of the present invention significantly improves the linearity of the system. The expressions for the 1dB compression point voltage Vpb and the third-order cutoff point voltage Vp3 of the circuit system of the present invention are shown in formulas (7), (8), and (9).

[0073] (7); (8); (9); In the formula, Vgt3 is the difference between the gate-source voltage and the threshold voltage of the field-effect transistor MF3, gs1 is the transconductance of the field-effect transistor MS1, λ is the channel length modulation coefficient of the field-effect transistor, Gz is the sum of the transconductances of the field-effect transistors, Kf is the feedback factor, and Af3 is the gain of the amplifier circuit section composed of the field-effect transistor MF3.

[0074] As can be seen from equations (7) and (9), the 1dB compression point voltage Vpb and the third-order cutoff voltage Vp3 of the circuit system of the present invention are higher than those of the conventional dual-input dual-output amplifier circuit without feedback loop. This indicates that the circuit system of the present invention has better linearity. As can be seen from equations (6), (7), and (9), the circuit system of the present invention has both high gain and high linearity.

Claims

1. A high gain, high linearity amplification circuit, characterized by, It includes an input circuit (mod1) and an output circuit (mod2); The input circuit (mod1) is connected to the output circuit (mod2). The input circuit (mod1) has a high gain and converts the received input voltage into current and amplifies it. The input circuit (mod1) transmits the amplified current to the output circuit (mod2); The output circuit (mod2) generates an output voltage and reduces the input impedance of the input circuit (mod1) through its included feedback loop; The feedback loop included in the output circuit (mod2) can also stabilize the gain of the entire circuit system and optimize the system linearity.

2. The high-gain, high-linearity amplifier circuit according to claim 1, characterized in that, The input circuit (mod1) includes a gain circuit (mod1.1) and a coupling circuit (mod1.2). The gain circuit (mod1.1) is connected to the coupling circuit (mod1.2). The coupling circuit (mod1.2) constructs a bias voltage transmission path, a signal transmission AC path, and a coupling path for the gain circuit (mod1.1), enabling the gain circuit (mod1.1) to work normally and have good frequency response characteristics. The gain circuit (mod1.1) significantly improves the gain of the circuit system of the present invention through the cascaded amplifier circuit structure and the back gate coupling circuit structure, and reduces the power consumption of the circuit system of the present invention through the bias current multiplexing circuit structure.

3. The high-gain, high-linearity amplifier circuit according to claim 1, characterized in that, The output circuit (mod2) includes a load circuit (mod2.1) and a feedback circuit (mod2.2). The load circuit (mod2.1) is connected to the feedback circuit (mod2.2). The load circuit (mod2.1) generates an output voltage, and the feedback circuit (mod2.2) feeds this output voltage back to the input circuit (mod1). The circuit structure of the load circuit (mod2.1) makes the output impedance of the circuit system of the present invention independent of the resistance increment of the input circuit (mod1); the load circuit (mod2.1) further improves the gain of the circuit system of the present invention and generates the output voltage of the circuit system of the present invention, which is output to the subsequent circuit through the port; The feedback circuit (mod2.2) includes both passive and active feedback loops, which are connected to the input circuit (mod1) respectively. The passive feedback loop in the feedback circuit (mod2.2) effectively reduces the input impedance of the circuit system of the present invention, stabilizes the system gain, and optimizes the system linearity. The active feedback loop in the feedback circuit (mod2.2) further reduces the input impedance of the circuit system without sacrificing the output impedance of the circuit system of the present invention, and significantly reduces the correlation between the system noise figure and the system impedance.

4. The high-gain, high-linearity amplifier circuit according to claim 2, characterized in that, The gain circuit (mod1.1) includes field-effect transistors MF2, MF3, MF6, and MF7; The gate of the field-effect transistor MF3 is connected to port VSP1 through capacitor C2 to receive the first input voltage, and based on its common-source amplification structure, the first input voltage is converted into the drain current of the field-effect transistor MF3; the gate of the field-effect transistor MF7 is connected to port VSN1 through capacitor C4 to receive the second input voltage, and based on its common-source amplification structure, the second input voltage is converted into the drain current of the field-effect transistor MF7. The substrate of field-effect transistor MF3 is connected to the source of field-effect transistor MF7, and the substrate of field-effect transistor MF7 is connected to the source of field-effect transistor MF3. The substrate of MOSFET MF2 is connected to the source of MOSFET MF6, and the substrate of MOSFET MF6 is connected to the source of MOSFET MF2. MOSFETs MF3, MOSFET MF7, MOSFET MF2, MOSFET MF6, capacitors C1, C2, C3, and C4 are interconnected to form a back-gate coupling structure. The back-gate modulation effect introduces an additional signal path, increases the transconductance of the input circuit (mod1) system, and thus improves the system gain. At the same time, it suppresses the nonlinear distortion caused by the nonlinear characteristics of the MOSFETs in the form of positive feedback enhancement.

5. A high-gain, high-linearity amplifier circuit according to claim 3, characterized in that, The feedback circuit (mod2.2) includes resistor R6, resistor R9, capacitor C5, capacitor C7, capacitor C9, capacitor C10, port SFP2, port BN2, port FN2, port SFN2, port BP2, and port FP2; Port VON is connected to resistor R6, resistor R6 is connected to capacitor C7, capacitor C7 is connected to port FN2, and port FN2 is connected to port FN1 of the input circuit (mod1), thus forming the first passive feedback loop; Port VON is connected to resistor R6, resistor R6 is connected to capacitor C5, capacitor C5 is connected to port BN2, and port BN2 is connected to port BN1 of the input circuit (mod1), thus forming the second passive feedback loop; Port VON is connected to resistor R6, resistor R6 is connected to port SFP2, and port SFP2 is connected to port SFP1 of the input circuit (mod1), thus forming the third passive feedback loop; Port VOP is connected to resistor R9, resistor R9 is connected to capacitor C9, capacitor C9 is connected to port FP2, and port FP2 is connected to port FP1 of the input circuit (mod1), thus forming the fourth passive feedback loop; Port VOP is connected to resistor R9, resistor R9 is connected to capacitor C10, capacitor C10 is connected to port BP2, and port BP2 is connected to port BP1 of the input circuit (mod1), thus forming the fifth passive feedback loop; Port VOP is connected to resistor R9, resistor R9 is connected to port SFN2, and port SFN2 is connected to port SFN1 of the input circuit (mod1), thus forming the sixth passive feedback loop.

6. A high-gain, high-linearity amplifier circuit according to claim 3, characterized in that, The feedback circuit (mod2.2) includes field-effect transistors MT1, MT2, MT3, and MT4, resistors R5 and R10, capacitors C6 and C8, port NOD2, and port NUE2. The power supply VHG is connected to the gate of the field-effect transistor MT1 through resistor R5, providing a bias voltage for the field-effect transistor MT1; the output terminal VON is connected to capacitor C6, capacitor C6 is connected to the gate of the field-effect transistor MT1, the source of the field-effect transistor MT1 is connected to the drain of the field-effect transistor MT2, and the source of the field-effect transistor MT1 is connected to port NOD2, and port NOD2 is connected to port NOD1 of the input circuit (mod1), thus forming the first active feedback loop; The power supply VHG is connected to the gate of the field-effect transistor MT3 through resistor R10, providing a bias voltage for MT3; the output terminal VOP is connected to capacitor C8, which is connected to the gate of MT3; the source of MT3 is connected to the drain of MT4; and the source of MT3 is connected to port NUE2, which is connected to port NUE1 of the input circuit (mod1), thus forming a second active feedback loop.

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