Stage multi-modal signal synchronous calibration and low-delay transmission method and system

Abstract

This invention belongs to the field of multiplexed communication technology. Specifically, it discloses a method and system for stage multi-mode signal synchronization calibration and low-latency transmission, comprising: At the transmitting end, a hardware frequency and phase detector quantizes the phase difference of each mode signal and converts it into a quantized bit length parameter, thereby generating a physical recording sequence containing a compliance prefix and fixed anomaly markers. This sequence is concatenated with line-encoded service data and idle codes to form a continuous baseband bitstream without a protocol header. At the receiving end, the recovered clock-driven bitstream is extracted and shifted without software buffering in a multi-tap shift register array. A logic gate array hard-matches the anomaly marker boundaries and outputs a synchronization trigger pulse, triggering the gating gate to synchronously release the decoded data of each mode. This invention eliminates protocol stack and software buffer delays, reducing synchronization errors across media devices.

Description

Technical Field

[0001] This invention belongs to the field of multiplexed communication technology, and relates to a method and system for stage multimodal signal synchronization calibration and low-latency transmission. Background Technology

[0002] Large-scale stage performances, live concerts, and theme park shows typically require the coordinated control of multiple types of performance equipment, such as large-scale LED displays, line array sound systems, computer-controlled lighting, special effects machinery, and kinetic sculptures. The signals generated by these devices differ significantly in physical form, data format, clock frequency, and transmission protocols, constituting independent modal data streams. In current industry practice, ensuring that these multimodal signals achieve synchronization that matches the auditory and visual experience in the final presentation is a pressing technical challenge.

[0003] Currently, the industry commonly employs a traditional layered overlay solution to handle the synchronization and transmission of such multimodal signals. This solution first relies on an independent system-level synchronization network, such as a network clock distribution system based on the IEEE 1588 precision time protocol or GPS timing, to provide a common logical time reference source for the local clocks of each subsystem. Subsequently, various modal signals are timestamped or encapsulated into formats conforming to network transmission protocols at the application layer or session layer, such as using Ethernet audio / video bridging technology or media streams based on real-time transmission protocols, and then distributed through standard network switching equipment. At the receiving end, each terminal device uses the timestamp information carried in the received data packets, combined with its local synchronization clock, to perform large-capacity buffering and flexible decoding of the data, aiming to realign the data streams at playback time.

[0004] However, this traditional approach, relying on abstract protocol parsing and software clock recovery, introduces microsecond-level uncertainties when facing the demands of ultra-low latency and precise synchronization in stage performances. First, the dynamic transmission delays and random jitter introduced at each stage—from the generation of physical layer signals to the marking of application layer timestamps, and then to the encapsulation and decapsulation of the network protocol stack—typically reach hundreds of microseconds or even milliseconds. This makes it difficult to meet the requirements of technical standards such as SMPTE ST2110, which require video and audio-related jitter control at the microsecond or even sub-microsecond level. Second, packet-based switching networks inherently possess uncertainties. Factors such as queue scheduling and routing oscillations can lead to differences in the transmission paths or waiting times of various modal data packets. Even with buffers at the receiving end, the time base accuracy and processing load of software compensation algorithms are limited by the local processor's responsiveness, potentially leading to technical problems such as "lip-sync asynchrony" or lighting lag behind the video feed in complex scenarios. Furthermore, this "layered first, then synchronized" architecture requires the deployment of complex precision clock servers and switches with corresponding protocol processing capabilities, increasing system integration redundancy and cost, and failing to make good use of the deterministic latency potential provided by direct transmission at the physical layer. Summary of the Invention

[0005] In order to overcome the above-mentioned defects of the prior art and to achieve the above objectives, the present invention proposes the following technical solution: a method for synchronous calibration and low-latency transmission of stage multimodal signals, comprising: S1, receiving stage multimodal signals, comparing the arrival time of the stage multimodal signals with the edge of a preset reference clock, and outputting the time span difference.

[0006] S2. Using the time span difference as the reverse compensation transmission time, and ensuring that the equivalent bit length is greater than the preset waveform defect mark length, divide the reverse compensation transmission time by the physical time consumption constant of single-bit level transmission and round it to generate the quantized bit length parameter.

[0007] S3. Generate a blank bit sequence with a bit count equal to the quantization bit length parameter. Inject a number of consecutive same-level signals at the end of the blank bit sequence that is greater than the maximum number of consecutive same-level signals allowed by the communication protocol to generate an asymmetric base level. Combine these signals to generate a physical recording sequence.

[0008] S4. Extract payload data frames from stage multimodal signals, attach the physical recording sequence to the payload data frames to generate mixed data, and splice the mixed data to generate a continuous baseband bit stream.

[0009] S5. Receive the continuous baseband bit stream, extract the recovery baud rate clock and output the cleaned bit stream, and use the recovery baud rate clock to drive the cleaned bit stream to shift step by step in the shift register array.

[0010] S6. Use a logic gate array to monitor the purified bit stream and output a synchronous trigger pulse when it matches the asymmetric base level.

[0011] S7. Transmit the payload data frame output from the shift register array and reside in the front end of the preset gating isolation gate. Use the synchronous trigger pulse to trigger the preset gating isolation gate to turn on and release the payload data frame residing in the front end of the gating isolation gate.

[0012] The second aspect of the present invention provides a stage multimodal signal synchronization calibration and low-latency transmission system, comprising: a signal synchronization preprocessing module, which receives stage multimodal signals, compares the arrival time of the stage multimodal signals with the edge of a preset reference clock, and outputs the time span difference.

[0013] The delay compensation mapping module uses the time span difference as the reverse compensation transmission time. Under the premise of ensuring that the equivalent bit length is greater than the preset waveform defect mark length, the reverse compensation transmission time is divided by the physical time consumption constant of single bit level transmission and rounded to generate the quantized bit length parameter.

[0014] The baseband recording sequence generation module generates a blank bit sequence with a bit count equal to the quantization bit length parameter. At the end of the blank bit sequence, a number of consecutive same-level signals exceeding the maximum number of consecutive same-level signals allowed by the communication protocol are injected to generate an asymmetric base level. These signals are then combined to generate the physical recording sequence.

[0015] The time-division multiplexing framing and transmission module extracts payload data frames from the stage multimodal signal, appends the physical recording sequence to the payload data frames to generate mixed data, and splices the mixed data to generate a continuous baseband bit stream.

[0016] The clock data recovery and shift throughput module receives a continuous baseband bit stream, extracts the recovered baud rate clock and outputs a clean bit stream, and uses the recovered baud rate clock to drive the clean bit stream to shift step by step in the shift register array.

[0017] The waveform breaking detection module uses a logic gate array to monitor the purified bit stream and outputs a synchronous trigger pulse when it matches an asymmetric base level.

[0018] Finally, the gating isolation module transmits the payload data frame output from the shift register array to the front end of the preset gating isolation gate, and uses the synchronous trigger pulse to trigger the conduction of the preset gating isolation gate, releasing the payload data frame residing in front of the gating isolation gate.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The time span difference generated by the present invention can directly compare the timing of the trigger edge of the multi-mode signal at the physical layer interface with the main edge of the global reference clock through a hardware polarity clock frequency and phase detector, and quantify the independent time drift of each mode signal. This mechanism avoids the software delay and processing jitter introduced by time marking through the protocol stack, and provides accurate input parameters with picosecond resolution that reflect the real timing state of the physical link for subsequent compensation, thereby realizing the time capture of multi-mode signals at the physical source.

[0020] (2) Based on the inherent clock period of the originating master baud rate clock and the physical time constant of single-bit level transmission, this invention directly converts the inverse compensation time, which characterizes time drift, into a quantized bit length parameter equivalent to the blank bit sequence required to compensate for that time through pure hardware frequency division. This method of reducing the abstract delay to the physical link space bit length allows subsequent compensation operations to be performed in a purely hardware logic-based manner, avoiding the processing overhead and uncertainty caused by software calculation of the compensation amount, and ensuring that the compensation process is synchronized with the physical layer of the physical transmission line speed.

[0021] (3) This invention constructs a physical recording sequence carrying a dedicated waveform defect marker. This sequence consists of a defined continuous non-alternating level signal, and at its end, an asymmetric base level that breaks the DC balance limitation of the standard communication protocol is embedded. This method of recording abnormal signaling at the physical layer constructs a trigger identifier that can be directly recognized by pure combinational logic hardware without frame parsing. This allows the receiving end to locate the synchronization trigger point in the signal flow level sequence in real time with a mechanism without software buffering and CPU intervention, thereby avoiding delay fluctuations caused by data packet splitting and protocol analysis.

[0022] (4) This invention deploys a multi-tap shift register array composed entirely of hardware cascades at the receiving end, and configures a dedicated waveform defect detection combinational logic gate array that works in parallel with it. This architecture enables the received continuous baseband bit stream to flow and advance in its silicon structure at the original physical line speed, while the logic gate array achieves instantaneous hard matching of waveform defect markers through bypass monitoring. This process does not cause any pause or buffering in the data stream. Once the matching is successful, a synchronous trigger pulse is output transiently. This pulse triggers the conduction of the last-stage gating isolation gate of each modal terminal device based on hardware logic, thereby reducing relative drift and enabling the synchronous release accuracy to reach the picosecond level of gate delay. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the implementation steps of the method of the present invention.

[0025] Figure 2 This is a schematic diagram of the system module connections of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Please see Figure 1 As shown, the stage multimodal signal synchronization calibration and low-latency transmission method proposed in this invention includes: S1, receiving stage multimodal signals, comparing the arrival time of the stage multimodal signals with the edge of a preset reference clock, and outputting the time span difference.

[0028] In a preferred embodiment, the time span difference is output by comparing the arrival time of the stage multimodal signal with the edge of a preset reference clock. Specifically, the stage multimodal signal is input into a hardware polarity clock frequency and phase detector, which captures the physical arrival time of the stage multimodal signal transition. The time-to-digital converter inside the hardware polarity clock frequency and phase detector is started to start timing until the edge of the preset reference clock is reached, and the timing stops. The time span difference recorded by the time-to-digital converter is then output.

[0029] Specifically, step S1 of this invention is executed by a signal synchronization preprocessing module deployed at the transmitting end. This module aims to phase-lock stage multimodal signals from different physical sources and clock domains with a unified local time reference and quantify their time drift. This module accesses the raw signal outputs from various stage performance equipment via a dedicated physical data channel. This dedicated physical data channel is, for example, directly connected to the module's front-end interface. Before accessing the input / output (I / O) pins of a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC), various multimodal signals must first undergo impedance matching and signal conditioning through a preset physical layer adaptation front-end circuit, converting them into a unified internal logic level (e.g., LVDS or LVCMOS). This bypasses the standard network protocol stack, achieving physical layer pass-through capture of the signals. The acquired stage multimodal signals refer to a collection of various signal streams with different physical characteristics and data formats that work collaboratively in the same stage performance scene. These include digital audio signal streams, serial digital interface video signals, lighting control bus data, and digital position feedback pulses from mechanical actuators.

[0030] Subsequently, the hardware polarity clock and phase detector integrated within this module performs precise capture of the physical arrival time for each modal signal channel. Specifically, this hardware polarity clock and phase detector is a parallel array of time-to-digital converters (TDCs) implemented entirely in hardware logic. Its reference clock input is uniformly connected to a global reference clock generated by a local high-precision crystal oscillator. The global reference clock is a local, high-stability clock source assembled internally by the transmitting device, independent of external network clock sources, such as a 250MHz temperature-compensated crystal oscillator (TCXO). The clock signal it generates has a period of 4ns, and this clock serves as the unified time reference for the entire transmitting end processing flow. When a critical timing edge of any stage multimodal signal, such as the rising edge of the frame sync pulse in a video signal, the start edge of the digital audio word clock, or a position trigger pulse level change in a mechanical encoder, reaches the corresponding physical input pin, this event is used as the start (START) trigger signal for the corresponding TDC. Through this hardware direct sampling method, within the hardware polarity clock phase detector, the precise physical arrival time is recorded when a specific trigger edge of the m-th mode signal crosses the logic level threshold (e.g., 100mV differential voltage in the LVDS standard) of the hardware input interface pin. The moment this physical arrival time is generated, the Time-to-Digital Converter (TDC) is triggered to start timing, which continues until the nearest valid edge of the (k+1)-th global reference clock arrives. The module then combines this with the known global reference clock period to output a raw digital count value representing the time difference between the physical arrival time and the edge of the (k+1)-th main cycle. This time span difference actually measured by the TDC directly represents the reverse compensation time required to postpone the arrival time of the mode signal to the next global reference clock edge, eliminating the need for additional phase difference conversion calculations and providing a precise input with physical time significance for subsequent compensation operations.

[0031] Inside the hardware polarized clock phase detector, the calculation process for the time span difference (i.e., the reverse compensation transmission time) generated for the m-th mode signal can be expressed by the following formula:

[0032] In the formula, This represents the reverse compensation transmission time required for the m-th mode signal. This represents the physical arrival time of the m-th signal. It indicates the time of the next global reference clock edge that is closest in time. This indicates the time span difference of the actual measured output of the time-to-digital converter. The value is a positive value no greater than the global reference clock period. Its specific digital form is the quantized integer obtained by dividing the actual time span difference by the inherent resolution of the time-to-digital converter (TDC). Its accuracy is determined by the inherent resolution of the time-to-digital converter (TDC), which is usually in the range of tens of picoseconds (ps) to a few nanoseconds (ns), much less than 1 microsecond (µs).

[0033] For example, in a specific implementation scenario, assume that the signal synchronization preprocessing module at the transmitting end is configured with a global reference clock, the frequency of which is... 250MHz, corresponding clock cycle The time is 4ns. At any given moment, this module processes two signals simultaneously, one of which is a high-definition video signal (labeled as modal). The other path is a digital audio signal (labeled as modal). During system runtime, at a specific point in time... At this point, a rising edge of the global reference clock is generated, which is the kth available major cycle edge. Subsequently, at the point in time... The moment when the frame synchronization pulse of the video signal arrives at its dedicated input pin is recorded as the physical arrival time. At this point, the TDC for the corresponding channel starts timing, until... The (k+1)th rising edge of the reference clock Stop and measure the time span difference. It is 2.5 ns. Almost simultaneously, at time point The rising edge of the word clock of the audio signal arrives at its input pin, and this moment is recorded as the physical arrival time. The corresponding time span difference measured by TDC The time difference is 0.8 ns. For video signal modes, the hardware polarity clock frequency and phase detector directly outputs the time span difference as the inverse compensation time. For audio signal modes, the inverse compensation time is... Therefore, after step S1 is completed, two time span differences are generated and output to the next step, representing 1.5ns of video modal time drift and 0.8ns of audio modal time drift, respectively.

[0034] S2. Using the time span difference as the reverse compensation transmission time, and ensuring that the equivalent bit length is greater than the preset waveform defect mark length, divide the reverse compensation transmission time by the physical time consumption constant of single-bit level transmission and round it to generate the quantized bit length parameter.

[0035] In a preferred embodiment, provided that the equivalent bit length is greater than the preset waveform malfunction mark length, the reverse compensation transmission time is divided by the physical time consumption constant of single-bit level conduction and rounded down to generate a quantized bit length parameter. Specifically, the time span difference is used as the reverse compensation transmission time input to the hardware arithmetic unit. It is determined whether the initial quantized bit length obtained by dividing the reverse compensation transmission time by the physical time consumption constant of single-bit level conduction is less than the preset waveform malfunction mark length constant plus one. If it is less, the reverse compensation transmission time is increased by a preset reference clock cycle. The updated reverse compensation transmission time is divided by the preset constant and rounded down using the division circuit built into the hardware arithmetic unit to output the quantized bit length parameter.

[0036] Specifically, step S2 follows immediately after S1, and its core task is to transform the abstract time metric obtained in the previous stage, i.e., the reverse compensation time, into a digital sequence description with a defined physical length. This process is completed by dedicated arithmetic logic circuits within the signal synchronization preprocessing module.

[0037] First, the time span differences corresponding to each mode, retrieved from the register of S1, are continuously input into a dedicated hardware arithmetic logic unit. This unit is physically implemented as one or more cascaded lookup tables (LUTs) and adder / subtractor circuits, functionally equivalent to a hardware frequency divider used to perform analog-to-digital time base conversion. This hardware frequency divider is not a traditional circuit that performs integer frequency division, but rather refers to a dedicated hardware calculation module that performs time-to-bit conversion. Within this unit, for each mode signal, the system directly uses the input time span difference as the physical arrival time of the current mode signal and delays it until it is precisely aligned to the reverse compensation transmission time required for the next global reference clock edge. Meanwhile, to ensure that the subsequently generated compensation sequence has a complete physical structure and to avoid invalid bits that are too short or even negative, the operation logic will first determine whether the initial quantization bit length obtained by dividing the reverse compensation transmission time by the physical time constant of single-bit level transmission is less than the preset waveform defect mark length constant plus one. If it is less, the reverse compensation transmission time will be increased by a preset reference clock cycle through the adder circuit to complete the boundary fallback.

[0038] Next, the operational logic directly divides the updated reverse compensation transmission time by the physical latency constant consumed by the single-bit level propagation on the line, using a built-in division circuit or shift register. This physical latency constant is directly determined by the transmission baud rate of the physical link. In the underlying hardware implementation, to avoid the overhead of complex floating-point division operations, this division circuit is specifically integrated into a hardware multiplier that directly multiplies by the transmitter's main baud rate clock frequency constant, or a pre-programmed lookup table circuit that directly maps the digital time value to an integer number of bits. The result of the integer division operation is forced down to generate a dimensionless integer value, which is the quantization bit length parameter with a specific placeholder length attribute. This parameter defines the number of bits that the padding sequence inserted to compensate for the initial time drift should contain, and is passed to step S3 to generate the physical carrier.

[0039] To ensure the generated compensation sequence has a complete physical structure and to prevent inter-modal clock cycle tearing errors caused by independent multi-modal compensation, a global common delay reference mechanism is established when calculating the quantization bit length parameter. The system first determines the inverse compensation transmission time of all modal signals belonging to the same synchronization event window (i.e., those requiring relative synchronization). Divide by The initial equivalent bit count is checked to see if it is less than a preset constant K+1. If the initial equivalent bit count of any mode signal is found to be less than this constant, a global delay carry signal is generated, forcibly causing the reverse compensation transmission time of all mode signals within the synchronization window to be unified and collectively added to a global reference clock cycle. To prevent negative length sequences, and to strictly ensure that the relative physical time deviations between modes are aligned to the same virtual reference edge, the updated reverse compensation transmission times are then divided and rounded down.

[0040] In the formula, reverse compensation transmission time The physical time value is determined by step S1 above. Its physical meaning is that an additional delay needs to be added to ensure that all modal signals, after their respective compensated delays, can be aligned to a unified virtual time point (i.e., the next global reference clock edge). The physical time constant for single-bit level transmission. This is the time required to transmit a single bit during baseband signal transmission at the physical layer; its value is the reciprocal of the transmitting end's master baud rate clock frequency. For example, in a 10 Gbit / s transmission system, A typical value is 0.1 ns. Quantization bit length parameter. It is an integer that directly indicates the length of the blank bit sequence to be generated in step S3. (Symbol) This indicates a floor operation, ensuring that the resulting bit length is an integer.

[0041] For example, continuing from the example in step S1, we obtain the video modality ( Reverse compensation time and audio modality ( Reverse compensation time The period of the global reference clock. The time constant is 4ns. Assuming the physical transmission link of this invention uses a line speed of 10 Gbit / s, the physical time constant for single-bit level transmission is... The time is 0.1 ns. For video modes, the system directly obtains their inverse compensation transmission time. The operation logic first determines the initial bit length (25) obtained by dividing by 0.1ns. Since 25 is greater than the constant 7(K+1), there is no need to trigger the boundary fallback mechanism. Then, it performs division and rounds down to calculate the corresponding quantization bit length. For audio modalities, the system directly obtains their inverse compensation transmission time. The operational logic determines that dividing by 0.1ns yields an initial bit length of 8. Since 8 is greater than the constant 7(K+1), no fallback compensation is needed. Then, division is performed and rounded down to calculate the corresponding quantization bit length. Finally, step S2 generates a quantization bit length parameter of 25 for the video modality and a quantization bit length parameter of 8 for the audio modality. These two integer values ​​will serve as the direct basis for the construction of the physical sequence in the next stage.

[0042] S3. Generate a blank bit sequence with a bit count equal to the quantization bit length parameter. Inject a number of consecutive same-level signals at the end of the blank bit sequence that is greater than the maximum number of consecutive same-level signals allowed by the communication protocol to generate an asymmetric base level. Combine these signals to generate a physical recording sequence.

[0043] In a preferred embodiment, a number of consecutive same-level signals exceeding the maximum number of consecutive same-level signals allowed by the communication protocol are injected at the end of the blank bit sequence to generate an asymmetric base level, which is then combined to generate a physical recording sequence. Specifically, a blank bit sequence consisting of continuous non-alternating levels is generated using a baseband encoder structure, and the total number of bits in the blank bit sequence is controlled to be equal to the quantization bit length parameter. The level state at the end of the blank bit sequence is controlled and maintained to be consistent for a preset number of consecutive clock cycles, and the preset number is greater than the maximum number of consecutive same-level signals allowed by the communication protocol, and an asymmetric base level is output. The asymmetric base level is then fixed at the end of the blank bit sequence to generate a physical recording sequence.

[0044] Specifically, in step S3, the system constructs a unique compensation sequence embedded with physical trigger markers for each modal signal based on the quantization bit length parameters generated in the previous stage. This process is executed by a component deployed at the transmitting end, typically hard-wired logic within an FPGA or ASIC. For a specified m-th modal signal baseband encoder structure, the baseband encoder structure is first driven to generate a blank bit sequence. The baseband encoder structure refers to the hardware module at the physical layer responsible for converting raw binary data into line-coded signals suitable for transmission over cables or optical fibers. A significant characteristic of this blank bit sequence is that its main body adopts a compliant level mode that does not violate the physical layer encoding rules. For example, in the NRZ (Non-Return-to-Zero) encoding system, it can be a continuous alternation of logic low levels "0" or "01" as simple time placeholders. More importantly, the total physical bit count of this blank bit sequence is set to the same as the quantization bit length parameters calculated for this mode in step S2. equal.

[0045] After generating this sequence, the next step is to physically mark its ends. Specifically, the baseband encoder structure controls the polarity reversal level criterion at the end of the blank bit sequence for a preset number (set as a constant K) of consecutive clock cycles. The polarity reversal level criterion is an encoding rule set in line encoding schemes such as Manchester encoding and 8B / 10B encoding to ensure signal spectral characteristics and clock recovery capability, requiring the signal level to change within a certain time. In standard physical network layer communication protocols, such as 8B / 10B or 64B / 66B encoding, to maintain DC balance and provide clock recovery information, the encoding rules limit the number of consecutive identical levels (i.e., "consecutive 0s" or "consecutive 1s"). This step configures the generation and output of an asymmetric base level segment that breaks this limitation. For example, if the leading part of the blank bit sequence consists of compliant logic "0s," the system will control and maintain a high-level output during the last K clock cycles, and the constant K is set to be greater than the maximum number of identical levels allowed by the protocol, thus generating a "long 1" level with a duration exceeding the protocol's allowed range. This level state that violates the physical layer coding rules is defined as a waveform breakage flag. The waveform breakage flag is a pre-generated physical layer signal anomaly that can be directly recognized by pure hardware logic.

[0046] Finally, the asymmetric base level is burned into the tail space of the blank bit sequence and combined with the compliance padding signal at the front end to generate a physical burning sequence that combines shift delay and hardware trigger enable attributes. The physical burning sequence consists of two parts: the first part is a variable-length compliance prefix sequence used for time compensation (its length is...). The latter half consists of a fixed-pattern waveform break marker (of constant length K) used as a hardware trigger signal. This sequence then awaits splicing with the service data frame.

[0047] It should be noted that the compliance prefix sequence refers to the signal state that maintains the polarity reversal requirement of the protocol for a relatively long time window. In regular data communication, this is usually a safety mode that is restricted by the protocol to avoid DC bias, ensuring that the receiver will not be falsely triggered before the mark arrives.

[0048] The asymmetric base level that breaks through the DC balance limitation of the physical network layer communication protocol refers to the signal pattern that violates the line coding rules through preset logic configuration. For example, in the Ethernet physical layer standard, the occurrence of more than five identical levels in a row is regarded as an aberration code. This invention uses this "waveform breaking" as a characteristic signaling with time deterministic characteristics.

[0049] For example, following step S2, we have already defined the video modality ( ) and audio modality ( Calculate the quantization bit length parameter respectively. and Assume that the line coding standard used in this system requires that the maximum number of consecutive bits at the same level not exceed 5. The system has a preset fixed length constant for waveform breakage markers. For the video mode, the baseband encoder structure first generates a sequence of 19 (25 minus 6) compliant logic "0"s. Then, in the last 6 bit clock cycles (bits 20 to 25), it forces a continuous output of logic "1" levels, forming a 25-bit signal segment ending with an extremely long continuous high level. This signal sequence of 19 "0"s and 6 consecutive "1"s constitutes the physical recording sequence for the video mode. The level state at its end that violates the "maximum consecutive 1s not exceeding 5" rule is the waveform breaking mark. For the audio mode, the process is similar. The baseband encoder structure generates a sequence of 2 (8 minus 6) compliant logic "0"s and outputs a continuous output of logic "1"s in the last 6 bit clock cycles, forming a 8-bit physical recording sequence ending with a continuous high level. This sequence also carries a waveform breaking mark at its end for hardware triggering. Thus, step S3 generates compensation sequences with precise physical lengths and hardware-identifiable markers for the two modes, preparing them for the next step of channel fusion.

[0050] S4. Extract payload data frames from stage multimodal signals, attach the physical recording sequence to the payload data frames to generate mixed data, and splice the mixed data to generate a continuous baseband bit stream.

[0051] In a preferred embodiment, the physical recording sequence is appended to the payload data frame to generate mixed data, and the mixed data is then concatenated to generate a continuous baseband bitstream. Specifically, the payload data frame is extracted from the stage multimodal signal using a low-level time-division multiplexing framer, and the payload data frame is imported into the idle service time slot preset by the low-level time-division multiplexing framer; the physical recording sequence is invoked and appended to the payload data frame after the physical end falling edge to generate mixed data; the multiple mixed data streams are merged to generate a continuous baseband bitstream after removing the abstract protocol parsing header.

[0052] Specifically, step S4 performs the final encapsulation and transmission of the signal, with the goal of directly concatenating the original service data with the compensation sequence generated in the previous steps at the physical channel layer. This process is dominated by the underlying time-division multiplexing (TDM) framer hardware module.

[0053] First, the framer extracts and segments the payload data frames corresponding to each modality from the parallel input stream of the stage multimodal signal. The payload data frame refers to the data portion carrying the actual information content extracted from the original multimodal signal, excluding protocol overhead unrelated to the synchronization mechanism of this invention. For example, for video signals, a complete video frame data block is extracted; for audio signals, a block consisting of one or more sampled data is extracted. The extracted payload data frames must be synchronously encoded using standard physical layer line coding (e.g., 8B / 10B or 64B / 66B coding) to ensure sufficient level transition density within the data block and maintain stable clock locking at the receiving end.

[0054] Subsequently, the framer imports these line-coded data blocks as a whole into a dedicated idle service slot pre-allocated for that mode. The dedicated idle service slot is a segment of physical transmission capacity reserved for a specific mode by the TDM multiplexer when constructing the overall output bitstream. This slot has a preset, fixed total physical bit length, and its capacity is designed to accommodate the maximum possible payload data frames, the maximum possible physical recording sequence, and the necessary guard bands.

[0055] Next, the framer invokes the physical recording sequence generated for that mode in step S3, corresponding to the dedicated idle service time slot for that specific mode. In terms of time sequence, the framer appends this physical recording sequence after the physical end falling edge of the payload data frame, forming a continuous data segment of "data frame + compensation sequence". The physical end falling edge refers to the physical transient boundary where the last bit signal level of the payload data frame transitions from high to low or from low to high. After compression, the framer fills the remaining unused physical space within the dedicated idle service time slot with a standard physical layer idle code (such as the K28.5 character in 8B / 10B encoding), thereby absorbing fluctuations caused by changes in the length of the physical recording sequence and ensuring that the entire TDM frame period remains constant. This operation is performed independently for all modes requiring synchronization.

[0056] Finally, the framer merges and encapsulates all the mixed data segments of all modes, each containing its own unique physical recording sequence and idle code padding. This encapsulation process generates a continuous baseband bitstream after removing abstract protocol parsing headers (such as MAC address, IP address, or TCP port number fields). This bitstream is a physical layer level sequence, and its internal structure and timing are preset and controlled by hardware logic. This continuous baseband bitstream is then continuously fed at a constant line speed to the distant receiving node through a wire (such as differential pair twisted pair) or optical fiber medium, awaiting direct processing by the physical layer at the receiving end. The wire or optical fiber medium is the physical transmission medium carrying this baseband bitstream from the transmitting end to the receiving end.

[0057] It is worth noting that the continuous baseband bitstream, after removing the abstract protocol parsing header, emphasizes that this invention bypasses the layered protocol stack of traditional networks during the transmission phase, directly organizing the data stream at the physical layer (Layer 1), thereby avoiding the latency and uncertainty caused by protocol parsing. Simultaneously, this bitstream macroscopically (payload and idle code portions) adheres to DC balance and polarity reversal rules, with preset, specific abnormal levels only present at microscopic, specific measurement nodes (i.e., waveform breakage markers), thus achieving hard triggering without compromising the stability of the underlying link.

[0058] For example, continuing the previous example, suppose a video modal payload data frame contains 1920×1080×10-bit pixel information, and an audio modal payload data frame contains 256 24-bit audio samples. In the TDM framer, the complete video data frame is first placed into its allocated first time slot. Then, the 25-bit physical recording sequence generated in step S3 is appended to the end of the video data frame. Subsequently, the framer processes the audio modality, placing a data block of 256 samples into its allocated second time slot. Then, the 8-bit physical recording sequence generated in step S3 is tightly appended to the end of the audio data block, and the time slot is padded with a free code. Afterward, data and compensation sequences from other modalities may be sequentially appended. All these combinations of "data + sequence + free code" are appended together without inserting additional frame gaps or protocol headers, forming a continuous binary level sequence of a set length. For example, the beginning of the stream might be "{video data frames (8B / 10B encoded)}…{19 '0's + 6 consecutive '1's}…{idle code}…{audio data frames (8B / 10B encoded)}…{2 '0's + 6 consecutive '1's}…{idle code}…". This continuous baseband bitstream, containing all modal information and its physical compensation markers, is ultimately driven directly to a fiber optic transceiver or differential line driver and transmitted to the receiving end at a rate of 10 Gbit / s.

[0059] S5. Receive the continuous baseband bit stream, extract the recovery baud rate clock and output the cleaned bit stream, and use the recovery baud rate clock to drive the cleaned bit stream to shift step by step in the shift register array.

[0060] In a preferred embodiment, the purified bit stream is shifted step-by-step in the shift register array using a recovered baud rate clock. Specifically, the following steps are taken: a clock data recovery hardware module is used to intercept a continuous baseband bit stream, lock the level transition edges contained in the continuous baseband bit stream, and reconstruct a frequency-synchronized recovered baud rate clock; the clock data recovery hardware module is used to perform purification processing on the continuous baseband bit stream to output a purified bit stream, which is then continuously input into the shift register array; the recovered baud rate clock is used to synchronously trigger the storage units in the shift register array, driving the purified bit stream to shift step-by-step.

[0061] Specifically, step S5 is executed at the receiving device end. Its core function is to use a pure hardware architecture to receive and process signals from the transmitting end in real time without buffering. When the continuous baseband bit stream arrives at the receiving end through the physical transmission medium, it is first intercepted by the Clock Data Recovery (CDR) hardware module integrated on the physical layer interface of the receiving end. The Clock Data Recovery (CDR) hardware module is a standard communication physical layer circuit whose function is to simultaneously extract data and a synchronized clock signal from a serial data stream that does not contain an independent clock signal. It is widely used in high-speed serial communication interfaces (SerDes). This CDR module locks the bit rate information contained in the input signal by analyzing the level transition edges of the input signal (especially the line-coded payload and idle code portions). Thanks to the fact that most of the data stream (payload and idle code) maintained DC balance and high transition density in the preceding steps, the phase-locked loop (PLL) inside the CDR can maintain sufficient loop inertia, thus smoothly crossing the extremely short waveform breakpoint at the end of the physically recorded sequence without loss of lock. This allows for the stripping and reconstruction of a recovered baud rate clock that is synchronized in frequency and phase with the transmitting node's master baud rate clock. The recovered baud rate clock is one of the outputs of the CDR module, and its frequency is consistent with the baud rate used by the transmitting end to modulate the baseband signal, ensuring timing synchronization at the physical layer between the transmitting and receiving ends. Simultaneously, the CDR module also outputs a purified serial data stream aligned with the recovered baud rate clock; this is the continuous baseband bit stream after clock level stripping and purification.

[0062] Next, the output pin of the data stream is directly hardwired to the serial data input of a fully hardware-cascaded multi-tap shift register array. The multi-tap shift register array is a long chain of registers consisting of numerous D-type flip-flops connected end-to-end. Its "multi-tap" characteristic means that in addition to the final output, the outputs of several intermediate flip-flops are also brought out as probe points, which will be used in step S6. The depth of the array (i.e., the number of flip-flops) is designed based on the maximum delay compensation capability required by the system. Its total capacity must be greater than the number of bits equivalent to the system's preset maximum physical link time drift margin to ensure it can accommodate and delay the longest compensation span of any mode. The fully hardware-cascaded configuration emphasizes that the array is a pure hardware logic circuit, with shift operation delays in the nanosecond or even picosecond range and high determinism. This connection does not go through memory buffers or software queues; data is continuously fed into the register array at the raw physical line rate of the current line, for example, 10 Gbit / s.

[0063] Finally, the recovered baud rate clock generated by the CDR module is used as the unified clock signal for the entire multi-tap shift register array. Driven by each valid edge (e.g., the rising edge) of the recovered baud rate clock, all memory cells (such as D-type flip-flops) in the array are synchronously triggered, causing all stored transmission signals to shift sequentially to the next level in the physical silicon chip pin configuration constituting the array at preset clock cycles. This process achieves real-time, software-buffer-free, pipelined hardware throughput for the entire bitstream.

[0064] For example, assume that at the receiving end, a 512-bit multi-tap shift register array is deployed. The continuous baseband bitstream from step S4, "{video data frames (8B / 10B encoded)}…{19 '0's + 6 consecutive '1's}…{idle code}…{audio data frames (8B / 10B encoded)}…{2 '0's + 6 consecutive '1's}…{idle code}…", arrives at the receiving end at a rate of 10 Gbit / s. The receiving end's CDR module successfully locks the data stream and outputs two signals: one is a 10 GHz recovery baud rate clock, and the other is a continuous baseband bitstream with the same content and aligned to that clock. This data stream is fed into the serial input of the 512-bit shift register array. Driven by the 10 GHz clock, every 0.1 ns, one bit from the bitstream is shifted into the first stage of the register, while the original 511 bits in the register are each shifted one stage to the right, and the last bit is shifted out. In the initial stage, the bit sequence of the video data frame sequentially fills the register array. After the video data frame transmission is complete, the subsequent physical recording sequence, consisting of 19 valid logic "0s" and 6 abnormal logic "1s," along with the remaining idle code, enters the register array and is shifted and transmitted within it. Throughout this process, the register array acts as a direct data channel, continuously receiving and shifting the bit stream from the transmitter. Its internal state at any given time precisely reflects the signal sequence received within the most recent 51.2 ns (512 bits × 0.1 ns / bit), providing an immediate, un-software-delayed hardware context for the next step of physical marker detection.

[0065] S6. Use a logic gate array to monitor the purified bit stream and output a synchronous trigger pulse when it matches the asymmetric base level.

[0066] In a preferred embodiment, a logic gate array is used to monitor the cleaned bitstream. When an asymmetric base level is matched, a synchronization trigger pulse is output. Specifically, tap probe pins are arranged at a specific physical depth position of the shift register array, and the tap probe pins are hard-wired into the logic gate array. The logic gate array is used to bypass and monitor the cleaned bitstream flowing through the tap probe pins, and real-time hard matching is performed on the cleaned bitstream. When the logic gate array determines that the cleaned bitstream fills the monitoring window and the level state is equivalent to the asymmetric base level, a synchronization trigger pulse with a pulse width of one clock cycle is output. After the logic gate array outputs the synchronization trigger pulse, a preset hardware counter is synchronously triggered to clear. The hardware counter is used to count the time interval between two adjacent synchronization trigger pulses in the cleaned bitstream. When the time interval exceeds a preset link jitter threshold, a hardware alarm level is output. The hardware alarm level is fed back to the clock data recovery hardware module to dynamically adjust the phase-locked bandwidth of the recovery baud rate clock.

[0067] Specifically, step S6 is executed in parallel with the signal throughput process at the receiving end. Its core is to achieve unresolved, hardware-level real-time detection of specific physical markers. For each independent mode that needs synchronization, a dedicated tap probe pin is placed at a specific physical depth position of the multi-tap shift register array during the system design phase. The specific physical depth position is a parameter fixed for each mode during hardware design. It determines the fixed number of shift stages that the signal must pass through from entering the register array to being inspected by the detector of that mode. The physical difference of this number of stages is directly determined by the physical offset of the time slot allocated to each mode during TDM framing in step S4. The selection of this position corresponds to the last hardware processing node before the final output of the mode data. The tap probe pin is a physically led-out probe on the multi-tap shift register array, which can reflect the current state of the internal flip-flop it is connected to in real time.

[0068] Simultaneously, a waveform breaking detection combinational logic gate array, specifically designed for identifying waveform breaking markers, is hard-wired and soldered onto the tap probe pin. This array is a stateless circuit composed of basic logic gates such as AND, OR, and NOT gates. Its output is directly determined by the current input, with no clock or storage elements, ensuring the instantaneous nature of the matching process. This gate array is bypassed and connected to the pin bundle of the tap probe pin and several adjacent pins, allowing for bypass monitoring of the transient level switching rate and fundamental polarity imbalance within a fixed-size window without hindering the shifting process of the main data stream.

[0069] During the continuous baseband bitstream shifting and transmission at physical line speed through a multi-tap shift register array, a waveform breaking detection combinational logic gate array continuously performs real-time hard matching on the bit sequence flowing through its monitoring window. Real-time hard matching refers to this clock-synchronized, nanosecond-level pattern comparison process implemented through solidified hardware logic. When the tail of the physically recorded sequence, i.e., the abnormal signal pattern composed of the asymmetric base level and its boundary transition edge with the front-end compliant prefix, shifts into and fills the monitoring window, the logic condition of the gate array is instantaneously satisfied, and it is determined to be consistent with the preset abnormal level transition pattern. The asymmetric base level is the specific signal pattern generated in step S3 that violates the physical layer coding rules, such as a continuous high-level sequence of length K. Within the same clock cycle when the logic condition is satisfied, the gate array transiently outputs a synchronization trigger pulse with a high-level pulse width of one clock cycle, dedicated to the corresponding independent mode control. The synchronization trigger pulse is a short and precise digital signal used as an enable or trigger signal for the next level of hardware, marking the precise occurrence time of a synchronization event.

[0070] For the m-th mode, the output of its corresponding waveform breaking detection combinational logic gate array, i.e., the synchronous trigger pulse, is... This can be described by a Boolean logic expression. Assuming the asymmetric base level is an abnormal sequence consisting of K consecutive logic "1"s, with its immediate prefix being a compliant logic "0", and the gate array monitors K+1 consecutive taps, then:

[0071] in, This indicates the output level state ("1" or "0") of the i-th tap in the multi-tap shift register array, with the symbol "·" representing a logical AND operation. Since the compliance prefix "0" enters the shift register array before the exception flag "1", "0" is shifted to a position with a deeper physical depth (larger index number). This represents performing a logical NOT operation on the state of the (j+K)th tap, used to locate the previously arrived compliance prefix. to This represents the continuous level of the subsequent arrival of the abnormal marker. In the formula, K is the fixed length constant of the waveform defect marker preset in step S3. This formula indicates that a trigger pulse is only activated when the output of the deeper tap is "0" and the outputs of the K subsequently monitored shallower taps are simultaneously "1". Only then is it "1".

[0072] For example, continuing the previous example, high-definition video (mode 1) and digital audio (mode 2) data streams are flowing in a multi-tap shift register array. Assuming the system uses a line coding specification that prohibits more than five consecutive "1"s, the waveform break marker generated in step S3 is a sequence of six consecutive "1"s (i.e., a constant). For the video mode, a dedicated tap probe pin and probe array are positioned at a physical depth of 300 in the register array. This probe array is a 7 (K+1) input AND gate with one inverting input and six non-inverting inputs. Its seven inputs are connected to taps 294, 295, 296, 297, 298, 299, and 300 of the register array. When the video data frame and the subsequent 25-bit physical recording sequence (19 "0"s followed by 6 "1"s) flow through this region, for most of the time, the AND gate output is always "0" because the data is random or does not satisfy the "leading 0 followed by 6 consecutive 1s" condition. Until a precise moment, the end of the physical recording sequence for this video mode, i.e., the 6 consecutive "1"s and their immediately preceding "0", precisely slides into positions 294 to 300. During this clock cycle, tap 300 is "0" (corresponding to a compliant prefix that enters the register earlier at a deeper physical depth, equivalent to "1" after inversion), and taps 294 to 299 are all "1" (corresponding to a fault flag that enters later at a shallower physical depth). All equivalent inputs of the 7-input AND gate are "1", and its output instantaneously jumps from "0" to "1", generating a synchronization trigger pulse specifically for the video modality. For the audio modality, its probe array may be positioned at a depth of 350 (the depth difference stems from the time slot after the video in the TDM frame), also a 7-input AND gate with inversion, connected to taps 344 to 350. When the end of the 8-bit physical recording sequence in the audio data stream (i.e., a leading "0" followed by 6 "1s") is precisely shifted to this position, the synchronization trigger pulse for the audio modality is generated in the same way.

[0073] S7. Transmit the payload data frame output from the shift register array and reside in the front end of the preset gating isolation gate. Use the synchronous trigger pulse to trigger the preset gating isolation gate to turn on and release the payload data frame residing in the front end of the gating isolation gate.

[0074] In a preferred embodiment, a preset gating isolation gate is triggered by a synchronous trigger pulse to release the payload data frame residing at the front end of the gating isolation gate. Specifically, the synchronous trigger pulse is guided to the control terminal of the gating isolation gate through a direct copper wire of a preset length; the gating isolation gate in a locked state is triggered by the high level or rising edge of the synchronous trigger pulse to open the release path of the payload data frame; and the payload data frame residing at the front end of the gating isolation gate is synchronously released and output at the same triggering moment when the synchronous trigger pulse arrives at its control terminal.

[0075] In a further preferred embodiment, the method further includes: after the payload data frame is synchronously released and output, receiving the payload data frame using a preset modal terminal execution device; converting the payload data frame into an analog drive voltage using a digital-to-analog electroacoustic conversion module inside the modal terminal execution device; and directly driving the mechanical actuator of the modal terminal execution device using the analog drive voltage.

[0076] Specifically, step S7 is the final execution stage of the method described in this invention. Its goal is to respond to the precise hardware pulse generated in the previous step and achieve hardware-level synchronous triggering of all stage edge modal effects. For each performance modality on stage, such as an audio reinforcement system, video display unit, or robotic arm controller, the corresponding synchronous trigger pulse generated in step S6 is directly guided to the control terminal of the final-stage gating isolation gate inside each modal terminal device through specially laid direct-connect copper wires or microstrip lines with low-latency characteristics. The direct-connect copper wires emphasize the physical directness and low impedance characteristics of the trigger signal transmission path to minimize transmission delay and signal distortion. The final-stage gating isolation gate is not a simple combinational logic AND gate that only maintains single-cycle conduction, but a trigger gate circuit with a hardware latch enable mechanism. One data input terminal is connected to the payload data to be output, and the other control input terminal is connected to the synchronous trigger pulse. The gate is only in continuous conduction state when the control terminal receives a high-level pulse trigger setting. These terminal devices include, but are not limited to, physical layer line decoding modules (such as the 8B / 10B decoding core corresponding to step S4) for restoring the original data, digital-to-analog electroacoustic conversion modules (such as DACs that drive speakers), video processing boards, and motor-mechanical digital control interfaces.

[0077] Before the arrival of the synchronization trigger pulse, the payload data frame has already been transmitted through another dedicated data output tap of the multi-tap shift register array and resides in the physical pipeline space (i.e., its starting bits are precisely dynamically aligned) at the front input of the final-stage gating isolation gate, in a synchronous waiting state. When the high-level synchronization trigger pulse signal reaches the control terminal of the gating gate, the gate is triggered and opened, instantly releasing the locked state. This action simultaneously opens the path between the payload data frame residing at the front end and the hardware release switch of the subsequent line decoding module and the external audio or video output terminal. Through this mechanism, all information frames residing at the front end of all parallel interfaces, belonging to different modal types, are synchronously released and fed into the decoding module at the same picosecond-level trigger moment when the synchronization trigger pulse arrives at its control terminal, and then released and output after restoration. This process effectively eliminates elastic buffer decomposition, software interrupt response, or protocol stack processing, thereby realizing direct synchronous playback without software delay between stage equipment across different electro-optical-mechanical media.

[0078] Picosecond-level trigger timing refers to the fact that, because all synchronization trigger pulses are generated based on the same recovery baud rate clock, and the physical length and characteristics of the transmission path are carefully designed to maintain consistency, the time difference between the opening of all gating gates can be controlled on the order of picoseconds, resulting in a shorter latency compared to the microsecond or millisecond precision of traditional software synchronization. Software-delay-free direct-connect synchronization means that once data arrives at the output interface front end and completes spatial alignment, its final release is determined by an external, data-content-independent hardware trigger signal, eliminating the need for data parsing and waiting processes.

[0079] For example, following step S6, the synchronization trigger pulse for the video mode is sent via a 5cm long PCB microstrip line to the control input of a high-speed latch enable gate on the video display interface board. The serial data input of this gate is connected to a video payload data frame shifted from a specific data tap of a multi-tap shift register array. Before the pulse arrives, the enable gate outputs a low level (or a high impedance state), blocking the video data. During the clock cycle of the pulse's arrival, the enable gate is set, and the video frame data begins to be continuously released to the 8B / 10B decoding logic for decoding. The recovered raw pixel data is then sent to the DAC and subsequent display driver circuitry. Simultaneously, the synchronization trigger pulse for the audio mode is also sent via a microstrip line of similar length to the enable terminal of a latching tri-state gate at the front end of the decoder inside the audio power amplifier module. The audio payload data frame is also waiting to be aligned here. When the pulse enables the tri-state gate, the audio data is immediately sent to the decoder for digital-to-analog conversion and drives the speaker to produce sound. Because the generation and transmission paths of the two pulses are physically designed to be of equal length, they open their respective output channels at essentially the same time point (theoretically, the difference is only a picosecond-level difference in circuit gate delay). The final effect is that the precise moment a preset scene appears on the large screen on the stage is synchronized with the moment the corresponding sound effect in the sound system is heard at the picosecond level, reducing relative delays or misalignments at the microsecond level or higher.

[0080] Please see Figure 2 As shown, the stage multimodal signal synchronization calibration and low-latency transmission system provided by the second aspect of the present invention includes: a signal synchronization preprocessing module, a time delay compensation mapping module, a baseband recording sequence generation module, a time division multiplexing framing and transmission module, a clock data recovery and shift throughput module, a waveform breaking detection module, and a final gating isolation module.

[0081] The signal synchronization preprocessing module receives the stage multimodal signal, compares the arrival time of the stage multimodal signal with the edge of the preset reference clock, and outputs the time span difference.

[0082] The delay compensation mapping module uses the time span difference as the reverse compensation transmission time. Under the premise of ensuring that the equivalent bit length is greater than the preset waveform defect mark length, the reverse compensation transmission time is divided by the physical time consumption constant of single bit level transmission and rounded to generate a quantized bit length parameter.

[0083] The baseband recording sequence generation module generates a blank bit sequence with a bit count equal to the quantization bit length parameter. At the end of the blank bit sequence, it injects a number of consecutive same-level signals greater than the maximum number of consecutive same-level signals allowed by the communication protocol to generate an asymmetric base level. These signals are then combined to generate a physical recording sequence.

[0084] The time-division multiplexing framing and transmission module extracts payload data frames from the stage multimodal signal, appends the physical recording sequence to the payload data frames to generate mixed data, and splices the mixed data to generate a continuous baseband bit stream.

[0085] The clock data recovery and shift throughput module receives a continuous baseband bit stream, extracts the recovered baud rate clock and outputs a clean bit stream, and uses the recovered baud rate clock to drive the clean bit stream to shift step by step in the shift register array.

[0086] The waveform breaking detection module uses a logic gate array to monitor the purified bit stream and outputs a synchronous trigger pulse when it matches an asymmetric base level.

[0087] The final gating isolation module transmits the shifted output payload data frame from the shift register array and stores it at the front end of a preset gating isolation gate. It then uses a synchronous trigger pulse to trigger the preset gating isolation gate to open and release the payload data frame stored at the front end of the gating isolation gate.

[0088] Each of the modules can be implemented in whole or in part through software, hardware, or a combination thereof. It supports hardware embedded in or independent of the processor in the computer device, and also supports software stored in the memory of the computer device, so that the processor can call and execute the operations corresponding to each of the above modules.

[0089] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for synchronous calibration and low-latency transmission of multimodal signals on a stage, characterized in that, include: S1. Receive stage multimodal signals, compare the arrival time of the stage multimodal signals with the edge of the preset reference clock, and output the time span difference; S2. Using the time span difference as the reverse compensation transmission time, under the premise of ensuring that the equivalent bit length is greater than the preset waveform defect mark length, the reverse compensation transmission time is divided by the physical time consumption constant of single bit level transmission and rounded to generate the quantized bit length parameter. S3. Generate a blank bit sequence with a bit count equal to the quantization bit length parameter. Inject a number of consecutive same-level signals at the end of the blank bit sequence that is greater than the maximum number of consecutive same-level signals allowed by the communication protocol to generate an asymmetric base level. Combine these signals to generate a physical recording sequence. S4. Extract payload data frames from stage multimodal signals, append physical recording sequences to the payload data frames to generate mixed data, and then splice the mixed data to generate a continuous baseband bit stream. S5. Receive the continuous baseband bit stream, extract the recovery baud rate clock and output the clean bit stream, and use the recovery baud rate clock to drive the clean bit stream to shift step by step in the shift register array. S6. Use a logic gate array to monitor and clean the bit stream, and output a synchronous trigger pulse when it matches the asymmetric base level. S7. Transmit the payload data frame output from the shift register array and reside in the front end of the preset gating isolation gate. Use the synchronous trigger pulse to trigger the preset gating isolation gate to turn on and release the payload data frame residing in the front end of the gating isolation gate.

2. The stage multimodal signal synchronization calibration and low-latency transmission method according to claim 1, characterized in that, Compare the arrival times of the stage multimodal signals with the edge of the preset reference clock, and output the time span difference, specifically: The stage multimodal signal is input into the hardware polarity clock frequency and phase detector, which is used to capture the physical arrival time of the stage multimodal signal transition. The time-to-digital converter inside the hardware polarity clock discriminator is activated to start timing until the preset reference clock edge is reached, at which point timing stops and the time difference recorded by the time-to-digital converter is output.

3. The stage multimodal signal synchronization calibration and low-latency transmission method according to claim 1, characterized in that, Provided that the equivalent bit length is greater than the preset waveform malfunction marker length, the reverse compensation transmission time is divided by the physical time constant of single-bit level transmission and rounded to generate the quantized bit length parameter, specifically: The time span difference is used as the input of the reverse compensation transmission time into the hardware computing unit. It is determined whether the initial quantization bit length obtained by dividing the reverse compensation transmission time by the physical time constant of single-bit level transmission is less than the preset waveform defect mark length constant plus one. If it is less, the reverse compensation transmission time is increased by a preset reference clock cycle. The updated inverse compensation transmission time is divided by a preset constant and rounded down using the division circuit built into the hardware arithmetic unit to output the quantization bit length parameter.

4. The stage multimodal signal synchronization calibration and low-latency transmission method according to claim 1, characterized in that, To generate an asymmetric base level, a number of consecutive level values ​​exceeding the maximum allowed number by the communication protocol are injected at the end of the blank bit sequence. These are then combined to generate the physical recording sequence. Specifically: The baseband encoder structure is used to generate a blank bit sequence consisting of continuous non-alternating levels, and the total number of bits in the blank bit sequence is controlled to be equal to the quantization bit length parameter. Control and maintain the consistent level state of the end of the blank bit sequence for a preset number of consecutive clock cycles, and the preset number is greater than the maximum number of consecutive identical levels allowed by the communication protocol, and output an asymmetric basic level; The asymmetric base level is fixed to the end of the blank bit sequence to generate a physical recording sequence.

5. The stage multimodal signal synchronization calibration and low-latency transmission method according to claim 1, characterized in that, The physical recording sequence is appended to the payload data frame to generate mixed data. The mixed data is then concatenated to generate a continuous baseband bitstream. Specifically: The payload data frame is extracted from the stage multimodal signal using the underlying time division multiplexing framer, and then imported into the idle service time slot preset by the underlying time division multiplexing framer. Call the physical recording sequence and append it to the falling edge of the physical end of the payload data frame to generate mixed data; Merge multiple mixed data streams to generate a continuous baseband bit stream after removing the header of the abstract protocol parsing packet.

6. The stage multimodal signal synchronization calibration and low-latency transmission method according to claim 1, characterized in that, The purified bitstream is shifted step-by-step in the shift register array using a restored baud rate clock. The clock data recovery hardware module is used to intercept continuous baseband bit streams, lock the level transition edges contained in the continuous baseband bit streams, and reconstruct a frequency-synchronized recovery baud rate clock. The clock data recovery hardware module performs purification processing on the continuous baseband bit stream and outputs a purified bit stream, which is then continuously input into the shift register array. The storage cells in the shift register array are triggered synchronously by the restored baud rate clock to drive the purification bit stream to shift and advance sequentially.

7. The stage multimodal signal synchronization calibration and low-latency transmission method according to claim 1, characterized in that, The logic gate array is used to monitor and clean the bit stream. When an asymmetric base level is matched, a synchronous trigger pulse is output. Specifically: Tap probe pins are placed at a specific physical depth position in the shift register array, and the tap probe pins are hardwired into the logic gate array. By using a logic gate array to bypass and monitor the cleaned bit stream flowing through the tap probe pin, a real-time hard match is performed on the cleaned bit stream. When the logic gate array determines that the clean bit stream fills the monitoring window and the level state is equivalent to the asymmetric base level, it outputs a synchronous trigger pulse with a pulse width of one clock cycle. After the logic gate array outputs a synchronous trigger pulse, the preset hardware counter is reset using the synchronous trigger pulse. The time interval between two adjacent synchronization trigger pulses in the purified bit stream is counted using a hardware counter. When the time interval exceeds the preset link jitter threshold, a hardware alarm level is output. The hardware alarm level is fed back to the clock data recovery hardware module to dynamically adjust the phase-locked bandwidth of the recovery baud rate clock.

8. The stage multimodal signal synchronization calibration and low-latency transmission method according to claim 1, characterized in that, The preset gating isolation gate is activated by a synchronous trigger pulse, releasing the payload data frame residing in front of the gating isolation gate. Specifically: The synchronous trigger pulse is guided to the control terminal of the gate isolation door through a direct copper wire of preset length; The high level or rising edge of the synchronous trigger pulse is used to trigger the conduction of the gate isolation gate that is in a locked state, thereby opening the release path of the payload data frame; The payload data frame residing at the front end of the gating isolation gate is synchronously released and output at the same trigger moment when the synchronous trigger pulse arrives at its control terminal.

9. The stage multimodal signal synchronization calibration and low-latency transmission method according to claim 8, characterized in that, The method also includes: After the payload data frame is synchronously released and output, the preset modal terminal execution device receives the payload data frame. The digital-to-analog electroacoustic conversion module inside the modal terminal execution device converts the payload data frame into an analog drive voltage; The mechanical actuator of the modal terminal execution device is directly driven by the analog driving voltage.

10. A stage multimodal signal synchronous calibration and low-latency transmission system, characterized in that, include: The signal synchronization preprocessing module receives stage multimodal signals, compares the arrival time of the stage multimodal signals with the edge of the preset reference clock, and outputs the time span difference. The delay compensation mapping module uses the time span difference as the reverse compensation transmission time. Under the premise of ensuring that the equivalent bit length is greater than the preset waveform defect mark length, the reverse compensation transmission time is divided by the physical time consumption constant of single bit level transmission and rounded to generate the quantized bit length parameter. The baseband recording sequence generation module generates a blank bit sequence with a bit count equal to the quantization bit length parameter. At the end of the blank bit sequence, a number of consecutive same-level signals greater than the maximum number of consecutive same-level signals allowed by the communication protocol are injected to generate an asymmetric base level. These signals are then combined to generate the physical recording sequence. The time-division multiplexing framing and transmission module extracts payload data frames from the stage multimodal signal, appends the physical recording sequence to the payload data frames to generate mixed data, and splices the mixed data to generate a continuous baseband bit stream. The clock data recovery and shift throughput module receives a continuous baseband bit stream, extracts the recovered baud rate clock and outputs a clean bit stream, and uses the recovered baud rate clock to drive the clean bit stream to shift step by step in the shift register array. The waveform breaking detection module uses a logic gate array to monitor and clean the bit stream, and outputs a synchronous trigger pulse when it matches an asymmetric base level. Finally, the gating isolation module transmits the payload data frame output from the shift register array to the front end of the preset gating isolation gate, and uses the synchronous trigger pulse to trigger the conduction of the preset gating isolation gate, releasing the payload data frame residing in front of the gating isolation gate.

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