Semiconductor structure and method of manufacturing the same

Abstract

This invention provides a semiconductor structure and its manufacturing method. The semiconductor structure includes: a substrate; an insulating layer located on the substrate; an active layer located on the insulating layer, the active layer having an etch-back region, an inverted trapezoidal trench within the etch-back region, and platforms on both sides thereof, the thickness of the active layer at the bottom of the inverted trapezoidal trench being less than the thickness of the active layer at the platforms; a gate structure located within the inverted trapezoidal trench; and source and drain electrodes located on the platforms. This invention utilizes the inverted trapezoidal trench design, combined with the characteristics of thick silicon being sensitive to reverse bias to reduce leakage current and thin silicon being sensitive to forward bias to increase conduction current, thus expanding the adjustment range of the back bias. Simultaneously, the thicker platform effectively suppresses source and drain diffusion, providing a possibility for device layout miniaturization.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] FDSOI (fully depletion silicon on insulator) technology, due to its structural characteristics, features an ultra-thin insulating layer, also known as a buried oxide layer (BOX), on the substrate. A very thin silicon film is used to fabricate the transistor channel. Because the channel is so thin, no doping process is required, and the depletion layer fills the entire channel region, resulting in a fully depleted transistor. Figure 1 As shown. Structurally, FD-SOI transistors exhibit superior electrostatic characteristics compared to traditional bulk silicon technology. The buried oxide layer reduces parasitic capacitance between the source and drain and effectively suppresses electron flow from the source to the drain, thereby significantly reducing leakage current that degrades performance. Furthermore, FD-SOI offers many other unique advantages, including back-side bias capability, excellent transistor matching characteristics, the ability to operate at near-threshold low supply voltages, ultra-low sensitivity to radiation, and very high intrinsic transistor operating speed and effective power consumption control. These advantages enable its operation in millimeter-wave frequency band applications. Because of its back-side silicon oxide layer, FDSOI allows for both positive and negative back-side voltage applications, facilitating adjustment of the device's operating range. Figure 2 As shown, during operation, the speed can be increased by applying a forward body bias (FBB); in the off state, the leakage current of the device can be reduced by applying a reverse body bias (RBB), which is beneficial for reducing static power consumption. This allows for a wide range of control over device speed and leakage current. By adjusting these parameters, the speed and power consumption of the chip can be effectively improved.

[0003] The thickness of silicon on the insulating layer of FDSOI is strongly correlated with device performance. A thicker silicon layer results in a lower threshold voltage, lower subthreshold swing (SS), reduced drain-induced barrier (DIBL), and increased leakage current. Simultaneously, the thickness of the insulating layer and the minimum channel length of the device are limited by supercoupling, requiring a certain ratio. The silicon thickness should be no less than one-quarter of the minimum channel length to ensure the channel can be adjusted by the substrate and form an effective channel length with the source and drain. For the same channel length and insulating layer, thicker silicon corresponds to a lower threshold voltage, while thinner silicon corresponds to a higher threshold voltage. At higher reverse bias, due to the thinness of the silicon, electrons and holes cannot coexist within it, causing the reverse backside voltage adjustment sensitivity to decrease with increasing voltage. This means that continuously reducing the silicon thickness on the insulating layer cannot improve leakage current. Forward bias has lower sensitivity to the decrease in mobility caused by electron saturation in thin silicon, so the forward bias adjustment speed has a slightly wider range. How to solve the problem of reverse leakage current adjustment, so as to achieve effective back pressure adjustment, is a problem that FDSOI technology faces in further reduction.

[0004] In existing technologies, some studies have proposed using a "V"-shaped bottom as a channel on bulk silicon to control ultra-short channels, achieving a control length of 30 angstroms. Other studies have proposed using a "U"-shaped channel on silicon-on-a-chip (SAP) to prevent source-drain diffusion and shorten the device layout length. However, these existing technologies still fail to effectively leverage the differences in backvoltage response to silicon thicknesses to extend the device's operating range, and further improvements are needed in suppressing source-drain diffusion and further miniaturizing the layout. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: in the existing fully depleted silicon-on-insulator technology, the thin silicon has a decreased adjustment sensitivity when the reverse bias voltage is large, which makes it impossible to continuously reduce leakage current and it is difficult to balance large-range back voltage adjustment and suppression of source-drain diffusion. The present invention provides a semiconductor structure and its manufacturing method.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising:

[0007] Substrate;

[0008] An insulating layer is located on the substrate;

[0009] An active layer is located on the insulating layer. The active layer has an etched-back region, an inverted trapezoidal trench and platforms located on both sides of the inverted trapezoidal trench. The thickness of the active layer at the bottom of the inverted trapezoidal trench is less than the thickness of the active layer at the platform.

[0010] The gate structure is located within the inverted trapezoidal trench;

[0011] The source and drain are located on the platform.

[0012] Preferably, the thickness of the active layer at the bottom of the inverted trapezoidal trench is not less than one-quarter of the minimum trench length.

[0013] Preferably, the gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer.

[0014] Preferably, the gate dielectric layer comprises a high dielectric constant dielectric layer, and the gate conductive layer comprises a metal gate layer.

[0015] Preferably, it further includes a sidewall located on the sidewall of the gate structure.

[0016] Preferably, the source / drain electrode includes a raised source / drain electrode.

[0017] Preferably, the substrate includes a potential well region, which includes a P-type potential well and an N-type deep potential well, or the potential well region includes an N-type potential well and a P-type deep potential well.

[0018] Preferably, it further includes a shallow trench isolation structure that penetrates the active layer and the insulating layer and extends into the substrate.

[0019] The present invention also provides a method for manufacturing a semiconductor structure, comprising:

[0020] Step 1: Provide a substrate, on which an insulating layer and an active layer are sequentially formed;

[0021] Step 2: Etch back the active layer to form an etch-back region;

[0022] Step 3: Perform sidewall etching in the etched area to form an inverted trapezoidal trench and platforms on both sides of the inverted trapezoidal trench. The active layer thickness at the bottom of the inverted trapezoidal trench is less than the active layer thickness at the platform.

[0023] Step 4: Form a gate structure within the inverted trapezoidal trench;

[0024] Step 5: Form the source and drain electrodes on the platform.

[0025] Preferably, step one further includes forming a shallow trench isolation structure, the shallow trench isolation structure penetrating the active layer and the insulating layer and extending into the substrate.

[0026] Preferably, in step four, forming the gate structure includes: forming a gate dielectric layer in the inverted trapezoidal trench, and forming a gate conductive layer on the gate dielectric layer.

[0027] Preferably, in step four, the gate dielectric layer includes a high dielectric constant dielectric layer, and the gate conductive layer includes a metal gate layer.

[0028] Preferably, after step four and before step five, the method further includes forming a sidewall on the sidewall of the gate structure.

[0029] Preferably, in step five, the source and drain electrodes include raised source and drain electrodes.

[0030] As described above, the semiconductor structure and its manufacturing method of the present invention have the following beneficial effects:

[0031] This invention proposes a semiconductor structure with an inverted trapezoidal trench, which expands the device's operating range by combining the different back voltage responses of silicon with varying thicknesses. Under low leakage current requirements, applying a reverse bias, the flat channel is far from the insulating layer, resulting in a low threshold voltage and high leakage current. The sufficiently thick silicon at the plateau is sensitive to bias, allowing for rapid shutdown of this region and reducing overall leakage current. Under high current requirements, applying a forward bias, the thin silicon at the bottom of the inverted trapezoidal trench is sensitive to forward bias, rapidly increasing the conduction current. By utilizing the response of silicon with different thicknesses, the adjustment range of the back bias is effectively expanded, enhancing the advantages of silicon-on-insulator (SiO2) technology. Simultaneously, because the source and drain regions are located on a relatively thick plateau, the diffusion of source and drain impurities can be effectively suppressed, providing a possibility for miniaturizing the semiconductor structure layout. Attached Figure Description

[0032] Figure 1 The diagram shows a schematic of a silicon-on-insulator structure in the prior art;

[0033] Figure 2 This diagram illustrates the relationship between the velocity and leakage current of a fully depleted silicon-on-insulator device in the prior art as a function of different back voltages.

[0034] Figure 3 The diagram shows a process flow diagram of the semiconductor structure manufacturing method of the present invention;

[0035] Figure 4 The diagram shown is a cross-sectional view of the semiconductor structure of the present invention after the shallow trench isolation structure is formed.

[0036] Figure 5 The diagram shown is a cross-sectional view of the semiconductor structure of the present invention after the formation of the gate dielectric layer.

[0037] Figure 6 The diagram shown is a cross-sectional view of the semiconductor structure of the present invention. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] Combination Figure 6 As shown, the semiconductor structure includes:

[0040] Substrate 101;

[0041] Insulating layer 102 is located on substrate 101;

[0042] The active layer 103 is located on the insulating layer 102. The active layer 103 has an etched area, an inverted trapezoidal trench and platforms located on both sides of the inverted trapezoidal trench. The thickness of the active layer 103 at the bottom of the inverted trapezoidal trench is less than the thickness of the active layer 103 at the platform.

[0043] The gate structure is located within an inverted trapezoidal trench;

[0044] The source and drain electrodes 110 are located on the platform.

[0045] like Figure 6 As shown, this semiconductor structure demonstrates the complete morphology of a fully depleted silicon-on-insulator (SiI) device, with contact terminals for electrical connections schematically outlined above. By employing an inverted trapezoidal trench design, combined with the different back voltage responses to varying silicon thicknesses, the operating range of the device can be effectively expanded. Specifically, thicker silicon is sensitive to reverse bias, while thinner silicon is sensitive to forward bias. Under low leakage current requirements, applying a reverse bias results in a flat channel far from the insulating layer 102, leading to a low threshold voltage and high leakage current. The sufficiently thick silicon at the platform is sensitive to bias, allowing for rapid shutdown of this region and reducing overall leakage current. Under high current requirements, applying a forward bias, the thinner silicon at the bottom of the inverted trapezoidal trench is sensitive to forward bias, rapidly increasing the conduction current. The response of silicon of different thicknesses expands the adjustment range of the back bias, thereby enhancing the advantages of SiI technology. Simultaneously, since the source / drain region 110 is located on a relatively thick platform, the diffusion of the source / drain 110 can be effectively suppressed, providing a possibility for miniaturizing the semiconductor structure layout. In semiconductor manufacturing processes, this structural design allows for optimization of electrical performance through topography control without adding additional complex masking steps.

[0046] In some embodiments, the substrate 101 includes a potential well region, which includes a P-type potential well 105 and an N-type deep potential well 104; alternatively, the potential well region includes an N-type potential well and a P-type deep potential well. Figure 6As shown, an N-type deep potential well 104 is located deep within the substrate 101, and a P-type potential well 105 is located above the N-type deep potential well 104. This dual-well or multi-well structure provides flexible bulk bias options for the device. The substrate 101 can be a bulk silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc. In other alternative embodiments, the substrate 101 may also include a III-V compound semiconductor material, such as gallium arsenide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof. The presence of the potential well region enables the semiconductor structure to have back-side bias capability, and the threshold voltage of the device can be adjusted by applying a forward bias or a reverse bias to the potential well region. During operation, a forward bias can increase the device speed; in the off state, a reverse bias can reduce the device leakage current, which is beneficial for reducing static power consumption and achieving a wide range of device speed and leakage current control. The formation of potential well regions is typically achieved through multiple ion implantation processes. For example, for a P-type potential well 105, P-type dopants such as boron, boron difluoride, or indium can be implanted; for an N-type potential well, N-type dopants such as phosphorus, arsenic, or antimony can be implanted. After implantation, a high-temperature annealing process, such as rapid thermal annealing or laser annealing, is usually performed to activate the dopants and repair lattice damage.

[0047] In some embodiments, a shallow trench isolation structure 106 is further included, which penetrates the active layer 103 and the insulating layer 102 and extends into the substrate 101. For example... Figure 6 As shown, the shallow trench isolation structure 106 penetrates the active layer 103 and the insulating layer 102, deeply embedding itself in the P-type potential well 105 and the N-type deep potential well 104, achieving complete physical and electrical isolation between different active regions. The insulating layer 102, also known as the buried oxide layer, can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, low-dielectric-constant dielectric materials, or combinations thereof. The insulating layer 102 reduces the parasitic capacitance between the source and drain 110 and effectively suppresses electron flow from the source to the drain, thereby significantly reducing leakage current that leads to performance degradation. The shallow trench isolation structure 106 is typically made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, or low-dielectric-constant dielectric materials. Its function is to achieve electrical isolation between different active regions and prevent crosstalk between adjacent devices. The shallow trench isolation structure 106 extends deep into the substrate 101, ensuring effective electrical isolation of the back gates of different devices in the silicon-on-a-silicon architecture of the fully depleted insulating layer. In some embodiments, the shallow trench isolation structure 106 may also include a multilayer structure, such as a thermally oxidized pad oxide layer covering the inner wall of the trench, and the interior filled with silicon oxide formed by high-density plasma chemical vapor deposition or silicon oxide formed by flowable chemical vapor deposition, to ensure good gap filling capability and avoid the formation of voids.

[0048] In some embodiments, the thickness of the active layer 103 at the bottom of the inverted trapezoidal trench is not less than one-quarter of the minimum channel length. The material of the active layer 103 may include single-crystal silicon, germanium, silicon-germanium, silicon carbide, or III-V semiconductor materials, etc. The thickness of silicon on the insulating layer 102 is strongly correlated with the device performance. When the silicon thickness is too thick, the corresponding threshold voltage decreases, the corresponding subthreshold swing, the drain-induced barrier decreases, and the leakage current increases. At the same time, the thickness on the insulating layer 102 and the minimum channel length of the device are limited by the supercoupling effect and need to maintain a certain ratio. Maintaining the thickness of the active layer 103 at the bottom of the inverted trapezoidal trench is not less than one-quarter of the minimum channel length ensures that the channel of the device can be adjusted by the substrate 101 and form an effective channel length with the source and drain 110. In some specific application scenarios, the thickness of the active layer 103 at the bottom of the inverted trapezoidal trench can be controlled at around 30 angstroms to achieve precise control of the ultra-short channel. This thickness control can be achieved through precise etching time management or by using atomic layer etching processes with high selectivity, thereby ensuring thickness uniformity within and between wafers.

[0049] In some embodiments, the gate structure includes a gate dielectric layer 107 and a gate conductive layer 108 located on the gate dielectric layer 107. In some embodiments, the gate dielectric layer 107 includes a high-dielectric-constant dielectric layer, and the gate conductive layer 108 includes a metal gate layer. Figure 6 As shown, the gate dielectric layer 107 conforms to the bottom and sidewall morphology of the inverted trapezoidal trench, and the gate conductive layer 108 fills the trench and is located above the gate dielectric layer 107. Before forming the high dielectric constant dielectric layer, an interface layer is typically formed on the surface of the active layer 103. The material of the interface layer can include chemically oxidized silicon or thermally oxidized silicon to improve the interface states between the high dielectric constant dielectric layer and the active layer 103. The material of the high dielectric constant dielectric layer can include materials with a dielectric constant greater than silicon oxide, such as hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, hafnium silicate, zirconium silicate, or combinations thereof. Using a high dielectric constant dielectric layer can increase the physical thickness while maintaining the same equivalent oxide layer thickness, thereby effectively reducing the gate leakage current. The metal gate layer is usually a multilayer structure, including a work function adjustment layer and a main conductive layer. For P-type devices, the work function adjustment layer material can include titanium nitride, tantalum nitride, tungsten nitride, titanium, or ruthenium; for N-type devices, the work function adjustment layer material can include aluminum titanium, aluminum titanium nitride, tantalum carbide, aluminum tantalum nitride, or tantalum. The main conductive layer material can include low-resistivity metals such as tungsten, aluminum, copper, ruthenium, or their alloys. The metal gate layer can eliminate the depletion effect present in polysilicon gates, reduce gate resistance, and improve the switching speed of the device.

[0050] In some embodiments, a sidewall 109 is also included, which is located on the sidewall of the gate structure. For example... Figure 6As shown, sidewalls 109 are located on both sides of the gate conductive layer 108, physically isolating it from the source and drain electrodes 110. The material of sidewalls 109 may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonoxynitride, silicon oxide, or a multilayer combination thereof. Sidewalls 109 are used to protect the gate structure during subsequent ion implantation or epitaxial growth processes and define the location of the source and drain electrodes 110, preventing short circuits between the source and drain electrodes 110 and the gate structure. In some embodiments, sidewalls 109 may include an L-shaped inner sidewall and a main sidewall located outside the inner sidewall. This multilayer sidewall design helps to better control the morphology of the epitaxial growth of the source and drain electrodes 110 and optimize the parasitic capacitance of the device.

[0051] In some embodiments, the source / drain 110 includes a raised source / drain. For example... Figure 6 As shown, the source and drain electrodes 110 are located on thicker platforms on both sides of the inverted trapezoidal trench, and their top surfaces are higher than the initial surface of the active layer 103, forming a raised structure. Furthermore, Figure 6 The diagram also shows a peripheral potential well contact region 111 for applying a bias voltage to the potential well. The raised source / drain electrodes are typically formed via epitaxial growth. For N-type devices, the materials for the raised source / drain electrodes may include phosphorus-, arsenic-, or antimony-doped silicon or silicon carbide; for P-type devices, the materials may include boron- or boron difluoride-doped silicon-germanium or germanium. Raising the source / drain electrodes not only reduces the source / drain contact resistance but also applies stress to the channel, thereby increasing carrier mobility and further enhancing the device's drive current. In some embodiments, a metal silicide layer, such as titanium silicide, nickel silicide, platinum silicide, or tungsten silicide, may also be formed on the surface of the raised source / drain electrodes to further reduce the contact resistance between the source / drain electrodes 110 and the subsequently formed contact plugs.

[0052] Combination Figure 3 The process flow diagram shown below provides a method for manufacturing semiconductor structures.

[0053] Methods for manufacturing semiconductor structures include:

[0054] Step 1: Provide a substrate 101, on which an insulating layer 102 and an active layer 103 are sequentially formed;

[0055] In some embodiments, step one further includes forming a shallow trench isolation structure 106, which penetrates the active layer 103 and the insulating layer 102 and extends into the substrate 101. The process for forming the shallow trench isolation structure 106 may include: firstly, depositing a pad oxide layer and a silicon nitride hard mask layer sequentially on the active layer 103; then forming a patterned photoresist layer through photolithography; next, using the photoresist layer as a mask, employing anisotropic dry etching processes, such as using plasma containing fluorine-based or chlorine-based gases, to sequentially penetrate the hard mask layer, pad oxide layer, active layer 103, insulating layer 102, and extend into the substrate 101 to form an isolation trench; subsequently, a thin pad oxide layer can be grown on the inner wall of the trench through thermal oxidation to repair etching damage; then, an insulating material, such as silicon oxide, is filled into the trench through high-density plasma chemical vapor deposition, flowable chemical vapor deposition, or spin-coating of an insulating medium; finally, excess insulating material and the hard mask layer are removed through chemical mechanical polishing, making the top surface of the shallow trench isolation structure 106 flush with the top surface of the active layer 103. After filling with insulating material, a high-temperature annealing process is usually carried out to densify the filled insulating material and improve its insulation performance.

[0056] Step 2: Imitate back the active layer 103 to form an etch-back region;

[0057] In step two, the active layer 103 can be etched back using a dry etching process, such as reactive ion etching or inductively coupled plasma etching. By controlling the flow rate of the etching gas (such as carbon tetrafluoride, trifluoromethane, chlorine, hydrogen bromide, and carrier gases such as argon or helium), the RF power, the chamber pressure, and the etching time, the depth of the etched-back region can be precisely controlled. During the etching process, the etching depth can be monitored in real time using endpoint detection techniques such as in-situ optical emission spectroscopy to ensure the accuracy of the etched-back depth. In step three, sidewall etching is performed in the etched-back region to form inverted trapezoidal trenches. This can be achieved by combining isotropic and anisotropic etching, or by using a wet etching process with a specific crystal orientation. For example, using alkaline etching solutions such as tetramethylammonium hydroxide and potassium hydroxide, the difference in etching rate between different silicon crystal planes (such as the (100) plane and the (111) plane) naturally forms inverted trapezoidal trenches with sidewalls at a specific tilt angle. The formation of the inverted trapezoidal trench retains a relatively thick platform on both sides, which not only provides a basis for the subsequent formation of the source and drain electrodes 110, but also effectively prevents the lateral diffusion of impurities in the source and drain electrodes 110 into the channel region during subsequent thermal cycling, thereby mitigating the short-channel effect.

[0058] Step 3: Perform sidewall etching in the etched area to form an inverted trapezoidal trench and platforms on both sides of the inverted trapezoidal trench. The thickness of the active layer 103 at the bottom of the inverted trapezoidal trench is less than the thickness of the active layer 103 at the platform.

[0059] Step 4: Form the gate structure within the inverted trapezoidal trench;

[0060] In some embodiments, step four, forming the gate structure, includes forming a gate dielectric layer 107 within an inverted trapezoidal trench and forming a gate conductive layer 108 on the gate dielectric layer 107. In some embodiments, in step four, the gate dielectric layer 107 includes a high-dielectric-constant dielectric layer, and the gate conductive layer 108 includes a metal gate layer. The gate dielectric layer 107 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes to ensure a high-dielectric-constant dielectric layer with uniform thickness and height is formed at the bottom and on the inclined sidewalls of the inverted trapezoidal trench. Before depositing the high-dielectric-constant dielectric layer, an ultrathin interface oxide layer can be formed by ozone oxidation or wet chemical oxidation. The gate conductive layer 108 can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or ALD processes, sequentially filling the inverted trapezoidal trench with a work function metal and a main filler metal. For example, a uniform titanium nitride or titanium aluminum work function layer can be formed by ALD, followed by filling with tungsten or aluminum as the main conductive layer via CVD. Subsequently, excess gate material outside the inverted trapezoidal trench can be removed by chemical mechanical polishing (CMP) to achieve surface planarization. In some embodiments, the formation of the gate structure can also be achieved using a post-gate process (i.e., a replacement gate process), which involves first forming a polysilicon dummy gate, removing the dummy gate after the source and drain 110 is fabricated, and then filling the formed trench with a high-dielectric-constant dielectric layer and a metal gate layer. This avoids the high-dielectric-constant material and the metal material being affected by high-temperature thermal balance during the annealing process of the source and drain 110.

[0061] In some embodiments, after step four and before step five, the process further includes: forming a sidewall 109 on the sidewall of the gate structure. The process for forming the sidewall 109 typically includes: firstly, conformally depositing one or more layers of sidewall dielectric material, such as silicon nitride or silicon carbonitride, across the entire semiconductor structure surface using low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition; then performing anisotropic dry etching, such as reactive ion etching using a fluorocarbon gas, to remove the dielectric material on the horizontal surface, retaining only the dielectric material on the gate structure sidewall, thereby forming the sidewall 109. During the etching process, the etching selectivity needs to be precisely controlled to avoid excessive damage to the active layer 103 at the plateau.

[0062] Step 5: Form source and drain electrodes 110 on the platform.

[0063] In some embodiments, in step five, the source / drain 110 includes a raised source / drain. The raised source / drain can be formed using selective epitaxial growth processes, such as low-pressure chemical vapor deposition (LPCVD) or ultra-high vacuum chemical vapor deposition (UCVD). During growth, the semiconductor material grows only on the active layer 103 on the exposed platform surface, without nucleation growth on insulating materials (such as sidewalls 109 and shallow trench isolation structures 106). In-situ doping can be achieved during epitaxial growth by introducing a precursor gas containing dopants (such as phosphine or arsine for N-type doping, or diborane for P-type doping) into the reaction gas, forming a raised source / drain with low resistivity. Because the active layer 103 at the platform is relatively thick, thermal shrinkage and impurity diffusion during epitaxial growth are effectively suppressed, thereby ensuring the electrical performance stability of the ultra-short channel device. After epitaxial growth, rapid thermal annealing or millisecond-level laser annealing is typically performed to further activate impurities and optimize the crystal quality of the epitaxial layer.

[0064] This manufacturing method, through five clearly defined process steps, forms an etch-back region with inverted trapezoidal trenches in the active layer 103, cleverly combining the physical characteristics of thick and thin silicon. During subsequent device operation, the different response sensitivities of regions with varying thicknesses to forward and reverse bias voltages enable wide-range speed and leakage current control. This process flow exhibits good compatibility with existing fully depleted silicon-on-insulator (SiI) processes, eliminating the need for entirely new and complex equipment, thus reducing manufacturing costs and improving yield.

[0065] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; An insulating layer is located on the substrate; An active layer is located on the insulating layer. The active layer has an etched-back region, an inverted trapezoidal trench and platforms located on both sides of the inverted trapezoidal trench. The thickness of the active layer at the bottom of the inverted trapezoidal trench is less than the thickness of the active layer at the platform. The gate structure is located within the inverted trapezoidal trench; The source and drain are located on the platform.

2. The semiconductor structure according to claim 1, characterized in that: The thickness of the active layer at the bottom of the inverted trapezoidal trench is not less than one-quarter of the minimum trench length.

3. The semiconductor structure according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer.

4. The semiconductor structure according to claim 3, characterized in that: The gate dielectric layer includes a high dielectric constant dielectric layer, and the gate conductive layer includes a metal gate layer.

5. The semiconductor structure according to claim 1, characterized in that: It also includes sidewalls, which are located on the sidewalls of the gate structure.

6. The semiconductor structure according to claim 1, characterized in that: The source and drain electrodes include raised source and drain electrodes.

7. The semiconductor structure according to claim 1, characterized in that: The substrate includes a potential well region, which includes a P-type potential well and an N-type deep potential well, or the potential well region includes an N-type potential well and a P-type deep potential well.

8. The semiconductor structure according to claim 1, characterized in that: It also includes a shallow trench isolation structure, which is located within the active layer and extends to the insulating layer.

9. A method for manufacturing a semiconductor structure, characterized in that, At least including: Step 1: Provide a substrate, on which an insulating layer and an active layer are sequentially formed; Step 2: Etch back the active layer to form an etch-back region; Step 3: Perform sidewall etching in the etched area to form an inverted trapezoidal trench and platforms on both sides of the inverted trapezoidal trench. The active layer thickness at the bottom of the inverted trapezoidal trench is less than the active layer thickness at the platform. Step 4: Form a gate structure within the inverted trapezoidal trench; Step 5: Form the source and drain electrodes on the platform.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: Step one also includes forming a shallow trench isolation structure that penetrates the active layer and the insulating layer and extends into the substrate.

11. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: In step four, forming the gate structure includes: forming a gate dielectric layer in the inverted trapezoidal trench, and forming a gate conductive layer on the gate dielectric layer.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: In step four, the gate dielectric layer includes a high dielectric constant dielectric layer, and the gate conductive layer includes a metal gate layer.

13. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: After step four and before step five, the method further includes: forming a sidewall on the sidewall of the gate structure.

14. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: In step five, the source and drain electrodes include raised source and drain electrodes.

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