Semiconductor device fabrication methods and semiconductor devices

Abstract

This application relates to a method for fabricating a semiconductor device and the semiconductor device itself. The method includes: providing a semiconductor material layer having a first conductivity type, the semiconductor material layer including a first device region and a second device region; forming a first well region and a second well region within the first device region; and forming a first trench, a second dielectric layer, and a first semiconductor structure within the second device region during a process of forming a second trench, a second dielectric layer, and a first semiconductor structure within the first device region; wherein the first well region and the second well region have a second conductivity type and a first conductivity type, respectively, and the second well region, the first well region, and the semiconductor material layer form a parasitic transistor, and the first semiconductor structure and the second semiconductor structure have the first conductivity type; and forming a conductive interconnect structure on the semiconductor material layer, the conductive interconnect structure enabling the first well region to be conductively connected to the first semiconductor structure; thus, the problem of parasitic transistors being easily turned on is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] The IPS (Intelligent Power Switch) process integrates BCD (Bipolar CMOS DMOS) and SGT (Shielded Gate Trench) processes. BCD is a monolithic integration technology that can fabricate bipolar, CMOS, and DMOS devices on the same chip, and is widely used in wireless chargers, Power over Ethernet, USB power controllers, smart devices, automobiles, electric bicycles, and data centers.

[0003] However, parasitic transistors are inevitably introduced into the device structure formed by the BCD process. These parasitic transistors are highly sensitive; even a tiny interference current in the chip's operating environment can easily cause a voltage drop across their base, accidentally turning them on. Once this parasitic transistor is turned on, it can potentially trigger an output latch-up mode in conjunction with other parasitic devices. This can lead to a short circuit between power and ground, either partially or entirely, causing functional failure or permanent damage.

[0004] How to prevent parasitic transistors from being turned on is an important technical problem that those skilled in the art are dedicated to solving. Summary of the Invention

[0005] In view of the above, this application provides a method for fabricating a semiconductor device and a semiconductor device to solve at least one problem existing in the background art.

[0006] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising: A semiconductor material layer having a first conductivity type is provided, the semiconductor material layer comprising a first device region and a second device region; A first well region and a second well region are formed within the first device region; and, during the process of forming a second trench within the second device region, a first trench is formed within the first device region; during the process of forming a second dielectric layer on the inner wall of the second trench, a first dielectric layer is formed on the inner wall of the first trench; and during the process of forming a second semiconductor structure on the second dielectric layer within the second trench, a first semiconductor structure is formed on the first dielectric layer within the first trench; wherein, the first well region and the second well region respectively have a second conductivity type and a first conductivity type, the second well region, the first well region, and the semiconductor material layer form a parasitic transistor, and the first semiconductor structure and the second semiconductor structure have a first conductivity type; A conductive interconnect structure is formed on the semiconductor material layer, the conductive interconnect structure enabling the first well region to be electrically connected to the first semiconductor structure.

[0007] In conjunction with the first aspect of this application, in an optional embodiment, the second device region is a region for forming a shielded gate trench type semiconductor device, the second trench is a gate trench, and the method further includes: Form an interlayer dielectric layer covering the first semiconductor structure; A portion of the second semiconductor structure is removed to form a control gate receiving trench, and the remaining second semiconductor structure is formed as a shielding gate; A gate dielectric layer and a control gate are formed within the control gate receiving groove.

[0008] In conjunction with a first aspect of this application, in an alternative embodiment, the projection of the first trench surrounds the projection of the first well region along the thickness direction of the semiconductor material layer.

[0009] In conjunction with the first aspect of this application, in an alternative embodiment, the first trench is disposed adjacent to the first well region.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, the method further includes: forming an interlayer dielectric layer covering the first semiconductor structure; Forming a conductive interconnect structure on the semiconductor material layer includes: forming a first via penetrating the interlayer dielectric layer above the first semiconductor structure, and forming a second via penetrating the interlayer dielectric layer above the first well region; filling the first via and the second via with conductive material to form a first conductive plug and a second conductive plug, respectively; forming a wiring layer on the interlayer dielectric layer, wherein the first conductive plug and the second conductive plug are conductively connected via the wiring layer; wherein the first via and the third via are formed simultaneously, and the third via is a via required to form a third conductive plug located in the second device region.

[0011] Secondly, embodiments of this application provide a semiconductor device, including: A semiconductor material layer having a first conductivity type, the semiconductor material layer comprising a first device region and a second device region; The first well region and the second well region are located in the first device region. The first well region and the second well region have a second conductivity type and a first conductivity type, respectively. The second well region, the first well region and the semiconductor material layer form a parasitic transistor. A second trench is located in the second device region, and a second dielectric layer and a gate structure are formed in the second trench. The second dielectric layer is located between the inner wall of the second trench and the gate structure. The first device region also includes a first trench, in which a first dielectric layer and a first semiconductor structure are formed. The first dielectric layer is located between the inner wall of the first trench and the first semiconductor structure. The first semiconductor structure and the gate structure have a first conductivity type. A conductive interconnect structure is located on the semiconductor material layer, such that the first well region is electrically connected to the first semiconductor structure.

[0012] In conjunction with a second aspect of this application, in an optional embodiment, the second device region is a region for forming a shielded gate trench semiconductor device, the gate structure is a shielded gate, and the second trench further includes a gate dielectric layer and a control gate.

[0013] In conjunction with a second aspect of this application, in an alternative embodiment, the projection of the first trench surrounds the projection of the first well region along the thickness direction of the semiconductor material layer.

[0014] In conjunction with a second aspect of this application, in an alternative embodiment, the first trench is disposed adjacent to the first well region.

[0015] In conjunction with the second aspect of this application, in an optional embodiment, it further includes: an interlayer dielectric layer covering the first semiconductor structure; The conductive interconnect structure includes: a first conductive plug that penetrates the interlayer dielectric layer and is conductively connected to the first semiconductor structure; a second conductive plug that penetrates the interlayer dielectric layer and is conductively connected to the first well region; and a wiring layer located on the interlayer dielectric layer; the first conductive plug and the second conductive plug are conductively connected via the wiring layer.

[0016] Compared with the prior art, the present application has the following beneficial effects: When interference current occurs, the semiconductor device fabrication method and semiconductor device provided in the embodiments of the present application can recombine the carriers in the first well region by the carriers in the first semiconductor structure, thereby discharging the current, reducing the probability of triggering the output latch-up mode, making it difficult for parasitic transistors to be turned on, and improving the safety and reliability of the device.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the cross-sectional structure of a semiconductor device in the related technology; Figure 2 A schematic flowchart illustrating the fabrication method of the semiconductor device provided in the embodiments of this application; Figures 3 to 10 This is a cross-sectional structural diagram of the semiconductor device provided in the embodiment of this application during the fabrication process.

[0019] Explanation of reference numerals in the attached figures: 110. Semiconductor material layer; 111. First surface; 112. Second surface; 1001. First device region; 1002. Second device region; 120. First trench; 121. First dielectric layer; 122. First semiconductor structure; 130. Second trench; 131. Second dielectric layer; 132. Second semiconductor structure; 132'. Shielding gate; 134. Isolation dielectric layer; 135. Gate dielectric layer; 136. Control gate; 137. Source doped region; 141. First well region; 142. Second well region Region; 143, Buried layer; 144, Second conductivity type heavily doped region; 145, Second conductivity type implanted region; 146, Field oxygen structure; 150, First via; 151, Second heavily doped region; 160, Third via; 161, First heavily doped region; 170, Second via; 180, Fourth via; 210, Isolation barrier layer; 220, Interlayer dielectric layer; 351, First conductive plug; 361, Third conductive plug; 371, Second conductive plug; 381, Fourth conductive plug; 391, Wiring layer. Detailed Implementation

[0020] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0021] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0022] In the accompanying drawings, for clarity, the dimensions of the structures and their relative dimensions may be exaggerated. The same reference numerals denote the same structural features throughout.

[0023] When structures are referred to as being "on," "adjacent to," "connected to," or "coupled to" other structures, they may be directly on, adjacent to, connected to, or coupled to other structures, or there may be intervening structures. Conversely, when a structure is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other structures, there are no intervening structures. Although the terms first, second, third, etc., may be used to describe structures or parts, these terms are only used to distinguish one structure or part from another. Therefore, without departing from the teachings of this application, the first structure or part discussed below may be referred to as the second structure or part. And the discussion of the second structure or part does not imply that the first structure or part necessarily exists in this application.

[0024] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated feature but do not exclude the presence or addition of one or more other features. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0027] Figure 1 This is a schematic cross-sectional view of a semiconductor device in related technologies. Figure 1Taking the structure shown as an example, a first well region 141 and a second well region 142 are formed in the semiconductor material layer 110. Since the semiconductor material layer 110 and the second well region 142 have a first conductivity type, while the first well region 141 has a second conductivity type, a parasitic transistor is formed between the semiconductor material layer 110, the first well region 141, and the second well region 142. Further, specifically taking the IPS process as an example (the device structure of the SGT region is not shown in the figure), due to the requirements of N-type SGT devices, IPS needs to use an N-type substrate. Some devices, such as NMOS, require PW and / or PBL implantation to separate the NW from the N-type substrate to prevent the NW from directly contacting the N-type substrate. For ease of understanding, PW (P-well) and NW (N-well) can be referred to as the first well region 141 and the second well region 142 in the figure, respectively; PBL (P-type Buried Layer) can be referred to as buried layer 143 in the figure; and the N-type substrate can be referred to as the semiconductor material layer 110 in the figure. At this point, NW, PW, and / or PBL, N-type substrates will form a parasitic NPN BJT (Bipolar Junction Transistor, hereinafter referred to as NPN transistor). The base of this parasitic NPN transistor is easily lifted by a small current generated by unstable factors, triggering the output latch-up mode. Specifically, the parasitic NPN transistor turns on, generating a collector current; other parasitic devices are inevitably present in the chip, and the aforementioned collector current will become the base drive current of other parasitic devices (such as another parasitic PNP transistor), causing it to also turn on; the collector current generated by the turned-on PNP transistor is then injected back into the base of the NPN transistor, further increasing the NPN transistor's current; this cycle repeats, forming a strong positive feedback, the current continuously amplifies, and eventually the circuit enters the latch-up mode. Even if the initial trigger current is removed, this huge conduction state will self-sustain until the power is cut off.

[0028] In addition, the first well region 141 serves as the base of the parasitic transistor. Figure 1 It is shown that it is electrically led out (through the heavily doped region 144 of the second conductivity type). The first well region 141 is typically connected to zero potential or floating.

[0029] Based on this, embodiments of this application provide a method for fabricating a semiconductor device. Please refer to... Figure 2 The method includes: Step S01: Provide a semiconductor material layer having a first conductivity type, the semiconductor material layer including a first device region and a second device region; Step S02: A first well region and a second well region are formed in the first device region; and, during the process of forming a second trench in the second device region, a first trench is formed in the first device region; during the process of forming a second dielectric layer on the inner wall of the second trench, a first dielectric layer is formed on the inner wall of the second trench; and during the process of forming a second semiconductor structure on the second dielectric layer in the second trench, a first semiconductor structure is formed on the first dielectric layer in the first trench; wherein, the first well region and the second well region have a second conductivity type and a first conductivity type, respectively; the second well region, the first well region, and the semiconductor material layer form a parasitic transistor; and the first semiconductor structure and the second semiconductor structure have a first conductivity type. Step S03: A conductive interconnect structure is formed on the semiconductor material layer, the conductive interconnect structure enabling the first well region to be electrically connected to the first semiconductor structure.

[0030] Understandably, in the embodiments of this application, the process steps of the second device region are used to simultaneously form a first trench and a first dielectric layer and a first semiconductor structure filling the first trench in the first device region. Since the first well region has a second conductivity type and the first semiconductor structure has a first conductivity type opposite to it, by conductively connecting the first well region and the first semiconductor structure, when an interference current occurs, the carriers in the first semiconductor structure can recombine with the carriers in the first well region, thereby discharging the current, reducing the probability of triggering the output latch-up mode, making it less likely for the parasitic transistor to be turned on, and improving the safety and reliability of the device.

[0031] Furthermore, the first trench is added to address the aforementioned technical problems. The first semiconductor structure itself does not bear the circuit requirements for normal device operation; therefore, conductively connecting the first well region to the first semiconductor structure will not adversely affect the normal operation of the device. The first semiconductor structure is separated from the semiconductor material layer by the first dielectric layer, which is equivalent to forming a deep trench isolation (DTI) structure through the first trench. This deep trench isolation structure is formed simultaneously using the process steps of the second device region, requiring only layout optimization and not additional photomasks, thus avoiding additional processes and costs, and is easy to implement in terms of process. At the same time, the deep trench isolation structure only needs to utilize the empty space of the first device region, without increasing the chip pitch or affecting the chip area. The embodiments of this application make devices that reduce trigger latch-up more marketable.

[0032] Below, we will combine Figures 3 to 10 The preparation method of the semiconductor device and the semiconductor device provided in the embodiments of this application will be further described in detail.

[0033] First, please refer to Figure 3Step S01 is performed to provide a semiconductor material layer 110 having a first conductivity type.

[0034] The semiconductor material layer 110 can be an epitaxial layer (EPI layer) formed by epitaxial growth on a substrate; although the substrate is not shown in the figure, it can be understood that the substrate is located below the epitaxial layer. The epitaxial layer and the substrate have the same conductivity type, for example, the substrate is an N-type substrate and the epitaxial layer is an N EPI layer. Of course, this application is not limited to this, and any semiconductor material layer that can provide a basis for the formation of subsequent device structures should be understood as the semiconductor material layer defined in this application. Therefore, the semiconductor material layer 110 may sometimes also be referred to as the substrate; the first conductivity type is not limited to N-type, and the embodiments of this application do not exclude the case that it is P-type.

[0035] In some specific applications, N-type SGT devices need to be formed on the semiconductor material layer 110. Due to the requirements of N-type SGT devices, the semiconductor material layer 110 needs to use N-type semiconductor materials, and thus use low-concentration PW as the P-type body region. This leads to a higher probability that the device itself will trigger a latch-up mode, so devices with reduced latch-up triggering are in greater market demand. However, it should be understood that the technical solution of this application is obviously also applicable to other devices with parasitic transistors.

[0036] like Figure 3 As shown, the semiconductor material layer 110 includes a first surface 111 and a second surface 112 that are opposite to each other. Depending on the formation location of the device structure, the first surface 111 and the second surface 112 can also be referred to as the upper surface and the lower surface, or the top surface and the bottom surface, respectively.

[0037] Ignoring the flatness of the first surface 111 and the second surface 112, the direction perpendicular to the first surface 111 and the second surface 112 of the semiconductor material layer 110 is defined as the thickness direction. The thickness direction is also the stacking direction for subsequent deposition of various structural layers on the semiconductor material layer 110, or the height direction of the semiconductor device; for structures formed by downward processes such as trenches or doped regions, this direction can be called the depth direction. The plane containing the first surface 111 and / or the second surface 112 of the semiconductor material layer 110 is perpendicular to the thickness direction.

[0038] The semiconductor material layer 110 includes a first device region 1001 and a second device region 1002. In some specific applications, the first device region 1001 is a BCD device region, and the second device region 1002 is an SGT device region. Therefore, in subsequent steps of this embodiment, the SGT process will be used to improve the problems of the BCD devices, thus eliminating the need for additional masks and processes and incurring no additional costs.

[0039] The material of the semiconductor material layer 110 can be selected according to the actual device requirements, such as common semiconductor materials like silicon (Si), and this application does not make specific limitations in this regard.

[0040] Next, step S02 is executed. In step S02, structures such as the first well region, the second well region, the first trench, and the second trench are formed. The formation order of these structures is not necessarily in the order described in the text. For example, the process of "forming the second trench in the second device region" described later can be performed before the process of "forming the first well region and the second well region in the first device region" described earlier. In addition, these process steps are not necessarily performed sequentially. This application does not exclude the possibility that at least two steps are completed at the same time or are completed alternately. The order of process execution should still be determined according to the specific logical relationship, and those skilled in the art can adjust it according to the actual device fabrication requirements.

[0041] The following explanation of step S02 uses the fabrication process of devices in specific applications as an example. It should be understood that this embodiment is compatible with the original fabrication process of devices in specific applications, and can achieve the simultaneous formation of new structures during the execution of the original process steps without changing the original process steps, only by adjusting the layout.

[0042] Please refer to Figure 4 During the process of forming the second trench 130 in the second device region 1002, the first trench 120 is formed in the first device region 1001.

[0043] In actual fabrication, the positions of the first trench 120 and the second trench 130 can be defined by photoresist coating, exposure, development and other processes, and then the corresponding trenches can be formed in the semiconductor material layer 110 by etching process.

[0044] Understandably, in the existing process, the second trench 130 is formed only in the second device region 1002, while the first device region 1001 is covered by the mask and no trench is formed. In this embodiment, the pattern of the photomask can be changed so that the preset position of the first device region 1001 is not covered by photoresist, thereby forming the first trench 120 simultaneously during the process of forming the second trench 130.

[0045] Next, please refer to Figure 5 In the process of forming a second dielectric layer 131 on the inner wall of the second trench 130, a first dielectric layer 121 is formed on the inner wall of the first trench 120. In the process of forming a second semiconductor structure 132 on the second dielectric layer 131 in the second trench 130, a first semiconductor structure 122 is formed on the first dielectric layer 121 in the first trench 120.

[0046] In some specific applications, the second trench 130 is a gate trench; the material of the second semiconductor structure 132 is a gate material, specifically, for example, polysilicon; the material of the second dielectric layer 131 is, for example, silicon oxide. The materials of the first dielectric layer 121 and the first semiconductor structure 122 are obviously the same as those of the second dielectric layer 131 and the second semiconductor structure 132, respectively. The first trench 120 and the second trench 130 are deep trenches (DT), and the etching process for the first trench 120 and the second trench 130 is deep trench etching.

[0047] The first semiconductor structure 122 and the second semiconductor structure 132 have a first conductivity type. Taking N-type as an example, the materials of the first semiconductor structure 122 and the second semiconductor structure 132 are specifically, for example, N-poly.

[0048] As an optional specific implementation, the doping concentration of the first semiconductor structure 122 and the second semiconductor structure 132 is greater than or equal to 2E20cm⁻¹. -3 To better achieve carrier recombination. Furthermore, the doping concentration of the first semiconductor structure 122 and the second semiconductor structure 132 is greater than or equal to 6E20cm⁻¹. -3 In this way, the basic functional requirements of the second semiconductor structure 132 as a gate are met, and the first semiconductor structure 122 is sufficient to recombine the excess carriers in the first well region.

[0049] In actual fabrication, a dielectric layer can be formed first, and then a semiconductor layer can be formed on the dielectric layer. In this case, the dielectric layer and the semiconductor layer inevitably include both the portion filled in the first trench 120 and the second trench 130, and the portion covering the first surface 111 of the semiconductor material layer 110. Next, the portion covering the first surface 111 of the semiconductor material layer 110 can be removed by a planarization process, so that the dielectric layer retains only the first dielectric layer 121 located in the first trench 120 and the second dielectric layer 131 located in the second trench 130, and the semiconductor layer retains only the first semiconductor structure 122 located in the first trench 120 and the second semiconductor structure 132 located in the second trench 130.

[0050] Next, please refer to Figure 6 A first well region 141 and a second well region 142 are formed in the first device region 1001; the first well region 141 and the second well region 142 have a second conductivity type and a first conductivity type, respectively.

[0051] The positional relationship between the first well region 141 and the second well region 142 is determined by the actual device. Figure 6The diagram shows the second well region 142 located within the first well region 141, but this application is not limited thereto. However, it should be noted that, since the purpose is to describe the three basic components for forming a parasitic transistor in a device, the positional relationship between the second well region 142, the first well region 141, and the semiconductor material layer 110 at least satisfies the requirement for forming a parasitic transistor.

[0052] As an optional specific implementation, the projection of the first trench 120 surrounds the projection of the first well region 141 along the thickness direction of the semiconductor material layer 110. This is more conducive to uniform current discharge.

[0053] As an optional specific implementation, the first trench 120 is disposed adjacent to the first well region 141. This saves wafer area and improves integration density.

[0054] Further optionally, along the thickness direction of the semiconductor material layer 110, the projection of the first trench 120 surrounds the projection of the first well region 141; and the first trench 120 is disposed adjacent to the first well region 141. Even further, in this case, the second well region 142 may be located within the first well region 141.

[0055] It should be understood that, regardless of whether the first well region 141 or the first trench 120 is formed first, the positional relationship between the first well region 141 and the first trench 120 can be predetermined during the layout design stage.

[0056] In addition, such as Figure 6 As shown, the actual fabrication process can obviously include steps such as forming other structures of the first device in the first device region 1001 and forming other structures of the second device in the second device region 1002. The structures of the first device region 1001 and the second device region 1002 will be described below. However, it should be understood that the order of description does not constitute a special restriction on the order in which these structures are formed; the specific process sequence can be determined according to actual needs.

[0057] In some specific applications, the first device region 1001 may also include steps such as forming a buried layer 143, a heavily doped region 144 of the second conductivity type, an implanted region 145 of the second conductivity type, and a field oxygen structure 146. The buried layer 143, like the first well region 141, has a second conductivity type; for example, if the first conductivity type is N-type and the second conductivity type is P-type, the buried layer 143 is a PBL.

[0058] Regarding the second device region 1002, in some specific applications, the second device region 1002 is a region used to form a shielded gate trench type semiconductor device, and the second trench 130 is a gate trench. The above method may further include: forming an interlayer dielectric layer 220 covering the first semiconductor structure 122; removing part of the second semiconductor structure 132 to form a control gate receiving trench, and forming the remaining second semiconductor structure 132 as a shielded gate 132'; forming a gate dielectric layer 135 and a control gate 136 in the control gate receiving trench.

[0059] Understandably, the control gate receiving groove is located within the second trench 130, specifically, for example, in the upper half of the second trench 130.

[0060] An insulating dielectric layer 134 can be formed within the control gate receiving groove to ensure insulation between the shielding gate 132' and the control gate 136. The material of the insulating dielectric layer 134 is, for example, silicon dioxide.

[0061] Next, excess material of the isolation dielectric layer 134 is removed, and then the gate dielectric layer 135 is formed. The gate dielectric layer 135 is isolated between the control gate 136 and the inner wall of the second trench 130. The material of the gate dielectric layer 135 is, for example, silicon dioxide.

[0062] Finally, the control gate 136 is filled. The material of the control gate 136 is, for example, polysilicon, specifically, N-type polysilicon.

[0063] The second dielectric layer 131 ultimately serves as a shielding dielectric layer that isolates the shielding gate 132' from the semiconductor material layer 110.

[0064] Understandably, in embodiments where the second device region 1002 is a region for forming a shielded gate trench type semiconductor device, the first dielectric layer 121 and the second dielectric layer 131, which serves as a shielding dielectric layer, are formed simultaneously, and the first semiconductor structure 122 and the second semiconductor structure 132, which serves as a shielding gate 132', are formed simultaneously. However, during the formation of the gate dielectric layer 135 and the control gate 136, the first semiconductor structure 122 is covered, and no corresponding structure is formed within the first trench 120.

[0065] Please continue to refer to this. Figure 6 After the fabrication of the corresponding structures in the first device region 1001 and the second device region 1002 is completed, a dielectric layer can be deposited again, so that the interlayer dielectric layer 220 completely covers the first surface 111 of the semiconductor material layer 110. The interlayer dielectric layer 220 is also called an ILD (Inter-Layer Dielectric) layer. In addition, an isolation barrier layer 210 may also be included between the interlayer dielectric layer 220 and the semiconductor material layer 110, etc., which is not specifically limited in this application.

[0066] Next, please refer to Figures 7 to 10 In step S03, a conductive interconnect structure is formed on the semiconductor material layer 110, which makes the first well region 141 electrically connected to the first semiconductor structure 122.

[0067] Forming a conductive interconnect structure on the semiconductor material layer 110 includes: forming a first via 150 penetrating the interlayer dielectric layer 220 above the first semiconductor structure 122, and forming a second via 170 penetrating the interlayer dielectric layer 220 above the first well region 141; filling the first via 150 and the second via 170 with conductive material to form a first conductive plug 351 and a second conductive plug 371, respectively. It should be noted that the order in which the first via 150 and the second via 170 are formed is not specifically limited in this application; the filling of conductive material into the first via 150 and the second via 170 can be performed simultaneously or asynchronously as needed, and this application does not impose specific limitations. Below, only one specific fabrication process is used as an example to illustrate step S03.

[0068] First, please refer to Figure 7 A first via 150 is formed above the first semiconductor structure 122, penetrating the interlayer dielectric layer 220.

[0069] The steps for forming the first through hole 150 can be carried out using photolithography and etching processes well known in the art, which will not be elaborated here.

[0070] It should be understood that conductive plugs need to be formed in both the first device region 1001 and the second device region 1002 to conduct electricity to the internal devices. However, due to the different process requirements of the two device regions, the vias required for the conductive plugs are often not formed in the same etching process.

[0071] The conductive plug used to bring out the conductivity of the second device in the second device region 1002 is referred to as the third conductive plug 361 (there are usually multiple such plugs, but they are not distinguished here; only the third conductive plug 361 is used as a representative). The conductive plugs used to bring out the conductivity of the first device in the first device region 1001 include, but are not limited to, the second conductive plug 371 and the fourth conductive plug 381 which is conductively connected to the second well region 142. The through-hole required for the third conductive plug 361 is referred to as the third through-hole 160, and the through-hole required for the fourth conductive plug 381 is referred to as the fourth through-hole 180. As an optional specific implementation, the first through-hole 150 and the third through-hole 160 are etched and formed simultaneously. Thus, although the first through-hole 150 is located in the first device region 1001, it is formed by means of the through-hole etching process of the second device region 1002, specifically by means of trenching in the SGT process.

[0072] Next, please refer to Figure 8In order to reduce contact resistance, a first heavily doped region 161 with the same conductivity type is formed in the source doped region 137 that needs to be conductive; and a second heavily doped region 151 is formed in the first semiconductor structure 122 that needs to be conductive.

[0073] The first heavily doped region 161 and the second heavily doped region 151 can be formed by ion implantation (IMP) of the source doped region 137 and the first semiconductor structure 122 exposed via the third via 160 and the first via 150, respectively.

[0074] Next, please refer to Figure 9 A second through-hole 170 is formed above the first well region 141, penetrating the interlayer dielectric layer 220.

[0075] The second through hole 170 can be formed in the same etching process as the fourth through hole 180.

[0076] Understandably, in order to reduce contact resistance, the second conductive plug 371 will be electrically connected to the first well region 141 through the heavily doped region 144 of the second conductivity type, thereby requiring the second via 170 to expose the heavily doped region 144 of the second conductivity type.

[0077] Next, please refer to Figure 10 Conductive material is filled into the first through hole 150 and the second through hole 170 to form the first conductive plug 351 and the second conductive plug 371, respectively.

[0078] In addition, conductive material may be filled into the third through hole 160 and the fourth through hole 180 to form a third conductive plug 361 and a fourth conductive plug 381, respectively.

[0079] In actual fabrication, the conductive filling material can specifically include the deposition of a bottom metal thin film and the deposition of a metal material layer. The material of the bottom metal thin film can include Ti and / or TiN; exemplarily, the bottom metal thin film may include a composite stack of Ti and TiN. The bottom metal thin film can also be referred to as an adhesion layer, and the deposition of the bottom metal thin film can also be referred to as adhesion layer deposition (Glue DEP). The metal material can include W; exemplarily, the metal material is specifically W.

[0080] Next, please continue to refer to... Figure 10 A wiring layer 391 is formed on the interlayer dielectric layer 220, and the first conductive plug 351 and the second conductive plug 371 are electrically connected through the wiring layer 391.

[0081] In actual fabrication, forming the wiring layer 391 may specifically include: depositing a conductive metal layer; etching the conductive metal layer to form the desired wiring pattern.

[0082] Thus, by adding a DTI isolation trench between the semiconductor material layer 110 having a first conductivity type and the first well region 141 having a second conductivity type, and by connecting the base (first well region 141) of the parasitic transistor and the first semiconductor structure 122 within the DTI with a metal material, the base-emitter voltage V of the parasitic transistor is... be With the base current (current from other transistors or the overall environment) relatively easy to discharge, it makes it difficult for parasitic transistors to be turned on.

[0083] Table 1

[0084] By comparing with Figure 1 The corresponding related technologies include semiconductor devices and Figure 10 Simulation tests were performed on the semiconductor devices in the corresponding embodiments of this application, and the breakdown voltage (BV) test results for Comparative Example 1 and Example 1 were obtained in Table 1. The BV value of Example 1 was approximately 6V higher than that of Comparative Example 1 (the specific difference during testing was 5.944118V). Based on the test results, the BV value of Example 1 is significantly improved; therefore, the improved structure can effectively improve the breakdown voltage of the device.

[0085] This application also provides a semiconductor device; please refer to the following embodiments. Figure 10 The semiconductor device includes: a semiconductor material layer 110 having a first conductivity type, the semiconductor material layer 110 including a first device region 1001 and a second device region 1002; a first well region 141 and a second well region 142 located in the first device region 1001, the first well region 141 and the second well region 142 having a second conductivity type and a first conductivity type, respectively, the second well region 142, the first well region 141 and the semiconductor material layer 110 forming a parasitic transistor; and a second trench 130 located in the second device region 1002, the second trench 130 having a second dielectric layer formed therein. The first device region 1001 also includes a first trench 120, in which a first dielectric layer 121 and a first semiconductor structure 122 are formed. The first dielectric layer 121 is located between the inner wall of the first trench 120 and the first semiconductor structure 122. The first semiconductor structure 122 and the gate structure have a first conductivity type. A conductive interconnect structure is located on the semiconductor material layer 110, so that the first well region 141 is conductively connected to the first semiconductor structure 122.

[0086] Understandably, in the semiconductor device provided in this application embodiment, when an interference current occurs, the carriers in the first semiconductor structure 122 can recombine with the carriers in the first well region 141, thereby discharging the current, reducing the probability of triggering the output latch-up mode, making it less likely for the parasitic transistor to be turned on, and improving the safety and reliability of the device.

[0087] Furthermore, the first trench 120 can be formed simultaneously with the second trench 130; the first dielectric layer 121 can be formed simultaneously with the second dielectric layer 131; and the first semiconductor structure 122 can be formed simultaneously with the second semiconductor structure 132 used to form the gate structure.

[0088] As an optional specific implementation, the second device region 1002 is a region for forming a shielded gate trench type semiconductor device, the gate structure is a shielded gate 132', and the second trench 130 also includes a gate dielectric layer 135 and a control gate 136.

[0089] Furthermore, the first semiconductor structure 122 can be formed simultaneously with the second semiconductor structure 132 used to form the shielding gate 132'.

[0090] As an optional specific implementation, along the thickness direction of the semiconductor material layer 110, the projection of the first trench 120 surrounds the projection of the first well region 141.

[0091] As an optional specific implementation, the first trench 120 is disposed adjacent to the first well region 141.

[0092] As an optional specific implementation, it further includes: an interlayer dielectric layer 220 covering the first semiconductor structure 122; a conductive interconnect structure including: a first conductive plug 351 penetrating the interlayer dielectric layer 220 and conductively connected to the first semiconductor structure 122, a second conductive plug 371 penetrating the interlayer dielectric layer 220 and conductively connected to the first well region 141, and a wiring layer 391 located on the interlayer dielectric layer 220; the first conductive plug 351 and the second conductive plug 371 are conductively connected via the wiring layer 391.

[0093] Furthermore, the via required to form the first conductive plug 351 and the via required to form the third conductive plug 361 are etched and formed simultaneously, wherein the third conductive plug 361 is used to conduct electricity out of the second device in the second device region 1002.

[0094] It should be noted that the semiconductor device embodiments and the semiconductor device fabrication method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the semiconductor device provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the semiconductor device provided in the embodiments of this application is not limited to the fabrication method of the semiconductor device provided in the embodiments of this application, and any semiconductor device prepared by a fabrication method that can form the semiconductor device structure provided in the embodiments of this application is within the scope of protection of this application.

[0095] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor material layer having a first conductivity type is provided, the semiconductor material layer comprising a first device region and a second device region; A first well region and a second well region are formed within the first device region; and, during the process of forming a second trench within the second device region, a first trench is formed within the first device region; during the process of forming a second dielectric layer on the inner wall of the second trench, a first dielectric layer is formed on the inner wall of the first trench; and during the process of forming a second semiconductor structure on the second dielectric layer within the second trench, a first semiconductor structure is formed on the first dielectric layer within the first trench; wherein, the first well region and the second well region respectively have a second conductivity type and a first conductivity type, the second well region, the first well region, and the semiconductor material layer form a parasitic transistor, and the first semiconductor structure and the second semiconductor structure have a first conductivity type; A conductive interconnect structure is formed on the semiconductor material layer, the conductive interconnect structure enabling the first well region to be electrically connected to the first semiconductor structure.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second device region is a region for forming a shielded gate trench type semiconductor device, and the second trench is a gate trench. The method further includes: Form an interlayer dielectric layer covering the first semiconductor structure; A portion of the second semiconductor structure is removed to form a control gate receiving trench, and the remaining second semiconductor structure is formed as a shielding gate; A gate dielectric layer and a control gate are formed within the control gate receiving groove.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, Along the thickness direction of the semiconductor material layer, the projection of the first trench surrounds the projection of the first well region.

4. The method for fabricating a semiconductor device according to claim 1 or 3, characterized in that, The first trench is disposed adjacent to the first well region.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method further includes: forming an interlayer dielectric layer covering the first semiconductor structure; Forming a conductive interconnect structure on the semiconductor material layer includes: forming a first via penetrating the interlayer dielectric layer above the first semiconductor structure, and forming a second via penetrating the interlayer dielectric layer above the first well region; filling the first via and the second via with conductive material to form a first conductive plug and a second conductive plug, respectively; forming a wiring layer on the interlayer dielectric layer, wherein the first conductive plug and the second conductive plug are conductively connected via the wiring layer; wherein the first via and the third via are formed simultaneously, and the third via is a via required to form a third conductive plug located in the second device region.

6. A semiconductor device, characterized in that, include: A semiconductor material layer having a first conductivity type, the semiconductor material layer comprising a first device region and a second device region; The first well region and the second well region are located in the first device region. The first well region and the second well region have a second conductivity type and a first conductivity type, respectively. The second well region, the first well region and the semiconductor material layer form a parasitic transistor. A second trench is located in the second device region, and a second dielectric layer and a gate structure are formed in the second trench. The second dielectric layer is located between the inner wall of the second trench and the gate structure. The first device region also includes a first trench, in which a first dielectric layer and a first semiconductor structure are formed. The first dielectric layer is located between the inner wall of the first trench and the first semiconductor structure. The first semiconductor structure and the gate structure have a first conductivity type. A conductive interconnect structure is located on the semiconductor material layer, such that the first well region is electrically connected to the first semiconductor structure.

7. The semiconductor device according to claim 6, characterized in that, The second device region is a region for forming a shielded gate trench semiconductor device. The gate structure is a shielded gate, and the second trench also includes a gate dielectric layer and a control gate.

8. The semiconductor device according to claim 6, characterized in that, Along the thickness direction of the semiconductor material layer, the projection of the first trench surrounds the projection of the first well region.

9. The semiconductor device according to claim 6 or 8, characterized in that, The first trench is disposed adjacent to the first well region.

10. The semiconductor device according to claim 6, characterized in that, Also includes: An interlayer dielectric layer covering the first semiconductor structure; The conductive interconnect structure includes: a first conductive plug that penetrates the interlayer dielectric layer and is conductively connected to the first semiconductor structure; a second conductive plug that penetrates the interlayer dielectric layer and is conductively connected to the first well region; and a wiring layer located on the interlayer dielectric layer; the first conductive plug and the second conductive plug are conductively connected via the wiring layer.

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