Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. This application provides a semiconductor device with minimal deviation in transistor characteristics. This application provides a semiconductor device including a transistor, wherein the transistor includes: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide; a second insulator on the second oxide; and a third conductor on the second insulator, wherein the top surface of the first oxide in the region overlapping with the third conductor is lower than the top surface of the first oxide in the region overlapping with the first conductor, and in the region overlapping with the third conductor, a curved surface is formed between the side surface and the top surface of the first oxide, the radius of curvature of the curved surface being 1 nm or more and 15 nm or less.

Description

[0001] This divisional application is a divisional application of Chinese patent application No. 201980083166.5, filed on November 19, 2019, entitled "Semiconductor Device and Method of Manufacturing a Semiconductor Device". Technical Field

[0002] One aspect of the present invention relates to a transistor, a semiconductor device, and an electronic device. Furthermore, one aspect of the present invention relates to a method for manufacturing a semiconductor device. Additionally, one aspect of the present invention relates to a semiconductor wafer and module.

[0003] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are also types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc., sometimes include semiconductor devices.

[0004] Note that one aspect of the present invention is not limited to the aforementioned technical fields. One aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Background Technology

[0005] The technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. In addition, oxide semiconductors have also garnered attention as other materials.

[0006] In oxide semiconductors, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single crystals nor amorphous, have been discovered (see Non-Patent Literature 1 to Non-Patent Literature 2).

[0007] Non-patent document 1 and non-patent document 2 disclose a technique for manufacturing transistors using an oxide semiconductor having a CAAC structure.

[0008] [Preliminary Technology Documents]

[0009] [Non-patent literature]

[0010] [Non-Patent Literature 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186

[0011] [Non-Patent Literature 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention

[0012] The technical problem that the invention aims to solve

[0013] One objective of this invention is to provide a semiconductor device with small deviations in transistor characteristics. Another objective of this invention is to provide a semiconductor device with high on-state current. Another objective of this invention is to provide a semiconductor device with good electrical characteristics. Another objective of this invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another objective of this invention is to provide a semiconductor device with high reliability. Furthermore, another objective of this invention is to provide a semiconductor device with low power consumption.

[0014] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above will be readily apparent from the description in the specification, drawings, claims, etc., and can be extracted from that description.

[0015] means of solving technical problems

[0016] One aspect of the present invention is a semiconductor device comprising: a transistor, wherein the transistor includes: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide; a second insulator on the second oxide; and a third conductor on the second insulator, wherein the top surface of the first oxide in the region overlapping with the third conductor is lower than the top surface of the first oxide in the region overlapping with the first conductor, and in the region overlapping with the third conductor, a curved surface is formed between the side surface and the top surface of the first oxide, and the radius of curvature of the curved surface is more than 1 nm and less than 15 nm.

[0017] In the aforementioned semiconductor device, it is preferable that, with the bottom surface of the first insulator as a reference, the difference between the height of the top surface of the first oxide in the region overlapping with the third conductor and the height of the top surface of the first oxide in the region overlapping with the first conductor is 1 nm or more and 5 nm or less.

[0018] In the semiconductor device described above, it is preferable that, in the channel width direction of the transistor, half of the difference between the length of the bottom surface of the first oxide in the region overlapping with the first conductor and the length of the bottom surface of the first oxide in the region overlapping with the third conductor is 2 nm or more and 10 nm or less.

[0019] In the aforementioned semiconductor device, it is preferred that the transistor includes a third oxide and a fourth oxide, the third oxide being disposed between the first oxide and the first conductor, the fourth oxide being disposed between the first oxide and the second conductor, and in the channel length direction of the transistor, the bottom surface of the second oxide is lower than the bottom surface of the third oxide and the bottom surface of the fourth oxide.

[0020] Another aspect of the present invention is a semiconductor device comprising: a plurality of transistors, wherein the plurality of transistors includes: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide; a second insulator on the second oxide; and a third conductor on the second insulator, wherein the top surface of the first oxide in the region overlapping with the third conductor is lower than the top surface of the first oxide in the region overlapping with the first conductor, and in the region overlapping with the third conductor, a curved surface is formed between the side surface and the top surface of the first oxide, and, in the Id-Vg characteristics of the plurality of transistors, the standard deviation σ of Vsh is less than 60mV.

[0021] In the above-described semiconductor device, it is preferred that the channel length of the plurality of transistors is 40 nm or more and 80 nm or less, and the channel width of the plurality of transistors is 40 nm or more and 80 nm or less.

[0022] In the aforementioned semiconductor device, the radius of curvature of the curved surface is preferably 1 nm or more and 15 nm or less.

[0023] Another aspect of the present invention is a semiconductor device comprising: a transistor, wherein the transistor includes: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide; a second insulator on the second oxide; a third conductor on the second insulator; and a third insulator disposed in contact with a portion of the top surface of the first conductor, the top surface of the second conductor, and a portion of the side surface of the first oxide, wherein, in the channel width direction of the transistor, the length of the bottom surface of the first oxide in the region overlapping with the first conductor is greater than the length of the bottom surface of the first oxide in the region overlapping with the third conductor, and a curved surface is formed between the side surface and the top surface of the first oxide in the region overlapping with the third conductor, the first oxide comprising indium, element M (M being gallium, yttrium, or tin), and zinc, the third insulator comprising an element that is an impurity of the first oxide, and the concentration ratio of the element to element M in the side surface of the first oxide in the region overlapping with the third conductor is less than the concentration ratio of the element to element M in the side surface of the first oxide in the region overlapping with the first conductor.

[0024] In the aforementioned semiconductor device, the third insulator preferably contains aluminum.

[0025] In the aforementioned semiconductor device, the radius of curvature of the curved surface is preferably 1 nm or more and 15 nm or less.

[0026] Invention Effects

[0027] According to one aspect of the present invention, a semiconductor device with small deviations in transistor characteristics can be provided. According to one aspect of the present invention, a semiconductor device with high on-state current can be provided. According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. According to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not require achieving all of the above-described effects. Effects other than those described above are readily apparent from the description in the specification, drawings, claims, etc., and can be extracted from that description. Attached Figure Description

[0029] Figure 1A This is a top view of a semiconductor device according to one aspect of the present invention. Figures 1B to 1D This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0030] Figure 2 This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0031] Figure 3A , Figure 3B This is a perspective view of a semiconductor device according to one aspect of the present invention.

[0032] Figure 4A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 4B to 4D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0033] Figure 5A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 5B to 5D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0034] Figure 6A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 6B to 6D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0035] Figure 7A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7B to 7D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0036] Figure 8A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8B to 8D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0037] Figure 9A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0038] Figure 10A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0039] Figure 11A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0040] Figure 12AThis is a top view of a semiconductor device according to one aspect of the present invention. Figures 12B to 12D This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0041] Figure 13A , Figure 13B This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0042] Figure 14 This is a cross-sectional view illustrating the structure of a storage device according to one embodiment of the present invention.

[0043] Figure 15 This is a cross-sectional view illustrating the structure of a storage device according to one embodiment of the present invention.

[0044] Figure 16A , Figure 16B This is a block diagram illustrating a structural example of a storage device according to one aspect of the present invention.

[0045] Figures 17A to 17H This is a circuit diagram illustrating a structural example of a storage device according to one aspect of the present invention.

[0046] Figure 18A , Figure 18B This is a schematic diagram of a semiconductor device according to one aspect of the present invention.

[0047] Figures 19A to 19E This is a schematic diagram of a storage device according to one aspect of the present invention.

[0048] Figures 20A to 20H This is a diagram illustrating an electronic device according to one aspect of the present invention.

[0049] Figure 21 This is a graph showing the normal probability of the Shift values ​​of the samples in the embodiment.

[0050] Figure 22 This is a graph illustrating the stress-time dependence of ΔVsh in the +GBT stress test of an embodiment.

[0051] Figure 23A This is a graph illustrating the stress-time dependence of Ion in the +GBT stress test of an embodiment. Figure 23B This is a graph showing the stress-time dependence of the S value in the +GBT stress test of the embodiment. Figure 23C This is a graph illustrating the stress-time dependence of μFE under +GBT stress testing according to an embodiment.

[0052] Figure 24 This is a graph illustrating the Id-Vg characteristics of the transistor in the embodiment.

[0053] Figure 25A This is a graph illustrating the normal probability of Vsh in an embodiment. Figure 25B This is a graph illustrating the normal probability diagram of Ion in an embodiment. Figure 25C This is a diagram illustrating the Vbg dependency of Vsh in an embodiment.

[0054] Figure 26A ΔVsh is the +GBT stress test result shown in the embodiment. Figure 26B This is a graph illustrating the stress-time dependence of the S value in an embodiment. Detailed Implementation

[0055] The embodiments will now be described with reference to the accompanying drawings. It should be noted that those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0056] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, ideal examples are schematically illustrated in the drawings, and the invention is not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting redundant descriptions. Furthermore, the same shading lines are sometimes used when indicating parts with the same function, without additional reference numerals.

[0057] Furthermore, especially in top views (also known as plan views) or perspective views, descriptions of some constituent elements are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines, etc., are sometimes omitted.

[0058] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are added for convenience, but they do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify one aspect of the present invention.

[0059] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate configuration, referring to the accompanying drawings to illustrate the positional relationships of the constituent elements. Furthermore, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0060] For example, in this specification, when it is explicitly stated as "X and Y are connected," it means the following: X and Y are electrically connected; X and Y are functionally connected; X and Y are directly connected. Therefore, connection relationships other than those shown in the drawings or text are disclosed in the drawings or text, not limited to those specified therein. Here, X and Y refer to objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0061] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as the channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) that forms a channel, and current can flow between the source and drain through the channel-forming region. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0062] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may sometimes be interchanged.

[0063] Note that channel length, for example, refers to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor, or between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel-forming region. Furthermore, the channel length in a transistor is not necessarily the same value in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length refers to any value, maximum, minimum, or average value in the channel-forming region.

[0064] The channel width, for example, refers to the length of the channel-forming region perpendicular to the channel length direction in the overlapping area of ​​the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor. Furthermore, the channel width in a transistor is not necessarily the same value in all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value within the channel-forming region.

[0065] In this specification, depending on the transistor structure, the actual channel width (hereinafter referred to as "effective channel width") in the region forming the channel sometimes differs from the channel width shown in the top view of the transistor (hereinafter referred to as "apparent channel width"). For example, when the gate electrode covers the side of the semiconductor, sometimes the effect cannot be ignored because the effective channel width is greater than the apparent channel width. For example, in miniature transistors where the gate electrode covers the side of the semiconductor, sometimes the proportion of the channel formation region formed on the side of the semiconductor is increased. In this case, the effective channel width is greater than the apparent channel width.

[0066] In the aforementioned situations, it can sometimes be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width based on design values ​​requires the assumption that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is uncertain, it is difficult to accurately determine the effective channel width.

[0067] In this specification, when simply described as "channel width," it sometimes refers to the apparent channel width. Alternatively, in this specification, when simply referred to as "channel width," it sometimes refers to the actual channel width. Note that the values ​​of channel length, channel width, actual channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0068] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1, Group 2, Group 13, Group 14, and Group 15 elements, as well as transition metals other than the main components of the oxide semiconductor. Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to oxygen vacancies (also known as V vacancies) in the oxide semiconductor. O The formation of oxygen vacancy.

[0069] Note that in this specification, silicon oxynitride refers to a substance with an oxygen content greater than its nitrogen content. Furthermore, silicon oxynitride refers to a substance with a nitrogen content greater than its oxygen content.

[0070] Note that in this specification, etc., "insulator" may be replaced with "insulating film" or "insulating layer". Additionally, "conductor" may be replaced with "conductive film" or "conductive layer". Furthermore, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

[0071] In this specification, "parallel" refers to a state where the angle between two straight lines is -10 degrees or more and less than 10 degrees. Therefore, it also includes a state where the angle is -5 degrees or more and less than 5 degrees. Furthermore, "approximately parallel" refers to a state where the angle between two straight lines is -30 degrees or more and less than 30 degrees. Additionally, "perpendicular" refers to a state where the angle between two straight lines is 80 degrees or more and less than 100 degrees. Therefore, it also includes a state where the angle is 85 degrees or more and less than 95 degrees. "Approximately perpendicular" refers to a state where the angle between two straight lines is 60 degrees or more and less than 120 degrees.

[0072] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor that contains metal oxides or oxide semiconductors.

[0073] Note that in this specification, "normally off" means that the drain current flowing through the transistor per channel width of 1 μm is 1 × 10⁻⁶ at room temperature when no gate potential is applied or when a ground potential is applied to the gate. -20 Below A, at 85℃, it is 1×10 -18 Below A, or 1×10 at 125℃ -16 Below A.

[0074] (Implementation Method 1)

[0075] In this embodiment, an example of a semiconductor device including a transistor 200 according to one aspect of the present invention will be described.

[0076] <Examples of semiconductor device structures>

[0077] Figures 1A to 1D It is a top view and cross-sectional view of a semiconductor device including transistor 200. Figure 1A This is a top view of the semiconductor device. Furthermore, Figures 1B to 1D This is a cross-sectional view of the semiconductor device. Here, Figure 1B It is along Figure 1A The cross-sectional view along the dotted line A1-A2 in the diagram corresponds to a cross-sectional view along the channel length of transistor 200. Additionally, Figure 1C It is along Figure 1A The cross-sectional view of the section marked with dotted lines A3-A4 in the figure corresponds to a cross-sectional view of the transistor 200 in the channel width direction. Figure 1D It is along Figure 1A The cross-sectional view of the section marked with dashed lines A5-A6. Note that in... Figure 1A In the top view, some constituent elements are omitted for clarity.

[0078] One aspect of the semiconductor device of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 281 on the insulator 274. Insulators 212, 214, 280, 282, 283, 274, and 281 are used as interlayer films. Additionally, the semiconductor device includes a conductor 240 (conductors 240a and 240b) electrically connected to the transistor 200 and used as a connector. Furthermore, insulators 241 (insulators 241a and 241b) are disposed in contact with the side surfaces of the conductor 240 used as a connector. Additionally, conductors 246 (conductor 246a and conductor 246b) are provided on insulator 281 and conductor 240, respectively, and are electrically connected to conductor 240 and used for wiring.

[0079] An insulator 241a is disposed in contact with the inner wall of the openings of insulators 254, 280, 282, 283, 274, and 281. A first conductor 240a is disposed in contact with the side of insulator 241a, and a second conductor 240a is disposed inside it. Similarly, an insulator 241b is disposed in contact with the inner wall of the openings of insulators 254, 280, 282, 283, 274, and 281. A first conductor 240b is disposed in contact with the side of insulator 241b, and a second conductor 240b is disposed inside it. Here, the height of the top surface of conductor 240 and the height of the top surface of insulator 281 can be approximately the same. Furthermore, in transistor 200, the first conductor and the second conductor of conductor 240 are stacked, but the present invention is not limited thereto. For example, conductor 240 may also have a single-layer structure or a stacked structure of three or more layers. In the case of a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for differentiation.

[0080] [Transistor 200]

[0081] like Figures 1A to 1DAs shown, transistor 200 includes an insulator 216 on an insulator 214; conductors 205 (conductors 205a and 205b) disposed in the insulator 216; an insulator 222 on the insulator 216 and on the conductors 205; an insulator 224 on the insulator 222; an oxide 230a on the insulator 224; an oxide 230b on the oxide 230a; and conductors 242a, 242b, and oxide on the oxide 230b. Oxide 230c; insulator 250 on oxide 230c; conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping oxide 230c; insulator 254 in contact with a portion of the top surface of insulator 224, a portion of the side surface of oxide 230a, a portion of the side surface of oxide 230b, the side surface of conductor 242a, the top surface of conductor 242a, the side surface of conductor 242b, and the top surface of conductor 242b. Furthermore, oxide 230c is in contact with the side surface of insulator 254, the side surface of conductor 242a, and the side surface of conductor 242b. Here, as... Figure 1B As shown, the top surface of the conductor 260 is arranged in a manner that substantially coincides with the top surface of the insulator 250 and the top surface of the oxide 230c. Furthermore, the insulator 282 is in contact with each of the top surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280.

[0082] An opening leading to oxide 230b is provided in insulators 280 and 254. Oxide 230c, insulator 250, and conductor 260 are disposed within this opening. Furthermore, conductor 260, insulator 250, and oxide 230c are disposed between conductor 242a and conductor 242b along the channel length direction of transistor 200. Insulator 250 includes a region overlapping with the side surface of conductor 260 and a region overlapping with the top surface of conductor 260. In addition, in the region overlapping with oxide 230b, oxide 230c includes a region in contact with oxide 230b, a region overlapping with the side surface of conductor 260 across insulator 250, and a region overlapping with the bottom surface of conductor 260 across insulator 250.

[0083] Transistor 200 preferably uses metal oxides (hereinafter also referred to as oxide semiconductors) as oxides 230 (oxides 230a, oxides 230b and oxides 230c) that include the channel forming region.

[0084] The metal oxide used as a semiconductor preferably has a band gap of 2 eV or more, and more preferably 2.5 eV or more. In this way, by using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced.

[0085] Because transistors using metal oxides in the channel formation region have extremely low leakage current when in the non-conducting state, they can provide low-power semiconductor devices. Furthermore, since metal oxides can be formed using methods such as sputtering, they can be used to construct transistors for highly integrated semiconductor devices.

[0086] For example, as oxide 230, an In-M-Zn oxide containing indium, element M, and zinc (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used. In addition, In-Ga oxide and In-Zn oxide may also be used as oxide 230.

[0087] Oxide 230 preferably includes oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, and oxide 230c disposed on oxide 230b, at least a portion of which is in contact with the top surface of oxide 230b. When oxide 230a is disposed under oxide 230b, the diffusion of impurities from the structure formed under oxide 230a to oxide 230b can be suppressed. When oxide 230c is disposed on oxide 230b, the diffusion of impurities from the structure formed above oxide 230c to oxide 230b can be suppressed.

[0088] Note that in transistor 200, oxide 230 has a three-layer structure consisting of oxide 230a, oxide 230b, and oxide 230c, but the present invention is not limited thereto. For example, it may also be provided as a single layer of oxide 230b, a two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers. Oxide 230a, oxide 230b, and oxide 230c may also each have a stacked structure.

[0089] Oxides 230a, 230b, 230c preferably contain a common element as a main component in addition to oxygen. This reduces the defect state density at the interfaces between oxides 230a and 230b, and between oxides 230b and 230c. Consequently, the impact of interface scattering on carrier conduction is reduced, resulting in high on-state current and high frequency characteristics in the transistor 200.

[0090] Conductors 242 (conductors 242a and 242b) are disposed on oxide 230b. Conductors 242a and 242b are used as the source electrode or drain electrode of transistor 200, respectively.

[0091] Conductor 260 includes conductor 260a and conductor 260b, and conductor 260a is arranged to surround the bottom and side surfaces of conductor 260b. Conductor 260 is used as the first gate (also called top gate) electrode of transistor 200.

[0092] Figure 2 Showing Figure 1B A magnified cross-sectional view of a portion of transistor 200 is shown. Figure 2 As shown, oxide 230 includes region 234, which serves as a channel formation region for transistor 200, and region 231 (regions 231a and 231b), which serve as source or drain regions. Region 231 is a low-resistivity region with high carrier concentration. Furthermore, region 231 sometimes includes a portion of the aforementioned low-resistivity region. Additionally, the carrier concentration in region 234 is lower than that in region 231. Note that at least a portion of region 231a and at least a portion of region 231b respectively include regions in contact with conductors 242a and 242b.

[0093] Note that in Figure 2 Regions 231 and 234 are shown to be formed in oxide 230b, but are not limited thereto. For example, regions 231 or 234 may also be formed in oxides 230a and 230b, in oxides 230b and 230c, or in oxides 230a, 230b and 230c.

[0094] In addition, Figure 2 The diagram shows that the boundaries of regions 231 and 234 are substantially perpendicular to the bottom surface of oxide 230b, but this embodiment is not limited to this. For example, sometimes region 234 extends toward the conductor 240 near the surface of oxide 230b and becomes narrower near the bottom surface of oxide 230b.

[0095] In transistors using oxide semiconductors in the channel formation region, when a low-resistance region is formed in the channel formation region, leakage current (parasitic channel) is easily generated between the source and drain electrodes of the transistor in this low-resistance region. Furthermore, this parasitic channel easily leads to transistor characteristic defects such as constant-on behavior, increased leakage current, and threshold voltage fluctuations (drift) due to pressure application. Moreover, when the transistor's fabrication precision is low, this parasitic channel, along with transistor deviations, causes deviations in transistor characteristics.

[0096] Furthermore, in transistors using oxide semiconductors, the presence of impurities and oxygen vacancies in the channel formation region can sometimes lead to low resistance in the oxide semiconductor. Additionally, the electrical characteristics can easily change, sometimes resulting in decreased reliability. Examples of such impurities include aluminum (Al) and silicon (Si). When these impurities enter the channel formation region, they can sometimes form defect states or oxygen vacancies.

[0097] Aluminum and silicon have higher bonding energies with oxygen than indium and zinc. For example, when In-M-Zn oxide is used as an oxide semiconductor, when aluminum is mixed into the oxide semiconductor, the oxygen contained in the oxide semiconductor is captured by the aluminum, and thus oxygen vacancies are sometimes formed near indium or zinc.

[0098] When the channel formation region in a metal oxide contains oxygen vacancies, the transistor tends to exhibit always-on characteristics. Furthermore, when hydrogen enters an oxygen vacancy in a metal oxide, the oxygen vacancy sometimes bonds with the hydrogen to form a V0. O H. Defects for oxygen vacancies entering hydrogen (V O Hydrogen (H) is used as a donor, sometimes generating electrons as charge carriers. Additionally, sometimes electrons are generated as charge carriers due to partial bonding between hydrogen and oxygen atoms bonded to metal atoms. Therefore, transistors using metal oxides containing a higher hydrogen content tend to have always-on characteristics. Furthermore, because hydrogen in metal oxides is easily moved by pressure such as heat and electric fields, the reliability of transistors may decrease when the metal oxide contains a higher hydrogen content.

[0099] Therefore, it is preferable to minimize the impurities and oxygen vacancies in and around the channel formation region of the oxide semiconductor.

[0100] Therefore, the structure in and around the channel formation region of the transistor is preferably in the shape described later. By making the structure constituting the transistor in the shape described later, the low-resistance region formed in the channel formation region can be reduced, thus suppressing the formation of parasitic channels. Therefore, deviations in transistor characteristics caused by parasitic channels can be suppressed. Here, transistor characteristics refer to the current value in the on-state (on-state current value), the current value in the off-state (off-state current value), the threshold voltage, the subthreshold swing value (S value), the field-effect mobility, etc. Furthermore, reducing the impurity concentration in and around the channel formation region of the oxide semiconductor can improve the reliability of the transistor.

[0101] <Preferred shape of the trench formation area and nearby structures>

[0102] The preferred shape of the channel formation region and the structure in its vicinity is described below. Note that, for simplicity, the region of transistor 200 used as the channel formation region is formed in oxide 230b.

[0103] Figure 3A yes Figures 1A to 1D A 3D view of transistor 200 and its vicinity is shown. Furthermore, Figure 3B Showing Figure 3A A magnified 3D view of a portion of transistor 200 shown. Note that in Figure 3A and Figure 3B In the 3D diagram, some of the constituent elements have been omitted for clarity.

[0104] Oxide 230b includes region 231a in contact with at least a portion of conductor 242a. Figure 3A , Figure 3B (Not shown), region 231b in contact with at least a portion of conductor 242b ( Figure 3A , Figure 3B (Not shown) Region 234, between region 231a and region 231b, is used as the channel forming region of transistor 200. Region 234 includes the region in oxide 230b where oxide 230b overlaps with conductor 260. Hereinafter, the region in oxide 230b where oxide 230b overlaps with conductor 242a can be referred to as region 231a, and the region in oxide 230b where oxide 230b overlaps with conductor 242b can be referred to as region 231b.

[0105] like Figure 1C and Figure 3B As shown, in the cross-section of the transistor 200 in the channel width direction, it is preferable that there is a curved surface between the side surface and the top surface of the oxide 230b in region 234. That is, the ends of the side surface and the ends of the top surface are preferably curved (hereinafter also referred to as circular).

[0106] Here, as Figure 2 and Figure 3B As shown, in the cross-section along the channel length of transistor 200, the distance between the side ends of conductors 242a and 242b, which are opposite each other, is L. Note that L can also be described as the length of the top surface of oxide 230b in the region of the cross-section along the channel length of transistor 200 that does not overlap with conductor 242.

[0107] In addition, such as Figure 3B As shown, in the cross-section of the transistor 200 in the channel width direction, the length of the region without a curved surface on the top surface of the oxide 230b in the region where the oxide 230b overlaps with the conductor 260 is W.

[0108] In addition, such as Figure 3BAs shown, the radius of curvature of the aforementioned curved surface is La. Note that, sometimes in a cross-section of the channel width direction of transistor 200, La is considered as the difference between the height of the top surface of oxide 230b and the height of the lower end of the curved surface region of the side surface of oxide 230b in the region where oxide 230b and conductor 260 overlap, with the bottom surface of insulator 224 as a reference.

[0109] The thickness of La is preferably greater than 0 nm and less than the thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half of the thickness of W. Specifically, La is greater than 0 nm and less than 20 nm, preferably more than 1 nm and less than 15 nm, and more preferably more than 2 nm and less than 10 nm. By adopting this shape, the concentrated electric field between the side surface and the top surface can be suppressed, thus suppressing variations in transistor characteristics. Furthermore, preventing a reduction in W can suppress a decrease in the turn-on current and mobility of the transistor 200. Therefore, a semiconductor device with good electrical characteristics can be provided.

[0110] Furthermore, by adopting the above-described shape, in region 234, the effective channel length on the side surface of oxide 230b is greater than the effective channel length on the top surface of oxide 230b, thereby reducing the current flowing through this side surface. Therefore, by suppressing the influence of parasitic channels formed on this side surface, the S-value of transistor 200 can be reduced. Furthermore, the influence of the deviation of each transistor in the parasitic channels formed on this side surface is reduced, thus providing a semiconductor device with less transistor characteristic deviation.

[0111] In the cross-section along the channel width direction of transistor 200, the length of the region without a curved surface on the side of oxide 230b in the area where oxide 230b overlaps with conductor 260 is Lb. Note that when the side of oxide 230b in the area where oxide 230b overlaps with conductor 260 has a tapered shape, Lb can also be referred to as the length of the tapered portion of oxide 230b. Furthermore, Lb is sometimes considered as the difference between the height of the upper end of the region without the curved surface and the height of the lower end of the region without the curved surface, with the bottom surface of insulator 224 as a reference. Lb depends on La, the thickness of oxide 230b, the taper angle of oxide 230b, etc. Here, the taper angle refers to the angle between the side surface of the tapered film and the bottom surface of the film.

[0112] Furthermore, the reduction in film thickness of the top surface of the oxide 230b in the region where the oxide 230b overlaps with the conductor 260 is Lc. For example, Lc can be calculated as the difference between the height of the top surface of the oxide 230b overlapping the conductor 242 and the height of the top surface of the oxide 230b overlapping the conductor 260 in a cross-section in the channel width direction of the transistor 200, with the bottom surface of the insulator 222 as a reference.

[0113] As explained later, when the elements contained in the conductive layer 242B, which is disposed on and in contact with the oxide 230b, have the function of absorbing oxygen from the oxide 230b, a low-resistance region is sometimes partially formed between the oxide 230b and the conductive layer 242B or near the surface of the oxide 230b. Furthermore, when the elements contained in the insulating film 254A, which is disposed in contact with the side of the channel formation region of the oxide 230b, have the function of absorbing oxygen from the oxide 230b, a low-resistance region is sometimes partially formed between the oxide 230b and the insulating film 254A or near the side of the channel formation region of the oxide 230b. That is, these elements sometimes become impurities in the oxide semiconductor. In this case, in the low-resistance region, impurities or impurities that enter oxygen vacancies (hydrogen, nitrogen, metal elements, etc.) are used as donors, and the carrier density increases.

[0114] Furthermore, when impurities are introduced into oxide semiconductors, defect states or oxygen vacancies are sometimes formed. Therefore, when impurities are introduced into the channel formation region of an oxide semiconductor, the electrical characteristics of transistors using oxide semiconductors may change, thereby reducing reliability. In addition, when oxygen vacancies are included in the channel formation region, the transistor will exhibit always-on characteristics (the characteristic that current flows through the transistor even when no voltage is applied to the gate electrode).

[0115] Therefore, the top surface of the oxide 230b in region 234 is preferably lower than the top surface of the oxide 230b in the region overlapping with the conductor 242. For example, Lc is preferably greater than 0 nm and less than the thickness of the oxide 230b in the region overlapping with the conductor 242. Specifically, Lc is greater than 0 nm and less than 15 nm, preferably more than 0.5 nm and less than 10 nm, and more preferably more than 1 nm and less than 5 nm. By adopting this shape, the aforementioned impurities are removed, and the low-resistance region formed near the top surface of region 234 is reduced, thus suppressing the formation of parasitic channels. Note that the effective channel length of the top surface of region 234 is L + 2 × Lc. Therefore, by reducing Lc, the reduction in the transistor's turn-on current can be suppressed.

[0116] Furthermore, the amount of film reduction on the side surface of the oxide 230b in the region where the oxide 230b overlaps with the conductor 260 is referred to as We. For example, We can be calculated as the difference between the side surface of the oxide 230b in the region overlapping with the conductor 242 and the side surface of the oxide 230b in the region without the aforementioned curved surface in a cross-section of the transistor 200 in the channel width direction. Furthermore, for example, We can be calculated as half the difference between the length of the bottom surface of the oxide 230b in the region overlapping with the conductor 242 and the length of the bottom surface of the oxide 230b in the region not overlapping with the conductor 242 in a cross-section of the transistor 200 in the channel width direction.

[0117] We is preferably greater than 0 nm and is less than or equal to the thickness of oxide 230b in the region overlapping with conductor 242. Specifically, We is greater than 0 nm and less than 20 nm, preferably more than 1 nm and less than 15 nm, and more preferably more than 2 nm and less than 10 nm. By making We greater than 0 nm, impurities near the side of region 234 are removed, the low-resistance region is reduced, and thus the formation of parasitic channels can be suppressed.

[0118] This reduces the low-resistance region formed in the channel formation region, thus suppressing the formation of parasitic channels. Consequently, deviations in transistor characteristics caused by parasitic channels can be suppressed. Furthermore, the impurity concentration in and around the channel formation region of the oxide semiconductor can be reduced, thereby improving transistor reliability.

[0119] By adopting the aforementioned shape for the channel formation region and surrounding structures of transistor 200, deviations in transistor characteristics can be reduced. For example, deviations in Vsh can be reduced. In this specification, Vsh is defined by the drain current Id = 1.0 × 10⁻⁶ on the transistor's Id-Vg curve. -12 The gate voltage Vg is defined at time A. For example, the deviation of Vsh can be evaluated using the standard deviation σ. The standard deviation σ of Vsh for each transistor (n is an integer greater than or equal to 3) is expressed by the following formula.

[0120] [Equation 1]

[0121]

[0122] In the above formula, x i Let Vsh be the value of the i-th transistor (i is an integer greater than or equal to 1 and less than or equal to n), and μ be the average value of Vsh of the n transistors.

[0123] In the Id-Vg characteristics of transistor 200, specifically, the standard deviation σ of Vsh is 60mV or less, preferably 40mV or less, and more preferably 20mV or less.

[0124] Furthermore, by adopting the aforementioned shape for the structure in and around the channel formation region of the transistor 200, the impurity concentration in and around the channel formation region of the oxide semiconductor can be reduced. Specifically, the impurity concentration obtained by secondary ion mass spectrometry (SIMS) in and around the channel formation region of the oxide semiconductor is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3Alternatively, in the channel formation region and vicinity of the oxide semiconductor, the impurity concentration obtained by elemental analysis using energy dispersive X-ray spectroscopy (EDX) is 1.0 atomic% or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of impurities to element M in the channel formation region and vicinity of the oxide semiconductor is less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio can be the concentration of the same region as the region where the impurity concentration is calculated or the concentration in the oxide semiconductor.

[0125] Furthermore, the impurity concentration on the sides of the oxide 230b in the channel forming region is lower than the impurity concentration on the sides of the oxide 230b in the region overlapping with the conductor 242. Alternatively, the ratio of impurity to element M concentration on the sides of the oxide 230b in the channel forming region is lower than the ratio of impurity to element M concentration on the sides of the oxide 230b in the region overlapping with the conductor 242. Furthermore, the ratio of impurity to element M concentration on the top surface of the oxide 230b in the channel forming region is lower than the ratio of impurity to element M concentration on the top surface of the oxide 230b in the region overlapping with the conductor 242.

[0126] <Detailed Structure of Semiconductor Devices>

[0127] The following describes a semiconductor device according to one aspect of the present invention and the detailed structure of the transistor 200 included in the semiconductor device.

[0128] Insulators 212, 214, 254, 282, 283, and 281 are preferably used as barrier insulating films to suppress the diffusion of impurities such as water and hydrogen from the substrate side or above the transistor 200 to the transistor 200. Therefore, insulators 212, 214, 254, 282, 283, and 281 are preferably made of insulating materials that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Furthermore, insulating materials that have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate) are preferably used.

[0129] For example, it is preferable to use silicon nitride as insulator 212, insulator 283, and insulator 281, and aluminum oxide as insulator 214, insulator 254, and insulator 282. This suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulator 212 and insulator 214. Furthermore, it suppresses the diffusion of oxygen contained in insulator 224 and the like to the substrate side via insulator 212 and insulator 214. Additionally, it suppresses the diffusion of impurities such as water and hydrogen from insulator 280, conductor 246, etc., disposed above insulator 254, through insulator 254 to the inside of transistor 200. Thus, it is preferable to surround transistor 200 with insulators 212, 214, 254, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0130] Additionally, it is sometimes preferable to reduce the resistivity of insulators 212, 283, and 281. For example, by setting the resistivity of insulators 212, 283, and 281 to 1 × 10⁻⁶. 13 With a resistivity of approximately Ωcm, insulators 212, 283, and 281 can mitigate charge buildup in conductors 205, 242, or 260 during processes such as plasma treatment in semiconductor device manufacturing. The resistivity of insulators 212, 283, and 281 is 1×10⁻⁶. 10 Ωcm or more and 1×10 15 Below Ωcm.

[0131] Furthermore, the dielectric constant of insulators 216, 280, and 274 is preferably lower than that of insulator 214. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen added, and porous silicon oxide are appropriately used as insulators 216, 280, and 274.

[0132] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Alternatively, the conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0133] Conductor 260 is sometimes used as the first gate electrode. Conductor 205 is sometimes used as the second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential supplied to conductor 205 without linking it to the potential supplied to conductor 260. In particular, by supplying a negative potential to conductor 205, the Vth of transistor 200 can be increased and the off-state current can be reduced. Therefore, compared with not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential supplied to conductor 260 is 0V.

[0134] In addition, such as Figure 1A As shown, the conductor 205 is preferably larger than the region of oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as Figure 1C As shown, conductor 205 preferably extends to the region outside the end of oxide 230 that intersects the channel width direction. That is, conductor 205 and conductor 260 preferably overlap with an insulator on the outer side of the side of oxide 230 in the channel width direction. With the above structure, a region can be formed around the channel of oxide 230 by the electric field of conductor 260 used as the first gate electrode and the electric field of conductor 205 used as the second gate electrode. In this specification, the structure of a transistor in which the electric fields of the first gate and the second gate form a region around the channel is referred to as a surround-channel (S-channel) structure.

[0135] In this specification, an S-channel transistor refers to a transistor structure in which the electric field of one of a pair of gate electrodes surrounds the channel forming region. Furthermore, in this specification, the S-channel structure has the following characteristics: similar to the channel forming region, the sides and peripheries of the oxide 230 in contact with the conductors 242a and 242b, which serve as the source and drain electrodes, are type I. Additionally, since it is in contact with the insulator 280, the sides and peripheries of the oxide 230 in contact with the conductors 242a and 242b may also be type I, similar to the channel forming region. In this specification, type I can be considered the same as the high-purity intrinsic structure described later. Furthermore, the S-channel structure disclosed in this specification differs from Fin-type and planar structures. By employing the S-channel structure, the tolerance to short-channel effects can be improved; in other words, a transistor less prone to short-channel effects can be realized.

[0136] In addition, such as Figure 1CAs shown, conductor 205 is extended for use as wiring. However, the invention is not limited to this; conductors used for wiring may also be provided under conductor 205. Furthermore, it is not necessary to provide a conductor 205 in every transistor. For example, conductor 205 can be shared in multiple transistors.

[0137] Furthermore, in transistor 200, conductors 205a and 205b are stacked together, but the present invention is not limited thereto. For example, conductor 205 may also have a single-layer structure or a stacked structure of three or more layers. In the case of a structure having a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for distinction.

[0138] Here, as the conductor 205a, it is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0139] By using a conductive material that inhibits oxygen diffusion as conductor 205a, the oxidation of conductor 205b and the resulting decrease in conductivity can be prevented. For example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used as conductive materials that inhibit oxygen diffusion. Therefore, conductor 205a can have a single-layer or multilayer structure of the aforementioned conductive materials. For example, conductor 205a can have a multilayer structure of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0140] As the conductor 205b, a conductive material with tungsten, copper, or aluminum as the main component is preferably used. In the accompanying drawings, the conductor 205b has a single-layer structure, but it can also have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the aforementioned conductive material can be used.

[0141] Insulators 222 and 224 are used as gate insulators.

[0142] Insulator 222 preferably has the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Additionally, insulator 222 is preferably a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, insulator 222 preferably has the function of suppressing the diffusion of one or both hydrogen and oxygen compared to insulator 224.

[0143] The insulator 222 is preferably an insulator containing an oxide of one or both of aluminum and hafnium as the insulating material. Aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as this insulator. When this material is used to form the insulator 222, the insulator 222 serves as a layer to suppress the release of oxygen from the oxide 230 to the substrate side or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inside of the transistor 200 can be suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 230. Furthermore, the reaction between the conductor 205 and the oxygen contained in the insulator 224 or the oxide 230 can be suppressed.

[0144] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to these insulators. Alternatively, the insulators can be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride can be laminated onto the aforementioned insulator as insulator 222.

[0145] Furthermore, as the insulator 222, insulators containing so-called high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST) can be used, either as a single layer or in a stack. When miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0146] Here, in the insulator 224 that is in contact with the oxide 230, it is preferable to remove the oxygen by heating. For example, silicon oxide, silicon oxynitride, etc., can be appropriately used as the insulator 224. By providing an oxygen-containing insulator in a manner that allows it to contact the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0147] Specifically, the insulator 224 preferably uses an oxide material that undergoes partial oxygen removal upon heating, i.e., an insulator material with an excess oxygen region. An oxide film that undergoes oxygen removal upon heating is defined as one in which the amount of oxygen removed, converted to oxygen molecules in TDS (Thermal Desorption Spectroscopy) analysis, is 1.0 × 10⁻⁶. 18 molecules / cm 3 The preferred value is 1.0 × 10⁴. 19 molecules / cm 3 The above is further preferred to be 2.0×10 19molecules / cm 3 Above, or 3.0 × 10 20 molecules / cm 3 The above-mentioned oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0148] Alternatively, the insulator and oxide 230 with excess oxygen regions described above can be subjected to one or more of the following treatments: heat treatment, microwave treatment, and RF treatment, in a manner that involves contact between them. This treatment can remove water or hydrogen from the oxide 230. For example, in the oxide 230, defects (V0) formed by hydrogen entering oxygen vacancies occur. O The reaction in which the H) bond is broken, in other words, the "V" reaction occurs. O H→V O The reaction of +H is used to achieve dehydrogenation. Some of the hydrogen produced here is sometimes bonded to oxygen and removed as H2O from oxide 230 or the insulator near oxide 230. In addition, some hydrogen sometimes diffuses into conductor 242 or is captured by conductor 242 (also known as gettering).

[0149] For example, the microwave processing described above preferably uses a device equipped with a power supply that generates high-density plasma or a device equipped with a power supply that applies RF to one side of the substrate. For example, by using a gas containing oxygen and using high-density plasma, high-density oxygen free radicals can be generated, and by applying RF to one side of the substrate, the oxygen free radicals generated by the high-density plasma can be efficiently introduced into oxide 230 or an insulator near oxide 230. In addition, the pressure of the microwave processing is set to 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. Furthermore, oxygen and argon are used as the gases introduced into the microwave processing device, and microwave processing is performed at an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% or more and 30% or less.

[0150] Furthermore, in the manufacturing process of transistor 200, the heat treatment is preferably performed with the surface of oxide 230 exposed. For example, the heat treatment is preferably performed at 100°C or higher and 450°C or lower, more preferably at 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This reduces oxygen vacancies by supplying oxygen to oxide 230. Alternatively, the heat treatment can also be performed under reduced pressure. Or, the heat treatment can be performed in an atmosphere of nitrogen or an inert gas followed by an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to replenish the released oxygen. Or, the heat treatment can be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas, followed by continuous heat treatment in an atmosphere of nitrogen or an inert gas.

[0151] By subjecting oxide 230 to oxidation treatment, the supplied oxygen can fill the oxygen vacancies in oxide 230, in other words, it can promote the "V" oxidation process. O The reaction "+O→null" can be avoided. Furthermore, when the supplied oxygen reacts with the hydrogen remaining in oxide 230, the hydrogen can be removed as H2O. This prevents the recombination of hydrogen and oxygen vacancies in oxide 230 to form V. O H.

[0152] Furthermore, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material, but may also be a multilayer structure made of different materials.

[0153] Oxide 230 preferably has a layered structure of oxides with different chemical compositions. Specifically, the atomic ratio of element M relative to the main metal element in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, the atomic ratio of element M relative to In in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Additionally, the atomic ratio of element M to In in the metal oxide used for oxide 230b is preferably greater than that in the metal oxide used for oxide 230a. Oxide 230c can use a metal oxide that can be used for oxide 230a or oxide 230b.

[0154] When it is necessary to increase the on-state current of transistor 200, In-Zn oxide is preferably used as oxide 230. When In-Zn oxide is used as oxide 230, for example, the following structures can be described: a stacked structure in which oxide 230a uses In-Zn oxide and oxides 230b and oxide 230c use In-M-Zn oxide; or a stacked structure in which oxide 230a uses In-M-Zn oxide and either oxide 230b or oxide 230c uses In-Zn oxide, etc.

[0155] Furthermore, oxides 230b and 230c preferably have crystallinity. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor), which will be described later, is preferred. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, oxygen extraction from oxide 230b at the source or drain electrode can be suppressed. Thus, even with heat treatment, oxygen extraction from oxide 230b can be reduced, and the transistor 200 remains stable at high temperatures (so-called thermal budget) during the manufacturing process.

[0156] Furthermore, CAAC-OS is preferably used as oxide 230c, and the c-axis of the crystals contained in oxide 230c is preferably oriented in a direction substantially perpendicular to the formed surface or top surface of oxide 230c. CAAC-OS has the property of readily allowing oxygen to move in a direction perpendicular to the c-axis. Thus, the oxygen contained in oxide 230c can be efficiently supplied to oxide 230b.

[0157] Preferably, the conduction band bottoms of oxides 230a and 230c are closer to the vacuum level than the conduction band bottom of oxide 230b. In other words, the electron affinity of oxides 230a and 230c is preferably lower than that of oxide 230b. In this case, oxide 230c is preferably a metal oxide that can be used for oxide 230a. At this time, the dominant carrier pathway is oxide 230b.

[0158] Here, at the junction of oxides 230a, 230b, and 230c, the conduction band bottom changes gradually. In other words, the above situation can also be expressed as the conduction band bottom at the junction of oxides 230a, 230b, and 230c changing continuously or continuously joined. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxides 230a and 230b, and at the interface between oxides 230b and 230c.

[0159] Specifically, by including oxides 230a and 230b, and oxides 230b and 230c, in addition to oxygen, a common element as the main component, a mixed layer with low defect state density can be formed. For example, when oxide 230b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide can be used as oxides 230a and 230c.

[0160] Specifically, for oxide 230a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or 1:1:0.5 is acceptable. Furthermore, for oxide 230b, a metal oxide with an In:Ga:Zn ratio of 1:1:1 or 4:2:3 is acceptable. Additionally, for oxide 230c, a metal oxide with an In:Ga:Zn ratio of 1:3:4, 4:2:3, 2:1, or 2:5 is acceptable.

[0161] Note that when metal oxides are formed by sputtering, the above atomic ratio is not limited to the atomic ratio of the metal oxides formed, but can also be the atomic ratio of the sputtering target used in forming the metal oxides.

[0162] By employing the above structure as oxides 230a and 230c, the defect state density at the interface between oxides 230a and 230b, and at the interface between oxides 230b and 230c, can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, thereby enabling the transistor 200 to achieve a large on-state current and high frequency characteristics.

[0163] As conductors 242 (conductors 242a and conductors 242b), nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum are preferably used. In one aspect of the invention, nitrides containing tantalum are particularly preferred. Furthermore, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may also be used, for example. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen.

[0164] Note that when conductor 242 comes into contact with oxide 230b, oxygen from oxide 230b may diffuse into conductor 242, thereby oxidizing conductor 242. When conductor 242 is oxidized, its conductivity may decrease. Note that the situation of oxygen from oxide 230b diffusing into conductor 242 can be described as conductor 242 absorbing oxygen from oxide 230b.

[0165] Furthermore, when oxygen in oxide 230b diffuses into conductors 242a and 242b, layers sometimes form between conductor 242a and oxide 230b, and between conductor 242b and oxide 230b. Since this layer has a higher oxygen content than conductor 242a or conductor 242b, it can be estimated to have insulating properties. In this case, the three-layer structure of conductor 242a or conductor 242b, this layer, and oxide 230b can be viewed as a three-layer structure formed by metal-insulator-semiconductor, or as a MIS (Metal-Insulator-Semiconductor) structure, or a diode junction structure dominated by an MIS structure.

[0166] Note that sometimes hydrogen contained in oxide 230b, etc., diffuses into conductor 242a or conductor 242b. In particular, by using a tantalum-containing nitride as conductor 242a and conductor 242b, sometimes hydrogen contained in oxide 230b, etc., readily diffuses into conductor 242a or conductor 242b, and this diffused hydrogen bonds with the nitrogen contained in conductor 242a or conductor 242b. That is, sometimes hydrogen contained in oxide 230b, etc., is absorbed by conductor 242a or conductor 242b.

[0167] Additionally, sometimes a curved surface exists between the side surface and the top surface of the conductor 242. That is, sometimes the ends of the side surface and the ends of the top surface are curved. For example, at the ends of the conductor 242, the radius of curvature of the curved surface is 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less. By eliminating the corners at the ends, the film coverage in subsequent forming processes can be improved.

[0168] like Figure 1B As shown, insulator 254 is preferably in contact with the top and side surfaces of conductor 242a, conductor 242b, oxide 230a, oxide 230b, and a portion of the top surface of insulator 224. By employing the above structure, insulator 280 is separated from insulator 224, oxide 230a, and oxide 230b by insulator 254.

[0169] Furthermore, insulator 254 preferably has the same function as insulator 222 in suppressing the diffusion of one or both of hydrogen and oxygen. For example, compared to insulator 224 and insulator 280, insulator 254 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen. Thus, the diffusion of hydrogen contained in insulator 280 to oxides 230a and 230b can be suppressed. Furthermore, by surrounding insulator 224, oxide 230, etc., with insulator 222 and insulator 254, the diffusion of impurities such as water and hydrogen from the outside to insulator 224 and oxide 230 can be suppressed. Therefore, transistor 200 can have good electrical characteristics and reliability.

[0170] The insulator 254 is preferably formed by sputtering. By forming the insulator 254 using sputtering in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region where the insulator 224 contacts the insulator 254. Oxygen can then be supplied from this region to the oxide 230 through the insulator 224. Here, by making the insulator 254 have the function of suppressing oxygen diffusion upwards, oxygen diffusion from the oxide 230 to the insulator 280 can be prevented. Furthermore, by making the insulator 222 have the function of suppressing oxygen diffusion downwards, oxygen diffusion from the oxide 230 to the substrate side can be prevented. Thus, oxygen is supplied to the channel formation region in the oxide 230. This reduces oxygen vacancies in the oxide 230 and suppresses the constant-on state of the transistor.

[0171] As the insulator 254, an insulator containing one or both of aluminum and hafnium oxides can be formed, for example. In this case, the insulator 254 is formed using atomic layer deposition (ALD). Because the ALD method has high coverage, it can prevent breakage of the insulator 254 due to unevenness or roughness.

[0172] As the insulator 254, an insulator containing aluminum nitride can be used, for example. Therefore, a film with high insulation and high thermal conductivity can be formed, thereby improving the heat dissipation generated when driving the transistor 200. Alternatively, silicon nitride, silicon oxynitride, etc., can also be used.

[0173] Alternatively, gallium-containing oxides can be used as insulators 254, for example. Gallium-containing oxides are preferred because they sometimes have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Gallium oxide, zinc gallium oxide, indium gallium zinc oxide, etc., can be used as gallium-containing oxides. When indium gallium zinc oxide is used as insulator 254, a large ratio of gallium atoms to indium is preferred. By increasing this atomic ratio, the insulating properties of the oxide can be improved.

[0174] Furthermore, the insulator 254 can have a multilayer structure with two or more layers. When the insulator 254 has a two-layer stacked structure, the methods described above can be used to form the lower and upper layers of the insulator 254. Moreover, the same or different methods can be used to form the lower and upper layers of the insulator 254. For example, the lower layer of the insulator 254 can be formed by sputtering in an oxygen-containing atmosphere, and then the upper layer of the insulator 254 can be formed by ALD (Alternating Layer Deposition). Because ALD is a film-forming method with good coverage, it can prevent breakage due to unevenness in the first layer.

[0175] Furthermore, the aforementioned materials can be used as the lower and upper layers of the insulator 254, and the materials of the lower and upper layers of the insulator 254 can be the same or different. For example, a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride with an insulator that has the function of suppressing impurities such as hydrogen and oxygen permeation can be used. In addition, as an insulator that has the function of suppressing impurities such as hydrogen and oxygen permeation, for example, an insulator containing one or both of aluminum and hafnium oxides can be used.

[0176] Insulator 250 is used as a gate insulator. Insulator 250 is preferably disposed in contact with at least a portion of oxide 230c. Insulator 250 may be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, etc. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0177] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating as insulator 250 in contact with at least a portion of oxide 230c, oxygen can be efficiently supplied to the channel formation region of oxide 230b, thereby reducing oxygen vacancies in the channel formation region of oxide 230b. Therefore, a transistor with improved reliability can be provided while suppressing variations in electrical characteristics to achieve stable electrical characteristics. Furthermore, similar to insulator 224, it is preferable to reduce the concentration of impurities such as water and hydrogen in insulator 250. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0178] Note that in Figures 1A to 1CThe structure of insulator 250 is shown as a single layer, but it can also be a stacked structure of two or more layers. When the structure of insulator 250 is a stacked structure of two layers, it is preferable that the lower layer of insulator 250 is formed using an insulator that releases oxygen upon heating, and the upper layer of insulator 250 is formed using an insulator that has the function of suppressing oxygen diffusion. By adopting this structure, the diffusion of oxygen contained in the lower layer of insulator 250 to conductor 260 can be suppressed. That is, the reduction of the amount of oxygen supplied to oxide 230 can be suppressed. In addition, the oxidation of conductor 260 caused by oxygen contained in the lower layer of insulator 250 can be suppressed. For example, the lower layer of insulator 250 can be provided with a material suitable for the above-described insulator 250, and the upper layer of insulator 250 can be provided with the same material as insulator 222.

[0179] Note that when the lower layer of insulator 250 is formed using silicon oxide or silicon oxynitride, the upper layer of insulator 250 can also be formed using an insulating material with a high relative permittivity (high-k). By employing a stacked structure of the lower and upper layers of insulator 250 as the gate insulator, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential supplied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0180] As the upper layer of insulator 250, specifically, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides suitable for use in oxide 230, may be used. In particular, an insulator containing oxides of one or both of aluminum and hafnium is preferred.

[0181] Alternatively, a metal oxide can be disposed between the insulator 250 and the conductor 260. This metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 caused by oxygen in the insulator 250 can be suppressed.

[0182] Note that the aforementioned metal oxide is preferably used as part of the first gate electrode. For example, a metal oxide suitable for oxide 230 can be used as the aforementioned metal oxide. In this case, by forming the conductor 260a using a sputtering method, the resistance value of the aforementioned metal oxide can be reduced, making it a conductor. The aforementioned conductor can be referred to as an OC (Oxide Conductor) electrode. For example, an oxide semiconductor suitable for oxide 230 can be used as the aforementioned metal oxide by making it have low resistance.

[0183] By providing the upper layer of insulator 250 and / or the aforementioned metal oxide, the on-state current of transistor 200 can be increased without reducing the influence of the electric field from conductor 260. Furthermore, by maintaining the distance between conductor 260 and oxide 230 using the physical thickness of insulator 250 and the aforementioned metal oxide, leakage current between conductor 260 and oxide 230 can be suppressed. Additionally, by providing a stacked structure of insulator 250 and the aforementioned metal oxide, the physical distance between conductor 260 and oxide 230 and the electric field strength applied from conductor 260 to oxide 230 can be easily adjusted.

[0184] The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed in a manner that surrounds the bottom and side surfaces of the conductor 260b. Note that in Figures 1A to 1C The conductor 260 is shown to have a two-layer structure of conductor 260a and conductor 260b, but it may also have a single-layer structure or a stacked structure of three or more layers.

[0185] The conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0186] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. As a conductive material with the function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used, for example.

[0187] Furthermore, since conductor 260 is also used for wiring, it is preferable to use a conductor with high conductivity. For example, conductor 260b can be a conductive material with tungsten, copper, or aluminum as the main components. Alternatively, conductor 260b can also adopt a laminated structure, such as a laminated structure of titanium or titanium nitride with the aforementioned conductive material.

[0188] Furthermore, in transistor 200, conductor 260 is formed in a self-aligned manner by filling the openings formed in insulator 280, etc. By forming conductor 260 in this way, conductor 260 can be reliably positioned in the region between conductor 242a and conductor 242b without alignment.

[0189] In addition, such as Figure 1C As shown, in the channel width direction of transistor 200, with the bottom surface of insulator 222 as a reference, the height of the bottom surface of the region where conductor 260 does not overlap with oxide 230b is preferably lower than the height of the bottom surface of oxide 230b. By using conductor 260 as a gate electrode, which covers the side and top surfaces of the channel formation region of oxide 230b via insulator 250 and the like, the electric field of conductor 260 can be easily applied to the entire channel formation region of oxide 230b. Therefore, the on-state current of transistor 200 can be increased and the frequency characteristics improved. With the bottom surface of insulator 222 as a reference, the difference between the height of the bottom surface of conductor 260 and the height of the bottom surface of oxide 230b in the region where oxide 230a and oxide 230b do not overlap with conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0190] Insulator 280 is disposed on insulator 224, oxide 230a, oxide 230b, conductor 242 and insulator 254. In addition, the top surface of insulator 280 may also be planarized.

[0191] The dielectric constant of the insulator 280, used as the interlayer film, is preferably low. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. Especially, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen that has been released through heating.

[0192] Furthermore, the concentration of impurities such as water and hydrogen in insulator 280 is preferably reduced. Additionally, insulator 280 preferably includes excess oxygen regions with low hydrogen concentration or excess oxygen; for example, the same material as insulator 216 may be used. Furthermore, insulator 280 may also have a structure with stacked materials; for example, it may have a stacked structure of a silicon oxide film formed by sputtering and a silicon oxynitride film stacked thereon and formed by chemical vapor deposition (CVD). Silicon nitride may also be stacked on top of it.

[0193] Insulator 282 or insulator 283 is preferably used as a barrier insulating film to inhibit the diffusion of impurities such as water and hydrogen from above into insulator 280. Furthermore, insulator 282 or insulator 283 is used as a barrier insulating film to inhibit oxygen permeation. Insulators such as alumina, silicon nitride, and silicon oxynitride can be used as insulators 282 and 283, respectively. For example, alumina, which has high oxygen barrier properties, can be used as insulator 282, and silicon nitride, which has high hydrogen barrier properties, can be used as insulator 283.

[0194] Furthermore, it is preferable to provide an insulator 274, which serves as an interlayer film, on the insulator 282. Similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 274 is reduced.

[0195] Conductors 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Alternatively, conductors 240a and 240b may also have a laminated structure.

[0196] Furthermore, when conductors 240a and 240b have a stacked structure, it is preferable to use a conductive material that suppresses the permeation of impurities such as water and hydrogen as the conductor in contact with insulators 281, 274, 283, 282, 280, and 254. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide are preferred. Furthermore, the conductive material that suppresses the permeation of impurities such as water and hydrogen can be used as a single layer or in a stacked manner. By using this conductive material, oxygen added to insulator 280 can be prevented from being absorbed by conductors 240a and 240b. Furthermore, impurities such as water and hydrogen contained in the layer above insulator 281 can be prevented from mixing into oxide 230 through conductors 240a and 240b.

[0197] For example, silicon nitride, aluminum oxide, and silicon oxynitride can be used as insulators 241a and 241b. Because insulators 241a and 241b are disposed in contact with insulator 254, impurities such as water and hydrogen contained in insulator 280 can be suppressed from being introduced into oxide 230 via conductors 240a and 240b. In particular, silicon nitride has high hydrogen barrier properties and is therefore preferred. Furthermore, it can prevent oxygen contained in insulator 280 from being absorbed by conductors 240a and 240b.

[0198] Conductors 246 (conductors 246a and 246b) used for wiring can be configured to contact the top surfaces of conductors 240a and 240b. Conductors 246 are preferably made of conductive materials primarily composed of tungsten, copper, or aluminum. Furthermore, the conductor can have a laminated structure, for example, a laminated structure of titanium or titanium nitride with the aforementioned conductive material. Additionally, the conductor can be embedded in an opening in an insulator.

[0199] <Materials Constituting Semiconductor Devices>

[0200] The following describes the constituent materials that can be used in semiconductor devices.

[0201] <<Substrate>>

[0202] For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates for forming the transistor 200. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples of insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators can also be used. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0203] <<Insulators>>

[0204] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0205] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a relatively low permittivity as the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0206] In addition, examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0207] In addition, examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide or resin with pores.

[0208] Furthermore, by surrounding a transistor using metal oxides with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Insulators that suppress the permeation of impurities such as hydrogen and oxygen can be, for example, single-layer or multi-layered insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, insulators that suppress the permeation of impurities such as hydrogen and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0209] Furthermore, the insulator used as the gate insulator is preferably an insulator having regions containing oxygen that has been removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having regions containing oxygen that has been removed by heating is contacted with oxide 230, oxygen vacancies contained in oxide 230 can be filled.

[0210] <<Conductors>>

[0211] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0212] Alternatively, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0213] Furthermore, when using oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0214] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Or, hydrogen entering from external insulators or the like can sometimes be trapped.

[0215] <<Metal Oxides>>

[0216] As oxide 230, a metal oxide (oxide semiconductor) that is used as a semiconductor is preferably used. Hereinafter, a metal oxide that can be used as oxide 230 according to one aspect of the present invention will be described.

[0217] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. In addition, it preferably also contains aluminum, gallium, yttrium, tin, etc. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0218] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of these elements can sometimes be combined as element M.

[0219] Note that in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0220] [Structure of metal oxides]

[0221] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0222] CAAC-OS exhibits c-axis orientation, with multiple nanocrystals linked along the ab-plane direction, resulting in a distorted crystal structure. Note that distortion refers to the portion of the lattice orientation that changes between regions with consistent lattice arrangement and other regions with consistent lattice arrangement within the region where multiple nanocrystals are linked.

[0223] Although nanocrystals are primarily hexagonal, they are not limited to regular hexagons and can be non-regular hexagonal. Furthermore, pentagonal, heptagonal, and other lattice arrangements sometimes exist in the distortion. Additionally, in CAAC-OS, clear grain boundaries (also known as grain boundaries) are difficult to observe even near the distortion. That is, it can be seen that the lattice arrangement distortion can suppress grain boundary formation. This is because CAAC-OS can contain the distortion due to the low density of oxygen atoms along the ab plane or the change in interatomic bonding distance caused by the substitution of metal elements.

[0224] Furthermore, CAAC-OS tends to have a layered crystal structure (also called a layered structure) consisting of layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M,Zn) layers). Additionally, indium and element M can substitute for each other; when element M in the (M,Zn) layer is replaced by indium, the layer can also be represented as an (In,M,Zn) layer. Similarly, when indium in the In layer is replaced by element M, the layer can also be represented as an (In,M) layer.

[0225] CAAC-OS is a highly crystalline metal oxide. Furthermore, distinct grain boundaries are not readily observed in CAAC-OS, thus reducing the likelihood of decreased electron mobility due to grain boundaries. Additionally, the crystallinity of metal oxides can sometimes decrease due to the introduction of impurities or the formation of defects; therefore, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Consequently, metal oxides containing CAAC-OS exhibit stable physical properties. Therefore, metal oxides containing CAAC-OS possess high heat resistance and high reliability.

[0226] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0227] Furthermore, In-Ga-Zn oxide (hereinafter, IGZO), which is a metal oxide containing indium, gallium, and zinc, may have a stable structure when it is in the form of nanocrystals as described above. In particular, IGZO tends to not readily grow crystals in the atmosphere, so it may be structurally stable when IGZO is in the form of small crystals (e.g., the aforementioned nanocrystals) compared to when IGZO is in the form of large crystals (here, crystals a few mm or a few cm).

[0228] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0229] Oxide semiconductors (metal oxides) have various structures and properties. One embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0230] [Impurities]

[0231] Here, we will explain the effects of various impurities in metal oxides.

[0232] When impurities are introduced into oxide semiconductors, defect state densities or oxygen vacancies are sometimes generated. Therefore, when impurities are introduced into the channel formation region of an oxide semiconductor, the electrical characteristics of transistors using oxide semiconductors can easily change, leading to reduced reliability. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is prone to exhibiting always-on characteristics.

[0233] The electrical characteristics of transistors using metal oxides vary due to impurities and oxygen vacancies in the metal oxide, and they are prone to always-on characteristics (the characteristic that current flows through the transistor even without applying a voltage to the gate electrode). In addition, when the transistor is driven in a state where the metal oxide contains more than an appropriate amount of excess oxygen, the oxidation state of the excess oxygen atoms sometimes changes, causing changes in the electrical characteristics of the transistor, thereby reducing reliability.

[0234] Therefore, metal oxides with low carrier concentrations are preferably used as channel formation regions in transistors. Reducing the carrier concentration of the metal oxide lowers the impurity concentration and thus the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Note that in this specification, the carrier concentration of the metal oxide in the channel formation region is 1 × 10⁻⁶. 16 cm -3 The following conditions are defined as high-purity intrinsic.

[0235] Furthermore, the carrier concentration of the metal oxide in the channel formation region is preferably 1×10⁻⁶. 18 cm -3 Hereinafter, 1×10 is more preferred. 17 cm -3 Hereinafter, 1×10 is further preferred. 16 cm -3 Below, a further preference is given to values ​​less than 1×10.13 cm -3 Especially preferred is less than 1×10 12 cm -3 Note that there is no particular limit to the lower limit of the carrier concentration of the metal oxide in the channel formation region; for example, it can be 1 × 10⁻⁶. -9 cm -3 .

[0236] Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies in metal oxides. Furthermore, when oxygen vacancies are present in the channel formation region of a metal oxide semiconductor, the transistor sometimes exhibits always-on characteristics. Moreover, when hydrogen enters an oxygen vacancy in a metal oxide, it sometimes bonds to the oxygen vacancy to form a Vo. O H. Defects where hydrogen enters oxygen vacancies (V O Hydrogen (H) is used as a donor, sometimes generating electrons as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen atoms bonded to the metal atom, generating electrons as charge carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to have always-on characteristics. However, the hydrogen in metal oxides is prone to change due to stresses such as heat and electric fields, so when metal oxides contain a large amount of hydrogen, the reliability of the transistor may decrease.

[0237] In one aspect of the invention, it is preferable to minimize V in oxide 230. O H makes oxide 230 intrinsically high-purity or substantially high-purity. Thus, in order to obtain a sufficiently reduced V... O For H metal oxides, it is important to remove impurities such as water and hydrogen (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to fill oxygen vacancies (sometimes referred to as peroxidation treatment). By using V... O Metal oxides with sufficiently reduced impurities such as hydrogen (H) can be used in the channel formation region of transistors to give them stable electrical characteristics.

[0238] The defect (V) where hydrogen enters an oxygen vacancy. O H) is used as a donor for the metal oxide. However, it is difficult to quantitatively evaluate this defect. Therefore, in metal oxides, carrier concentration is sometimes used instead of donor concentration for evaluation. Therefore, in this specification, etc., carrier concentration under the assumption of no applied electric field is sometimes used as a parameter for metal oxides, instead of donor concentration. In other words, sometimes "carrier concentration" described in this specification can be replaced with "donor concentration". In addition, "carrier concentration" described in this specification can be replaced with "carrier density".

[0239] Therefore, it is preferable to minimize the amount of hydrogen in metal oxides. Specifically, the hydrogen concentration in metal oxides, as measured by SIMS, should be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 By using metal oxides with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0240] Furthermore, the aforementioned defect state density sometimes includes trap levels. Additionally, the charge trapped by the trap levels in metal oxides takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical characteristics of transistors with channel formation regions in metal oxides with high trap state densities are sometimes unstable.

[0241] Furthermore, when impurities are present in the channel formation region of an oxide semiconductor, the crystallinity of the channel formation region may sometimes decrease. Additionally, the crystallinity of the oxide disposed in contact with the channel formation region may sometimes decrease. Low crystallinity in the channel formation region tends to reduce the stability or reliability of the transistor. Furthermore, low crystallinity of the oxide disposed in contact with the channel formation region may sometimes lead to the formation of interface energy levels, further reducing the stability or reliability of the transistor.

[0242] Therefore, reducing the impurity concentration in and around the channel formation region of an oxide semiconductor is effective in improving the stability or reliability of transistors. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Because the defect state density of metal oxides with reduced impurity concentration is low, the trap energy level sometimes also becomes lower.

[0243] <<Other Semiconductor Materials>>

[0244] The semiconductor materials that can be used for oxide 230 are not limited to the aforementioned metal oxides. Semiconductor materials with a band gap (semiconductor materials that are not zero-bandgap semiconductors) can also be used as oxide 230. For example, it is preferable to use single-element semiconductors such as silicon, compound semiconductors such as gallium arsenide, or layered materials used as semiconductors (also called atomic-layer materials, two-dimensional materials, etc.). In particular, it is preferable to use layered materials used as semiconductors as semiconductor materials.

[0245] In this specification and other references, layered materials are a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure formed by layers of covalent or ionic bonds stacked together by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, i.e., high two-dimensional conductivity. By using a material with high two-dimensional conductivity, which can be used as a semiconductor, in the channel formation region, a transistor with a large on-state current can be provided.

[0246] As layered materials, there are graphene, silicene, and sulfides. Sulfides are compounds containing sulfur. Furthermore, sulfur is a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and protium. Other examples of sulfides include transition metal chalcogenides and Group 13 chalcogenides.

[0247] As oxide 230, transition metal chalcogenides used as semiconductors are preferred, for example. Specifically, examples of transition metal chalcogenides that can be used for oxide 230 include: molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc.

[0248] <Methods for Manufacturing Semiconductor Devices>

[0249] Next, use Figures 4A to 11D illustrate Figures 1A to 1D The invention illustrates a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0250] Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A It's a top view. Also, Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B They correspond to Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A The cross-sectional view of the portion indicated by the dotted line A1-A2 in the diagram is also a cross-sectional view along the channel length of transistor 200. Additionally, Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C and Figure 11C They correspond to Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A The cross-sectional view of the portion indicated by the dotted lines A3-A4 in the diagram is also a cross-sectional view of the channel width direction of transistor 200. Additionally, Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D and Figure 11D They correspond to Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A The cross-sectional view of the area indicated by the dotted lines in A5-A6 format. Note that in... Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A In the top view, some of the constituent elements are omitted for clarity.

[0251] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate. The insulator 212 can be formed using sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD methods.

[0252] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo-CVD. Furthermore, CVD methods can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0253] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a film deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup due to receiving charge from plasma. This accumulated charge can sometimes damage these wiring, electrodes, and components. On the other hand, thermal CVD, which does not use plasma, avoids this plasma damage, thus improving the yield of semiconductor devices. Additionally, since thermal CVD does not generate plasma damage during film deposition, films with fewer defects can be obtained.

[0254] ALD (Alternating Layer Deposition) utilizes the self-regulating nature of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films formed at low temperatures. Furthermore, ALD also includes PEALD (Plasma Enhanced ALD), which utilizes plasma. By using plasma, film deposition can be performed at even lower temperatures, making it sometimes preferred. Note that the precursors used in ALD sometimes contain impurities such as carbon. Therefore, films formed using ALD sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Additionally, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0255] Unlike film formation methods that deposit particles released from a target or similar material, CVD and ALD methods form films based on reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed using ALD exhibit excellent step coverage and thickness uniformity, making ALD suitable for applications requiring coverage of surfaces with high aspect ratio openings. Note that ALD has a relatively slow film formation rate, so it is sometimes preferable to combine it with other film formation methods with faster rates, such as CVD.

[0256] CVD and ALD methods allow for control of the film composition by adjusting the source gas flow rate ratio. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate ratio. Furthermore, for instance, when using CVD and ALD, films with continuously varying compositions can be formed by changing the source gas flow rate ratio while forming the film. When forming a film while changing the source gas flow rate ratio, the time required for stress transfer and adjustment is eliminated, thus reducing the film formation time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0257] In this embodiment, silicon nitride is formed as the insulator 212 using a CVD method. Thus, by using an insulator such as silicon nitride, which does not easily allow copper to pass through, as the insulator 212, even if a metal such as copper, which easily diffuses, is used as the conductor in the layer below the insulator 212 (not shown), the diffusion of that metal through the layer above the insulator 212 can be suppressed. Furthermore, by using an insulator such as silicon nitride, which does not easily allow impurities such as water and hydrogen to pass through, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed.

[0258] Next, an insulator 214 is formed on the insulator 212. The insulator 214 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, aluminum oxide is used as the insulator 214.

[0259] Next, insulator 216 is formed on insulator 214. Insulator 216 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods.

[0260] Next, an opening leading to insulator 214 is formed in insulator 216. The opening may include, for example, a groove or a slit. Furthermore, the area where the opening is formed is sometimes referred to as the opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. As insulator 214, it is preferable to select an insulator that serves as an etch stop film when etching insulator 216 to form a groove. For example, when silicon oxide is used as insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide are preferably used as insulator 214.

[0261] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. The CCP etching apparatus including parallel planar electrodes can also employ a structure in which a high-frequency voltage is applied to one of the parallel planar electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of the same frequency are applied to each of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of different frequencies are applied to each of the parallel planar electrodes can be used. Alternatively, a dry etching apparatus having a high-density plasma source can also be used. For example, as a dry etching apparatus having a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0262] After the opening is formed, a conductive film is formed to become the conductor 205a. This conductive film preferably contains a conductor that inhibits oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of a conductor that inhibits oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. This conductive film can be formed using sputtering, CVD, MBE, PLD, ALD, etc.

[0263] In this embodiment, a multilayer structure is adopted as the conductive film that serves as conductor 205a. First, tantalum nitride is formed by sputtering, and titanium nitride is stacked on top of the tantalum nitride. By using this metal nitride as the lower layer of conductor 205b, even if a metal that easily diffuses, such as copper, is used as the conductive film that serves as conductor 205b as described later, the diffusion of this metal from conductor 205a to the outside can be suppressed.

[0264] Next, a conductive film is formed to become the conductor 205b. This conductive film can be formed using methods such as plating, sputtering, CVD, MBE, PLD, and ALD. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film.

[0265] Next, CMP processing is performed to remove the conductive film that becomes conductor 205a and a portion of the conductive film that becomes conductor 205b, exposing the insulator 216. As a result, conductors 205a and 205b remain only at the opening. Thus, a conductor 205 with a flat top surface can be formed (see reference). Figures 4B to 4D Note that sometimes a portion of insulator 216 is removed due to this CMP process.

[0266] Note that in the above process, the conductor 205 is formed by embedding it into the opening of the insulator 216, but this embodiment is not limited to this. For example, the conductor 205 is formed on the insulator 214, the insulator 216 is formed on the conductor 205, and the insulator 216 is subjected to CMP treatment to remove a portion of the insulator 216, thereby exposing the surface of the conductor 205.

[0267] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. Preferably, the insulator 222 is an oxide containing one or both of aluminum and hafnium. An insulator containing oxides of one or both of aluminum and hafnium provides a barrier against oxygen, hydrogen, and water. When the insulator 222 provides a barrier against hydrogen and water, the diffusion of hydrogen and water contained in the surrounding structure of the transistor 200 through the insulator 222 to the inside of the transistor 200 can be suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0268] Insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD and other methods.

[0269] Next, a heat treatment is preferably performed. The heat treatment is performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas.

[0270] In this embodiment, as a heat treatment, after the insulator 222 is formed, it is treated at 400°C for 1 hour in a nitrogen atmosphere, followed by continuous treatment at 400°C for 1 hour in an oxygen atmosphere. By performing this heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Alternatively, the heat treatment can also be performed after the insulator 224 is formed, or at other times.

[0271] Next, an insulator 224 is formed on the insulator 222. The insulator 224 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, a silicon oxynitride film is formed as the insulator 224 using CVD.

[0272] To create an excess oxygen region in the insulator 224, an oxygen-containing plasma treatment can be performed under reduced pressure. The oxygen-containing plasma treatment preferably employs a device including a power supply for generating high-density plasma using microwaves. Alternatively, a power supply applying RF (Radio Frequency) to one side of the substrate can also be used. High-density oxygen radicals can be generated using high-density plasma, and applying RF to one side of the substrate allows the oxygen radicals generated by the high-density plasma to be efficiently introduced into the insulator 224. Alternatively, an oxygen-containing plasma treatment can be performed after a plasma treatment containing an inert gas using such a device to replenish the detached oxygen. Furthermore, by appropriately selecting the conditions of this plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, heating treatment may not be necessary.

[0273] Here, after forming alumina on insulator 224, for example by sputtering, CMP treatment can be performed on the alumina until the insulator 224 is reached. This CMP treatment can planarize and smooth the surface of insulator 224. By applying the alumina to insulator 224 and performing CMP treatment, the endpoint of the CMP treatment can be easily detected. Furthermore, sometimes the thickness of insulator 224 may become thinner due to polishing of a portion of it through CMP treatment, but this can be corrected by adjusting the thickness during film formation on insulator 224. Planarizing and smoothing the surface of insulator 224 can sometimes prevent a decrease in the coverage of the oxide film to be formed underneath and prevent a decrease in the yield of semiconductor devices. Moreover, forming alumina on insulator 224 using sputtering allows oxygen to be added to insulator 224, which is therefore preferable.

[0274] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see reference). Figures 4B to 4D Preferably, oxide films 230A and 230B are formed continuously without exposure to the atmospheric environment. By forming the oxide films without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to oxide films 230A and 230B, thus keeping the area near the interface between oxide films 230A and 230B clean.

[0275] Oxide film 230A and oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD and other methods.

[0276] For example, when forming oxide films 230A and 230B using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. Furthermore, when forming the aforementioned oxide films using sputtering, the aforementioned In-M-Zn oxide target can be used, for example.

[0277] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas is sometimes supplied to the insulator 224. Therefore, the oxygen content in the sputtering gas can be 70% or more, preferably 80% or more, and more preferably 100%.

[0278] Furthermore, when forming the oxide film 230B using sputtering, an oxygen-excess oxide semiconductor is formed when the oxygen ratio in the sputtering gas is set to be greater than 30% and less than 100%, preferably more than 70% and less than 100%. High reliability can be achieved by using an oxygen-excess oxide semiconductor in the channel formation region of the transistor, but the present invention is not limited thereto. When forming the oxide film 230B using sputtering, an oxygen-deficient oxide semiconductor is formed when the oxygen ratio in the sputtering gas is set to be more than 1% and less than 30%, preferably more than 5% and less than 20%. A transistor using an oxygen-deficient oxide semiconductor in the channel formation region can have a higher field-effect mobility. Additionally, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0279] In this embodiment, an oxide film 230A is formed using an oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic number ratio) via sputtering. Additionally, an oxide film 230B is formed using an oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic number ratio) via sputtering. The formation conditions and atomic number ratios of the oxide films can be appropriately selected based on the desired characteristics of oxides 230a and 230b.

[0280] Insulators 222 and 224, oxide film 230A and oxide film 230B are preferably formed in a manner that does not expose them to the atmosphere. For example, a multi-chamber film-forming apparatus can be used.

[0281] Next, a heat treatment can be performed. The aforementioned heat treatment conditions can be used as the conditions for this heat treatment. By performing this heat treatment, impurities such as water and hydrogen in the oxide films 230A and 230B can be removed. In this embodiment, the treatment is performed at 400°C for 1 hour under a nitrogen atmosphere, followed by a continuous treatment at 400°C for 1 hour under an oxygen atmosphere.

[0282] Next, a conductive film 242A is formed on the oxide film 230B (refer to...). Figures 4B to 4D The conductive film 242A can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Alternatively, a heat treatment can be performed before forming the conductive film 242A. This heat treatment can be performed under reduced pressure, during which the conductive film 242A is continuously formed without exposure to the atmosphere. This treatment removes moisture and hydrogen adhering to the surface of the oxide film 230B, and reduces the moisture and hydrogen concentrations in both oxide films 230A and 230B. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is set to 200°C.

[0283] Next, the oxide film 230A, oxide film 230B, and conductive film 242A are processed into islands using photolithography to form oxide 230a, oxide 230b, and conductive layer 242B (see reference). Figures 5A to 5D This process can be performed using dry etching, wet etching, or other methods. Dry etching is suitable for microfabrication. Furthermore, oxide films 230A, 230B, and conductive films 242A can be formed under different conditions. Additionally, during this process, the thickness of the region in insulator 224 that does not overlap with oxide 230a may sometimes decrease.

[0284] In photolithography, a photoresist is first exposed through a mask. Then, a developer is used to remove or leave the exposed areas, forming a photoresist mask. Next, etching is performed through this photoresist mask to process conductors, semiconductors, insulators, etc., into the desired shape. For example, a photoresist mask can be formed by exposing the photoresist with KrF stimulated excimer laser, ArF stimulated excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion lithography can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Note that a mask is not required when using electron or ion beams. Furthermore, when removing the photoresist mask, dry etching (such as ashing) or wet etching can be performed, or wet etching can be performed after dry etching, or dry etching can be performed after wet etching.

[0285] Alternatively, a hard mask made of an insulator or conductor can be used instead of a photoresist mask. When using a hard mask, an insulating or conductive film, which serves as the hard mask material, can be formed on the conductive film 242A, and a photoresist mask can be formed on it. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the conductive film 242A can be performed either after removing the photoresist mask or without removing it. In the latter case, the photoresist mask may sometimes disappear during etching. Alternatively, the hard mask can be removed by etching after etching the conductive film 242A. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to remove the hard mask.

[0286] Here, oxides 230a and 230b, and conductive layer 242B are formed such that at least a portion overlaps with conductor 205. Furthermore, the side surfaces of oxides 230a, 230b, and conductive layer 242B are preferably substantially perpendicular to the top surface of insulator 222. When the side surfaces of oxides 230a, 230b, and conductive layer 242B are substantially perpendicular to the top surface of insulator 222, a smaller area and higher density can be achieved when multiple transistors 200 are provided. Alternatively, a structure with a lower angle formed between the side surfaces of oxides 230a, 230b, and conductive layer 242B and the top surface of insulator 222 can be used. In this case, the angle formed between the side surfaces of oxides 230a, 230b, and conductive layer 242B and the top surface of insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting this shape, the coverage of insulator 254, etc., is improved in the following processes, and defects such as voids can be reduced.

[0287] Furthermore, a curved surface is provided between the side surface and the top surface of the conductive layer 242B. That is, the ends of the side surface and the top surface are preferably curved. For example, at the ends of the conductive layer 242B, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, more preferably 5 nm or more and 6 nm or less. When the ends do not have corners, the film coverage in subsequent film deposition processes can be improved.

[0288] Next, an insulating film 254A is formed on insulator 224, oxide 230a, oxide 230b and conductive layer 242B (see reference). Figures 6B to 6D ).

[0289] The insulating film 254A can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Preferably, the insulating film 254A has the function of inhibiting oxygen permeation. For example, alumina, silicon nitride, silicon oxide, or gallium oxide can be deposited using sputtering or ALD. Alternatively, alumina can be deposited using sputtering and then deposited on the alumina using ALD.

[0290] Next, an insulating film forming the insulator 280 is formed on the insulating film 254A. This insulating film can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, a silicon oxide film is formed using CVD or sputtering as the insulating film. Note that a heat treatment can also be performed before forming the insulating film. The heat treatment can also be performed under reduced pressure to continuously form the insulating film without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the insulating film 254A can be removed, and the moisture and hydrogen concentrations in the oxides 230a, 230b, and the insulator 224 can be reduced. The heat treatment conditions described above can be used as the heat treatment.

[0291] Furthermore, the aforementioned insulating film can also have a multilayer structure. For example, it can also have a structure in which a silicon oxide film is formed by sputtering and a silicon oxide film is formed on the silicon oxide film by CVD.

[0292] Next, the above insulating film is subjected to CMP treatment to form an insulator 280 with a flat top surface (refer to...). Figures 6B to 6D ).

[0293] Microwave treatment can also be performed here. Microwave treatment is preferably carried out in an oxygen-containing atmosphere and under reduced pressure. By performing microwave treatment, the electric field generated by the microwaves is applied to the insulator 280, oxide 230b, oxide 230a, etc., which can cause the V in oxide 230b and oxide 230a to... O H is divided into oxygen vacancies (V) O The hydrogen (H) and hydrogen molecules are separated at this time. Sometimes, a portion of the separated hydrogen bonds with the oxygen contained in the insulator 280 and is removed as a water molecule. In addition, sometimes a portion of the hydrogen is getted by the conductive layer 242B through the insulating film 254A.

[0294] Alternatively, heat treatment can be performed after microwave treatment while maintaining a reduced pressure. This treatment efficiently removes hydrogen from insulator 280, oxide 230b, and oxide 230a. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0295] Furthermore, by performing microwave treatment to modify the film of insulator 280, the diffusion of hydrogen, water, impurities, etc., can be suppressed. Therefore, by subsequent processes or heat treatment after the formation of insulator 280, the diffusion of hydrogen, water, impurities, etc., through insulator 280 to oxide 230 can be suppressed.

[0296] Next, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B are processed to form an opening reaching the oxide 230b. This opening is preferably formed in a manner that overlaps with the conductor 205. Through the formation of this opening, the insulator 254, conductor 242a, and conductor 242b are formed (see reference). Figures 7A to 7D ).

[0297] At this point, it is preferable to thin the oxide 230b in the region overlapping with the opening. The reduction in film size in this region is equivalent to... Figure 3B The Lc shown. By thinning the oxide 230b in this region, the formation of a low-resistance region near the top surface of the channel formation region can be suppressed, and the formation of parasitic channels can be suppressed. Therefore, deviations in transistor characteristics caused by parasitic channels can be suppressed.

[0298] Furthermore, it is preferable to remove a portion of the side surface of oxide 230b in the area overlapping with the opening. The film reduction in this area is equivalent to... Figure 3B As shown in the diagram, We. Therefore, the formation of a low-resistance region near the side of the channel formation region can be suppressed, and the formation of parasitic channels can be suppressed. Thus, deviations in transistor characteristics caused by parasitic channels can be suppressed.

[0299] Furthermore, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B can be processed under different conditions. For example, a portion of the insulator 280 can be processed by dry etching, a portion of the insulating film 254A can be processed by wet etching, and a portion of the conductive layer 242B can be processed by dry etching.

[0300] Here, it is preferable to remove impurities adhering to the surface of oxides 230a, oxides 230b, etc., or those diffused into the interior. Examples of such impurities include those originating from components such as those contained in the insulator 280, insulating film 254A, and conductive layer 242B; components contained in the components of the device used to form the opening; and components contained in the gas or liquid used for etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0301] To remove the aforementioned impurities, a washing process can also be performed. Washing methods include wet washing using a washing liquid, plasma treatment using plasma, and washing using heat treatment; combinations of these methods are also possible.

[0302] As a wet washing method, aqueous solutions of ammonia, oxalic acid, phosphoric acid, hydrofluoric acid, etc., prepared by diluting them with carbonated water or pure water, or pure water, can be used for washing. Alternatively, ultrasonic washing can be performed using the aforementioned aqueous solutions, pure water, or carbonated water. Furthermore, a combination of the above washing methods can be appropriately combined.

[0303] Next, a heat treatment may be performed. This heat treatment is preferably carried out in an oxygen-containing atmosphere. Alternatively, this heat treatment can be performed under reduced pressure to continuously form an oxide film at 230°C without exposure to the atmosphere (see reference). Figures 8A to 8D By performing the above treatment, moisture and hydrogen adhering to the surface of oxide 230b can be removed, and the moisture and hydrogen concentrations in oxides 230a and 230b can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is set to 200°C.

[0304] The oxide film 230C can be formed using sputtering, CVD, MBE, PLD, ALD, and other methods. The oxide film 230C can be formed using the same formation method as oxide film 230A or oxide film 230B, depending on the desired properties of oxide film 230C. In this embodiment, the oxide film 230C is formed using an oxide target with an In:Ga:Zn ratio of 4:2:4.1 [atomic ratio] via sputtering.

[0305] Note that the oxide film 230C can also be a stack. For example, a film can be formed using an oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic ratio) by sputtering, followed by a continuous formation of a film using an oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic ratio).

[0306] During the formation of oxide film 230C, sometimes a portion of the oxygen contained in the sputtering gas is supplied to oxides 230a and 230b. Alternatively, during the formation of oxide film 230C, sometimes a portion of the oxygen contained in the sputtering gas is supplied to insulator 280. Therefore, the oxygen content in the sputtering gas of oxide film 230C can be 70% or more, preferably 80% or more, and more preferably 100%.

[0307] Next, heat treatment can also be performed. Heat treatment can also be performed under reduced pressure to continuously form an insulating film 250A without exposure to the atmosphere (see reference). Figures 8A to 8D By performing the above treatment, moisture and hydrogen adhering to the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in oxides 230a, 230b, and the oxide film 230C can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0308] The insulating film 250A can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, silicon oxynitride is deposited as the insulating film 250A using CVD. Note that the formation temperature of the insulating film 250A is preferably 350°C or higher and lower than 450°C, and particularly preferably around 400°C. By forming the insulating film 250A at a temperature of 400°C, an insulating film with fewer impurities can be formed.

[0309] When the insulator 250 has a two-layer laminated structure, the insulating film that forms the lower layer of the insulator 250 and the insulating film that forms the upper layer of the insulator 250 are preferably formed continuously in a manner that does not expose them to the atmospheric environment. By forming them in a manner that does not expose them to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the insulating film that forms the lower layer of the insulator 250 and the insulating film that forms the upper layer of the insulator 250, thereby keeping the area near the interface between the insulating film that forms the lower layer of the insulator 250 and the insulating film that forms the upper layer of the insulator 250 clean.

[0310] Here, microwave treatment can also be performed under an oxygen-containing atmosphere and reduced pressure after the formation of the insulating film 250A. Through microwave treatment, an electric field generated by the microwaves is applied to the insulating film 250A, oxide film 230C, oxide 230b, oxide 230a, etc., thereby increasing the Vo in oxide film 230C, oxide 230b, and oxide 230a. O H separated into V O With hydrogen. At this time, a portion of the separated hydrogen is bonded to oxygen and is sometimes removed as H₂O from the insulating film 250A, oxide film 230C, oxide 230b, and oxide 230a. Additionally, a portion of the hydrogen is sometimes doped by the conductors 242 (conductors 242a and 242b). Thus, by performing microwave treatment, the hydrogen concentration in the insulating film 250A, oxide film 230C, oxide 230b, and oxide 230a can be reduced. Furthermore, by reducing the V in oxide 230a, oxide 230b, and oxide film 230C... O H separated into V O V produced after reacting with hydrogen O Supplying oxygen can repair or replenish V O .

[0311] Alternatively, heating treatment can be performed while maintaining a reduced pressure after microwave treatment. This process efficiently removes hydrogen concentration from the insulating film 250A, oxide film 230C, oxide 230b, and oxide 230a. Additionally, some hydrogen may be attracted by the conductors 242 (conductors 242a and 242b). The step of performing heating treatment while maintaining a reduced pressure after microwave treatment can be repeated. Repeated heating treatment further efficiently removes hydrogen concentration from the insulating film 250A, oxide film 230C, oxide 230b, and oxide 230a. The preferred heating temperature is 300°C or higher and 500°C or lower.

[0312] Furthermore, by altering the film quality of the insulating film 250A through microwave treatment, the diffusion of hydrogen, water, impurities, etc., can be suppressed. This prevents hydrogen, water, impurities, etc., from diffusing through the insulator 250 to oxides 230b, oxides 230a, etc., due to subsequent processes such as film formation or heat treatment that result in the conductive film becoming the conductor 260.

[0313] Next, conductive film 260A and conductive film 260B are formed sequentially (refer to...). Figures 9A to 9D Conductive films 260A and 260B can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, conductive film 260A is formed using ALD, and conductive film 260B is formed using CVD.

[0314] Next, the oxide film 230C, insulating film 250A, conductive film 260A, and conductive film 260B are polished using CMP treatment until the insulator 280 is exposed, forming oxide 230c, insulator 250, and conductor 260 (conductor 260a and conductor 260b) (see reference). Figures 10A to 10D Therefore, oxide 230c is disposed in such a way that it covers the inner wall (side wall and bottom surface) of the opening reaching oxide 230b. Additionally, insulator 250 is disposed across oxide 230c in such a way that it covers the inner wall of the opening. Furthermore, conductor 260 is disposed across oxide 230c and insulator 250 in such a way that it fills the opening.

[0315] Next, heat treatment can also be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in insulators 250 and 280.

[0316] Next, an insulator 282 is formed on oxide 230c, insulator 250, conductor 260, and insulator 280 (see reference). Figures 11B to 11DThe insulator 282 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. For example, an alumina film is preferably formed by sputtering as the insulator 282. By forming the insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to the insulator 280 simultaneously with film formation. In this case, it is preferable to form the insulator 282 while heating the substrate. Furthermore, by forming the insulator 282 in contact with the top surface of the conductor 260, the absorption of oxygen contained in the insulator 280 by the conductor 260 can be suppressed during subsequent heat treatment, which is therefore preferable.

[0317] Next, insulator 283 is formed on insulator 282 (see reference). Figures 11B to 11D The insulator 283 can be formed by sputtering, CVD, MBE, PLD, ALD, etc. Silicon nitride or silicon oxynitride is preferably used as the insulator 283.

[0318] Next, a heat treatment can be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. This heat treatment allows the oxygen added during the formation of insulator 282 to diffuse into insulator 280 and be supplied to oxides 230a and 230b via oxide 230c. Note that this heat treatment can be performed not only after the formation of insulator 283, but also after the formation of insulator 282.

[0319] Next, insulator 274 can also be formed on insulator 283. Insulator 274 can be formed by sputtering, CVD, MBE, PLD, ALD, etc.

[0320] Next, insulator 281 can also be formed on insulator 274. Insulator 281 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. For example, silicon nitride film is preferably formed by sputtering as insulator 281.

[0321] Next, openings leading to conductors 242a and 242b are formed in insulators 254, 280, 282, 283, 274, and 281. These openings can be formed using photolithography.

[0322] Next, an insulating film is formed to become insulator 241 (insulator 241a and insulator 241b), and the insulating film is anisotropically etched to form insulator 241. The insulating film can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. Preferably, an insulating film with oxygen-suppressing properties is used. For example, silicon nitride is preferably formed using the PEALD method. Silicon nitride has high hydrogen-barrier properties and is therefore preferred.

[0323] Furthermore, anisotropic etching of the insulating film, which serves as the insulator 241, can be performed using methods such as dry etching. By providing the insulator 241 on the sidewall of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed subsequently can be prevented. In addition, impurities such as water and hydrogen can be prevented from diffusing from the conductors 240a and 240b to the outside.

[0324] Next, conductive films 240a and 240b are formed. This conductive film preferably employs a multilayer structure containing a conductor that inhibits the permeation of impurities such as water and hydrogen. For example, a multilayer of tantalum nitride, titanium nitride, etc., with tungsten, molybdenum, copper, etc., can be used. This conductive film can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0325] Next, a portion of the conductive film that will become conductors 240a and 240b is removed by CMP processing, exposing the insulator 281. As a result, the conductive film remains only in the opening, thereby forming conductors 240a and 240b with flat top surfaces (see reference). Figures 1A to 1D Note that sometimes a portion of insulator 281 is removed due to this CMP process.

[0326] Next, a conductive film is formed to become the conductor 246. This conductive film can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0327] Next, the conductive film that becomes the conductor 246 is processed by photolithography to form conductor 246a, which is in contact with the top surface of conductor 240a, and conductor 246b, which is in contact with the top surface of conductor 240b (see reference). Figures 1A to 1D ).

[0328] Through the above processes, it is possible to manufacture including Figures 1A to 1D The semiconductor device shown is transistor 200. (As shown) Figures 4A to 11D As shown, transistor 200 can be manufactured by using the semiconductor device manufacturing method shown in this embodiment.

[0329] <Examples of variations of semiconductor devices>

[0330] The following uses Figures 12A to 12D as well as Figure 13A and Figure 13B An example of a semiconductor device illustrating one aspect of the present invention.

[0331] [Example 1 of a variation of a semiconductor device]

[0332] Figure 12AThis is a top view of a semiconductor device. Figure 12B It is along Figure 12A A cross-sectional view of the section with the dotted and dashed lines A1-A2 in the diagram. Figure 12C It is along Figure 12A The cross-sectional view of the dashed section in A3-A4. Figure 12D It is along Figure 12A The cross-sectional view of the dashed section in A5-A6 format. Figure 12A In the top view, some constituent elements are omitted for clarity.

[0333] Note that in Figures 12A to 12D In the semiconductor device shown, the same reference numerals are used for components that have the same function as those in the semiconductor device shown in the <Structure Examples of Semiconductor Devices>. Note that the materials constituting the semiconductor device in this section may be the materials described in detail in the <Structure Examples of Semiconductor Devices>.

[0334] Figures 12A to 12D The semiconductor device shown is Figures 1A to 1D The example shown is a modified version of the semiconductor device. Figures 12A to 12D The semiconductor device shown is Figures 1A to 1D The semiconductor device shown differs in the shape of the insulator 283. Furthermore, it includes oxide 243 (oxide 243a and oxide 243b). Figures 12A to 12D The oxide 230c and the insulator 254 are shown to have a two-layer stacked structure.

[0335] exist Figures 12A to 12D In the semiconductor device shown, insulators 214, 216, 222, 224, 254 (insulators 254a and 254b), 280, and 282 are patterned, and insulator 283 covers these insulators. That is, insulator 283 is in contact with the top and side surfaces of insulator 282, the side surface of insulator 280, the side surface of insulator 254, the side surface of insulator 224, the side surface of insulator 222, the side surface of insulator 216, the side surface of insulator 214, and the top surface of insulator 212. Thus, oxide 230, insulators 214, 216, 222, 224, 254, 280, and 282 are separated from the outside by insulators 283 and 212. In other words, transistor 200 is disposed in a region sealed by insulators 283 and 212.

[0336] The ability of insulators 212 and 283 to suppress the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules) or water molecules is preferably high. For example, silicon nitride or silicon oxynitride, which have higher hydrogen barrier properties, are preferably used as insulators 212 and 283.

[0337] The above structure can suppress hydrogen contained outside the sealed area from mixing into the sealed area.

[0338] In addition, Figures 12A to 12D The transistor 200 shown has insulators 212, 214, and 283 as single layers, but the invention is not limited thereto. For example, insulators 212, 214, and 283 may also have a stacked structure of two or more layers.

[0339] also, Figures 12A to 12D The transistor 200 shown includes an oxide 243 (oxide 243a and oxide 243b) between the conductor 242 (conductors 242a and 242b) and the oxide 230, which has the function of inhibiting oxygen permeation. By distributing the oxide 243, which has the function of inhibiting oxygen permeation, between the conductor 242 and the oxide 230b, which are used as source or drain electrodes, the resistance between the conductor 242 and the oxide 230b can be reduced, and this is therefore preferred. By adopting this structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0340] Metal oxides containing element M can also be used as oxide 243. In particular, aluminum, gallium, yttrium, or tin can be used as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Furthermore, gallium oxide can also be used as oxide 243. In addition, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the atomic ratio of element M relative to In in the metal oxide used for oxide 243 is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, the thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. In addition, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, the release of oxygen in oxide 230 can be appropriately suppressed. For example, when oxide 243 has a hexagonal crystal structure, the release of oxygen in oxide 230 can sometimes be suppressed.

[0341] Note that in the cross-section along the channel length of transistor 200, the bottom surface of oxide 230c in the region overlapping with conductor 260 is preferably equal to or lower than the bottom surface of oxide 243 (oxide 243a and oxide 243b). By adopting this shape, impurities near the interface between oxide 230b and oxide 230c can be removed, thereby reducing the low-resistance region formed near the top surface of region 234. For example, in the cross-section along the channel length of transistor 200, with the bottom surface of insulator 224 as a reference, the difference between the height of the bottom surface of oxide 243 and the height of the bottom surface of oxide 230c in the region overlapping with conductor 260 is 0 nm or more and 10 nm or less, preferably 0 nm or more and 5 nm or less, more preferably 0 nm or more and 3 nm or less.

[0342] In addition, Figures 12A to 12D In the transistor 200 shown, oxide 230c has a stacked structure of oxide 230c1 and oxide 230c2.

[0343] Oxide 230c2 preferably includes at least one of the metal elements constituting the metal oxide for oxide 230c1, and more preferably includes all of the aforementioned metal elements. For example, it is preferred that In-Ga-Zn oxide or In-Zn oxide is used as oxide 230c1, and In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide is used as oxide 230c2. This reduces the defect state density at the interface between oxide 230c1 and oxide 230c2.

[0344] Preferably, the conduction band bottoms of oxides 230a and 230c2 are closer to the vacuum level than those of oxides 230b and 230c1. In other words, the electron affinity of oxides 230a and 230c2 is preferably lower than that of oxides 230b and 230c1. In this case, oxide 230c2 is preferably made of a metal oxide that can be used with oxide 230a, and oxide 230c1 is preferably made of a metal oxide that can be used with oxide 230b. At this time, in addition to oxide 230b, oxide 230c1 sometimes also becomes the main path for charge carriers. By using a metal oxide that can be used with oxide 230b with oxide 230c1, the increase in the effective channel length at the top surface of the channel formation region can be suppressed, thereby suppressing the decrease in the on-state current of transistor 200.

[0345] Specifically, as oxide 230c1, metal oxides with an In:Ga:Zn ratio of 4:2:3 or 5:1:6, or In-Zn oxides, can be used. As oxide 230c2, metal oxides with an In:Ga:Zn ratio of 1:3:4, Ga:Zn ratio of 2:1, Ga:Zn ratio of 2:5, or gallium oxide can be used.

[0346] Furthermore, oxide 230c2 is preferably a metal oxide that inhibits the diffusion or permeation of oxygen compared to oxide 230c1. By providing oxide 230c2 between insulator 250 and oxide 230c1, the diffusion of oxygen contained in insulator 280 to insulator 250 can be suppressed. Thus, the oxygen can be efficiently supplied to oxide 230b through oxide 230c1.

[0347] Furthermore, by using a metal oxide 230c2 with a lower atomic ratio of In to the main metal element in the metal oxide 230c1 than the same ratio, In diffusion to the insulator 250 side can be suppressed. Since the insulator 250 is used as the gate insulator, In entering the insulator 250 or similar components leads to poor transistor performance. Therefore, by providing oxide 230c2 between oxide 230c1 and insulator 250, a highly reliable semiconductor device can be provided.

[0348] Note that oxide 230c1 can also be disposed in each transistor 200. In other words, the oxide 230c1 of transistor 200 may not be in contact with the oxide 230c1 of adjacent transistors 200. Alternatively, the oxide 230c1 of transistor 200 and the oxide 230c1 of adjacent transistors 200 may be separated. In other words, oxide 230c1 may not be disposed between transistor 200 and adjacent transistors 200.

[0349] When a semiconductor device having the above-described structure has multiple transistors 200 arranged in the channel width direction, oxide 230c is independently provided in each transistor 200. Therefore, the generation of parasitic transistors between transistors 200 and adjacent transistors 200 can be suppressed, thereby suppressing the aforementioned leakage paths. Thus, a semiconductor device with good electrical characteristics and capable of miniaturization or high integration can be provided.

[0350] For example, when L1 is used to represent the distance between the side ends of oxide 230c1 of transistor 200 that are opposite each other in the channel width direction of transistor 200 and the side ends of oxide 230c1 of transistor 200 adjacent to transistor 200, L1 is set to be greater than 0 nm. Furthermore, when L2 is used to represent the distance between the side ends of oxide 230a of transistor 200 that are opposite each other in the channel width direction of transistor 200 and the side ends of oxide 230a of transistor 200 adjacent to transistor 200, the ratio of L1 to L2 (L1 / L2) is preferably greater than 0 and less than 1, more preferably 0.1 or more and 0.9 or less, and even more preferably 0.2 or more and 0.8 or less. Alternatively, L2 can also be the distance between the side ends of oxide 230b of transistor 200 that are opposite each other and the side ends of oxide 230b of transistor 200 adjacent to transistor 200.

[0351] By reducing the ratio of L1 to L2 (L1 / L2), even if a misalignment occurs between transistor 200 and the region of transistor 200 adjacent to transistor 200 where oxide 230c1 is not provided, the oxide 230c1 of transistor 200 and the oxide 230c1 of the adjacent transistor 200 can be separated.

[0352] Furthermore, by increasing the ratio of L1 to L2 (L1 / L2), even if the spacing between transistor 200 and the transistor 200 adjacent to it is reduced, the minimum processing size width can be ensured, which can further miniaturize or highly integrate the semiconductor device.

[0353] Note that conductor 260, insulator 250, and oxide 230c2 are all shared between adjacent transistors 200. In other words, the conductor 260 of transistor 200 has a region where the conductor 260 of adjacent transistors 200 is continuously disposed. Similarly, the insulator 250 of transistor 200 has a region where the insulator 250 of adjacent transistors 200 is continuously disposed. Furthermore, the oxide 230c2 of transistor 200 has a region where the oxide 230c2 of adjacent transistors 200 is continuously disposed.

[0354] In addition, by adopting the above structure, the oxide 230c2 has a region that contacts the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0355] Similarly, the oxide 230c2 of transistor 200 and the oxide 230c2 of transistor 200 adjacent to transistor 200 can also be separated. In this case, insulator 250 has a region in contact with insulator 224 between transistor 200 and transistor 200 adjacent to transistor 200.

[0356] In addition, Figures 12A to 12D The transistor 200 shown has an insulator 254 with a structure of stacked insulators 254a and 254b. Note that the materials, formation methods, etc. of insulators 254a and 254b can be described in the description of the lower layer and upper layer of insulator 254 as described in <Detailed Structure of Semiconductor Devices>.

[0357] Alternatively, an insulator serving as a barrier layer can be provided between the top surface of the conductor 242 and the insulator 280, instead of providing the insulator 254. By employing this structure, the absorption of excess oxygen contained in the insulator 280 by the conductor 242 can be suppressed. Furthermore, by suppressing the oxidation of the conductor 242, the increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, the transistor 200 can possess excellent electrical characteristics and reliability.

[0358] Therefore, the insulator described above preferably has the function of inhibiting oxygen diffusion. For example, the function of the insulator in inhibiting oxygen diffusion is preferably higher than that of insulator 280.

[0359] As the aforementioned insulator, an insulator comprising one or both of aluminum and hafnium oxides can be formed, for example. In particular, alumina is preferably deposited using the ALD method. By forming using the ALD method, a dense film with few defects such as cracks or pinholes or with a uniform thickness can be formed. Furthermore, as the aforementioned insulator, an insulator comprising aluminum nitride can be used, for example.

[0360] [Example 2 of a variation of a semiconductor device]

[0361] exist Figure 13A and Figure 13B The diagram shows a structure in which multiple transistors (transistors 200_1 to 200_n) are surrounded and sealed by insulators 283 and 212. Note that in... Figure 13A and Figure 13B In this configuration, transistors 200_1 to 200_n are arranged along the channel length direction, but are not limited to this arrangement. Transistors 200_1 to 200_n can also be arranged along the channel width direction, or in a matrix configuration, or in an irregular configuration.

[0362] like Figure 13AAs shown, a portion (hereinafter sometimes referred to as sealing portion 265) is formed on the outside of a plurality of transistors (transistors 200_1 to 200_n) where insulator 283 contacts insulator 212. Sealing portion 265 is formed to surround the plurality of transistors (also referred to as a transistor group). By employing this structure, the plurality of transistors can be surrounded by insulator 283 and insulator 212. That is, the four sides and top of the plurality of transistors can be surrounded by insulator 283 and insulator 281, and the bottom of the plurality of transistors can be surrounded by insulator 212. Thus, a plurality of transistor groups surrounded by sealing portion 265 are disposed on a substrate.

[0363] Here, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is preferably short. For example, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is preferably 1 μm or less, more preferably 500 nm or less. By adopting this structure, the volume of the insulator 280 sealed by the insulator 283, etc., can be reduced, thereby reducing the amount of hydrogen contained in the insulator 280.

[0364] Alternatively, a dicing line (sometimes also called a dividing line, severing line, or cut-off line) can be provided in a manner that overlaps with the sealing portion 265. The substrate is cut along the dicing line to extract a chip containing a group of transistors surrounded by the sealing portion 265.

[0365] In addition, Figure 13A The diagram shows an example of multiple transistors (transistors 200_1 to 200_n) surrounded by a sealing portion 265, but it is not limited to this. Figure 13B As shown, multiple transistors (transistor 200_1 to transistor 200_n) can also be surrounded by multiple sealing portions. Figure 13B In the middle, the multiple transistors are surrounded by a sealing portion 265a and also by an outer sealing portion 265b.

[0366] Thus, by surrounding multiple transistors (transistors 200_1 to 200_n) with multiple sealing portions, the contact area between insulator 283 and insulator 212 is increased, thereby further improving the tightness of the seal between insulator 283 and insulator 212. As a result, the multiple transistors can be sealed more reliably.

[0367] At this time, the cutting line can also be provided in a manner that overlaps with the sealing part 265a or the sealing part 265b, or the cutting line can be provided between the sealing part 265a and the sealing part 265b.

[0368] Note that in Figure 13A and Figure 13BThe diagram shows an insulator 212 having a structure comprising a lower layer and an upper layer of stacked insulator 212. For example, silicon nitride is deposited as the lower layer of insulator 212 using PECVD, and silicon nitride is deposited as the upper layer of insulator 212 using sputtering. Therefore, the formation rate of the lower layer of insulator 212 is faster than that of the upper layer, thus improving productivity. Furthermore, the hydrogen concentration in the upper layer of insulator 212, which is closer to oxide 230 than the lower layer, is lower than that in the lower layer. Thus, by using an insulator such as silicon nitride, which is less permeable to impurities such as water and hydrogen, the diffusion of impurities such as water and hydrogen from the lower layer of insulator 212 (not shown) can be suppressed. Moreover, by using an insulator such as silicon nitride, which is less permeable to copper, even if a metal such as copper, which is easily diffused, is used as the conductor in the lower layer of insulator 212, the diffusion of that metal through insulator 212 to the upper layer can be suppressed.

[0369] Note that the structure is not limited to the one described above; a single-layer structure can also be used, in which one of the lower layer and the upper layer of the insulator 212 is provided. Furthermore, in Figure 13A and Figure 13B The structure with insulator 214 is used in the example, but it is not limited to this and a structure without insulator 214 can also be used.

[0370] According to one aspect of the present invention, a semiconductor device with small deviations in transistor characteristics can be provided. According to one aspect of the present invention, a semiconductor device with high on-state current can be provided. According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. According to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0371] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and examples.

[0372] (Implementation Method 2)

[0373] In this embodiment, refer to Figure 14 and Figure 15 One way to describe a semiconductor device.

[0374] [Storage Device 1]

[0375] Figure 14An example of a semiconductor device (memory device) using a semiconductor device as one aspect of the present invention is shown. In the semiconductor device of one aspect of the present invention, a transistor 200 is disposed above a transistor 300, and a capacitor 100 is disposed above both transistor 300 and transistor 200. Furthermore, the transistor 200 described in the above embodiments can be used as the transistor 200. Therefore, the transistor 200 and the layer including the transistor 200 can be referred to the description of the above embodiments.

[0376] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 200 has a low off-state current, it can retain stored content for a long time when used in a memory device. In other words, since refresh operations are not required or occur at extremely low frequencies, the power consumption of the memory device can be significantly reduced.

[0377] exist Figure 14 In the semiconductor device shown, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Additionally, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100.

[0378] In addition, by Figure 14 The storage devices shown are configured in a matrix shape, which can form a storage cell array.

[0379] <Transistor 300>

[0380] Transistor 300 is disposed on substrate 311 and includes: a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 may be p-channel or n-channel.

[0381] Here, in Figure 14In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulator 315 in between. The conductor 316 can be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Alternatively, an insulator used to form a mask for the convex portion may be provided in contact with the upper surface of the convex portion. Furthermore, although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0382] Notice, Figure 14 The structure of transistor 300 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0383] <Capacitor 100>

[0384] The capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric.

[0385] Alternatively, conductors 112 and 110 may be formed simultaneously on conductor 240. Additionally, conductor 112 serves as a plug or wiring for electrical connection to capacitor 100, transistor 200, or transistor 300.

[0386] exist Figure 14 In this embodiment, conductors 112 and 110 have a single-layer structure, but are not limited to this structure and may also have a stacked structure of two or more layers. For example, a conductor with high density between the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0387] In addition, the insulator 130 may be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride, etc., and may be provided in a stacked or single layer.

[0388] For example, the insulator 130 preferably uses a laminated structure of materials with high dielectric strength, such as silicon oxynitride, and materials with high dielectric constant (high-k). By adopting this structure, the capacitor 100 can include an insulator with high dielectric constant (high-k) to ensure sufficient capacitance, and can include an insulator with high dielectric strength to improve dielectric strength, thereby suppressing electrostatic discharge damage to the capacitor 100.

[0389] Note that insulators that are high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0390] On the other hand, materials with high insulation and high withstand pressure (materials with relatively low dielectric constant) include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0391] <Wiring Layer>

[0392] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductive bodies that function as plugs or wiring, multiple structures are sometimes represented by the same reference numeral. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of a conductive body is sometimes used as wiring, and a portion of a conductive body is sometimes used as a plug.

[0393] For example, in transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductors 328 and 330, which are electrically connected to capacitor 100 or transistor 200, are embedded within insulators 320, 322, 324, and 326. Additionally, conductors 328 and 330 are used as connectors or wiring.

[0394] Furthermore, the insulator used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulator 322, planarization can also be achieved by using a planarization process such as chemical mechanical polishing (CMP).

[0395] A wiring layer can also be provided on the insulator 326 and the conductor 330. For example, in Figure 14 In the structure, insulators 350, 352, and 354 are stacked sequentially. Furthermore, a conductor 356 is formed within insulators 350, 352, and 354. The conductor 356 serves as a plug or wiring.

[0396] Similarly, conductors 218 and conductors constituting transistor 200 (conductor 205) are filled in insulators 210, 212, 214, and 216. Furthermore, conductor 218 serves as a plug or wiring for electrical connection with capacitor 100 or transistor 300. Additionally, insulator 150 is provided on conductor 120 and insulator 130.

[0397] Here, similar to the insulator 241 shown in the above embodiment, the insulator 217 is provided in contact with the side of the conductor 218 used as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that since the conductor 205 can be formed parallel to the conductor 218, the insulator 217 is sometimes formed in contact with the side of the conductor 205.

[0398] Insulator 217 can be made of materials such as silicon nitride, aluminum oxide, or silicon oxynitride. Since insulator 217 is disposed in contact with insulators 210, 212, 214, 216, and 222, impurities such as water and hydrogen contained in insulators 210 and 216 can be prevented from entering oxide 230 through conductor 218. Silicon nitride is particularly preferred due to its high hydrogen barrier properties. Furthermore, oxygen contained in insulators 210 or 216 can be prevented from being absorbed by conductor 218.

[0399] Insulator 217 can be formed in the same way as insulator 241. For example, a silicon nitride film can be formed using the PEALD method, and an opening reaching conductor 356 can be formed using anisotropic etching.

[0400] Insulators that can be used as interlayer films include oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, all of which possess insulating properties.

[0401] For example, by using a material with a low relative permittivity as an insulator for use as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0402] For example, insulators 150, 210, 352, and 354 preferably have a low relative permittivity. For example, the insulator preferably contains silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, porous silicon oxide, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, or porous silicon oxide and resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with resin, a laminated structure with thermal stability and a low relative permittivity can be achieved. Examples of resins include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylics.

[0403] Furthermore, by surrounding the transistor using an oxide semiconductor with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, it is sufficient to use an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, such as insulator 214, insulator 212, and insulator 350.

[0404] As an insulator that suppresses impurities such as hydrogen and oxygen permeation, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in layers. Specifically, as an insulator that suppresses impurities such as hydrogen and oxygen permeation, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as silicon oxynitride and silicon nitride, can be used.

[0405] The preferred conductor for use in wiring and plugs is a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Alternatively, highly conductive semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0406] For example, conductors 328, 330, 356, 218, and 112 can be made of conductive materials such as metallic materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above-mentioned materials, either in a single layer or in layers. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0407] <Wires or connectors with oxide semiconductor layers>

[0408] Note that when an oxide semiconductor is used in a transistor 200, an insulator with an excess oxygen region is sometimes provided near the oxide semiconductor. In this case, it is preferable to provide a barrier insulator between the insulator with the excess oxygen region and the conductor provided in the insulator with the excess oxygen region.

[0409] For example, in Figure 14 Preferably, insulator 241 is disposed between insulator 224 (which has excess oxygen), insulator 280, and conductor 240. By displacing insulator 241 in contact with insulators 222 and 254, insulator 224 and transistor 200 can have a structure sealed by a barrier insulator. Furthermore, insulator 241 preferably contacts a portion of insulator 280. As insulator 241 extends to insulator 274, the diffusion of oxygen and impurities can be further suppressed.

[0410] In other words, by providing insulator 241, the absorption of excess oxygen present in insulators 224 and 280 by conductor 240 can be suppressed. Furthermore, by having insulator 241, the diffusion of hydrogen as an impurity through conductor 240 to transistor 200 can be suppressed.

[0411] Furthermore, as the insulator 241, an insulating material with the function of suppressing the diffusion of impurities such as water, hydrogen, and oxygen is preferably used. For example, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. are preferred. In particular, silicon nitride has high hydrogen barrier properties, so it is preferred. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, etc., can also be used.

[0412] The above is an explanation of the structural examples. By adopting this structure, reliability can be improved while suppressing electrical characteristic variations in semiconductor devices using transistors containing oxide semiconductors. Furthermore, a transistor containing an oxide semiconductor with a large on-state current can be provided. Additionally, a transistor containing an oxide semiconductor with a low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0413] [Storage Device 2]

[0414] Figure 15 An example of a memory device using a semiconductor device as an embodiment of the present invention is shown. Figure 15 The storage device shown includes, in addition to Figure 14 In addition to the semiconductor devices shown, transistors 200, 300, and capacitor 100, transistor 400 is also included.

[0415] Transistor 400 can control the second gate voltage of transistor 200. For example, a structure can be adopted in which the first and second gates of transistor 400 are connected to a source diode, and the source of transistor 400 is connected to the second gate of transistor 200. When the second gate of transistor 200 is maintained at a negative potential in this structure, the voltage between the first gate and source of transistor 400 and the voltage between the second gate and source of transistor 400 become 0V. In transistor 400, since the drain current is very small when the second gate voltage and the first gate voltage are 0V, the negative potential of the second gate of transistor 200 can be maintained for a long time even if no power is supplied to transistors 200 and 400. Therefore, a storage device including transistors 200 and 400 can retain stored content for a long period.

[0416] Therefore, in Figure 15 In this configuration, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100. Wiring 1007 is electrically connected to the source of transistor 400, wiring 1008 is electrically connected to the gate of transistor 400, wiring 1009 is electrically connected to the second gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Wiring 1006, 1007, 1008, and 1009 are also electrically connected.

[0417] In addition, by Figure 15 The storage device shown is Figure 14 The illustrated memory device is also configured in a matrix shape, which can form a memory cell array. Note that one transistor 400 can control the second gate voltage of multiple transistors 200. Therefore, it is preferable that the number of transistors 400 is less than the number of transistors 200.

[0418] <Transistor 400>

[0419] Transistor 400 is formed on the same layer as transistor 200, thereby allowing them to be manufactured simultaneously. Transistor 400 includes: a conductor 460 (conductor 460a and conductor 460b) serving as a first gate; a conductor 405 serving as a second gate; insulators 222, 224, and 450 serving as gate insulating layers; an oxide 430c including a channel forming region; conductors 442a, 431a, and 431b serving as sources; conductors 442b, 432a, and 432b serving as drains; conductors 440 (conductor 440a and conductor 440b) serving as plugs; and an insulator 441 (insulator 441a and insulator 441b) serving as a barrier insulating film for conductor 440.

[0420] Conductor 405 and conductor 205 are formed in the same layer. Oxides 431a and 432a are formed in the same layer as oxide 230a, and oxides 431b and 432b are formed in the same layer as oxide 230b. Conductors 442a and 442b are formed in the same layer as conductor 242. Oxide 430c and oxide 230c are formed in the same layer. Insulator 450 and insulator 250 are formed in the same layer. Conductor 460 and conductor 260 are formed in the same layer. Conductor 440 and conductor 240 are formed in the same layer. Insulator 441 and insulator 241 are formed in the same layer.

[0421] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing an oxide film that has become oxide 230c.

[0422] Similar to oxide 230, the oxide 430c used as the active layer of transistor 400 has fewer oxygen vacancies and impurities such as hydrogen and water. Therefore, the threshold voltage of transistor 400 can be increased, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are both 0V can be made very small.

[0423] <cut line>

[0424] The following describes the dicing lines (also called dividing lines, severing lines, or cut-off lines) used when dividing a large-area substrate into multiple semiconductor devices in the shape of a chip by dividing each semiconductor element. As a dicing method, for example, sometimes, grooves (dicing lines) for dividing semiconductor elements are first formed in the substrate, and then the substrate is cut off at the dicing lines to obtain multiple semiconductor devices that have been divided (segmented).

[0425] Here, for example, such as Figure 15As shown, it is preferable to design the area in contact with insulator 254 and insulator 222 as a cut line. That is, an opening is provided in insulator 224 near the area that forms a cut line with the edges of the memory cells including the plurality of transistors 200 and the transistors 400. Furthermore, insulator 254 is provided in such a way that it covers the sides of insulator 224.

[0426] In other words, insulator 222 and insulator 254 are in contact within the opening provided in insulator 224. For example, insulator 222 and insulator 254 can be formed using the same material and the same method. By using the same material and the same method to form insulator 222 and insulator 254, the tightness can be improved. For example, alumina is preferably used.

[0427] By employing this structure, insulators 222 and 254 can surround insulator 224, transistor 200, and transistor 400. Since insulators 222 and 254 have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips to form the circuit region of the semiconductor element as shown in this embodiment, impurities such as hydrogen and water can be prevented from mixing in from the side direction of the truncated substrate and diffusing into transistor 200 or transistor 400.

[0428] By employing this structure, excess oxygen in insulator 224 can be prevented from diffusing to the outside through insulators 254 and 222. Therefore, excess oxygen in insulator 224 is efficiently supplied to the oxide forming the channel in transistor 200 or transistor 400. This oxygen reduces oxygen vacancies in the oxide forming the channel in transistor 200 or transistor 400. Consequently, the oxide forming the channel in transistor 200 or transistor 400 can become an oxide semiconductor with low defect state density and stable characteristics. In other words, reliability can be improved while suppressing variations in the electrical characteristics of transistor 200 or transistor 400.

[0429] The configurations and methods shown in this embodiment can be appropriately combined with the configurations, structures, and methods shown in other embodiments and examples.

[0430] (Implementation Method 3)

[0431] In this embodiment, refer to Figure 16A and Figure 16B , Figures 17A to 17HThe following describes a storage device (hereinafter sometimes referred to as an OS storage device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor, according to one embodiment of the present invention. An OS storage device is a storage device comprising at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Because the off-state current of an OS transistor is extremely small, an OS storage device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0432] <Example of storage device structure>

[0433] Figure 16A An example of the structure of an OS storage device is shown. Storage device 1400 includes peripheral circuitry 1411 and a storage cell array 1470. Peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0434] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 via the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select the row to be accessed.

[0435] The storage device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). In addition, the storage device 1400 receives external control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0436] The control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals can be input as needed.

[0437] The memory cell array 1470 includes a plurality of memory cells MCs configured in a row and column configuration and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a column, etc. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a row, etc.

[0438] In addition, although Figure 16A An example is shown where the peripheral circuitry 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited thereto. For example, as Figure 16B As shown, the memory cell array 1470 can also be arranged overlapping a portion of the peripheral circuitry 1411. For example, the readout amplifier can also be arranged overlapping the memory cell array 1470.

[0439] Figures 17A to 17H This section describes a structural example of a memory cell that can be applied to the aforementioned memory cell MC.

[0440] [DOSRAM]

[0441] Figures 17A to 17C An example of the circuit structure of a DRAM memory cell is shown. In this specification and other materials, DRAM using a 1OS transistor 1 capacitor type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Figure 17A The memory cell 1471 shown includes a transistor M1 and a capacitor CA. In addition, the transistor M1 includes a gate (sometimes called the top gate) and a back gate.

[0442] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0443] Wiring BIL is used as the bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. During data writing and reading, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0444] Here, Figure 17AThe storage cell 1471 shown corresponds to Figure 14 The storage device shown is as follows: That is, transistor M1 corresponds to transistor 200, capacitor CA corresponds to capacitor 100, wiring BIL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, and wiring CAL corresponds to wiring 1005. Note that... Figure 14 The transistor 300 described corresponds to the one set in Figure 16B The transistors of the peripheral circuit 1411 of the storage device 1400 shown.

[0445] Furthermore, the memory cell MC is not limited to memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt... Figure 17B The transistor M1 in the illustrated memory cell 1472 has a back gate that is not connected to wiring BGL, but to wiring WOL. Alternatively, for example, the memory cell MC could also be as follows: Figure 17C The memory cell shown is a memory cell 1473, which is composed of a single-gate transistor, i.e., a transistor M1 excluding the back gate.

[0446] When the semiconductor device shown in the above embodiment is used in memory cell 1471, transistor 200 can be used as transistor M1, and capacitor 100 can be used as capacitor CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be kept extremely low. In other words, since the written data can be held by transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, the memory cell refresh operation can be eliminated. In addition, since the leakage current is extremely low, multi-valued data or analog data can be stored in memory cells 1471, 1472, and 1473.

[0447] Furthermore, in DOSRAM, when the read amplifier is arranged in a manner overlapping the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cells.

[0448] [NOSRAM]

[0449] Figures 17D to 17G This illustrates an example of a gain-cell type memory cell with two transistors and one capacitor. Figure 17DThe shown memory cell 1474 includes transistor M2, transistor M3, and capacitor CB. Additionally, transistor M2 includes a top gate (sometimes simply referred to as the gate) and a back gate. In this specification and other materials, a memory device that includes a gain-cell type memory cell using an OS transistor for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0450] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; transistor M2's gate is connected to wiring WOL; and transistor M2's back gate is connected to wiring BGL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0451] Wiring WBL is used as the write bit line, wiring RBL is used as the read bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CB. It is preferable to apply a low-level potential to wiring CAL during data writing, holding, and reading. Wiring BGL is used to apply a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0452] Here, Figure 17D The storage cell 1474 shown corresponds to Figure 14 The storage device shown is as follows: transistor M2 corresponds to transistor 200, capacitor CB corresponds to capacitor 100, transistor M3 corresponds to transistor 300, wiring WBL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, wiring CAL corresponds to wiring 1005, wiring RBL corresponds to wiring 1002, and wiring SL corresponds to wiring 1001.

[0453] Furthermore, the memory cell MC is not limited to memory cell 1474, and its circuit structure can be appropriately modified. For example, the memory cell MC can also adopt... Figure 17E The transistor M2 in the illustrated memory cell 1475 has its back gate connected to the wiring BGL, but not to the wiring WOL. Alternatively, the memory cell MC could also be, for example, as... Figure 17F The memory cell 1476 shown is a memory cell composed of a single-gate transistor, i.e., a transistor M2 excluding the back gate. Furthermore, for example, the memory cell MC may also have... Figure 17GThe storage cell 1477 shown has a structure that combines wiring WBL and wiring RBL into a wiring BIL.

[0454] When the semiconductor device shown in the above embodiment is used in memory cell 1474, transistor 200 can be used as transistor M2, transistor 300 can be used as transistor M3, and capacitor 100 can be used as capacitor CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be kept extremely low. Therefore, since the written data can be held by transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, memory cell refresh operations can be eliminated. Moreover, due to the extremely low leakage current, multi-valued data or analog data can be stored in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0455] Alternatively, transistor M3 can also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of a Si transistor can be n-channel or p-channel. The field-effect mobility of a Si transistor is sometimes higher than that of an OS transistor. Therefore, a Si transistor can also be used as the readout transistor M3. Furthermore, by using a Si transistor in transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the footprint of the memory cell and enabling high integration of the memory device.

[0456] Furthermore, transistor M3 can also be an OS transistor. When OS transistors are used for transistors M2 and M3, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0457] in addition, Figure 17H An example of a gain-cell type memory cell with 3 transistors and 1 capacitor is shown. Figure 17H The illustrated memory cell 1478 includes transistors M4 through M6 and capacitor CC. Capacitor CC can be appropriately configured. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wiring RBL and wiring WBL without being electrically connected to wiring BIL.

[0458] Transistor M4 is an OS transistor that includes a back gate, which is electrically connected to wiring BGL. Alternatively, the back gate and gate of transistor M4 can be electrically connected to each other. Or, transistor M4 may not include a back gate.

[0459] Alternatively, transistors M5 and M6 can each be either n-channel or p-channel Si transistors. Or, transistors M4 through M6 can all be OS transistors. In this case, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0460] When the semiconductor device shown in the above embodiment is used in the memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitor 100 can be used as capacitor CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be made extremely low.

[0461] Note that the structure of the peripheral circuit 1411, the memory cell array 1470, etc. shown in this embodiment is not limited to the structure described above. These circuits and the configuration or function of the wiring, circuit elements, etc., connected to them can be changed, removed, or added as needed.

[0462] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0463] (Implementation Method 4)

[0464] In this embodiment, refer to Figure 18A and Figure 18B An example of a chip 1200 in which the semiconductor device of the present invention is mounted is described. Multiple circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a System on Chip (SoC).

[0465] like Figure 18A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0466] A bump (not shown) is provided on chip 1200, such as... Figure 18B It is connected to the first side of the printed circuit board (PCB) 1201 as shown. In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, which are connected to the motherboard 1203.

[0467] Alternatively, storage devices such as DRAM 1221 and flash memory 1222 can be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to the DRAM 1221. Furthermore, for example, the NOSRAM shown in the above embodiment can be applied to the flash memory 1222.

[0468] CPU 1211 preferably has multiple CPU cores. Furthermore, GPU 1212 preferably has multiple GPU cores. Additionally, CPU 1211 and GPU 1212 may each have a memory for temporary data storage. Alternatively, a memory shared by both CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned NOSRAM or DOSRAM can be used in this memory. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations. By incorporating an image processing circuit or product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and product operations can be performed with low power consumption.

[0469] Furthermore, since the CPU1211 and GPU1212 are located on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation result from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed at high speed.

[0470] The analog arithmetic unit 1213 includes one or both of an analog-to-digital (A / D) conversion circuit and a digital-to-analog (D / A) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog arithmetic unit 1213.

[0471] The storage controller 1214 has circuitry that serves as a controller for the DRAM 1221 and circuitry that serves as an interface for the flash memory 1222.

[0472] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, imaging devices, and controllers. Controllers include mice, keyboards, and game console controllers. As the aforementioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc., can be used.

[0473] Network circuit 1216 includes network circuits such as LAN (Local Area Network). Additionally, it may include network security circuits.

[0474] The aforementioned circuit (system) can be formed on chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, no additional manufacturing process is required, and chip 1200 can be manufactured at low cost.

[0475] The motherboard 1203, which includes a PCB 1201 with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0476] The GPU module 1204 can reduce its size due to the presence of the chip 1200 using SoC technology. Furthermore, the GPU module 1204, with its high image processing capabilities, is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Moreover, by utilizing the product-sum operation circuitry of the GPU 1212, methods such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be executed, thereby allowing the chip 1200 to be used as an AI chip, or the GPU module to be used as an AI system module.

[0477] The structure shown in this embodiment can be appropriately combined with the structures shown in other embodiments, examples, etc.

[0478] (Implementation Method 5)

[0479] In this embodiment, an application example of a storage device using the semiconductor device described in the above embodiments is explained. The semiconductor device described in the above embodiments can be applied, for example, to the storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book reader terminals, digital cameras (including camcorders), video recording devices, navigation systems, etc.). Note that here, "computer" includes tablet computers, notebook computers, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiments can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB storage devices, and SSDs (solid-state drives). Figures 19A to 19E Several structural examples of removable storage devices are illustrated schematically. For example, the semiconductor devices shown in the above embodiments are fabricated into packaged memory chips and used in various storage devices or removable memories.

[0480] Figure 19AThis is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled onto the memory chip 1105, etc.

[0481] Figure 19B This is a schematic diagram of the SD card's appearance. Figure 19C This is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, data can be read from and written to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The semiconductor device described in the above embodiment can be assembled onto the memory chip 1114, etc.

[0482] Figure 19D This is a schematic diagram of the SSD's appearance. Figure 19E This is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled onto the memory chip 1154, etc.

[0483] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0484] (Implementation Method 6)

[0485] The semiconductor device according to one aspect of the present invention can be applied to processors or chips such as CPUs and GPUs. Figures 20A to 20H Specific examples of electronic devices having a processor or chip such as a CPU or GPU according to one aspect of the present invention are shown.

[0486] <Electronic Devices and Systems>

[0487] The GPU or chip according to one aspect of the present invention can be installed in a wide variety of electronic devices. Examples of electronic devices include, in addition to television sets, displays for laptop information terminals, digital signage, and large-screen game consoles such as pinball machines, digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. Furthermore, by incorporating a GPU or chip according to one aspect of the present invention into an electronic device, the electronic device can possess artificial intelligence.

[0488] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0489] An electronic device according to one aspect of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0490] An electronic device according to one aspect of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, animated images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date, or time; executing various software (programs); performing wireless communication; reading programs or data stored in a storage medium; etc. Figures 20A to 20H Examples of electronic devices are shown.

[0491] [Information Terminal]

[0492] Figure 20A A mobile phone (smartphone) is shown as one of the information terminals. The information terminal 5100 includes a housing 5101 and a display unit 5102. The display unit 5102 has a touch panel as an input interface, and buttons are provided on the housing 5101.

[0493] By applying a chip according to one aspect of the present invention to an information terminal 5100, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include applications that identify a session and display the content of that session on a display unit 5102, applications that identify text or graphics input by a user to a touch panel provided with the display unit 5102 and display that text or graphics on the display unit 5102, and applications that perform biometric identification such as fingerprints or voiceprints.

[0494] Figure 20B A notebook-type information terminal 5200 is shown. The notebook-type information terminal 5200 includes an information terminal body 5201, a display unit 5202, and a keyboard 5203.

[0495] Similar to the aforementioned information terminal 5100, by applying a chip according to one aspect of the present invention to the notebook information terminal 5200, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include design support software, document proofreading software, and automatic menu generation software. Furthermore, by using the notebook information terminal 5200, novel artificial intelligence technologies can be developed.

[0496] Note that in the example above, Figure 20A and Figure 20B Examples of smartphones and laptops as electronic devices are shown, but other information terminals besides smartphones and laptops can also be applied. Examples of information terminals other than smartphones and laptops include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0497] [Game console]

[0498] Figure 20C A portable game console 5300 is shown as an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connector 5305, and operation keys 5306. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connector 5305 provided in the housing 5301 to another housing (not shown), the image output to the display unit 5304 can be output to another video display device (not shown). At this time, the housings 5302 and 5303 can each be used as controllers. Thus, multiple players can play games simultaneously. Chips, etc., as shown in the above embodiment, can be embedded in the substrates provided in the housings 5301, 5302, and 5303.

[0499] in addition, Figure 20DThe image shows a stationary game console 5400, one of the game consoles. The stationary game console 5400 is connected to a controller 5402 via wireless or wired connection.

[0500] By applying a GPU or chip according to one aspect of the present invention to game consoles such as the portable game console 5300 and the stationary game console 5400, a low-power game console can be achieved. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuits, and modules.

[0501] Furthermore, by applying a GPU or chip according to one aspect of the present invention to a portable game console 5300, a portable game console 5300 with artificial intelligence can be realized.

[0502] The progress of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are normally governed by the game's programming. However, by applying artificial intelligence to the portable game console 5300, it is possible to achieve performances that are not limited to the game's programming. For example, it is possible to display the content of the player's questions, the progress of the game, the time elapsed, and changes in the behavior of characters appearing in the game.

[0503] Furthermore, when playing games that require multiple players using the portable game console 5300, artificial intelligence can be used to create human-like game players, allowing one person to play a game that can be played by multiple people.

[0504] Although Figure 20C and Figure 20D Portable and stationary game consoles are shown as examples of game consoles, but game consoles using GPUs or chips according to one aspect of the present invention are not limited to these. Examples of game consoles using GPUs or chips according to one aspect of the present invention include arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0505] [Mainframe Computer]

[0506] A GPU or chip based on one aspect of this invention can be applied to large-scale computers.

[0507] Figure 20E The image shows the Supercomputer 5500 as an example of a large computer. Figure 20F The image shows the rack-mount computer 5502 included in the supercomputer 5500.

[0508] The supercomputer 5500 includes a rack 5501 and multiple rack-mounted computers 5502. Note that the multiple computers 5502 are housed in the rack 5501. Additionally, each computer 5502 has multiple substrates 5504 on which the GPU or chip described in the above embodiments can be mounted.

[0509] The Supercomputer 5500 is primarily a large-scale computer suitable for scientific computing. Scientific computing requires massive calculations at high speeds, resulting in high power consumption and significant chip heat generation. By applying a GPU or chip according to one aspect of this invention to the Supercomputer 5500, a low-power supercomputer can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat on the circuitry itself, peripheral circuits, and modules.

[0510] exist Figure 20E and Figure 20F The example shown is a supercomputer, but the supercomputer using a GPU or chip according to one aspect of the present invention is not limited to this. Examples of supercomputers using a GPU or chip according to one aspect of the present invention include service-providing computers (servers), large general-purpose computers (hosts), etc.

[0511] [Moving Object]

[0512] One embodiment of the present invention, the GPU or chip, can be applied to a car as a moving body and the area around the driver's seat of the car.

[0513] Figure 20G This is a diagram showing the perimeter of the windshield inside a car interior, illustrating an example of a moving object. Figure 20G Display panels 5701, 5702, and 5703 are shown mounted on the dashboard, and display panel 5704 is mounted on the support column.

[0514] Display panels 5701 to 5703 can provide various other information by displaying speedometer, tachometer, distance traveled, fuel gauge, gear position, and air conditioning settings. Furthermore, users can customize the display content and layout according to their preferences, enhancing design flexibility. Display panels 5701 to 5703 can also be used as lighting devices.

[0515] By displaying images captured by a camera (not shown) installed in the vehicle on display panel 5704, blind spots (obstructions to the vehicle's view) can be filled. In other words, by displaying images captured by a camera installed on the exterior of the vehicle, blind spots can be filled, thereby improving safety. Furthermore, by displaying images that supplement areas that are not visible, safety can be confirmed more naturally and comfortably. Display panel 5704 can also be used as a lighting device.

[0516] Because the GPU or chip of one aspect of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an autonomous driving system for automobiles. The chip can also be used in systems for navigation, hazard prediction, etc. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0517] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (UAVs), airplanes, rockets), etc., can also be used as mobile bodies to apply the chip of one aspect of the present invention to provide a system utilizing artificial intelligence.

[0518] [Electrical Products]

[0519] Figure 20H An example of an electrical appliance is shown: an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes an outer casing 5801, a refrigerator door 5802, and a freezer door 5803, etc.

[0520] By applying a chip according to one aspect of the present invention to an electric refrigerator / freezer 5800, an electric refrigerator / freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator / freezer 5800 can have the function of automatically generating a menu based on the food stored in the electric refrigerator / freezer 5800 or the consumption period of the food, and automatically adjusting the temperature of the electric refrigerator / freezer 5800 according to the stored food.

[0521] Electric refrigerators and freezers are one example of electrical appliances, but other electrical appliances that can be cited include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners with heating and cooling), washing machines, dryers, and audio-visual equipment.

[0522] The electronic device described in this embodiment, its functions, examples of artificial intelligence applications, and their effects can be implemented by appropriately combining them with descriptions of other electronic devices.

[0523] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0524] [Example 1]

[0525] In this embodiment, it is manufactured in the same process. Figures 1A to 1D The diagram shows multiple transistors 200 comprising oxide semiconductors, and measures transistor characteristics and evaluates deviations in transistor characteristics.

[0526] In addition, Figures 1A to 1D The semiconductor device shown, including transistor 200, is referred to as sample 1A. Furthermore, the semiconductor device manufactured as a sample includes 161 transistors manufactured in the same process. Additionally, the designed channel length and channel width in sample 1A are both 60 nm.

[0527] The following is a description of sample 1A.

[0528] In sample 1A, oxide 230a is formed by sputtering an In-Ga-Zn oxide film using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide 230b is formed by sputtering an In-Ga-Zn oxide film using an oxide target with an In:Ga:Zn ratio of 4:2:4.1. Furthermore, films used as oxide 230a and oxide 230b are formed by sequential deposition.

[0529] In addition, oxide 230c is formed using the following film stack structure: an In-Ga-Zn oxide film deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio] and an In-Ga-Zn oxide film deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4 [atomic number ratio].

[0530] Conductor 242 is formed using a tantalum nitride film. Insulator 250 is formed using a silicon oxynitride film.

[0531] Conductor 260a is formed using a titanium nitride film. Conductor 260b is formed using a tungsten film. Furthermore, the films used as conductor 260a and conductor 260b are formed by continuous deposition.

[0532] <Characteristics of the transistors included in Sample 1A>

[0533] First, sample 1A was heated at 400°C for 4 hours under a nitrogen atmosphere. Next, the electrical characteristics of the 161 transistors included in sample 1A were measured. Furthermore, as electrical characteristics, the Id-Vg characteristic was measured by setting the drain voltage Vd to 1.2V and varying the gate voltage Vg from -4V to +4V.

[0534] Here, in the Id-Vg transistor characteristics, with drain current Id = 1.0 × 10⁻⁶, -12 The gate voltage Vg at time A is the Shift value (Vsh).

[0535] Figure 21 The diagram shows the normal probability plot of the electrical characteristics of the 161 transistors included in sample 1A. Figure 21 In the diagram, the horizontal axis represents the Shift value (Vsh) [V], and the vertical axis represents the estimated cumulative probability [%].

[0536] Note that methods for calculating the estimated cumulative probability (also known as the cumulative relative frequency) include the median-rank method, the average-rank method, the symmetrical sample cumulative distribution method, and the Kaplan-Meier method; any appropriate method can be chosen. In this embodiment, the median-rank method is used to calculate the estimated cumulative probability.

[0537] according to Figure 21 It can be seen that in sample 1A, the average value of Shift is -0.231V and the standard deviation σ is 0.056V.

[0538] As can be seen from the above, the electrical characteristic deviation of the transistor 200 using the present invention is small.

[0539] At least a portion of the structures, methods, etc. shown in this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0540] [Example 2]

[0541] In this embodiment, the manufacturing process is described. Figures 12A to 12DThe semiconductor device shown was subjected to a reliability evaluation of transistor 200, and the results of stress-time dependence were investigated. The reliability evaluation was performed on four transistors, samples A to D, in a substrate. In the substrate including samples A to D, oxide 243 was formed using a sputtering method with an In:Ga:Zn target ratio of 1:3:4 (atomic number ratio) to form a 2 nm thick oxide layer at a substrate temperature of 200 °C. Furthermore, the substrate was subjected to a heat treatment at 400 °C for 8 hours under a nitrogen atmosphere. The reliability evaluation was performed using a +GBT (Gate Bias Temperature) stress test with a stress temperature set to 150 °C. The set temperature was set to 150 °C, and the drain potential Vd, source potential Vs, and bottom gate potential Vbg were set to 0 V, while the top gate potential Vg was set to +3.63 V. The transistors in samples A to D have a channel length of 60 nm and a channel width of 60 nm (both design values). In addition, in this stress test, the stress time when ΔVsh exceeds ±100mV is defined as the transistor's lifetime. Furthermore, the stress time-based variations of Ion, S value, and μFE are also evaluated.

[0542] Figure 22 The results of the +GBT stress test are shown. Figure 22 In the diagram, the horizontal axis represents stress time (hr), and the vertical axis represents ΔVsh (mV). For example... Figure 22 As shown, the lifetime of sample A was 1230 hours, that of sample B was 1410 hours, that of sample C was 1240 hours, and that of sample D was 1230 hours. All four samples achieved good results with lifetimes exceeding 1200 hours.

[0543] Compared to the +GBT stress test set temperature of 125°C, the degradation rate is estimated to be approximately 24 times higher at the +GBT stress test set temperature of 150°C evaluated in this embodiment. Therefore, the lifespan at a stress temperature of 125°C can be estimated to be over 28,000 hours.

[0544] Figure 23A The stress-time-based variation of Ion is shown for samples A through D. Figure 23B The variation of S values ​​based on stress time is shown for samples A to D. Figure 23C The stress-time-based variation of μFE is shown for samples A through D.

[0545] Note that Ion(A) is the Id value at Vd = +1.2V and Vg = +3.3V. The S value (mV / dec) is the Vg value required for Id to change by one digit in the subthreshold region at Vd = +1.2V. μFE (cm 2 / Vs) is a value calculated based on the formula for the linear region approximated by the gradually varying channel.

[0546] like Figures 23A to 23C As shown, in samples A through D, the stress-time-based variations in Ion, S, and μFE were all small.

[0547] Based on the results described above, it has been confirmed that the transistor 200 of one embodiment of the present invention has high reliability.

[0548] This embodiment can be implemented by appropriately combining with other embodiments and the configurations, structures, methods, etc. shown in other embodiments.

[0549] [Example 3]

[0550] In this embodiment, manufacturing Figures 12A to 12D The semiconductor device shown includes a transistor 200, and the transistor characteristics are measured and the deviation of the transistor characteristics is evaluated.

[0551] Note that the semiconductor device including the manufactured transistor 200 comprises 215 transistors manufactured in the same process. Note that the designed channel length and channel width are both 60 nm.

[0552] <Electrical characteristics of transistors>

[0553] First, the manufactured semiconductor device was heat-treated at 400°C for 8 hours under a nitrogen atmosphere. Then, the electrical characteristics of the 215 transistors included in the semiconductor device were measured. Note that, as electrical characteristics, the Id-Vg characteristic was measured by setting Vd to 0.1V or 1.2V and varying Vg from -4V to +4V.

[0554] Figure 24 A graph showing the Id-Vg characteristics of 215 transistors included in a semiconductor device. Figure 24 In the diagram, the horizontal axis represents Vg (V), and the vertical axis represents Id (A).

[0555] also, Figure 25A The normal probability distribution of Vsh is shown. Figure 25A In the graph, the horizontal axis represents Vsh (V), and the vertical axis represents the estimated cumulative probability (%). Furthermore, Figure 25B The diagram shows the normal probability distribution of Ion. Figure 25B In the graph, the horizontal axis represents Ion (μA), and the vertical axis represents the estimated cumulative probability (%). Furthermore, Figure 25C A graph showing the Vbg dependency of Vsh for 9 transistors is displayed.

[0556] Note that methods for calculating the estimated cumulative probability (also known as the cumulative relative frequency) include the median-rank method, the average-rank method, the symmetric sample cumulative distribution method, and the Kaplan-Meier method; any appropriate method can be chosen. In this embodiment, the median-rank method is used to calculate the estimated cumulative probability.

[0557] exist Figure 24 In the figure, the Id-Vg characteristics of the 215 transistors are shown in an overlapping manner.

[0558] from Figure 25A It can be seen that the standard deviation σ of Vsh for 215 transistors is approximately 64mV.

[0559] from Figure 25B It can be seen that the average Ion of 215 transistors is approximately 7.78 μA, and the standard deviation σ is approximately 6.71 μA.

[0560] Therefore, it can be confirmed that the transistor 200 using one aspect of the present invention has good electrical characteristics and small deviation. Furthermore, it can be confirmed that Vsh can be controlled via Vbg.

[0561] At least a portion of the structures, methods, etc. shown in this embodiment can be implemented in appropriate combinations with other embodiments and other embodiments described in this specification.

[0562] [Example 4]

[0563] In this embodiment, a reliability evaluation is performed on two transistors (element A and element B) in the semiconductor device including transistor 200 used in Embodiment 2.

[0564] <Transistor Reliability>

[0565] Reliability was evaluated using a +GBT stress test. In this embodiment, the +GBT stress test was set to a temperature of 150°C, with Vd = Vs = Vbg = 0V and Vg = +3.63V. Note that Vs is the drain potential and Vbg is the bottom gate potential.

[0566] In the +GBT stress test, Id-Vg testing is performed at regular intervals. The Id-Vg test is conducted by scanning Vg from -3.3V to +3.3V with the transistor's Vd=1.2V, Vs=0V, and Vbg=0V. Note that a semiconductor parameter analyzer manufactured by Dextronix is ​​used in the Id-Vg test. Furthermore, in the +GBT stress test, ΔVsh, representing the change in Vsh from the start of measurement, is used as an indicator of the variation in the transistor's electrical characteristics. Additionally, the variation of the S value based on the operating time is evaluated.

[0567] Figure 26AThe results of the +GBT stress test for components A and B are shown. Figure 26A In the figure, the horizontal axis represents stress time (hr), and the vertical axis represents ΔVsh (mV).

[0568] like Figure 26A As shown, even under the aforementioned stress conditions for 490 hours, the change in drift voltage ΔVsh for components A and B is less than 100mV. Specifically, the ΔVsh for component A after 490 hours is -16mV, and the ΔVsh for component B after 490 hours is -23mV.

[0569] Figure 26B The variation of the S-value in the +GBT stress test is shown for components A and B. Figure 26B In the figure, the horizontal axis represents stress time (hr), and the vertical axis represents the S value (mV / dec).

[0570] like Figure 26B As shown, even under the above-mentioned stress conditions for 490 hours, the variation of the S value of components A and B does not exceed the range of 100mV / dec to 140mV / dec.

[0571] Based on the results described above, it has been confirmed that the transistor 200 using one aspect of the present invention has high reliability.

[0572] At least a portion of the structures, methods, etc. shown in this embodiment can be implemented in appropriate combinations with other embodiments and other embodiments described in this specification.

[0573] [Symbol Explanation]

[0574] 100: Capacitor, 110: Conductor, 112: Conductor, 120: Conductor, 130: Insulator, 150: Insulator, 200: Transistor, 200_1: Transistor, 200_2: Transistor, 200_n: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 217: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230c1: Oxide, 230c2: Oxide 230C: Oxide film; 231: Region; 231a: Region; 231b: Region; 234: Region; 240: Conductor; 240a: Conductor; 240b: Conductor; 241: Insulator; 241a: Insulator; 241b: Insulator; 242: Conductor; 242a: Conductor; 242A: Conductive film; 242b: Conductor; 242B: Conductive layer; 243: Oxide; 243a: Oxide; 243b: Oxide; 246: Conductor; 246a: Conductor; 246b: Conductor; 250: Insulator; 250A: Insulating film; 254: Insulator; 254a: Insulator; 254A: Insulating film; 254b: Insulator; 260: Conductor; 26 0a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 265: Sealing part, 265a: Sealing part, 265b: Sealing part, 274: Insulator, 280: Insulator, 281: Insulator, 282: Insulator, 283: Insulator, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 400: Transistor 405: Conductor; 430c: Oxide; 431a: Oxide; 431b: Oxide; 432a: Oxide; 432b: Oxide; 440: Conductor; 440a: Conductor; 440b: Conductor; 441: Insulator; 441a: Insulator; 441b: Insulator; 442a: Conductor; 442b: Conductor; 450: Insulator; 460: Conductor; 460a: Conductor; 460b: Conductor; 1001: Wiring; 1002: Wiring; 1003: Wiring; 1004: Wiring; 1005: Wiring; 1006: Wiring; 1007: Wiring; 1008: Wiring; 1009: Wiring; 1010: Wiring; 1100: USB memory.1101: Casing, 1102: Cover, 1103: USB Connector, 1104: Substrate, 1105: Memory Chip, 1106: Controller Chip, 1110: SD Card, 1111: Casing, 1112: Connector, 1113: Substrate, 1114: Memory Chip, 1115: Controller Chip, 1150: SSD, 1151: Casing, 1152: Connector, 1153: Substrate, 1154: Memory Chip, 1155: Memory Chip, 1156: Controller Chip 1200: Chip; 1201: PCB; 1202: Bump; 1203: Motherboard; 1204: GPU module; 1211: CPU; 1212: GPU; 1213: Analog processing unit; 1214: Memory controller; 1215: Interface; 1216: Network circuit; 1221: DRAM; 1222: Flash memory; 1400: Storage device; 1411: Peripheral circuit; 1420: Row circuit; 1430: Column circuit; 1440: Output circuit; 1460: Control logic. 1470: Memory cell array; 1471: Memory cell; 1472: Memory cell; 1473: Memory cell; 1474: Memory cell; 1475: Memory cell; 1476: Memory cell; 1477: Memory cell; 1478: Memory cell; 5100: Information terminal; 5101: Housing; 5102: Display unit; 5200: Notebook information terminal; 5201: Main body; 5202: Display unit; 5203: Keyboard; 5300: Portable game console; 5301: Housing 5302: Outer casing; 5303: Outer casing; 5304: Display unit; 5305: Connecting unit; 5306: Operation keys; 5400: Fixed game console; 5402: Controller; 5500: Supercomputer; 5501: Rack; 5502: Computer; 5504: Circuit board; 5701: Display panel; 5702: Display panel; 5703: Display panel; 5704: Display panel; 5800: Electric refrigerator / freezer; 5801: Outer casing; 5802: Refrigerator door; 5803: Freezer door.

Claims

1. A semiconductor device comprising a plurality of transistors, each of the plurality of transistors comprising: First conductor; First insulator; The first metal oxide on the first insulator; The second and third conductors on the first metal oxide; A second metal oxide on the first metal oxide, the second metal oxide including the region between the second conductor and the third conductor; A second insulator on the second metal oxide; as well as The fourth conductor on the second insulator The first metal oxide and the second metal oxide each contain indium. In the Id-Vg characteristics of the plurality of transistors, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is less than 60mV. Furthermore, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is achieved by reducing the thickness of the first metal oxide in the region overlapping with the fourth conductor by an amount greater than 0 nm and less than 20 nm.

2. A semiconductor device comprising a plurality of transistors, each of the plurality of transistors comprising: First conductor; First insulator; The first metal oxide on the first insulator; The second and third conductors on the first metal oxide; A second metal oxide on the first metal oxide, the second metal oxide including the region between the second conductor and the third conductor; A second insulator on the second metal oxide; as well as The fourth conductor on the second insulator The first metal oxide and the second metal oxide each contain indium. The top surface of the first metal oxide in the region overlapping with the third conductor is lower than the top surface of the first metal oxide in the region overlapping with the second conductor. In the region overlapping with the fourth conductor, the first metal oxide has a curved surface between its side and top surfaces. In the Id-Vg characteristics of the plurality of transistors, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is less than 60mV. Furthermore, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is achieved by reducing the thickness of the first metal oxide in the region overlapping with the fourth conductor by an amount greater than 0 nm and less than 20 nm.

3. A semiconductor device comprising a plurality of transistors, each of the plurality of transistors comprising: First conductor; First insulator; The first metal oxide on the first insulator; The second and third conductors on the first metal oxide; A second metal oxide on the first metal oxide, the second metal oxide including the region between the second conductor and the third conductor; A second insulator on the second metal oxide; as well as The fourth conductor on the second insulator The first metal oxide and the second metal oxide each contain indium. In the Id-Vg characteristics of the plurality of transistors, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is less than 60mV. The standard deviation σ of the drift value Vsh of each of the plurality of transistors is achieved by reducing the thickness of the first metal oxide in the region overlapping with the fourth conductor by an amount greater than 0 nm and less than 20 nm. The channel length of each of the plurality of transistors is greater than 40 nm and less than 80 nm. Furthermore, the channel width of each of the plurality of transistors is greater than 40 nm and less than 80 nm.

4. A semiconductor device comprising a plurality of transistors, each of the plurality of transistors comprising: First conductor; First insulator; The first metal oxide on the first insulator; The second and third conductors on the first metal oxide; A second metal oxide on the first metal oxide, the second metal oxide including the region between the second conductor and the third conductor; A second insulator on the second metal oxide; as well as The fourth conductor on the second insulator The first metal oxide and the second metal oxide each contain indium. The top surface of the first metal oxide in the region overlapping with the third conductor is lower than the top surface of the first metal oxide in the region overlapping with the second conductor. In the region overlapping with the fourth conductor, the first metal oxide has a curved surface between its side and top surfaces. In the Id-Vg characteristics of the plurality of transistors, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is less than 60mV. The standard deviation σ of the drift value Vsh of each of the plurality of transistors is achieved by reducing the thickness of the first metal oxide in the region overlapping with the fourth conductor by an amount greater than 0 nm and less than 20 nm. The channel length of each of the plurality of transistors is greater than 40 nm and less than 80 nm. Furthermore, the channel width of each of the plurality of transistors is greater than 40 nm and less than 80 nm.

5. A semiconductor device comprising a plurality of transistors, each of the plurality of transistors comprising: First conductor; First insulator; The first metal oxide on the first insulator; The second and third conductors on the first metal oxide; A second metal oxide on the first metal oxide, the second metal oxide including the region between the second conductor and the third conductor; A second insulator on the second metal oxide; as well as The fourth conductor on the second insulator Wherein, the first metal oxide and the second metal oxide each contain indium oxide. In the Id-Vg characteristics of the plurality of transistors, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is less than 60mV. Furthermore, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is achieved by reducing the thickness of the first metal oxide in the region overlapping with the fourth conductor by an amount greater than 0 nm and less than 20 nm.

6. A semiconductor device comprising a plurality of transistors, each of the plurality of transistors comprising: First conductor; First insulator; The first metal oxide on the first insulator; The second and third conductors on the first metal oxide; A second metal oxide on the first metal oxide, the second metal oxide including the region between the second conductor and the third conductor; A second insulator on the second metal oxide; as well as The fourth conductor on the second insulator The first metal oxide and the second metal oxide each contain indium. In the Id-Vg characteristics of the plurality of transistors, the standard deviation σ of the drift value Vsh of each of the plurality of transistors is less than 60mV. The standard deviation σ of the drift value Vsh of each of the plurality of transistors is achieved by reducing the thickness of the first metal oxide in the region overlapping with the fourth conductor by an amount greater than 0 nm and less than 20 nm. Furthermore, at least one of the first metal oxide and the second metal oxide contains indium oxide.

Images