Semiconductor structure and method of forming the same

Abstract

The present disclosure describes semiconductor devices having a two-step source or drain contact structure. The two-step source or drain contact structure includes a first portion on a source or drain structure of a transistor and a second portion on the first portion and extending laterally beyond the first portion toward another transistor source or drain structure. Embodiments of the present disclosure provide semiconductor structures and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs is growing. To meet these demands, the semiconductor industry is continuously scaling down the size of semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and FinFETs, gate-all-around field-effect transistors (GAAFETs), complementary field-effect transistors (CFETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other similar transistor structures. This scaling down increases the complexity of semiconductor manufacturing processes and the difficulty of controlling semiconductor device manufacturing processes. Summary of the Invention

[0003] Some embodiments of this disclosure provide a semiconductor structure comprising: a substrate; a gate structure located on the substrate; a first source or drain (S / D) structure of a first transistor located on the substrate and adjacent to the gate structure; and a first source or drain contact structure located on the first source or drain structure, the first source or drain contact structure comprising a first portion and a second portion located on the first source or drain structure, the first portion being located on the first source or drain structure, and the second portion being located on the first portion and extending laterally beyond the first portion.

[0004] Other embodiments of this disclosure provide a semiconductor structure comprising: a substrate; a gate structure located on the substrate; a first source or drain (S / D) structure of a first transistor located on the substrate and adjacent to the gate structure; a first source or drain contact structure located on the first source or drain structure; a first metallization level including a first conductive line and a second conductive line; and a metal wing structure located on a level immediately above the first source or drain contact structure and below the first metallization level.

[0005] Another embodiment of this disclosure provides a method for forming a semiconductor structure, the method comprising: forming a first source / drain (S / D) structure and a second source / drain structure on a substrate; depositing a dielectric layer on the first source / drain structure and the second source / drain structure; forming a gate structure between the first source / drain structure and the second source / drain structure, wherein the gate structure is at least partially located in the dielectric layer; forming a first metal contact structure on the first source / drain structure and in the dielectric layer; and forming a second metal contact structure on the first metal contact structure, wherein the second metal contact structure extends laterally beyond the first metal contact structure toward the second source / drain structure, wherein the second metal contact structure is separated from the second source / drain structure in the vertical direction by a gap. Attached Figure Description

[0006] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 2 A semiconductor structure including a two-step source or drain contact structure is shown according to exemplary embodiments herein.

[0008] Figure 3 A process for forming a semiconductor structure according to exemplary embodiments herein is illustrated.

[0009] Figures 4 to 6 The following is illustrated in accordance with exemplary embodiments of the present invention: Figure 3 Semiconductor structures at each stage of the process.

[0010] Figure 7 Semiconductor structures including source or drain flying wing structures according to exemplary embodiments herein are shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Additionally, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for clarity and simplicity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] It is worth noting that references to "an embodiment," "embodiment," "exemplary embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include specific components, structures, or features, but each embodiment does not necessarily include specific components, structures, or features. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific component, structure, or feature is described in connection with an embodiment, whether explicitly described or not, implementing such a component, structure, or feature in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0014] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, so that the terminology or terminology in this specification will be interpreted by those skilled in the art based on the teachings herein.

[0015] In some embodiments, the terms "about" and "substantially" may refer to a given amount of value that varies within 20% of a value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one of skill in the art based on the teachings herein.

[0016] As the demand for low-power, high-performance, and miniaturized semiconductor devices continues to grow, the size of semiconductor devices is also shrinking proportionally. This continuous scaling down of device size and the need for increased device performance may require improvements to various processes and materials, which can present numerous challenges. For example, the first source or drain (S / D) structure of a first nanostructure transistor can be electrically connected to the second S / D structure of a second nanostructure transistor located on different sides of the gate structure via source or drain (S / D) contact structures, via structures, first-level metal lines (M0), first-level metal vias (V0), and second-level metal lines (M1). However, metal wiring for one source / drain contact (MD) structure in a different row and another source / drain contact (MD) structure may occupy multiple signal tracks, increasing cell height. Additionally, due to overlay offset, the contact structure of a third nanostructure transistor may be closer to the S / D structure of an adjacent fourth nanostructure transistor. A reduction in the distance between the source / drain contact structure and the adjacent S / D structure may lead to time-dependent dielectric breakdown (TDDB) and reduce the reliability of semiconductor devices.

[0017] This document discloses embodiments of metal traces for source / drain contacts (MDs) in different rows of transistors, where metal wiring for one source / drain contact occupies only one metal layer (e.g., a first metal layer (M0)). In some embodiments, the source / drain contact (MD) comprises two parts, referred to herein as a "two-step source or drain contact," wherein a first part of the source or drain (S / D) contact, or "MD1," is located on and electrically coupled to a first source or drain (S / D) structure; and a second part of the S / D contact, or "MD2," is located on the first part and extends from the first part to an adjacent, uncoupled second source or drain structure. The second part of the S / D contact structure is also referred to as an "S / D contact wing" because the second part of the S / D contact structure flies over at least one S / D structure not connected to it. There is a gap between the S / D contact flying wing structure (MD2) and the second S / D structure, thus separating the S / D contact flying wing structure (MD2) from the second S / D structure.

[0018] A second portion of the source or drain contact structure (MD2) is coupled to a via (VD) structure. For example, the via (VD) structure is located on the second portion of the S / D contact structure. In some embodiments, a first end of the second portion of the S / D contact (MD) structure is located on the first portion of the S / D contact (MD1) structure, and the via (VD) structure is located on the second end of the second portion of the S / D contact (MD2) structure. The second end is opposite to the first end. The via (VD) structure is coupled to a conductive line in the first metal layer (MO). Thus, a two-step S / D contact structure is formed in the mid-process (MOL) step, and due to the S / D contact wing structure (MD2), the connection between the S / D structures of different transistor lines can be achieved using only one layer of the back-end (BOL) metallization components.

[0019] Nanostructured transistors can be gate-all-around (GAA) transistors. GAA transistor structures can be patterned using any suitable method. For example, these structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller spacing than patterns achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0020] Figure 1 A portion of a semiconductor device 100, including a two-step source or drain contact structure, is shown according to some embodiments. For example... Figure 1 As shown, a portion of the semiconductor device 100 may include transistors 102A and 102B. In some embodiments, transistors 102A and 102B may include nanostructured transistors. Nanostructured transistors may include FinFETs, gate-all-around field-effect transistors (GAAFETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other similarly structured transistors. For example, nanostructured transistors can provide channels in a stacked nanosheet / nanowire configuration.

[0021] In some embodiments, transistors 102A and 102B can both be n-type field-effect transistors (NFETs) or p-type field-effect transistors (PFETs). In some embodiments, either transistor 102A or 102B can be the same type of transistor (NFET or PFET), or it can be a different type of transistor. In some embodiments, transistors 102A and 102B can be located in a cell. Although Figure 1Two transistors are shown, but semiconductor device 100 can have any number of transistors. Additionally, semiconductor device 100 can be incorporated into the IC through other structural components such as conductive vias, wires, dielectric layers, passivation layers, and interconnects; some of these components are not shown in the figure for simplicity. Unless otherwise stated, the discussion of elements with the same reference numerals as transistors 102A, 102B applies to each other. The same reference numerals generally denote identical, functionally similar, and / or structurally similar elements.

[0022] Semiconductor device 100 having transistors 102A and 102B can be formed on a substrate (not shown for simplicity) and can be isolated by shallow trench isolation (STI) regions. Each of transistors 102A and 102B may include channel regions 106A and 106B (e.g., Figure 4 As shown, for example, fin structures (protrusion structures extending from the substrate), gate structure 108 (including a gate dielectric, gate electrode, and / or gate work function adjustment layer), and S / D structures 110A, 110B, and one or more S / D contact structures (MD) 112A, 112B. Some S / D contact structures 112A, 112B are coupled to metal conductive lines or traces 114 located in a metallization level (e.g., a first metallization level (MO)), such as power lines or signal lines. In some embodiments, S / D contact structures 112A, 112B are coupled to metal conductive lines 114 via interconnect structures 116A, 116B (e.g., via structures, jumper structures, or other interconnect structures). In some embodiments, contact structures 112B and metal conductive lines 114 extend in different directions. In some embodiments, contact structure 112B extends in a direction substantially perpendicular to the extension direction of metal conductive lines 114.

[0023] Some S / D contact structures, such as Figure 1 The 112B shown comprises a two-step structure—a first portion (MD1) 112B-1 located on the corresponding S / D structure 110B and a second portion (MD2) 112B-2 located on the first portion 112B-1. The first portion 112B-1 and the second portion 112B-2 do not completely overlap each other in the vertical z-axis direction (relative to the substrate of transistor 102B) and have different dimensions in one or more lateral directions along the x-axis or y-axis. Figure 1As shown, as an illustrative example, the second portion 112B-2 extends beyond or protrudes from the first portion 112B-1 toward the S / D structure 110A of the other transistor 102A, such that the second portion 112B-2 at least partially overlaps with the conductive line 114. This at least partial overlap with the conductive line 114 allows for easy direct coupling between the second portion 112B-2 of the S / D contact structure 112B and the conductive line 114, or coupling via the interconnect structure 116B.

[0024] In some embodiments, the S / D structure 110B of transistor 102B is offset relative to the conductive line 114, and the S / D structure 110A of transistor 102A overlaps with the conductive line 114. The S / D structure 110A is not coupled to the conductive line 114. The second portion 112B-2 extends beyond the first portion 112B-1 and extends from the first portion 112B-1 to a lateral position that at least partially overlaps with the conductive line 114, and thus also at least partially overlaps with the S / D structure 110A of transistor 102A. It should be noted that the S / D contact structure 112B is coupled to the S / D structure 110B of transistor 102B. Due to the two-step structure of the S / D contact structure 112B, the second portion 112B-2 is located on the first portion 112B-1 such that the second portion 112B-2 is suspended or flies over the S / D structure 110A, and a gap 118 exists between the second portion 112B-2 and the S / D structure 110A. The gap 118 helps to keep the S / D structure 110A isolated and insulated from the S / D contact structure 112B.

[0025] In some embodiments, such as Figure 2 As shown, transistor 102A is arranged in the first line LA of the transistor, and each transistor in the first line LA overlaps with conductive line 114A; transistor 102B is arranged in the second line LB of the transistor, and each transistor overlaps with conductive line 114B. A second portion 112B-2 of the S / D contact structure 112B is coupled to the S / D structure 110B1 in the second line LB of the transistor, and extends in the y-axis direction from the first portion 112B-1 to the point between the S / D structure 110A of transistor 102A and conductive line 114A in the first line LA of the transistor. Another S / D structure 110B2 of transistor 102B is coupled to conductive line 114B via a one-step S / D contact structure 112BB and an interconnect structure 116BB.

[0026] like Figure 2As shown, conductive line 114G is located between conductive lines 114A and 114B. Conductive line 114G is coupled to gate 108 via interconnect structure 116G. A second portion 112B-2 of S / D contact structure 112B spans conductive line 114G to reach the site overlapping with conductive line 114A.

[0027] In some embodiments, the second portion 112B-2 of the MD structure 112B extends alongside an adjacent gate structure 108. For example, in the y-axis direction, the second portion 112B-2 extends between the S / D structure 110B1 of transistor 102B and the S / D structure 110A1 of transistor 102A, both of which are located on the first side of the gate 108 (exemplarily shown as...). Figure 2 (On the right side). For example... Figure 2 As shown, another S / D structure 110A2 of transistor 102A is coupled to conductive line 114A, and an S / D structure 110B1 of transistor 102B is coupled to conductive line 114A via an S / D contact structure 112B, which has a second portion 112B-2 extending from the second transistor line LB to the first transistor line LA. The second portion 112B-2 includes a first end 120B coupled to the first portion 112B-1 and a second end 120A that at least partially overlaps with conductive line 114A. In some embodiments, the second end 120A is coupled to conductive line 114A via interconnect structure 116B. S / D structure 110A2 is coupled to conductive line 114A via interconnect structure 116A. In some embodiments, interconnect structures 116A and 116B are substantially aligned with each other in the x-axis direction.

[0028] like Figure 2 Further shown, in some embodiments, a gate isolation member 115 is located between the first gate structure 108 and the second gate structure 108, and separates the first gate structure 108 and the second gate structure 108. The gate structures 108 are longitudinally aligned with each other in the y-axis direction. The gate isolation member 115 extends along the x-axis direction. The gate isolation member 115 may be a discrete portion located between adjacent gate structures 108 and separating adjacent gate structures 108. The active region 119 extends longitudinally in the x-axis direction. The active region 119 includes a channel 106 and an S / D structure 110. A gate spacer 423 (such as...) Figure 4 (As shown) It extends along the sidewall of the gate structure 108. The gate isolation member 115 intersects with the gate structure 108 and the gate spacer 423.

[0029] In some embodiments, the isolation structure 117 extends along the y-axis. Gate isolation members 115 are located between two active regions 119. The isolation structure 117 is disposed adjacent to the ends of the active regions 119.

[0030] In some embodiments, the gate structure 108 is disposed above the active region 119, or more specifically, above the channel 106 of the active region 119.

[0031] In some embodiments, the gate isolation component 115 is located above the dielectric layer, which is situated between the active regions 119 along the y-axis. Furthermore, the gate isolation components 115 are all disposed in the interlayer dielectric (ILD) along the y-axis direction. Figure 2 Between two parts (not shown in the image).

[0032] Figure 3 An exemplary manufacturing process 300 for forming an exemplary gate-all-around (GAA) transistor is shown, the exemplary GAA transistor having a configuration similar to... Figure 1 and Figure 2 The two-step S / D contact structure shown is the same as the two-step S / D contact structure. Figure 4 An exemplary structure is shown after operation 390 is completed.

[0033] In operation 310, on the substrate (e.g.) Figure 4 Channel layers and sacrificial layers are alternately stacked over the protruding portion (referred to as the "fin structure") of the substrate 104. In some embodiments, the channel layers and sacrificial layers may have nanostructures located on the fin structure.

[0034] The substrate may include a semiconductor material, such as silicon. In some embodiments, the substrate includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, and / or aluminum gallium arsenide; or (iv) a combination thereof. Furthermore, depending on design requirements (e.g., p-type or n-type substrate), the substrate may be doped. In some embodiments, the substrate may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0035] In some embodiments, operation 310 includes forming a short trench isolation (STI) region 406, which provides electrical isolation between adjacent transistors 102A and 102B and / or between adjacent active and passive elements (not shown) integrated with or deposited on the substrate. The STI region 406 may be made of a dielectric material. In some embodiments, the STI region 406 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the STI region 406 may include a multilayer structure.

[0036] In some embodiments, the sacrificial layer includes etch selectivity relative to the channel layer. For example, when the channel layer is silicon, the sacrificial layer is silicon-germanium.

[0037] The channel layer and sacrificial layer can be patterned to form nanostructures on the patterned portions of the substrate 104. Embodiments of the nanostructures disclosed herein can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the nanostructures, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitch than patterns achievable using a single direct photolithography process.

[0038] like Figure 4 and Figure 4A As shown, for transistors 102A and 102B (such as...) Figure 4A As shown), the nanostructure can extend along the x-axis. In some embodiments, the nanostructure 422 and the fin structure 408 can be disposed on the substrate 404. The nanostructure 422 (in...) Figure 4 and Figure 4A The process (in which the sacrificial nanostructure has been removed) may include a group of channel nanostructures 422-1, 422-2, and 422-3, which may be in the form of nanosheets, nanowires, or nanoribbons. Each nanostructure 422 may serve as a channel structure and form part of the channel regions 106A and 106B located below the gate structure 108 of transistors 102A and 102B. In some embodiments, the nanostructures 422 and fin structures 408 may include semiconductor materials similar to or different from the substrate 404. In some embodiments, the nanostructures 422 and fin structures 408 may include silicon. In some embodiments, the nanostructures 422 and fin structures 408 may include silicon germanium. The semiconductor materials of the nanostructures 422 and fin structures 408 may be undoped or may be in-situ doped during their formation process.

[0039] In some embodiments, such as Figure 4A As shown, the channel region 106B includes three channel nanostructures 422 located below the gate structure 108. Although Figure 4A A three-layer nanostructure 422 is shown, but it will be understood that transistors 102A and 102B may each have any number of nanostructures 422. In some embodiments, transistors 102A and 102B may each have two to six layers of nanostructures 422.

[0040] In some embodiments, the nanostructure 422 may have a thickness in the range of about 3 nm to about 8 nm along the Z-axis. In some embodiments, the nanostructure 422 may have a width in the range of about 15 nm to about 80 nm along the Y-axis. In some embodiments, the spacing between adjacent nanostructures 422 along the Z-axis may be in the range of about 5 nm to about 20 nm.

[0041] It is understood that the specific structural configurations and manufacturing operations of transistors 102A and 102B provided herein are for illustrative purposes only and do not limit the scope of this disclosure. The two-step S / D contact structure discussed herein can be formed on any type of transistor device in a MOL process, all of which are included within the scope of this disclosure.

[0042] In operation 320, a pseudo-gate structure is formed over the patterned nanostructure 422 and the fin structure 408 (collectively referred to as the "fin structure" for simplicity). The pseudo-gate stack may include pseudo-dielectric layers located on the sidewalls and top surface of the fin structure.

[0043] In other instances, the pseudo-dielectric layer may include one or more dielectric materials, such as silicon oxide (SiO2). x Such as SiO2) and / or silicon nitride (Si x N y Pseudo-dielectric layers can be deposited using deposition tools employing PVD, ALD, CVD, epitaxial, oxidation, and / or another suitable deposition technique.

[0044] The dummy gate stack may include a dummy electrode layer located above and / or on the dummy dielectric layer. The dummy electrode layer may include polysilicon and / or other suitable materials. The dummy dielectric layer and the dummy electrode layer may be patterned (e.g., etched) to define one or more dummy gate structures. The dummy gate structure is a temporary gate structure formed as a placeholder for the gate structure (e.g., a metal gate structure) of transistors 102A and 102B.

[0045] In operation 330, a gate spacer 423 is formed adjacent to the dummy gate structure. The gate spacer 423 is a dielectric material, such as SiN.

[0046] In operation 340, a source or drain trench 425 is formed in a fin structure located on the side of the dummy gate structure. The source or drain trench can be formed by etching. In some embodiments, both the nanostructure layer 422 and the sacrificial layer are removed from the source or drain trench 425. In some embodiments, only the sacrificial layer is removed from the source or drain trench 425, and the nanostructure layer 422 may remain in the source or drain trench. The nanostructure layer 422 between two source or drain trenches 425 becomes channel regions 106A, 106B, and is also referred to as channel layers 106A, 106B.

[0047] In operation 350, an internal spacer structure 427 is formed. Forming the internal spacer 427 may include recessing the sacrificial nanostructure through a source or drain trench 425, and filling the trench with a dielectric material.

[0048] In operation 360, source or drain (S / D) structures 110A and 110B are formed in source or drain trench 425. In some embodiments, source or drain structures 110A and 110B can be formed by growing a semiconductor epitaxial layer in source or drain trench 425 using an epitaxial process. In some embodiments, source or drain structures 110A and 110B can be formed by doping a nanostructure layer 422 in source or drain trench 425.

[0049] In some embodiments, the S / D structures 110A, 110B can have arbitrary geometries, such as polygons, ellipses, and circles. In some embodiments, the S / D structures 110A, 110B can include epitaxially grown semiconductor materials, such as silicon (e.g., the same material as substrate 104). In some embodiments, the epitaxially grown semiconductor material can include an epitaxially grown semiconductor material different from the material of substrate 404, such as silicon-germanium, and will apply strain to the channel regions 106A, 106B below the gate structure 108. Because the lattice constant of this epitaxially grown semiconductor material is different from that of the substrate 104, strain can be applied to the channel regions 106A, 106B to improve carrier mobility in the channel regions of the semiconductor device 100. The epitaxially grown semiconductor material can include: (i) semiconductor materials, such as germanium and silicon; (ii) compound semiconductor materials, such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys, such as silicon-germanium and gallium arsenide phosphide.

[0050] In some embodiments, S / D structures 110A and 110B may include silicon, and may be in-situ doped with n-type dopants (such as phosphorus and arsenic) during the epitaxial growth process. In some embodiments, S / D structures 110A and 110B may include silicon, silicon germanium, germanium, or group III-V materials (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped with p-type dopants (such as boron, indium, and gallium) during the epitaxial growth process. In some embodiments, S / D structures 110A and 110B may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition. In some embodiments, S / D structures 110A and 110B may have a height in the range of about 9 nm to about 60 nm along the Z-axis.

[0051] In operation 370, a replacement gate structure 108 is formed. In some embodiments, the replacement gate process includes replacing the dummy gate structure with the gate structure 108 (e.g., a metal gate structure) of transistors 102A and 102B.

[0052] For example, in a gate replacement process, an interlayer dielectric (ILD) layer can be deposited around the dummy gate structure. In some embodiments, the ILD layer is deposited to have a thickness of 100-400 nm (e.g., 200 nm) such that the ILD layer covers the dummy gate structure, and a planarization operation (e.g., CMP operation) is performed using a planarization tool to expose the top of the dummy gate structure, such that the top of the ILD layer is at approximately the same level as the top of the dummy gate structure.

[0053] In other instances, the ILD layer may include one or more dielectric materials, such as silicon oxide (SiO2). x Such as SiO2) and / or silicon nitride (Si x N y (e.g., Si3N4). ILD layers can be deposited using deposition tools employing PVD, ALD, CVD, epitaxial, oxidation, and / or another suitable deposition technique.

[0054] In some embodiments, the ILD layer is a silicon nitride layer 430, or an additional silicon nitride layer 430 may be formed in the region adjacent to the dummy gate structure or around the region adjacent to the source or drain contact structure to be formed.

[0055] One or more etching operations can be performed to remove the dummy gate structure to form a gate opening through which portions of the fin structure (including the channel nanostructure layer and the sacrificial nanostructure layer) are exposed.

[0056] The sacrificial nanostructure layer within the gate opening is selectively removed by etching, while the channel layers 106A, 106B and the internal spacer 427 are retained.

[0057] After removing the sacrificial nanostructure layer from the gate opening, a gate structure 108 is formed in the gate opening. In some embodiments, the gate structure 108 surrounds the channel layers 106A, 106B.

[0058] The gate structure 108 may include a conformal stack of one or more of an interface layer, a gate dielectric layer, or a work function metal layer, and other examples may also be included. The gate structure may also include a gate electrode layer located on the conformal stack.

[0059] The interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the interface layer may have a thickness in the range of about 0.1 nm to about 1.5 nm. For example, the interface layer may include an oxide layer formed by a chemical reaction with the surfaces of the channel layers 106A, 106B. For example, a chemical oxidation process may be used to oxidize the exposed portions of the channel layers 106A, 106B in the gate opening, using a combination of ozone (O3) with hydrofluoric acid (HF) and / or hydrochloric acid (HCl).

[0060] Alternatively, the interface layer can be formed by a thermal oxidation process, such as rapid thermal annealing (RTA).

[0061] In some embodiments, the interface layer is formed by deposition, and the interface layer can be deposited using deposition tools, ALD technology, CVD technology, and / or another suitable deposition technology.

[0062] The gate dielectric layer may include a high-k dielectric material having a dielectric constant greater than approximately 3.9. This high-k dielectric material may include hafnium oxide (HfO). x Such as HfO2), aluminum oxide (Al x O y Such as Al2O3), zirconium oxide (ZrO2) x Such as ZrO2), hafnium zirconium oxide (HfZrO) x Hafnium oxide (HfSiO) x lanthanum oxide (La) x O y Such as La2O3), and / or titanium dioxide (TiO2), x For example, TiO2). Additionally and / or optionally, the gate dielectric layer may include one or more low-k dielectric materials, such as silicon oxide (SiO2). x (e.g., SiO2).

[0063] In some embodiments, the gate dielectric layer is formed by deposition, and the gate dielectric layer can be deposited using deposition tools employing ALD, CVD, and / or another suitable deposition technique. In some embodiments, the gate dielectric layer is formed to include a thickness ranging from about 1 nanometer to about 4 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0064] After depositing the gate dielectric layer, annealing can be performed on the gate dielectric layer to repair bulk defects in the gate dielectric layer. Annealing can be performed in an environment containing hydrogen, oxygen and / or nitrogen, or other gas environments.

[0065] The work function metal layer may include one or more metals and / or one or more metal alloys for adjusting the work function of the gate structure 108. In some embodiments, the work function metal layer of the n-type transistor may include an n-type metal that adjusts or modulates the work function of the n-type transistor gate structure 108 to be close to the conduction band of the material of the channel layers 106A, 106B. Examples of such n-type metals include titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), and / or another aluminum-containing metal. In some embodiments, the work function metal layer of the p-type transistor may include one or more p-type metals, such as titanium nitride (TiN), tungsten nitride (WN), and / or another metal having a work function greater than approximately 4.7 eV. Including a p-type metal can adjust the work function of the p-type transistor such that the work function is adjusted to be close to the valence band of the material of the channel layers 106A, 106B.

[0066] In some embodiments, a work function metal layer is formed by deposition, and the work function metal layer can be deposited using deposition tools employing ALD, CVD, and / or another suitable deposition technique. In some embodiments, the work function metal layer is formed to include a thickness in the range of approximately 2 nanometers to approximately 8 nanometers. However, other values ​​and ranges are within the scope of this disclosure.

[0067] The gate electrode layer may include one or more metals, such as tungsten (W), titanium (Ti), and / or copper (Cu). In some embodiments, the gate electrode layer is formed by deposition, and the gate electrode layer may be deposited using ALD technology, CVD technology, and / or another suitable deposition technology using deposition tools. In some embodiments, after depositing the gate electrode layer, a planarization tool is used to planarize the gate structure 108.

[0068] In operation 380, an isolation structure or wire-cut structure 432 is formed. For example, in a metal gate (CMG) dicing process, a patterned hard mask layer is formed. The patterned hard mask layer has an opening defining the wire cut to be formed. For example, the opening is aligned with a designated portion of the gate structure 108 located between two fin structures, which will later be removed from the gate structure 108. In some embodiments, portions of the gate structure 108, the gate spacer 423, and the ILD layer 430 are removed through the opening in the hard mask to form the wire-cut opening. The wire cut opening is filled with a dielectric material to form the wire-cut structure 432.

[0069] In operation 390, a first portion (MD1) of a two-step S / D contact structure or a one-step S / D contact structure (MD1) is formed. In some embodiments, the first portion (MD1) of the two-step S / D contact structure and the one-step S / D contact structure (MD1) are formed at the same layer; for descriptive purposes, the first portion (MD1) of the two-step S / D contact structure and the one-step S / D contact structure (MD1) are also collectively referred to as the MD1 structure. For example, an S / D contact trench 434 is formed in a silicon nitride layer 430 by trench etching. Thus, the specified S / D structures 110A, 110B are exposed within the S / D contact trench. Trench etching may include selective wet etching, selective dry etching, and / or combinations thereof. For example, trench etching includes a plasma dry etching process using fluorine-based chemicals such as CF4, SF6, CH2F2, CHF3, and / or C2F6.

[0070] Subsequently, a conductive layer or S / D contact metal is deposited in the S / D contact trench 434 to form an MD1 structure (including the first part of a two-step S / D contact structure or a one-step S / D contact structure). For example... Figure 4 and Figure 4A As shown, MD1 structures 112B-1 and 112BB are formed on S / D structures 110B1 and 110B2, respectively. The S / D contact metal of the MD1 structure extends within the S / D contact trench 434 to contact the S / D structures 110B1 and 110B2. The S / D contact metal may include copper (Cu), aluminum (Al), tungsten (W), copper-magnesium (CuMg), copper-aluminum (CuAl), or copper-silicon (CuSi), and / or other suitable conductive materials. The S / D contact metal can be formed by PVD, CVD, metal-organic chemical vapor deposition (MOCVD), or plating. In some embodiments, a CMP process is performed to remove excess S / D contact metal.

[0071] In some embodiments, the MD1 structures are located at substantially the same level, for example, they are coplanar with each other. That is, the upper surface of the first portion 112B-1 of the two-step S / D contact structure 112B is substantially coplanar with the upper surface of the one-step S / D contact structure 112BB.

[0072] In some embodiments, the upper surface 112U of the MD1 structure (including the first portion 112B-1 of the two-step S / D contact structure 112B or the one-step S / D contact structure 112BB) is located at substantially the same level as the upper surface 108U of the gate structure 108, or the upper surface 112U of the MD1 structure (including the first portion 112B-1 of the two-step S / D contact structure 112B or the one-step S / D contact structure 112BB) is higher than the upper surface 108U of the gate structure 108.

[0073] In operation 392, a second part (MD2) 112B-2 of the two-step S / D contact structure 112B is formed on the first part (MD1) 112B-1 of the two-step S / D contact structure 112B. See also... Figure 5 For example, an interlayer dielectric (ILD) layer 502 and an etch stop layer 504 are formed on the first portion 112B-1 of the two-step S / D contact structure 112B. The etch stop layer 504 is a different dielectric material from the ILD 502 and can be one or more of aluminum oxide (AlOx, AlON), silicon carbide (SiC), silicon nitride (SiN), hafnium oxide (HfO2), or other suitable dielectric materials (such as boron nitride, silicon boron nitride, silicon boron carbon nitride, or combinations thereof).

[0074] ILD layer 502 may include a dielectric material deposited using a deposition method suitable for flowable dielectric materials. For example, flowable silicon oxide may be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material of ILD layer 502 may include silicon oxide.

[0075] Patterned ILD layer 502 and etch stop layer 504 are used to form flying wing trench 510. See illustrative example. Figure 5 As shown, the flying wing trench 510 exposes the underlying first portion 112B-1, and extends laterally from the first portion 112B-1 across the STI structure 406 to the site overlapping with the S / D structure 110A of transistor 102A. The S / D structure 110A of transistor 102A can be the same type of semiconductor structure (N-type or P-type) as the S / D structure 110B of transistor 102B, or it can be a different type of semiconductor structure.

[0076] In some embodiments, due to over-etching, the flying wing trench 510 extends vertically or is recessed into the silicon nitride layer 430 (see also...). Figure 6 The recessed depth of the flying wing trench 510 can be in the range of 0-10 nm. This prevents the flying wing trench 510 from recessing too deeply into the S / D structure 110A of the transistor 102A, and maintains a gap 518 between the flying wing trench 510 and the S / D structure 110A of the transistor 102A. In some embodiments, the gate spacer 423 helps ensure that the flying wing trench 510 does not extend into the gate structure 108.

[0077] Etching of the flying wing trench 510 may include selective wet etching, selective dry etching, and / or combinations thereof. For example, trench etching includes a plasma dry etching process using fluorine-based chemicals such as CF4, SF6, CH2F2, CHF3, and / or C2F6.

[0078] Subsequently, a conductive layer or S / D contact metal is deposited in the flying wing trench 510 to form the second portion of the two-step S / D contact structure. The S / D contact metal may include copper (Cu), aluminum (Al), tungsten (W), copper-magnesium (CuMg), copper-aluminum (CuAl), or copper-silicon (CuSi), and / or other suitable conductive materials. In some embodiments, the S / D contact metal of the second portion 112B-2 comprises the same conductive material as the S / D contact metal of the first portion 112B-1, which does not limit the scope of this disclosure. The S / D contact metal of the second portion 112B-2 can be formed by PVD, CVD, metal-organic chemical vapor deposition (MOCVD), or plating. In some embodiments, a CMP process is performed to remove excess S / D contact metal.

[0079] In some embodiments, the upper layer 112B-2U of the second portion 112B-2 of the S / D contact structure 112B is located at a level higher than the upper layer 108U of the gate structure 108.

[0080] In this specification, the second portion 112B-2 of the S / D contact structure 112B may also be referred to as the "S / D contact wing". However, as we discuss herein, in some embodiments, the S / D contact wing may not be connected to any S / D structure and may not be part of the S / D contact structure. In some embodiments, the second portion 112B-2 of the S / D contact structure 112B may have a height or thickness 112B-2H along the z-axis above the upper surface 108U of the gate structure 108 (in the range of about 6 nm to about 12 nm). Figure 6 If the height difference is less than 6 nm, the resistance will increase. If the height difference is greater than 12 nm, the parasitic capacitance will increase.

[0081] In some embodiments, because the flying wing trench 510 is recessed into the silicon nitride layer 430, the second portion 112B-2 extends into the silicon nitride layer 430 to a depth D1. Figure 6 The depth D1 is in the range of 0-10 nm. In this case, the second part 112B-2 and the first part 112B-1 intersect each other laterally through the interface 112B-12.

[0082] In some embodiments, the distance D2 between the second portion 112B-2 of the S / D contact structure 112B and the gap 118 between the transistor 102A and the S / D structure 110A is ( Figure 6 The size is equal to or greater than 4.5 nm, which ensures electrical isolation between the second part 112B-2 and the S / D structure 110A.

[0083] The length of the second part, 112B-2L, is in the range of 8–200 nm.

[0084] In some embodiments, the ILD layer 502 may be one or more of SiOCN, high-k compound dielectric materials, or other suitable dielectric materials.

[0085] In some embodiments, a metal silicide layer 429 is disposed between the S / D structure 110 and the S / D contact structure 112. The conductivity of the metal silicide layer 429 is between the conductivity of the S / D structure 110 and the conductivity of the S / D contact structure 112. In some embodiments, the metal silicide layer 429 includes a curved profile.

[0086] In some embodiments, the conductivity of the metal silicide layer 429 is greater than the conductivity of the S / D structure 110. In some embodiments, the conductivity of the S / D contact structure 112 is greater than the conductivity of the metal silicide layer 429.

[0087] In some embodiments, the S / D contact structure 112 is spaced apart from an adjacent dielectric layer (e.g., an ILD layer or STI region 406) by a metal-containing interface layer 431. The interface layer 431 comprises a material composition different from that of the S / D contact structure 112.

[0088] Return to reference Figure 3 In operation 395, an interconnect structure is formed on the S / D contact structures 112B and 112BB. (See reference...) Figure 6An ILD layer 602 is formed on the S / D contact structures 112B and 112BB. Interconnect structures 116BB and 116B are formed in trenches / holes formed in the ILD layer 602 and on the respective S / D contact structures 112BB and 112B. In some embodiments, the upper layers of interconnect structures 116BB and 116B are located at substantially the same layer, for example, they are coplanar with each other. Due to the height difference (e.g., 6-12 nm height difference) between the one-step S / D contact structure 112BB and the two-step S / D contact structure 112B, the corresponding interconnect structures 116BB and 116B have different height / thickness values. For example, the interconnect structure 116BB located on the one-step S / D contact structure 112BB has a height / thickness in the range of 6-18 nm, while the interconnect structure 116B located on the two-step S / D contact structure 112B has a height / thickness in the range of 12-30 nm.

[0089] In some embodiments, operation 392 includes forming a wiring structure at a level above the S / D structure. For example... Figure 7 As shown, the wiring structure 702 is formed in the ILD layer 502 and is immediately above the S / D structure 110. The wiring structure 702 is spaced apart from the S / D structure 110, and there are no S / D contact structures on the S / D structure 110. That is, the wiring structure 702 is not connected to any S / D contact structures and can be left unconnected to any S / D structure. Figure 7 As shown, one or more interconnect structures 704 are formed on the wiring structure 702, which connect the wiring structure to metal components at a higher level (e.g., a first metallization level M0). For example, the wiring structure 702 may extend between two separated conductors 708 on the metallization level and be connected to each conductor 708 via a corresponding interconnect structure 704. In some embodiments, the conductors 708 may all overlap with the S / D structure 110.

[0090] Figure 6 An exemplary embodiment is shown, wherein the S / D contact flying wing structure (MD2) 112B-2 is connected to a first portion (MD1) 112B-1 of the two-step S / D contact structure 112B, flying over the S / D structure (EPI) 110A, and connected to an interconnect structure (VD) 116B. This exemplary embodiment does not limit the scope of this disclosure. Figure 7 As shown, the S / D contact flying wing structure (MD2) can be configured to connect to various numbers of first parts (MD1) of a two-step S / D contact, fly over various numbers of S / D structures (EPI), and connect to various numbers of interconnect structures (VD).

[0091] As described in more detail above, some embodiments described herein provide semiconductor structures. The semiconductor structure includes: a substrate; a gate structure located on the substrate; a first source or drain (S / D) structure of a first transistor located on the substrate and adjacent to the gate structure; and a first S / D contact structure located on the first S / D structure, the first S / D contact structure including a first portion located on the first S / D structure and a second portion located on the first portion and extending laterally beyond the first portion.

[0092] In some embodiments, the semiconductor structure includes: a substrate; a gate structure on the substrate; a first source or drain (S / D) structure of a first transistor on the substrate and adjacent to the gate structure; a first S / D contact structure on the first S / D structure; a first metallization layer including a first conductive line and a second conductive line; and a metal wing structure located immediately above the first S / D contact structure and below the first metallization layer.

[0093] In some embodiments, a method includes: forming a first source / drain (S / D) structure and a second S / D structure on a substrate; depositing a dielectric layer on the first S / D structure and the second S / D structure; forming a gate structure between the first S / D structure and the second S / D structure, wherein the gate structure is at least partially located in the dielectric layer; forming a first metal contact structure on the first S / D structure and in the dielectric layer; and forming a second metal contact structure on the first metal contact structure, wherein the second metal contact structure extends laterally beyond the first metal contact structure toward the second S / D structure, wherein the second metal contact structure is separated from the second S / D structure in the vertical direction by a gap.

[0094] According to one aspect of this application, a semiconductor structure is disclosed, comprising: a substrate; a gate structure located on the substrate; a first source or drain structure of a first transistor located on the substrate and adjacent to the gate structure; and a first source or drain contact structure located on the first source or drain structure, the first source or drain contact structure comprising a first portion and a second portion, the first portion being located on the first source or drain structure, and the second portion being located on the first portion and extending laterally beyond the first portion. In some embodiments, the upper surface of the first portion of the first source or drain contact structure is located at substantially the same layer as or above the upper surface of the gate structure. In some embodiments, the semiconductor structure includes a first conductive line offset from the first source or drain structure, wherein the second portion of the first source or drain contact structure extends to a site at least partially overlapping the first conductive line. In some embodiments, the semiconductor structure includes a second source or drain structure of a second transistor different from the first transistor, wherein the second portion of the first source or drain contact structure extends to a site at least partially overlapping the second source or drain structure. In some embodiments, a second portion of the first source or drain contact structure is separated from the second source or drain structure by a gap. In some embodiments, the distance between the second portion of the first source or drain contact structure and the second source or drain structure is equal to or greater than 4.5 nm. In some embodiments, the semiconductor structure includes: a second source or drain structure of a second transistor different from the first transistor; a second source or drain contact structure located on the second source or drain structure; and a first conductive line, wherein the second portion of the first source or drain contact structure and the second source or drain structure are connected to the first conductive line. In some embodiments, the second source or drain contact structure and the first portion of the first source or drain contact structure are located at substantially the same level. In some embodiments, the second portion of the first source or drain contact structure is connected to the first conductive line through a first interconnect structure, the second source or drain contact structure is connected to the first conductive line through a second interconnect structure, and the second interconnect structure has a height greater than the first interconnect structure. In some embodiments, the first portion and the second portion intersect each other in the lateral direction. In some embodiments, the upper surface of the gate structure and the upper surface of the first portion of the first source or drain contact structure are located at substantially the same level. In some embodiments, the upper surface of a first portion of the first source or drain contact structure is higher than the upper surface of the gate structure. In some embodiments, a second portion of the first source or drain contact structure extends alongside the gate structure.In some embodiments, the semiconductor structure includes: a second conductive line overlapping a first source or drain structure and a second source or drain structure of the first transistor; and a second source or drain contact structure located on the second source or drain structure and connected to the second conductive line, wherein the second source or drain contact structure and a first portion of the first source or drain contact structure are located at substantially the same layer. In some embodiments, a second portion of the first source or drain contact structure is connected to the first conductive line via a first interconnect structure, the second source or drain contact structure is connected to the second conductive line via a second interconnect structure, and the second interconnect structure has a height greater than the first interconnect structure. In some embodiments, the first source or drain structure is located in an active region extending in a first direction, and a gate structure is disposed above the active region and extends in a second direction intersecting the first direction.

[0095] According to another aspect of this application, a semiconductor structure is disclosed, comprising: a substrate; a gate structure located on the substrate; a first source or drain structure of a first transistor located on the substrate and adjacent to the gate structure; a first source or drain contact structure located on the first source or drain structure; a first metallization layer including a first conductive line and a second conductive line; and a metal wing structure located on a layer immediately above the first source or drain contact structure and below the first metallization layer. In some embodiments, the metal wing structure is not directly connected to the first source or drain structure, and the metal wing structure extends between the first conductive line and the second conductive line.

[0096] According to another aspect of this application, a method of forming a semiconductor structure includes: forming a first source / drain structure and a second source / drain structure on a substrate; depositing a dielectric layer on the first source / drain structure and the second source / drain structure; forming a gate structure between the first source / drain structure and the second source / drain structure, wherein the gate structure is at least partially located in the dielectric layer; forming a first metal contact structure on the first source / drain structure and in the dielectric layer; and forming a second metal contact structure on the first metal contact structure, wherein the second metal contact structure extends laterally beyond the first metal contact structure toward the second source / drain structure, wherein the second metal contact structure is separated from the second source / drain structure by a gap in the vertical direction. In some embodiments, the method of forming a semiconductor structure includes: forming a third source / drain structure; forming a source / drain contact structure on the third source / drain structure; forming a first interconnect structure on the source / drain contact structure; and forming a second interconnect structure on the second metal contact structure, wherein the second interconnect structure is substantially aligned with the first interconnect structure in the lateral direction. The terms “approximately” and “substantially” can refer to the value of a given quantity that varies within a range of 5% of its value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It is understood that, in accordance with this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0097] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: Substrate; A gate structure is located on the substrate; The first source or drain structure of the first transistor is located on the substrate and adjacent to the gate structure; as well as A first source or drain contact structure is located on the first source or drain structure. The first source or drain contact structure includes a first portion and a second portion, the first portion being located on the first source or drain structure, and the second portion being located on the first portion and extending laterally beyond the first portion.

2. The semiconductor structure of claim 1, wherein, The upper surface of the first portion of the first source or drain contact structure is located at substantially the same level as or above the upper surface of the gate structure.

3. The semiconductor structure of claim 1, comprising a first conductive line offset from the first source or drain structure, wherein, The second portion of the first source or drain contact structure extends to a site that at least partially overlaps with the first conductive line.

4. The semiconductor structure of claim 1, comprising a second source or drain structure of a second transistor different from the first transistor, wherein, The second portion of the first source or drain contact structure extends to a site that at least partially overlaps with the second source or drain structure.

5. The semiconductor structure of claim 4, wherein, The second portion of the first source or drain contact structure is separated from the second source or drain structure by a gap.

6. The semiconductor structure of claim 5, wherein, The distance between the second portion of the first source or drain contact structure and the second source or drain structure is equal to or greater than 4.5 nm.

7. The semiconductor structure according to claim 1, comprising: The second source or drain structure of the second transistor is different from that of the first transistor; The second source or drain contact structure is located on the second source or drain structure; as well as First conductive line, The second portion of the first source or drain contact structure and the second source or drain structure are connected to the first conductive line.

8. The semiconductor structure of claim 7, wherein, The second source or drain contact structure is located at substantially the same level as the first portion of the first source or drain contact structure.

9. A semiconductor structure, comprising: Substrate; A gate structure is located on the substrate; The first source or drain structure of the first transistor is located on the substrate and adjacent to the gate structure; The first source or drain contact structure is located on the first source or drain structure; The first metallization layer includes a first conductive line and a second conductive line; as well as The metal wing structure is located on a layer immediately above the first source or drain contact structure and below the first metallization layer.

10. A method for forming a semiconductor structure, comprising: A first source / drain structure and a second source / drain structure are formed on the substrate; Dielectric layers are deposited on the first source / drain structure and the second source / drain structure; A gate structure is formed between the first source / drain structure and the second source / drain structure, and the gate structure is at least partially located in the dielectric layer; A first metal contact structure is formed on the first source / drain structure and in the dielectric layer; as well as A second metal contact structure is formed on the first metal contact structure, and the second metal contact structure extends laterally beyond the first metal contact structure toward the second source / drain structure, wherein the second metal contact structure is separated from the second source / drain structure in the vertical direction by a gap.

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