Preparation method of high-reliability deep ultraviolet flip chip LED and ultraviolet flip chip LED

Abstract

This invention relates to a method for fabricating a high-reliability deep ultraviolet (DUV) flip-chip LED and the UV flip-chip LED itself, belonging to the field of semiconductor device technology. The fabrication method includes: forming an epitaxial wafer on the upper surface of a substrate; performing mesa etching on the epitaxial wafer; fabricating an n-type ohmic contact layer and a p-type ohmic contact layer on the etched mesa; fabricating a passivation layer; etching a tapered connection channel (wider at the bottom and narrower at the top) within the passivation layer through an initial etching stage, a cone corner formation stage, and a channel connection stage; and fabricating a PAD metal layer and a gold-tin eutectic layer within the tapered connection channel. The method of etching a tapered connection channel (wider at the bottom and narrower at the top) within the passivation layer through the initial etching stage, cone corner formation stage, and channel connection stage achieves precise control of the passivation layer etching process, ensuring the accuracy of the shape and size of the tapered connection channel, thereby improving the thrust value of the UV flip-chip LED and thus enhancing its reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for fabricating a high-reliability deep ultraviolet flip-chip LED and the ultraviolet flip-chip LED itself. Background Technology

[0002] With advancements in global LED (light-emitting diode) technology, the emission wavelength of LEDs has expanded from the visible light band to the ultraviolet and deep ultraviolet bands. Ultraviolet LEDs have received continuous attention due to their broad application prospects in photocatalysis, medical phototherapy, healthcare and air purification, and sterilization. However, the external quantum efficiency and luminous efficiency of current ultraviolet LED chips remain relatively low, and problems such as insufficient brightness and current congestion exist, severely limiting their application scope and development potential.

[0003] To improve the performance of ultraviolet (UV) LED chips, existing technologies primarily focus on optimizing the chip design and fabrication process. For example, light extraction efficiency can be increased by altering the chip's geometry, improving material selection, and optimizing structural design. However, these methods often require complex fabrication processes, leading to high costs and hindering large-scale production and widespread application. Furthermore, the electrode fabrication of UV LED chips typically employs a flip-chip structure. This structure, due to the strong absorption of deep ultraviolet light by p-type GaN, results in low luminous efficiency and low brightness. Simultaneously, with the n-electrode and p-electrode located on the same side of the epitaxial wafer, current congestion persists, further impacting the UV LED chip's heat dissipation, lifetime, and external quantum efficiency.

[0004] Given the aforementioned shortcomings of existing technologies, improving the reliability and performance of ultraviolet (UV) LED chips while reducing manufacturing costs is a pressing technical challenge. Particularly in downstream applications, thrust testing is a method for evaluating the structural strength and connection reliability of UV LED chips. Low thrust values ​​in UV LED devices pose a risk of detachment, severely impacting their application in home appliances, baby products, industrial water treatment, medical devices, and curing industries. Therefore, developing a new technical solution to improve the reliability and thrust value of UV LED chips while reducing manufacturing costs has significant practical importance and application value. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a high-reliability deep ultraviolet flip-chip LED and the same LED. The technical solution of this invention is as follows: This invention provides a method for fabricating a high-reliability deep ultraviolet flip-chip LED, comprising: S1, an epitaxial wafer is formed by growing an AlN template layer, an n-type AlGaN layer, a multiple quantum well layer, a p-type AlGaN layer and a p-type GaN layer sequentially from bottom to top on the upper surface of the substrate. S2, prepare mesa etching patterns using photolithography, and perform mesa etching on the epitaxial wafer using the mesa etching patterns; S3, prepare an n-type ohmic contact layer and a p-type ohmic contact layer on the etched mesa; S4, a passivation layer is prepared on the structure obtained in S3; S5, through the initial etching stage, the cone corner formation stage and the channel connection stage, a cone-shaped connection channel with a wider bottom and a narrower top is etched in the passivation layer; S6, Prepare a PAD metal layer in a tapered connecting channel; S7, a gold-tin eutectic layer is prepared on the PAD metal layer.

[0006] Preferably, the initial etching stage includes: introducing a mixed gas of SF6 and C4F8 at a flow rate of 80-120 sccm: 20-30 sccm, activating an ICP source with a power of 800-1000W to generate high-density plasma, applying a lower radio frequency power of 20-50W, and initiating anisotropic etching to form a preliminary vertical connection channel, wherein the depth of the preliminary vertical connection channel is 10-30% of the passivation layer thickness; The etching process in the cone-shaped formation stage includes: a stepwise increase in RF power, increasing by 10-50W every 5 minutes; a decrease in SF6 flow rate from 80-120 sccm to 20-30 sccm; an increase in C4F8 flow rate from 20-30 sccm to 80-120 sccm; and the formation of a cone-shaped connection channel, wherein the depth of the cone-shaped connection channel is 60-80% of the passivation layer thickness. The etching process in the channel connection stage includes: reducing the RF power to 30W, maintaining it for 10-30 seconds and then ending the etching; processing the connection channels corresponding to the upper surfaces of the n-type ohmic contact layer and the p-type ohmic contact layer; and removing the passivation layer from the upper surfaces of the n-type ohmic contact layer and the p-type ohmic contact layer.

[0007] Preferably, the initial etching stage includes: introducing a mixed gas of CF4 and H2 at a flow rate of 70-140 sccm: 10-20 sccm, activating an ICP source with a power of 600-800W to generate high-density plasma, applying a lower radio frequency power of 30-60W, and initiating anisotropic etching to form a preliminary vertical connection channel, wherein the depth of the preliminary vertical connection channel is 10-30% of the passivation layer thickness; The etching process in the cone corner formation stage includes: increasing the RF power in a stepwise manner by 10-70W every 5 minutes, increasing the flow rate of C4F8 from 70-140 sccm to 80-155 sccm, decreasing the flow rate of H2 from 10-20 sccm to 5-10 sccm, and forming a cone corner connection channel, wherein the depth of the cone corner connection channel is 60-80% of the passivation layer thickness; The etching process in the channel connection stage includes: reducing the RF power to 30W, maintaining it for 10-30 seconds and then ending the etching; processing the connection channels corresponding to the upper surfaces of the n-type ohmic contact layer and the p-type ohmic contact layer; and removing the passivation layer from the upper surfaces of the n-type ohmic contact layer and the p-type ohmic contact layer.

[0008] Preferably, the process further includes the following steps before step S2: The epitaxial wafer was cleaned using a mixed solution of H2SO4 and H2O2.

[0009] Preferably, S1 includes: S11, an AlN template layer and an n-type AlGaN layer are sequentially grown on the upper surface of a substrate using the MOCVD method, wherein the thickness of the AlN template layer is 20-30 nm and the thickness of the n-type AlGaN layer is 2.5-3 μm. S12, using MOCVD to sequentially grow a multi-quantum-well layer and a p-type AlGaN layer on the surface of an n-type AlGaN layer; wherein, the multi-quantum-well layer contains 5 InGaN quantum wells and 4 InGaN barrier layers, with a total thickness of 1.5-2 μm; the thickness of the p-type AlGaN layer is 2-3 μm; S13, a p-type GaN layer is grown on the surface of a p-type AlGaN layer using the MOCVD method, wherein the thickness of the p-type GaN layer is 0.5-1 μm.

[0010] Preferably, S2 includes: S21, Prepare a mesa photomask, wherein the thickness of the mesa photomask is 200-700nm; S22 uses UV lithography, with a light source of 365nm UV light and an exposure time of 30-60s. It is developed using a suitable developer to form a mesa etching pattern. S23, the wet etching process is used to roughen the etching pattern on the mesa; S24 introduces a mixed gas of Cl2, BCl3, and Ar in a flow ratio of 20:6:5. The upper RF power is set to 400W and the lower RF power to 150W. The epitaxial wafer is then dry-etched using the roughened mesa etching pattern.

[0011] Preferably, S1 further includes: A GaN buffer layer is grown between an AlN template layer and an n-type AlGaN layer, wherein the thickness of the GaN buffer layer is 2-3 μm.

[0012] Preferably, S3 includes: An n-type ohmic contact layer is grown on the surface of an etched n-type AlGaN layer using a metal evaporation process, and a p-type ohmic contact layer is grown on the surface of a p-type GaN layer using a metal evaporation process.

[0013] Preferably, the thickness of the PAD metal layer is greater than the thickness of the passivation layer.

[0014] The present invention also provides a high-reliability deep ultraviolet flip-chip LED, which is prepared by the above-described method for preparing a high-reliability deep ultraviolet flip-chip LED.

[0015] All of the above-mentioned optional technical solutions can be combined arbitrarily, and the present invention will not provide a detailed description of the structure after each combination.

[0016] By means of the above solution, the beneficial effects of the present invention are as follows: By etching a tapered connection channel that is wider at the bottom and narrower at the top in the passivation layer through the initial etching stage, the cone corner formation stage, and the channel connection stage, precise control of the passivation layer etching process is achieved. This ensures the accuracy of the shape and size of the tapered connection channel, which can improve the thrust value of UV flip LEDs and thus improve the reliability of UV flip LEDs.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a flowchart of the fabrication method of a high-reliability deep ultraviolet flip-chip LED provided in the embodiments of the present invention.

[0019] Figure 2 This is a schematic diagram of the structure formed during the initial etching stage of an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the structure formed during the cone angle formation stage in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the structure of the high-reliability deep ultraviolet flip LED prepared according to an embodiment of the present invention. Detailed Implementation

[0022] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0023] like Figure 1 As shown, the method for fabricating a high-reliability deep ultraviolet flip-chip LED provided in this embodiment of the invention includes: S1, an epitaxial wafer is formed by growing an AlN template layer 102, an n-type AlGaN layer 103, a multi-quantum-well layer 104, a p-type AlGaN layer 105, and a p-type GaN layer 106 sequentially from bottom to top on the upper surface of the substrate 101.

[0024] The substrate 101 can be a sapphire substrate with a thickness of approximately 250 μm. After obtaining the substrate 101, it can be pretreated to remove foreign matter from its surface. During pretreatment, the substrate 101 can be baked in an MOCVD furnace at 950℃~1350℃ for 15-30 min, preferably 20 min.

[0025] In one specific embodiment, S1 includes S11 to S13: S11. An AlN template layer 102 and an n-type AlGaN layer 103 are sequentially grown on the upper surface of a substrate 101 using the MOCVD method. The thickness of the AlN template layer 102 is 20-30 nm, and the thickness of the n-type AlGaN layer 103 is 2.5-3 μm.

[0026] Specifically, when growing the AlN template layer 102, the substrate 101 is placed in the MOCVD equipment, hydrogen is introduced into the MOCVD equipment, and the temperature of the MOCVD equipment is controlled at 1300-1400℃ to perform high-temperature cleaning of the substrate 101. Then, nitrogen and trimethylaluminum are introduced for growth.

[0027] Specifically, when growing the n-type AlGaN layer 103, the growth temperature of the MOCVD equipment is controlled at 1000-1300℃, and ammonia, silane, trimethylgallium, trimethylaluminum and hydrogen are introduced during the growth.

[0028] S12, a multi-quantum well layer 104 and a p-type AlGaN layer 105 are sequentially grown on the surface of an n-type AlGaN layer 103 using MOCVD. The multi-quantum well layer 104 contains 5 InGaN quantum wells and 4 InGaN barrier layers, with a total thickness of 1.5-2 μm. The p-type AlGaN layer 105 has a thickness of 2-3 μm.

[0029] Specifically, when growing the multi-quantum well layer 104, the growth temperature of the MOCVD equipment is controlled at 900-1000℃, and ammonia, silane, trimethylgallium, trimethylaluminum and hydrogen are introduced during growth to alternately grow InGaN quantum wells and InGaN barrier layers.

[0030] Specifically, during the growth of the p-type AlGaN layer 105, the growth was carried out at a temperature of 950-1100℃ and a pressure of 20-100 torr, using pure H2 as the carrier gas. Ammonia, nitrogen, magnesium pyrocene, and trimethylgallium were introduced during the growth process. The V / III molar ratio was controlled at 1000-10000, the Mg / III molar ratio at 5000-50000, and the Mg doping concentration at 1×10⁻⁶. 18 -1×10 20 cm -3 .

[0031] S13, a p-type GaN layer 106 is grown on the surface of the p-type AlGaN layer 105 using MOCVD, wherein the thickness of the p-type GaN layer 106 is 0.5-1 μm.

[0032] Specifically, when growing the p-type GaN layer 106, the growth temperature of the MOCVD equipment is controlled at 900-1300℃, and nitrogen, trimethylgallium and hydrogen are introduced during the growth process.

[0033] Optionally, S1 further includes: A GaN buffer layer with a thickness of 2-3 μm is grown between the AlN template layer 102 and the n-type AlGaN layer 103. By setting the GaN buffer layer, the lattice mismatch and stress buffering between the AlN template layer 102 and the n-type AlGaN layer 103 can be adjusted, thereby improving the epitaxial growth quality.

[0034] S2, a mesa etching pattern is prepared by photolithography, and the epitaxial wafer is etched using the mesa etching pattern.

[0035] Optionally, before step S2, the process further includes cleaning the epitaxial wafer with a mixed solution of H2SO4 and H2O2. The purpose of this step is to remove impurities from the surface of the epitaxial wafer. Specifically, the epitaxial wafer is cleaned using a mixed solution of H2SO4 and H2O2 at a volume ratio of 8:1 at a temperature >70°C, wherein the concentration of H2SO4 is 92-98% and the concentration of H2O2 is 28-30%. Cleaning typically takes 5-10 minutes.

[0036] Specifically, during mesa etching, the epitaxial wafer is transferred to the ICP etching disk for execution. In one specific embodiment, S2 includes S21 to S24: S21, Prepare a mesa photomask, wherein the thickness of the mesa photomask is 200-700nm.

[0037] S22 uses UV (ultraviolet) lithography, with a light source of 365nm UV light and an exposure time of 30-60s. It is developed using a suitable developer to form a mesa pattern.

[0038] S23 uses a wet etching process to roughen the etched pattern on the platform.

[0039] When performing the roughening treatment, a mixture of sulfuric acid and hydrogen peroxide is used with a volume ratio of 8:1. The sulfuric acid concentration is 96-98%, the hydrogen peroxide concentration is 30-32%, the temperature is controlled above 65℃, and the time is 3-5 minutes.

[0040] S24 introduces a mixed gas of Cl2, BCl3, and Ar in a flow ratio of 20:6:5. The upper RF power is set to 400W and the lower RF power to 150W. The epitaxial wafer is then dry-etched using the roughened mesa etching pattern.

[0041] S3, an n-type ohmic contact layer 107 and a p-type ohmic contact layer 108 are prepared on the etched mesa.

[0042] Specifically, S3 includes: growing an n-type ohmic contact layer 107 on the surface of the etched n-type AlGaN layer 103 using a metal vapor deposition process, and growing a p-type ohmic contact layer 108 on the surface of the p-type GaN layer 106 using a metal vapor deposition process.

[0043] The p-type ohmic contact layer 108 and the n-type ohmic contact layer 107 can be fabricated using methods such as vapor deposition or photolithography. The p-type ohmic contact layer 108 is made from one or more of the following metals that have high reflectivity in the ultraviolet band: chromium, nickel, aluminum, silver, gold, titanium, tin, rhodium, and platinum. The n-type ohmic contact layer 107 is made from similar materials. Equipment used for fabricating the p-type ohmic contact layer 108 and the n-type ohmic contact layer 107 includes electron beam evaporation, thermal resistance evaporation, and sputtering evaporation.

[0044] S4, a passivation layer 109 is prepared on the structure obtained in S3.

[0045] The passivation layer 109 is achieved by vapor deposition or deposition. The material used to prepare the passivation layer 109 can be silicon dioxide, silicon nitride, or aluminum oxide.

[0046] Specifically, the passivation layer 109 covers the upper surface of the p-type GaN layer 106, the sidewalls of the epitaxial wafer after mesa etching, and the upper surface of the n-type AlGaN layer 103 that is not covered by the multi-quantum-well layer 104.

[0047] S5, through the initial etching stage, the cone corner formation stage and the channel connection stage, a cone-shaped connection channel with a wider bottom and a narrower top is etched in the passivation layer 109.

[0048] Specifically, the etching in the initial etching stage, the cone corner formation stage, and the channel connection stage can be achieved in the following two ways: The first method: The initial etching stage includes: introducing a mixed gas of SF6 and C4F8 at a flow rate of 80-120 sccm: 20-30 sccm; activating an ICP (inductively coupled plasma) source with a power of 800-1000W to generate high-density plasma; applying a lower radio frequency power of 20-50W; and initiating anisotropic etching to form a preliminary vertical connection channel, wherein the depth of the preliminary vertical connection channel is 10-30% of the passivation layer 109 thickness; for example... Figure 2 As shown, it is a schematic diagram of the structure formed in the initial etching stage of an embodiment of the present invention.

[0049] The etching process during the cone-angle formation stage includes: a stepped increase in RF power, increasing by 10-50W every 5 minutes; a decrease in SF6 flow rate from 80-120 sccm to 20-30 sccm; and an increase in C4F8 flow rate from 20-30 sccm to 80-120 sccm, forming a cone-angle connection channel. The depth of the cone-angle connection channel is 60-80% of the passivation layer 109 thickness. Figure 3 As shown, it is a schematic diagram of the structure formed during the cone angle formation stage in an embodiment of the present invention.

[0050] The etching process in the channel connection stage includes: reducing the RF power to 30W, maintaining it for 10-30 seconds and then ending the etching; processing the connection channels corresponding to the upper surfaces of the n-type ohmic contact layer 107 and the p-type ohmic contact layer 108; and removing the passivation layer 109 from the upper surfaces of the n-type ohmic contact layer 107 and the p-type ohmic contact layer 108.

[0051] The second method: The initial etching stage includes: introducing a mixed gas of CF4 and H2 at a flow rate of 70-140 sccm: 10-20 sccm, activating the ICP source at a power of 600-800W to generate high-density plasma, applying a lower radio frequency power of 30-60W, and initiating anisotropic etching to form a preliminary vertical connection channel, wherein the depth of the preliminary vertical connection channel is 10-30% of the passivation layer 109 thickness; for example... Figure 2 As shown, it is a schematic diagram of the structure formed in the initial etching stage of an embodiment of the present invention.

[0052] The etching process during the cone-angle formation stage includes: a stepped increase in RF power, increasing by 10-70W every 5 minutes; an increase in the flow rate of C4F8, from 70-140 sccm to 80-155 sccm; and a decrease in the flow rate of H2, from 10-20 sccm to 5-10 sccm, forming a cone-angle connection channel. The depth of the cone-angle connection channel is 60-80% of the passivation layer 109 thickness. Figure 3 As shown, it is a schematic diagram of the structure formed during the cone angle formation stage in an embodiment of the present invention.

[0053] The etching process in the channel connection stage includes: reducing the RF power to 30W, maintaining it for 10-30 seconds and then ending the etching; processing the connection channels corresponding to the upper surfaces of the n-type ohmic contact layer 107 and the p-type ohmic contact layer 108; and removing the passivation layer 109 from the upper surfaces of the n-type ohmic contact layer 107 and the p-type ohmic contact layer 108.

[0054] In summary, this embodiment of the invention increases the lower RF power of the ICP in a stepped manner, forming a tapered connection channel that is wider at the bottom and narrower at the top in the passivation layer 109. This tapered connection channel can be a cone, a pyramid, or other shapes and combinations. Of course, the principle of this embodiment can also be applied to RIE etching processes to form a tapered connection channel that is wider at the bottom and narrower at the top in the passivation layer 109.

[0055] By etching a tapered connection channel that is wider at the bottom and narrower at the top within the passivation layer 109 through an initial etching stage, a cone corner formation stage, and a channel connection stage, precise control of the etching process of the passivation layer 109 is achieved. This avoids excessive expansion at the bottom and ensures the accuracy of the shape and size of the tapered connection channel, thereby improving the reliability of the UV flip-chip LED. By adjusting the SF6 / C4F8 (or CF4 / H2) gas ratio and the lower RF power, precise control of the etching rate and sidewall passivation is achieved, forming an ideal tapered connection channel structure that is wider at the bottom and narrower at the top. This effectively improves the heat dissipation performance, current distribution, and thrust performance of the UV flip-chip LED.

[0056] S6, Prepare a PAD metal layer 110 in a tapered connecting channel.

[0057] S7, a gold-tin eutectic layer 111 is prepared on the PAD metal layer 110.

[0058] Specifically, the PAD metal layer 110 and the gold-tin eutectic layer 111 can be grown using deposition or photolithography. The PAD metal layer 110 is formed by stacking multiple metal materials such as chromium, nickel, titanium, platinum, gold, and tin, with gold and tin forming the top layer to facilitate the formation of the gold-tin eutectic layer 111. The thickness of the PAD metal layer 110 is greater than the thickness of the passivation layer 109. The metal plating rate of each layer of the PAD metal layer is less than 0.5 nm / s.

[0059] like Figure 4 As shown, it is a schematic diagram of the structure of the ultraviolet flip LED prepared in an embodiment of the present invention.

[0060] It should be noted that the photolithography used in the embodiments of the present invention can be divided into ordinary photolithography, electron beam photolithography, nanoimprint lithography, or holographic photolithography, etc. The evaporation used in the present invention can be divided into electron beam evaporation, thermal resistance evaporation, or sputtering evaporation, etc.

[0061] Table 1 shows a comparison of the thrust values ​​of a conventional UV flip-chip LED (as shown in the photograph) and a UV flip-chip LED (experimental chip) prepared by the method provided in this invention. As can be seen from Table 1, the thrust value of the experimental chip is significantly increased compared to the photograph, thereby improving the reliability of the UV flip-chip LED.

[0062]

[0063] In summary, the method for fabricating ultraviolet flip-chip LEDs provided in this invention has the following beneficial effects: (1) By increasing the lower RF power in the ICP or RIE etching process, a tapered connection channel with a wider bottom and a narrower top is formed in the passivation layer 109, which effectively improves the thrust value in the reliability test of UV flip LED, significantly reduces the risk of UV flip LED falling off in downstream applications, and improves the reliability and stability of the product. (2) A three-stage etching process is adopted, including the initial etching stage, the cone corner formation stage and the channel connection stage, which realizes precise control of the etching process, avoids excessive expansion at the bottom, ensures the shape and size accuracy of the connection channel that is wider at the bottom and narrower at the top, and further improves the reliability of UV flip LEDs. (3) By adjusting the ratio of SF6 / C4F8 (or CF4 / H2) gas and the lower RF power, the etching rate and sidewall passivation were precisely controlled, forming an ideal tapered connection channel structure that is wide at the bottom and narrow at the top, which effectively improved the heat dissipation performance and current distribution of the ultraviolet flip LED. (4) The method provided in the embodiments of the present invention does not require changing the geometry or material system of the ultraviolet flip LED, is easy to be compatible with existing production processes, has good practicality and economy, and is conducive to large-scale production and promotion of application; (5) By optimizing the etching process parameters, the light output efficiency and brightness of the ultraviolet flip LED were improved, the current congestion phenomenon was reduced, the service life of the ultraviolet flip LED was extended, and the competitiveness of the ultraviolet flip LED in various application fields was enhanced.

[0064] It should be noted that the ultraviolet flip-chip LEDs involved in the embodiments of the present invention are, in particular, deep ultraviolet flip-chip LEDs.

[0065] This invention also provides a high-reliability deep ultraviolet flip-chip LED, which is prepared using the high-reliability deep ultraviolet flip-chip LED preparation method described in the above embodiments, and its structure is as follows. Figure 4 As shown.

[0066] The ultraviolet flip-chip LED provided in this embodiment of the invention forms a tapered connection channel that is wider at the bottom and narrower at the top by etching in the passivation layer 109 through an initial etching stage, a cone corner formation stage, and a channel connection stage. This achieves precise control over the etching process of the passivation layer 109, ensuring the accuracy of the shape and size of the tapered connection channel, which can improve the thrust value of the ultraviolet flip-chip LED and thus improve its reliability.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a high-reliability deep ultraviolet flip-chip LED, characterized in that, include: S1, an epitaxial wafer is formed by growing an AlN template layer (102), an n-type AlGaN layer (103), a multi-quantum well layer (104), a p-type AlGaN layer (105), and a p-type GaN layer (106) sequentially from bottom to top on the upper surface of the substrate (101). S2, prepare mesa etching patterns using photolithography, and perform mesa etching on the epitaxial wafer using the mesa etching patterns; S3, an n-type ohmic contact layer (107) and a p-type ohmic contact layer (108) are prepared on the etched mesa. S4, a passivation layer (109) is prepared on the structure obtained in S3. S5, a tapered connection channel with a wider bottom and a narrower top is formed by etching in the passivation layer (109) through the initial etching stage, the cone corner formation stage and the channel connection stage; S6, a PAD metal layer (110) is prepared in the tapered connection channel. S7, a gold-tin eutectic layer (111) is prepared on the PAD metal layer (110).

2. The method for fabricating a high-reliability deep ultraviolet flip-chip LED according to claim 1, characterized in that, The initial etching stage includes: introducing a mixed gas of SF6 and C4F8 at a flow rate of 80-120 sccm: 20-30 sccm, starting the ICP source power at 800-1000W to generate high-density plasma, applying a lower radio frequency power of 20-50W, and initiating anisotropic etching to form a preliminary vertical connection channel, wherein the depth of the preliminary vertical connection channel is 10-30% of the thickness of the passivation layer (109); The etching process in the cone corner formation stage includes: increasing the RF power in a stepwise manner by 10-50W every 5 minutes, reducing the SF6 flow rate from 80-120 sccm to 20-30 sccm, increasing the C4F8 flow rate from 20-30 sccm to 80-120 sccm, and forming a cone corner connection channel, wherein the depth of the cone corner connection channel is 60-80% of the thickness of the passivation layer (109); The etching process in the channel connection stage includes: reducing the RF power to 30W, maintaining it for 10-30s and then ending the etching, processing the connection channels corresponding to the upper surfaces of the n-type ohmic contact layer (107) and the p-type ohmic contact layer (108), and removing the passivation layer (109) on the upper surfaces of the n-type ohmic contact layer (107) and the p-type ohmic contact layer (108).

3. The method for fabricating a high-reliability deep ultraviolet flip-chip LED according to claim 1, characterized in that, The initial etching stage includes: introducing a mixed gas of CF4 and H2 at a flow rate of 70-140 sccm: 10-20 sccm, starting the ICP source power at 600-800W to generate high-density plasma, applying a lower radio frequency power of 30-60W, and initiating anisotropic etching to form a preliminary vertical connection channel, wherein the depth of the preliminary vertical connection channel is 10-30% of the thickness of the passivation layer (109); The etching process in the cone corner formation stage includes: stepwise increase of the lower RF power, increasing by 10-70W every 5 minutes; increasing the flow rate of C4F8 from 70-140 sccm to 80-155 sccm; decreasing the flow rate of H2 from 10-20 sccm to 5-10 sccm; and forming a cone corner connection channel, wherein the depth of the cone corner connection channel is 60-80% of the thickness of the passivation layer (109). The etching process in the channel connection stage includes: reducing the RF power to 30W, maintaining it for 10-30s and then ending the etching, processing the connection channels corresponding to the upper surfaces of the n-type ohmic contact layer (107) and the p-type ohmic contact layer (108), and removing the passivation layer (109) on the upper surfaces of the n-type ohmic contact layer (107) and the p-type ohmic contact layer (108).

4. The method for fabricating a high-reliability deep ultraviolet flip-chip LED according to claim 1, characterized in that, Before S2, the following also applies: The epitaxial wafer was cleaned using a mixed solution of H2SO4 and H2O2.

5. The method for fabricating a high-reliability deep ultraviolet flip-chip LED according to claim 1, characterized in that, S1 includes: S11, an AlN template layer (102) and an n-type AlGaN layer (103) are sequentially grown on the upper surface of a substrate (101) using the MOCVD method. The thickness of the AlN template layer (102) is 20-30 nm, and the thickness of the n-type AlGaN layer (103) is 2.5-3 μm. S12, a multi-quantum well layer (104) and a p-type AlGaN layer (105) are sequentially grown on the surface of an n-type AlGaN layer (103) using MOCVD; wherein, the multi-quantum well layer (104) contains 5 InGaN quantum wells and 4 InGaN barrier layers, with a total thickness of 1.5-2 μm; the p-type AlGaN layer (105) has a thickness of 2-3 μm; S13, a p-type GaN layer (106) is grown on the surface of a p-type AlGaN layer (105) using the MOCVD method, wherein the thickness of the p-type GaN layer (106) is 0.5-1 μm.

6. The method for fabricating a high-reliability deep ultraviolet flip-chip LED according to claim 1, characterized in that, S2 includes: S21, Prepare a mesa photomask, wherein the thickness of the mesa photomask is 200-700nm; S22 uses UV lithography, with a light source of 365nm UV light and an exposure time of 30-60s. It is developed using a suitable developer to form a mesa etching pattern. S23, the wet etching process is used to roughen the etching pattern on the mesa; S24 introduces a mixed gas of Cl2, BCl3, and Ar in a flow ratio of 20:6:

5. The upper RF power is set to 400W and the lower RF power to 150W. The epitaxial wafer is then dry-etched using the roughened mesa etching pattern.

7. The method for fabricating a high-reliability deep ultraviolet flip-chip LED according to claim 1 or 6, characterized in that, S1 further includes: A GaN buffer layer is grown between an AlN template layer (102) and an n-type AlGaN layer (103), wherein the thickness of the GaN buffer layer is 2-3 μm.

8. The method for fabricating a high-reliability deep ultraviolet flip-chip LED according to claim 1, characterized in that, S3 includes: An n-type ohmic contact layer (107) is grown on the surface of the etched n-type AlGaN layer (103) using a metal vapor deposition process, and a p-type ohmic contact layer (108) is grown on the surface of the p-type GaN layer (106) using a metal vapor deposition process.

9. The method for fabricating a high-reliability deep ultraviolet flip-chip LED according to claim 1, characterized in that, The thickness of the PAD metal layer (110) is greater than the thickness of the passivation layer (109).

10. A high-reliability deep ultraviolet flip-chip LED, characterized in that, The high-reliability deep ultraviolet flip-chip LED was prepared using the preparation method described in any one of claims 1 to 9.

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