Epitaxial structure, manufacturing method thereof, light emitting chip and display panel
By growing N-type and P-type (AlmGa1-m)0.5In0.5P confinement layers with specific lattice constant ranges on GaAs substrates, the lattice mismatch problem in semiconductor AlGaInP light-emitting LEDs was solved, improving the crystal quality and photoelectric performance of the epitaxial wafer.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2026-07-03
Smart Images
Figure CN122340980A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of LED chips, and in particular, to an epitaxial structure, a manufacturing method thereof, a light-emitting chip, and a display panel. Background Art
[0002] As a new display technology, Micro LED has its size reduced from millimeter level to micronano level compared with traditional LEDs. When integrated into a high-density and small-size array and applied to the display field, it has advantages such as high brightness, high resolution, high contrast, low power consumption, long service life, etc., and also has excellent performance in aspects such as response speed and thermal stability.
[0003] However, in semiconductor AlGaInP light-emitting LEDs, there are large thermal mismatches and lattice mismatches between each layer, resulting in poor quality of epitaxial wafers. Therefore, how to improve the mismatch between layers is one of the ways to obtain high-quality epitaxial wafers. Good lattice-quality epitaxial wafers have a great impact on the improvement of optoelectronic properties and defects. Summary of the Invention
[0004] In view of the above deficiencies of the prior art, the purpose of the present application is to provide an epitaxial structure, a manufacturing method thereof, a light-emitting chip, and a display panel, aiming to reduce lattice mismatch to improve the quality of epitaxial wafers.
[0005] In the first aspect, the present application provides an epitaxial structure, including:
[0006] A GaAs substrate;
[0007] On the GaAs substrate, a buffer layer, an N-type (Al 0.5 , 0.5 , 1-n , 1-m , 0.5 , 0.5 , 1-m , 1-m , m , 0.5 , n , 0.5 ,
[0008] , 0.5 , m , m , 0.5 Ga 1-m ) 0.5 In 0.5 P confinement layer, an N-type waveguide layer, an active layer, a P-type waveguide layer, a P-type (Al n Ga 1-n ) 0.5 In 0.5 P confinement layer, a transition layer, and a P-type current spreading layer are successively provided;
[0008] Where 0.8 < m < 1, the minimum value of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is greater than the lattice constant of the N-type waveguide layer, and the maximum value of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is less than 5.666;
[0009] 0.8 < n < 1, the minimum value of the lattice constant of the P-type (Al n Ga 1-n ) 0.5 In 0.5 P confinement layer is greater than the lattice constant of the P-type waveguide layer, and the P-type (Al m Ga 1-m ) 0.5 In 0.5 The maximum value of the lattice constant of the P confinement layer is less than 5.666.
[0010] In a possible embodiment, the thickness of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is 0.25 - 0.45 μm.
[0011] In a possible embodiment, the thickness of the P-type (Al n Ga 1-n ) 0.5 In 0.5 P confinement layer is 0.3 - 0.8 μm.
[0012] In a possible embodiment, the thickness of the N-type waveguide layer is 0.06 - 0.1 μm.
[0013] In a possible embodiment, the N-type waveguide layer is an N-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P layer, the lattice constant of the N-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 layer is 5.664, and the value range of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is (5.664, 5.666).
[0014] In a possible embodiment, the thickness of the P-type waveguide layer is 0.07 - 0.1 μm.
[0015] In a possible embodiment, the P-type waveguide layer is a P-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P layer, the P-type (Al 0.7 Ga 0.3 ) 0.5 In 0.5The lattice constant of the layer is 5.664, and the P-type (Al m Ga 1-m ) 0.5 In 0.5 The value range of the lattice constant of the P-InP confinement layer is (5.664, 5.666).
[0016] In a possible embodiment, the thickness of the buffer layer is 0.2 - 0.5 μm.
[0017] In a possible embodiment, a reflective layer is further included, and the reflective layer is disposed between the buffer layer and the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layers.
[0018] In a possible embodiment, the thickness of the reflective layer is 2.0 - 4.0 μm.
[0019] In a second aspect, the present application further provides a method for fabricating an epitaxial structure, including:
[0020] Providing a GaAs substrate;
[0021] Successively growing a buffer layer, an N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer, an N-type waveguide layer, an active layer, a P-type waveguide layer, a P-type (Al n Ga 1-n ) 0.5 [[ID=4 eighty]]In 0.5 P confinement layer, a transition layer, and a P-type current spreading layer on the GaAs substrate;
[0022] Where 0.8 < m < 1, the minimum value of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is greater than the lattice constant of the N-type waveguide layer, and the maximum value of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is less than 5.666;
[0023] 0.8 < n < 1, the minimum value of the lattice constant of the P-type (Al n Ga 1-n ) 0.5 In[[ID=7 ninety]] 0.5 P confinement layer is greater than the lattice constant of the P-type waveguide layer, and the P-type (Al m Ga1-m ) 0.5 In 0.5 The maximum value of the lattice constant of the p-confined layer is less than 5.666.
[0024] In one possible embodiment, the N-type (Al) m Ga 1-m ) 0.5 In 0.5 The thickness of the P-confining layer is 0.25–0.45 μm.
[0025] In one possible embodiment, the P-type (Al) n Ga 1-n ) 0.5 In 0.5 The thickness of the P-confinement layer is 0.3–0.8 μm.
[0026] Thirdly, this application also provides a light-emitting chip, characterized in that it comprises:
[0027] The first electrode, the second electrode, and the epitaxial structure as described in the first aspect, wherein the GaAs substrate and the buffer layer are removed by a substrate removal process, and the first electrode is connected to the N-type (Al) epitaxial structure. m Ga 1-m ) 0.5 In 0.5 The P-type confinement layer is electrically connected, and the second electrode is electrically connected to the P-type current spreading layer.
[0028] Fourthly, this application also provides a display panel, characterized in that it comprises:
[0029] The driving substrate and a plurality of light-emitting chips as described in the third aspect, wherein the plurality of light-emitting chips are disposed on the driving substrate and electrically connected to the driving substrate, and the driving substrate is used to transmit electrical signals to the plurality of light-emitting chips to control the plurality of light-emitting chips to emit light.
[0030] Beneficial effects:
[0031] The epitaxial structure, its fabrication method, light-emitting chip, and display panel provided in this application utilize N-type (Al)... m Ga 1-m ) 0.5 In 0.5 P-confined layer and P-type (Al) n Ga 1-n ) 0.5 In 0.5 The values of m and n in the p-confinement layer are both set between 0.8 and 1, resulting in a lattice constant of (5.664, 5.666). This lattice constant is higher than that of N / P type Al in conventional LED structures. 0.5In 0.5 The lattice constant of the P-confined layer is 5.666, which is smaller than that of the adjacent waveguide layer (5.664). Therefore, this type of confinement layer can better grow the active layer (waveguide layer and MQW), the subsequent transition layer, and the current spreading layer, thereby reducing lattice mismatch and improving crystal quality. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of a method for fabricating an epitaxial structure provided in an embodiment of this application;
[0033] Figure 2 for Figure 1 A schematic diagram of the structure after epitaxial structure growth in a method for fabricating an epitaxial structure is shown.
[0034] Figure 3 This is a schematic diagram of an epitaxial structure provided in an embodiment of this application;
[0035] Figure 4 This is a schematic diagram of another epitaxial structure provided in an embodiment of this application.
[0036] Explanation of reference numerals in the attached figures:
[0037] 1-GaAs substrate; 2-Buffer layer; 3-Reflective layer; 31-First reflective AlAs layer; 33-Second reflective AlGaAs layer; 4-N-type (Al m Ga 1-m ) 0.5 In 0.5 P-confining layer; 5-N-type waveguide layer; 6-active layer; 7-P-type waveguide layer; 8-P-type (Al) waveguide layer. n Ga 1-n ) 0.5 In 0.5 P-confined layer; 9-transition layer; 10-P-type current spreading layer. Detailed Implementation
[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0039] This invention discloses many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described herein. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Generally, terms can be understood at least in part according to their usage in accordance with the invention. For example, the term "one or more" as used herein, depending at least in part on the invention, can be used to describe any component, structure, or feature in the singular or in the plural form to describe a combination of components, structures, or features. Similarly, terms such as "a," "an," or "the" can also be understood, depending at least in part on the invention, to convey either a singular or a plural usage. Furthermore, the term "based on..." can be understood not necessarily to convey an exclusive set of factors, but rather, depending at least in part on the invention, can alternatively allow for additional factors that do not necessarily have to be explicitly described.
[0041] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this invention should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including the presence of an intermediate component or layer between the two, and “on something” or “above something” means not only “on something” or “above something,” but also “on something” or “above something” where no intermediate component or layer between the two exists.
[0042] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used in this invention to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways, rotated 90°, or otherwise oriented, and the spatial relative descriptive terms used in this invention can be interpreted accordingly.
[0043] As used herein, the term "layer" refers to a portion of a material that includes a region having a certain thickness. A layer can extend over the entire underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. In addition, a layer can be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below it. A layer can include multiple layers. For example, a semiconductor layer can include one or more doped or undoped semiconductor layers and can have the same or different materials.
[0044] Reference Figure 1 , which is a schematic flow diagram of a method for fabricating an epitaxial structure provided by an embodiment of the present application. The method includes:
[0045] 101: Provide a GaAs substrate.
[0046] 102: Sequentially grow a buffer layer, an N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer, an N-type waveguide layer, an active layer, a P-type waveguide layer, a P-type (Al n Ga 1-n ) 0.5 In 0.5 P confinement layer, a transition layer, and a P-type current spreading layer on the GaAs substrate.
[0047] Among them, 0.8 < m < 1, the minimum value of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is greater than the lattice constant of the N-type waveguide layer, and the maximum value of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is less than 5.666; The maximum value of the lattice constant of the p-confined layer is less than 5.666.
[0049] Optionally, the value of m can be 0.81, 0.9, 0.95, 0.99, etc. No specific limitation is made here.
[0050] Optionally, the value of n can be 0.81, 0.9, 0.95, 0.99, etc. No specific limitation is made here.
[0051] Optionally, the N-type (Al) m Ga 1-m ) 0.5 In 0.5 The thickness of the P-confining layer 4 is 0.25 to 0.45 μm, for example, 0.25 μm, 0.3 μm, 0.35 μm or 0.45 μm.
[0052] Optionally, the N-type (Al) m Ga 1-m ) 0.5 In 0.5 The dopant in the P-confined layer 4 is silicon.
[0053] Optionally, the P-type (Al) n Ga 1-n ) 0.5 In 0.5 The thickness of the P-confining layer 8 is 0.3 to 0.8 μm, for example, 0.3 μm, 0.55 μm, 0.5 μm or 0.8 μm.
[0054] Optionally, the P-type (Al) n Ga 1-n ) 0.5 In 0.5 The dopant in the P-confined layer 8 is magnesium.
[0055] Optionally, the thickness of the N-type waveguide layer 5 is 0.06 to 0.1 μm, for example, 0.06 μm, 0.08 μm, 0.09 μm or 0.1 μm.
[0056] Optionally, the N-type waveguide layer 5 is an N-type (Al) waveguide layer. 0.7 Ga 0.3 ) 0.5 In 0.5 P layer, the N-type (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The lattice constant of the layer is 5.664, and the N-type (Al) m Ga 1-m ) 0.5 In 0.5The lattice constant of the p-confined layer ranges from 5.664 to 5.666.
[0057] Optionally, the N-type (Al) m Ga 1-m ) 0.5 In 0.5 The lattice constant of the p-confined layer is 5.665.
[0058] Optionally, the thickness of the P-type waveguide layer 7 is 0.07 to 0.1 μm, for example, 0.07 μm, 0.085 μm, 0.09 μm or 0.1 μm.
[0059] Optionally, the P-type waveguide layer 7 is a P-type (Al) waveguide layer. 0.7 Ga 0.3 ) 0.5 In 0.5 P layer, the P-type (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The lattice constant of the layer is 5.664, and the P-type (Al) m Ga 1-m ) 0.5 In 0.5 The lattice constant of the p-confined layer ranges from 5.664 to 5.666.
[0060] Optionally, the P-type (Al) m Ga 1-m ) 0.5 In 0.5 The lattice constant of the p-confined layer is 5.665.
[0061] Optionally, the thickness of the buffer layer 2 is 0.2 to 0.5 μm, for example, 0.2 μm, 0.35 μm or 0.5 μm.
[0062] Optionally, the thickness of the active layer 6 is 0.2 to 0.3 μm, for example, 0.2 μm, 0.35 μm or 0.3 μm.
[0063] Optionally, the thickness of the P-type AlGaInP waveguide layer 7 is 0.07 to 0.1 μm, for example, 0.07 μm, 0.085 μm, 0.09 μm or 0.1 μm.
[0064] Optionally, the thickness of the transition layer 9 is 0.06 μm.
[0065] Optionally, the thickness of the P-type current spreading layer 10 is 5 to 10 μm, for example, 5 μm, 7 μm, 7.5 μm or 10 μm.
[0066] Based on the same inventive concept, this embodiment also provides a method for fabricating an epitaxial structure, the method comprising:
[0067] 201: Provide a GaAs substrate;
[0068] 202: A reflective layer is grown on the buffer layer;
[0069] 203: N-type (Al) sequentially applied to the reflective layer m Ga 1-m ) 0.5 In 0.5 P-type confinement layer, N-type waveguide layer, active layer, P-type waveguide layer, P-type (Al) n Ga 1-n ) 0.5 In 0.5 P-confinement layer, transition layer, and P-type current spread layer.
[0070] Optionally, the thickness of the reflective layer is 2.0 to 4.0 μm.
[0071] Optionally, the reflective layer includes an alternately arranged first reflective AlAs layer 31 and a second reflective AlGaAs layer 33, wherein the reflectivity of the first reflective AlAs layer 31 is less than that of the second reflective AlGaAs layer 33, and growth begins with the first reflective AlAs layer 31 and ends with the second reflective AlGaAs layer 33.
[0072] For example, such as Figure 2 As shown, during the MOCVD growth process, the GaAs substrate 1 is first purged with H2, while the reaction chamber temperature is maintained at 650-750℃. This high-temperature treatment effectively removes any moisture. First, a GaAs buffer layer 2 is grown, primarily composed of GaAs. Then, a reflective layer 3 (also called a DBR layer) is grown. This DBR distributed Bragg reflector composite structure includes alternating first reflectivity AlAs layers 31 and second reflectivity AlGaAs layers 33. The reflectivity of the first reflectivity AlAs layer 31 is less than that of the second reflectivity AlGaAs layer 33. Growth begins with the first reflectivity AlAs layer 31 and ends with the second reflectivity AlGaAs layer 33. Finally, N-type (Al... m Ga 1-m ) 0.5 In 0.5 P-type confinement layer 4 and N-type AlGaInP waveguide layer 5; then active layer 6, during the growth of each barrier and well layer, the growth switching of wells and barriers is accurately controlled; after growth is completed, P-type AlGaInP waveguide layer 7 and P-type (Al n Ga 1-n ) 0.5 In 0.5P confinement layer 8; regrowth transition layer 9; finally grow P-type current spreading layer 10.
[0073] In summary, in this embodiment, by making the values of m and n of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer and the P-type (Al n Ga 1-n ) 0.5 In 0.5 P confinement layer both fall within the range of 0.8 and 1, the corresponding lattice constant thereof is located at (5.664, 5.666), and its lattice constant is smaller than that of the N / P-type Al 0.5 In 0.5 P confinement layer in the conventional LED structure, which is 5.666, but is close to the lattice constant of 5.664 of the adjacent waveguide layer thereto. Therefore, by using such a confinement layer, the active layer (waveguide layer and MQW), the subsequent transition layer and the current spreading layer can be grown better, thereby reducing lattice mismatch and improving crystal quality.
[0074] Reference Figure 3-4 , based on the same inventive concept, the present application further provides an epitaxial structure, including: GaAs substrate 1; a buffer layer 2, a N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer 4, a N-type waveguide layer 5, an active layer 6, a P-type waveguide layer 7, a P-type (Al n Ga 1-n ) 0.5 In 0.5 P confinement layer 8, a transition layer 9 and a P-type current spreading layer 10 are sequentially provided on the GaAs substrate 1.
[0075] Among them, 0.8 < m < 1, the minimum value of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer 4 is greater than the lattice constant of the N-type waveguide layer 5, and the maximum value of the lattice constant of the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer 4 is less than 5.666;
[0076] 0.8 < n < 1, the minimum value of the lattice constant of the P-type (Al n Ga 1-n ) 0.5 In 0.5The minimum lattice constant of the P-confinement layer 8 is greater than the lattice constant of the P-type waveguide layer 7, wherein the P-type (Al) m Ga 1-m ) 0.5 In 0.5 The maximum lattice constant of the P-confined layer 8 is less than 5.666.
[0077] Optionally, the N-type (Al) m Ga 1-m ) 0.5 In 0.5 The thickness of the P-confining layer 4 is 0.25–0.45 μm.
[0078] Optionally, the P-type (Al) n Ga 1-n ) 0.5 In 0.5 The thickness of the P-confining layer 8 is 0.3–0.8 μm.
[0079] Optionally, the thickness of the N-type waveguide layer 5 is 0.06 to 0.1 μm.
[0080] Optionally, the N-type waveguide layer 5 is an N-type (Al) waveguide layer. 0.7 Ga 0.3 ) 0.5 In 0.5 P layer, the N-type (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The lattice constant of the layer is 5.664, and the N-type (Al) m Ga 1-m ) 0.5 In 0.5 The lattice constant of the p-confined layer ranges from 5.664 to 5.666.
[0081] Optionally, the thickness of the P-type waveguide layer 7 is 0.07 to 0.1 μm.
[0082] Optionally, the P-type waveguide layer 7 is a P-type (Al) waveguide layer. 0.7 Ga 0.3 ) 0.5 In 0.5 P layer, the P-type (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The lattice constant of the layer is 5.664, and the P-type (Al) m Ga 1-m ) 0.5 In 0.5 The lattice constant of the p-confined layer ranges from 5.664 to 5.666.
[0083] Optionally, the thickness of the buffer layer 2 is 0.2 to 0.5 μm.
[0084] In one possible embodiment, a reflective layer 3 is further included, the reflective layer 3 being disposed between the buffer layer 2 and the N-type (Al) m Ga 1-m ) 0.5 In 0.5 Between P-restricted layers 4.
[0085] Optionally, the reflective layer 3 is a DBR distributed Bragg reflector composite structure, and the thickness of the reflective layer 3 is 2.0 to 4.0 μm.
[0086] Optionally, the aforementioned reflective layer 3 includes an alternately arranged first reflective AlAs layer 31 and a second reflective AlGaAs layer 33, wherein the reflectivity of the first reflective AlAs layer 31 is less than that of the second reflective AlGaAs layer 33, and growth begins with the first reflective AlAs layer 31 and ends with the second reflective AlGaAs layer 33.
[0087] Optionally, the alternation of the first reflective AlAs layer 31 and the second reflective AlGaAs layer 33 can be multiple layers, and no specific limitation is made here.
[0088] Optionally, the thickness of the active layer 6 is 0.2–0.3 μm.
[0089] Optionally, the thickness of the P-type AlGaInP waveguide layer 7 is 0.07–0.1 μm.
[0090] Optionally, the thickness of the transition layer 9 is 0.06 μm.
[0091] Optionally, the thickness of the P-type current spreading layer 10 is 5–10 μm.
[0092] It is understood that, in this embodiment, by using N-type (Al) m Ga 1-m ) 0.5 In 0.5 P-confined layer and P-type (Al) n Ga 1-n ) 0.5 In 0.5 The values of m and n in the p-confinement layer are both set between 0.8 and 1, resulting in a lattice constant of (5.664, 5.666). This lattice constant is higher than that of N / P type Al in conventional LED structures. 0.5 In 0.5The lattice constant of the P-confined layer is 5.666, which is smaller, but close to the lattice constant of its adjacent waveguide layer of 5.664. Therefore, this type of confinement layer can better grow the active layer (waveguide layer and MQW) and the subsequent transition layer and current spreading layer, thereby reducing lattice mismatch and improving crystal quality.
[0093] Based on the same inventive concept, this application also provides a light-emitting chip, including: a first electrode, a second electrode, and an epitaxial structure as described in the above embodiments, wherein the GaAs substrate and buffer layer in the epitaxial structure are removed by a substrate removal process, and the first electrode is connected to an N-type (Al) light-emitting chip. m Ga 1-m ) 0.5 In 0.5 The P-type confinement layer is electrically connected, and the second electrode is electrically connected to the P-type current spreading layer.
[0094] Optionally, the first electrode is an N-type metal electrode and the second electrode is a P-type metal electrode.
[0095] Optionally, the light-emitting chip is a microLED chip or a miniLED chip.
[0096] Based on the same inventive concept, this application also provides a display panel, including: a driving substrate and a plurality of light-emitting chips as described above, wherein the plurality of light-emitting chips are disposed on the driving substrate and electrically connected to the driving substrate, and the driving substrate is used to transmit electrical signals to the plurality of light-emitting chips to control the plurality of light-emitting chips to emit light.
[0097] In summary, the epitaxial structure and its fabrication method, the light-emitting chip, and the display panel provided in this application embodiment utilize N-type (Al) m Ga 1-m ) 0.5 In 0.5 P-confined layer and P-type (Al) n Ga 1-n ) 0.5 In 0.5 The values of m and n in the p-confinement layer are both set between 0.8 and 1, resulting in a lattice constant of (5.664, 5.666). This lattice constant is higher than that of N / P type Al in conventional LED structures. 0.5 In 0.5 The lattice constant of the P-confined layer is 5.666, which is smaller than that of the adjacent waveguide layer (5.664). Therefore, this type of confinement layer can better grow the active layer (waveguide layer and MQW), the subsequent transition layer, and the current spreading layer, thereby reducing lattice mismatch and improving crystal quality.
[0098] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. An epitaxial structure, characterized in that, include: GaAs substrate; The GaAs substrate is sequentially provided with a buffer layer, an N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer, an N-type waveguide layer, an active layer, a P-type waveguide layer, a P-type (Al n Ga 1-n ) 0.5 In 0.5 P confinement layer, a transition layer and a P-type current spreading layer; Among them, 0.8 < m < 1, the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer has a minimum lattice constant greater than that of the N-type waveguide layer. The N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer has a maximum lattice constant less than 5.666; 0.8 < n < 1, the P-type (Al n Ga 1-n ) 0.5 In 0.5 The minimum value of the lattice constant of the P-type InP confinement layer is greater than the lattice constant of the P-type waveguide layer. The P-type (Al m Ga 1-m ) 0.5 In 0.5 The maximum value of the lattice constant of the P-type InP confinement layer is less than 5.
666.
2. The epitaxial structure of claim 1, wherein, The N-type (Al) m Ga 1-m ) 0.5 In 0.5 The thickness of the P-confining layer is 0.25–0.45 μm.
3. Epitaxial structure according to claim 1 or 2, characterized in that The P-type (Al n Ga 1-n ) 0.5 In 0.5 The thickness of the P-limiting layer is 0.3-0.8 μm.
4. The epitaxial structure of claim 3, wherein, The thickness of the N-type waveguide layer is 0.06–0.1 μm.
5. The epitaxial structure of claim 4, wherein, The N-type waveguide layer is N-type (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 P layer, the N-type (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The lattice constant of the layer is 5.664, and the N-type (Al) m Ga 1-m ) 0.5 In 0.5 The lattice constant of the p-confined layer ranges from 5.664 to 5.
666.
6. The epitaxial structure of claim 4, wherein, The thickness of the P-type waveguide layer is 0.07–0.1 μm.
7. The epitaxial structure of claim 6, wherein, The P-type waveguide layer is P-type (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 P layer, the P-type (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The lattice constant of the layer is 5.664, and the P-type (Al) m Ga 1-m ) 0.5 In 0.5 The lattice constant of the p-confined layer ranges from 5.664 to 5.
666.
8. The epitaxial structure as described in claim 5 or 7, characterized in that, The thickness of the buffer layer is 0.2 to 0.5 μm.
9. The epitaxial structure as described in claim 8, characterized in that, It also includes a reflective layer, which is disposed between the buffer layer and the N-type (Al) m Ga 1-m ) 0.5 In 0.5 Between P-restricted layers.
10. The epitaxial structure as described in claim 9, characterized in that, The thickness of the reflective layer is 2.0–4.0 μm.
11. A method for fabricating an epitaxial structure, characterized in that, include: Provide a GaAs substrate; A buffer layer and an N-type (Al2O3) layer are sequentially grown on the GaAs substrate. m Ga 1-m ) 0.5 In 0.5 P-type confinement layer, N-type waveguide layer, active layer, P-type waveguide layer, P-type (Al) n Ga 1-n ) 0.5 In 0.5 P-confinement layer, transition layer, and P-type current spread layer; Among them, 0.8 < m < 1, the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer has a minimum lattice constant greater than that of the N-type waveguide layer, and the N-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer has a maximum lattice constant less than 5.666; 0.8 < n < 1, the minimum value of the lattice constant of the P-type (Al n Ga 1-n ) 0.5 In 0.5 P confinement layer is greater than the lattice constant of the P-type waveguide layer, and the maximum value of the lattice constant of the P-type (Al m Ga 1-m ) 0.5 In 0.5 P confinement layer is less than 5.
666.
12. The method for fabricating an epitaxial structure as described in claim 11, characterized in that, The N-type (Al m Ga 1-m ) 0.5 In 0.5 The thickness of the P-limiting layer is 0.25-0.45 μm.
13. The method for fabricating an epitaxial structure as described in claim 11 or 12, characterized in that, The P-type (Al n Ga 1-n ) 0.5 In 0.5 The thickness of the P-limiting layer is 0.3-0.8 μm.
14. A light-emitting chip, characterized in that, include: The first electrode, the second electrode, and the epitaxial structure as described in any one of claims 1-10, wherein the GaAs substrate and the buffer layer are removed by a substrate removal process, and the first electrode is connected to the N-type (Al) epitaxial structure. m Ga 1-m ) 0.5 In 0.5 The P-type confinement layer is electrically connected, and the second electrode is electrically connected to the P-type current spreading layer.
15. A display panel, characterized in that, include: The driving substrate and a plurality of light-emitting chips as described in claim 14, wherein the plurality of light-emitting chips are disposed on the driving substrate and electrically connected to the driving substrate, and the driving substrate is used to transmit electrical signals to the plurality of light-emitting chips to control the plurality of light-emitting chips to emit light.