A control method of a display driving chip and a related device

Abstract

The application relates to the field of display screen control and provides a display driving chip control method and related equipment, the method comprising the following steps: before a MIPI bus enters an ultra-low power consumption mode, in response to receiving a sleep instruction sent by a host, monitoring the state of a clock channel of a MIPI D-PHY; in the case that the state of the clock channel meets a preset condition, performing a reset operation to reset the display driving chip, and the display driving chip no longer receives or responds to a reset instruction sent by the host, so that the display driving chip cannot be triggered by the host to perform the reset operation. Through the software reset before exiting the ultra-low power consumption mode, the reset instruction sent by the host is no longer relied on, so that even if the LP-11 state of the clock channel appears temporarily when the ultra-low power consumption mode is exited, high-speed data can be normally received subsequently.

Description

Technical Field

[0001] This invention relates to the field of display screen control, and more specifically to a control method for a display driver chip and related equipment. Background Technology

[0002] When exiting the ultra-low power mode, the host sets the state of the MIPI D-PHY clock channel to LP-11 and then sends a reset command to the slave. After the slave receives the reset command and completes the reset, it updates the state machine to be able to process the high-speed data subsequently sent by the host.

[0003] However, in practice, it was found that after the slave device is reset, it cannot switch from sleep mode to normal working mode in time, which leads to abnormal data reception in the initial stage of wake-up. Specifically, the previous image cannot be received normally, resulting in missing images or abnormal display. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a control method for a display driver chip that avoids image display abnormalities when exiting ultra-low power mode.

[0005] To address the above problems, this application provides the following technical solution: In a first aspect, embodiments of this application provide a control method for a display driver chip. The method includes: before the MIPI bus enters an ultra-low power mode, in response to receiving a sleep command sent by the host, monitoring the state of the clock channel of the MIPI D-PHY; if the state of the clock channel meets preset conditions, performing a reset operation to reset the display driver chip, and the display driver chip no longer receives or responds to reset commands sent by the host, so that the display driver chip cannot be triggered by the host to perform a reset operation; in response to the host changing the state of the clock channel to LP-11 when the MIPI bus exits the ultra-low power mode, the display driver chip identifies the LP-11 state of the clock channel and updates the state machine to be able to process high-speed data subsequently sent by the host.

[0006] Optionally, the step of monitoring the state of the clock channel of MIPI D-PHY in response to receiving a sleep command sent by the host before the MIPI bus enters the ultra-low power mode includes: performing a sleep operation in response to receiving a sleep command sent by the host before the MIPI bus enters the ultra-low power mode; and monitoring the state of the clock channel of MIPI D-PHY after the sleep operation is completed.

[0007] Optionally, the host is an application processor in a mobile phone, and the display driver chip is an integrated touch and display driver chip.

[0008] Optionally, the sleep operation includes at least one of the following: stopping display output; stopping touch scanning.

[0009] Optionally, the preset conditions include the clock channel being in a state of LP-00, or the clock channel being in a state of LP-00 for a preset period of time.

[0010] Optionally, the reset pin of the display driver chip is disconnected from the host, so that the display driver chip no longer receives the sent reset command.

[0011] Secondly, this application provides a control system, comprising: a host and a display driver chip; the host is used to send a sleep command; the display driver chip is used to receive the sleep command and monitor the state of the clock channel of the MIPI D-PHY; the host is used to control the state of the clock channel of the MIPI D-PHY to switch from LP-11 to LP-00 to enter an ultra-low power mode; the display driver chip is used to perform a reset operation to reset the display driver chip when the state of the clock channel meets preset conditions; the host is used to control the state of the clock channel of the MIPI D-PHY to switch from LP-11 to LP-10, and then from LP-10 to LP-00 to exit the ultra-low power mode; the display driver chip is used to update the state machine when it detects that the clock channel is in the LP-11 state, so as to be able to process high-speed data subsequently sent by the host.

[0012] Optionally, the reset pin of the display driver chip is open-circuited with the host.

[0013] Thirdly, embodiments of this application provide a control device for a display driver chip. The device includes: a monitoring unit, configured to monitor the state of the clock channel of the MIPI bus in response to receiving a sleep command sent by the host before the MIPI bus enters an ultra-low power mode; a reset unit, configured to perform a reset operation to reset the display driver chip when the state of the clock channel meets preset conditions, and the display driver chip no longer receives or responds to a reset command sent by the host, so that the display driver chip cannot be triggered by the host to perform a reset operation; and an activation unit, configured to, in response to the host changing the state of the clock channel to LP-11 when the MIPI bus exits the ultra-low power mode, the display driver chip identifies the LP-11 state of the clock channel and updates its state machine to be able to process high-speed data subsequently sent by the host.

[0014] Fourthly, embodiments of this application provide an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a control method for a display driver chip as described in the first aspect or any embodiment of the first aspect.

[0015] Optionally, the electronic device is a mobile terminal, the host is an application processor in the mobile terminal, and the display driver chip is used to control the display screen of the mobile terminal; or, the electronic device is a vehicle, the host is a controller in the vehicle, and the display driver chip is used to control the vehicle's in-vehicle screen.

[0016] Fifthly, embodiments of this application also provide a computer-readable storage medium storing an executable program, which is executed by a processor to implement the control method of the display driver chip as described in the first aspect or any embodiment of the first aspect.

[0017] Sixthly, embodiments of this application provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the control method of the display driver chip as described in the first aspect or any embodiment of the first aspect.

[0018] One of the beneficial effects of this application is that by resetting via software before exiting the ultra-low power mode, the system no longer relies on a reset command sent by the host. Thus, even if the LP-11 state of the clock channel briefly appears when exiting the ultra-low power mode, high-speed data can still be received normally afterwards. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the normal process of the related technologies provided in the embodiments of this application.

[0020] Figure 2 This is a schematic diagram of an abnormal process in the related technology provided in the embodiments of this application.

[0021] Figure 3 This is a flowchart illustrating a control system provided in an embodiment of this application.

[0022] Figure 4 This is a flowchart illustrating a control method for a display driver chip provided in this application.

[0023] Figure 5 This is a schematic diagram of the architecture of a control system provided in an embodiment of this application.

[0024] Figure 6This is a schematic diagram of the structure of a control device for a display driver chip provided in an embodiment of this application.

[0025] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0026] Figure 8 This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] The relevant technical background of this application will be introduced below.

[0030] In this application, the host and slave (display driver chip) communicate through the Display Serial Interface (DSI) protocol in the Mobile Industry Processor Interface (MIPI). The physical layer of this communication link adopts the MIPI D-PHY specification, including a clock lane and at least one data lane.

[0031] The MIPI bus includes the MIPI DSI protocol layer and the MIPI D-PHY physical layer.

[0032] The Ultra-Low Power State (ULPS) of the MIPI DSI protocol is a special state of the physical layer. In ULPS, both the clock and data channels are driven as LP-00 (both lines are low).

[0033] ULPS differs from the "Sleep In" command in DCS. The Sleep In command puts the internal functional modules of the display driver chip into sleep mode, while ULPS puts the MIPI bus itself into low-power mode. The two are usually used together: first, a Sleep In command is issued (the MIPI bus is still LP-11), and after the display driver chip goes into sleep mode, the MIPI bus (hereinafter referred to as the bus) is then put into ULPS (LP-00).

[0034] In LP mode, D-PHY defines four basic bus states: LP-00, LP-01, LP-10, and LP-11. These states are determined by the combination of the level levels of the two signal lines in the differential pair. LP-00 indicates that both lines are low, LP-11 indicates that both lines are high, and LP-01 and LP-10 are transitional states with one low and one high level. These states form the underlying physical basis of the MIPI DSI link state machine. The master transmits control information to the slave by driving the bus into different LP states. For example, LP-11 represents the stop state, indicating that the link is idle and ready; LP-00 represents ULPS (Ultra-Low Power State), in which the bus enters an ultra-low power mode. The slave (display control chip or TDDI) can understand the master's control intentions and adjust its own state machine accordingly by continuously monitoring the LP states of the clock channel.

[0035] Specifically, LP-11 represents the "idle-ready" state of the link. When the bus is in LP-11, it indicates that the physical layer has completed initialization or the end of the previous communication, there is no ongoing transmission, and both the master and slave are ready for the next communication. Any normal data transmission (whether in high-speed mode or low-power command transmission) must begin in the LP-11 state; this is a fundamental premise of the protocol state machine.

[0036] Secondly, for the slave device, LP-11 is a necessary condition for the initialization and synchronization of its internal state machine. After a hardware reset or power-on, the chip's MIPI DSI receiver needs to first detect that the clock channel has stabilized at LP-11 before confirming that the link has entered a working state. This is because LP-11 represents the most certain idle level, which the slave device can use as a reference point to calibrate the common-mode level of its internal receiving circuit, clock recovery circuit, and timing reference. If the slave device detects LP-00 (ULPS state) or other transitional states after reset, it means that the bus may still be in a low-power sleep or unknown state. The slave device cannot guarantee the correct sampling of subsequent signals, so the state machine will stagnate and wait until LP-11 appears.

[0037] Finally, LP-11 is also a necessary state after exiting ULPS (Ultra-Low Power State). When the master wakes the bus from LP-00, it must first drive LP-10 (Mark-1) for at least 1ms, and then switch to LP-11. The slave device detects LP-11 and considers the link to be restored, and can continue subsequent communication. Therefore, LP-11 acts as an indication signal for "wake-up complete".

[0038] Please see Figure 1 , Figure 1 This is a schematic diagram of the normal process of the related technologies provided in this application. For example... Figure 1 As shown, the process in the related technology includes steps S01 to S09.

[0039] Step S01: The host sends a sleep command to the display driver chip. At this time, the MIPI bus is in LP-11 state.

[0040] Step S02: The display driver chip performs a sleep operation.

[0041] Step S03: The host puts the MIPI bus into ultra-low power mode and changes the MIPI bus status to LP-00.

[0042] Step S04: The host causes the MIPI bus to exit the ultra-low power mode, and changes the state of the MIPI bus from LP-00 to LP-10, and then to LP-11.

[0043] Step S05: The host sends a reset command.

[0044] Step S06: The display driver chip (slave) performs a reset operation.

[0045] Step S07: The display driver chip (slave) has completed its reset and detected LP-11, indicating that the state machine is functioning normally.

[0046] Step S08: The host sends high-speed data.

[0047] Step S09: The display driver chip (slave) processes high-speed data and displays images normally.

[0048] The above process illustrates the flowchart of how the host normally exits the MIPI bus from the ultra-low power mode in the prior art. It can be seen that after exiting the ultra-low power mode in the normal process, the MIPI bus will remain in the LP-11 state. Then the display driver chip will be reset. After the display driver chip is reset, it detects the LP-11 state of the MIPI bus and updates the state machine normally, so that it can receive high-speed data sent by the host normally.

[0049] Specifically, in the MIPI DSI protocol, high-speed data refers to data transmitted via high-speed mode. This is one of the two main operating modes of the MIPI DSI physical layer (D-PHY); the other is low-power mode.

[0050] However, in practice, it was found that when the host sends high-speed data, the display driver chip cannot immediately display the image normally. Only after the MIPI bus is changed to LP-11 state during the high-speed data transmission process can the display driver chip update the state machine normally and process the subsequent high-speed data, resulting in image loss.

[0051] Therefore, please refer to Figure 2 , Figure 2 This is a schematic diagram of an abnormal process in the related technology provided in the embodiments of this application. For example... Figure 2 As shown, the applicant discovered through research that the abnormal process includes steps S11 to S19.

[0052] Step S11: The host sends a sleep command to the display driver chip. At this time, the MIPI bus is in LP-11 state.

[0053] Step S12: The display driver chip performs a sleep operation.

[0054] Step S13: The host puts the MIPI bus into ultra-low power mode and changes the MIPI bus status to LP-00.

[0055] Step S14: The host causes the MIPI bus to exit the ultra-low power mode, changes the state of the MIPI bus from LP-00 to LP-10, then to LP-11, but finally returns to LP-00.

[0056] Step S15: The host sends a reset command.

[0057] Step S16: The display driver chip (slave) performs a reset operation.

[0058] Step S17: The display driver chip (slave) has completed the reset, but LP-00 is detected, indicating an abnormal state machine.

[0059] Step S18: The host sends high-speed data.

[0060] Step S19: The display driver chip (slave) is unable to process high-speed data properly due to a state machine malfunction, resulting in image loss.

[0061] As shown in steps S11 to S19, the main problem with the abnormal process is in step S14. Although the host changes the state of the MIPI bus from LP-00 to LP-10 and then to LP-11 when exiting the ultra-low power mode according to the standard, the MIPI bus is maintained in LP-11 for a very short time. After the display driver chip (slave) is reset, the MIPI bus has already changed back to the LP-00 state, which causes the display driver chip (slave) to be unable to update the state machine normally, and the high-speed data received subsequently cannot be processed.

[0062] In order to solve such Figure 2 When exiting ultra-low power mode, the MIPI bus did not exhibit the abnormal issue of maintaining LP-11 for an extended period. Please refer to [link / reference]. Figure 3 , Figure 3 This is a flowchart illustrating a control system provided in an embodiment of this application. Figure 3 As shown, the control method for the display driver chip of this application includes steps S21 to S29.

[0063] Step S21: The host sends a sleep command to the display driver chip. At this time, the MIPI bus is in LP-11 state.

[0064] Step S22: The display driver chip performs a sleep operation and determines whether the MIPI bus has entered ultra-low power mode.

[0065] Step S23: The host puts the MIPI bus into ultra-low power mode and changes the MIPI bus status to LP-00.

[0066] Step S24: After the display driver chip determines that the MIPI bus has entered the ultra-low power mode, it performs a reset operation and continuously monitors the clock channel status after the reset is completed.

[0067] Step S25: The host causes the MIPI bus to exit the ultra-low power mode, changes the state of the MIPI bus from LP-00 to LP-10, then to LP-11, but finally returns to LP-00.

[0068] Step S26: When the display driver chip is in the MIPI bus state of LP-11, it successfully detects LP-11, updates the state machine, and can then receive high-speed data normally.

[0069] Step S27: The host sends a reset command, and the display driver chip does not receive or respond to the reset operation.

[0070] Step S28: The host sends high-speed data.

[0071] Step S29: The display driver chip (slave) state machine is normal, and it processes high-speed data and displays images normally.

[0072] Figure 3 The control method shown for the display driver chip is applied to the display driver chip (slave). The slave has a limitation: it cannot change / influence the operation of the master, so the process executed by the master remains unchanged.

[0073] but Figure 3 By performing a reset operation in advance, the system can capture the brief LP-11 state when the MIPI bus exits the ultra-low power mode, thereby updating the state machine. Subsequent reset commands sent by the host will no longer be received or responded to, thus allowing the image to be displayed normally even when the exit from the ultra-low power mode is abnormal.

[0074] The following section provides a detailed description of the execution process of the display driver chip. Please refer to [link / reference needed]. Figure 4 , Figure 4 This is a flowchart illustrating a control method for a display driver chip provided in this application. Figure 4 As shown, the control method 100 for the display driver chip of this application includes steps 110 to 130.

[0075] Step S110: Before the MIPI bus enters the ultra-low power mode, in response to receiving a sleep command sent by the host, monitor the status of the clock channel of the MIPI D-PHY.

[0076] Optionally, step S110 includes steps S111 to S112.

[0077] Step S111: Before the MIPI bus enters ultra-low power mode, in response to receiving a sleep command from the host, perform a sleep operation.

[0078] Step S112: After the hibernation operation is completed, monitor the status of the clock channel of the MIPI D-PHY.

[0079] The above steps prevent the execution time of the hibernation operation from conflicting with the reset operation, thus avoiding incomplete execution, by performing the hibernation operation first and then the reset operation.

[0080] Optionally, the sleep operation includes at least one of the following: stopping display output; stopping touch scanning.

[0081] Step S120: When the state of the clock channel meets the preset conditions, a reset operation is performed to reset the display driver chip, and the display driver chip no longer receives or responds to the reset command sent by the host, so that the display driver chip cannot be triggered by the host to perform a reset operation.

[0082] Specifically, when the display driver chip performs a reset operation, it initiates a series of internal operations to ensure that the chip returns to a known initial state, thereby preparing for subsequent normal communication and display.

[0083] Optionally, the reset operation includes one or more of the following: 1. All configuration registers inside the chip are reset to factory default values. These registers control display timing parameters, gamma correction, touch sensitivity, MIPI interface configuration, power management settings, etc. After the reset, these parameters no longer retain the custom values ​​previously written by the host.

[0084] 2. The internal state machine is forced to zero and return to the initial idle state. Any ongoing operations (such as transmitting image frames or scanning touch points) will be immediately stopped.

[0085] 3. The internal buffers of the chip (such as image frame buffer, command FIFO, touch data buffer) are completely cleared.

[0086] 4. For the MIPI DSI physical layer (D-PHY), the reset operation resets the receiver state, including clearing any detected bus state latches and causing the physical layer to resume monitoring the level states of the clock and data channels (LP-00, LP-01, LP-10, LP-11).

[0087] 5. Clear all unprocessed interrupt flags and disable interrupt output pins to prevent the host from receiving false interrupts. The clock management unit will also be reset, and the internal PLL (phase-locked loop) may be disabled or restored to its default frequency, awaiting host reconfiguration.

[0088] 6. For chips that support multiple power domains, a reset may reset the state of each power domain to the specified power-on sequence.

[0089] 7. In the event of a software reset, selective retention of data in certain critical registers (such as certain security configurations) is permitted.

[0090] In this application, the reset operation is triggered by a hibernation command because this is one of the few, or even the only, commands that the host will send to the slave when entering and exiting the ultra-low power mode. By triggering the reset operation through the hibernation command, the reset can be performed at an appropriate time.

[0091] In this application, the MIPI bus is determined to enter ultra-low power mode by judging whether the state of the clock channel meets the preset conditions. The reset operation is only performed after the MIPI bus enters ultra-low power mode, so that the reset operation and the normal sleep operation can be staggered, and the display driver chip can still enter the sleep mode normally.

[0092] Optionally, the preset conditions include the clock channel being in a state of LP-00, or the clock channel being in a state of LP-00 for a preset period of time.

[0093] For example, the preset time is 1 second.

[0094] Furthermore, to minimize conflicts between hibernation and reset operations, the method also includes: (1) Add a sleep state to the state machine. The sleep state includes the first state representing the sleep operation, the second state representing the sleep operation, and the third state representing the non-sleep operation.

[0095] (2) Upon receiving a hibernation command, update the hibernation state from the third state to the first state.

[0096] (3) When the hibernation operation is completed, update the hibernation state from the first state to the second state.

[0097] (4) When the state of the link initialization state machine is detected to be ready, the sleep state is updated from the second state to the third state.

[0098] The preset conditions also include: detecting that the hibernation state is the second state.

[0099] Step S130: In response to the host changing the state of the clock channel to LP-11 when the MIPI bus exits the ultra-low power mode, the display driver chip identifies the LP-11 state of the clock channel and updates the state machine to be able to process high-speed data subsequently sent by the host.

[0100] According to the MIPI DSI protocol standard, when exiting the ultra-low power mode, the host needs to change the state of the clock channel from LP-00 to LP-10, and then from LP-10 to LP-11. In this application, because the display driver chip performs a reset operation in advance, it does not go through a long hardware reset process. It can immediately and reliably capture this brief LP-11 signal. After capturing LP-11, the state machine of the display driver chip is correctly activated, and then it can seamlessly receive high-speed image data sent by the host, completely solving the problem of image loss after wake-up.

[0101] Among them, the state machine of the display driver chip is usually called the link initialization state machine. Its core responsibility is to coordinate the startup and synchronization of the MIPI D-PHY physical layer and ensure that the physical layers of the master and slave can reach a consensus.

[0102] In order to prevent the display driver chip from receiving / responding to reset operations sent by the host in subsequent implementations, in one possible implementation, the reset pin of the display driver chip is disconnected from the host, so that the display driver chip no longer receives hardware reset commands.

[0103] Specifically, by modifying the hardware design, the connection between the reset (RST) pin of the display driver chip and the host is disconnected, and the RST pin of the display driver chip is fixed at a high level (the display driver chip internally recognizes a high level as a normal working state), so that the display driver chip no longer responds to the hardware RST command issued by the host.

[0104] Optionally, the display driver chip in this application includes a display controller integrated circuit (DDIC) without touch functionality and a touch and display driver integration chip (TDDI). The sole responsibility of the display control chip is to drive the display panel. It receives image data and display control commands from the host computer (such as the application processor in a mobile phone or the cockpit domain controller in a vehicle) via the MIPI DSI interface. Internally, it includes source drivers, gate drivers, a gamma voltage generator, timing control logic, and a frame buffer. When the display driver chip performs a reset operation, all display-related registers are reset to their default values, the timing state machine is returned to zero, the output driver is turned off, and the screen is turned off. When performing a sleep operation, it completes the current frame scan, turns off the display output, retains the register configuration for quick wake-up, and shuts down the high-voltage circuitry to reduce power consumption. It does not handle any touch functionality; therefore, the touch portion is handled by a separate touch chip, and the two are physically separated.

[0105] The touch and display driver integrated chip integrates both display driving and touch control functions into a single chip. In the display driving section, its internal architecture is similar to that of a dedicated display driver chip, containing a complete display output control chain. In the touch section, it integrates touch scanning control, touch signal acquisition and processing, coordinate calculation, and other functions. The TDDI contains two independent subsystems—a display subsystem and a touch subsystem—which share some resources (such as power management and clock) but each has its own independent state machine. During a reset operation, the TDDI needs to reset not only the registers, state machine, and output driver of the display section but also the scanning state, buffer, and interrupt flags of the touch section, ensuring that both subsystems return to their initial states synchronously. During a sleep operation, the TDDI needs to coordinate the shutdown of the display subsystem's output and the cessation of the touch subsystem's scanning. Typically, it first stops touch scanning, then shuts down the display output, and finally enters a unified low-power mode. The advantages of the TDDI are saving board space, reducing overall cost, reducing signal interference, and facilitating timing coordination between display and touch. Unlike display driver chips, TDDI and the host typically communicate via I2C or SPI interfaces in addition to the MIPI DSI interface for display communication, or by using the bidirectional channel in the MIPI DSI protocol to send touch data back to the host.

[0106] If the solution of this application is applied to a mobile phone, the host is the application processor (AP) in the mobile phone, and the display driver chip is the TDDI chip that controls the mobile phone display screen.

[0107] Please see Figure 5 , Figure 5 This is a schematic diagram of the architecture of a control system provided in an embodiment of this application. Figure 5 As shown, the control system 1000 includes a host 1100 and a display driver chip 1200.

[0108] The host 1100 is used to send hibernation commands.

[0109] The display driver chip 1200 is used to receive the sleep command and monitor the status of the clock channel of the MIPI D-PHY.

[0110] The host 1100 is used to control the state of the clock channel of the MIPI D-PHY to switch from LP-11 to LP-00 in order to enter the ultra-low power mode.

[0111] The display driver chip 1200 is used to perform a reset operation to reset the display driver chip 1200 when the state of the clock channel meets the preset conditions.

[0112] The host 1100 is used to control the state of the clock channel of the MIPI D-PHY to switch from LP-11 to LP-10, and then from LP-10 to LP-00, so as to exit the ultra-low power mode.

[0113] The display driver chip 1200 is used to update the state machine when the clock channel is identified as being in the LP-11 state, so as to be able to process the high-speed data subsequently sent by the host 1100.

[0114] Optionally, the reset pin of the display driver chip is open-circuited with the host.

[0115] For specific details of each step, please refer to [link / reference]. Figures 1 to 4 The description in the text will not be repeated here.

[0116] Optionally, the mobile terminal includes the control system described above, the host is the application processor in the mobile terminal, and the display driver chip is used to control the display screen of the mobile terminal.

[0117] For example, the mobile terminal can be a mobile phone, tablet, smartwatch, etc., and this application does not impose any restrictions.

[0118] Optionally, the vehicle includes the control system described above, the host being the controller in the vehicle, and the display driver chip being used to control the vehicle's in-vehicle screen.

[0119] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a control device for a display driver chip provided in an embodiment of this application. Figure 6 As shown, the control device 200 for the display driver chip includes a monitoring unit 210, a reset unit 220, and an activation unit 230.

[0120] The monitoring unit 210 is used to monitor the status of the clock channel of the MIPI D-PHY in response to receiving a sleep command sent by the host before the MIPI bus enters the ultra-low power mode.

[0121] The reset unit 220 is used to perform a reset operation to reset the display driver chip when the state of the clock channel meets the preset conditions, and the display driver chip no longer receives or responds to the reset command sent by the host, so that the display driver chip cannot be triggered by the host to perform a reset operation.

[0122] The activation unit 230 is used to respond to the situation where the host changes the state of the clock channel to LP-11 when the MIPI bus exits the ultra-low power mode. The display driver chip recognizes the LP-11 state of the clock channel and updates the state machine to be able to process high-speed data subsequently sent by the host.

[0123] Optionally, the monitoring unit 210 is specifically used to: perform a sleep operation in response to receiving a sleep command sent by the host before the MIPI bus enters the ultra-low power mode; and monitor the status of the clock channel of the MIPI D-PHY after the sleep operation is completed.

[0124] Optionally, the display driver chip is an integrated touch and display driver chip.

[0125] Optionally, the sleep operation includes at least one of the following: stopping display output; stopping touch scanning.

[0126] Optionally, the preset conditions include the clock channel being in a state of LP-00, or the clock channel being in a state of LP-00 for a preset period of time.

[0127] Optionally, the reset pin of the display driver chip is disconnected from the host, so that the display driver chip no longer receives the sent reset command.

[0128] Please refer to the following: Figure 7 , Figure 7This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 7 As shown, the electronic device 300 includes: one or more processors 310 and a memory 320. Figure 7 Take the 310 processor as an example.

[0129] Optionally, the processor 310 and the memory 320 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0130] Optionally, the processor 310 is configured to, before the MIPI bus enters ultra-low power mode, in response to receiving a sleep command sent by the host, monitor the state of the clock channel of the MIPI D-PHY; if the state of the clock channel meets preset conditions, perform a reset operation to reset the display driver chip, and the display driver chip no longer receives or responds to the reset command sent by the host, so that the display driver chip cannot be triggered by the host to perform a reset operation; in response to the host changing the state of the clock channel to LP-11 when the MIPI bus exits the ultra-low power mode, the display driver chip identifies the LP-11 state of the clock channel and updates the state machine to be able to process high-speed data subsequently sent by the host.

[0131] Optionally, the memory 320, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules of the control method for the display driver chip in the embodiments of this application. The processor 310 executes various functional applications and data processing of the electronic device by running the non-volatile software programs, instructions, and modules stored in the memory 320, thereby implementing the control method for the display driver chip in the above method embodiments.

[0132] Optionally, the memory 320 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the breast pump, etc. Furthermore, the memory 320 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 320 may optionally include memory remotely located relative to the processor 310, and these remote memories may be connected to the controller via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0133] Optionally, one or more modules are stored in memory 320, and when executed by one or more processors 310, they execute the control method of the display driver chip in any of the above method embodiments, for example, executing the above-described... Figure 4 Steps 110 to 130 of the method.

[0134] Please refer to Figure 8 , Figure 8 This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. The computer-readable storage medium 400 stores program code 410, which can be called by a processor to execute the control method of the display driver chip described in the above method embodiments.

[0135] The computer-readable storage medium 400 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium includes a non-volatile computer-readable medium. The computer-readable storage medium 400 has storage space for program code that performs any of the method steps of the control method described above. This program code can be read from or written to one or more computer program products. The program code may, for example, be compressed in a suitable form.

[0136] This application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the control method for the display driver chip in any of the above method embodiments.

[0137] In summary, this application provides a control method and related equipment for a display driver chip. The method includes: before the MIPI bus enters ultra-low power mode, in response to receiving a sleep command sent by the host, monitoring the state of the clock channel of the MIPI D-PHY; if the state of the clock channel meets preset conditions, performing a reset operation to reset the display driver chip, and the display driver chip no longer receives or responds to reset commands sent by the host, so that the display driver chip cannot be triggered by the host to perform a reset operation. By resetting via software before exiting ultra-low power mode, it no longer relies on a reset command sent by the host, so that even if the LP-11 state of the clock channel briefly appears when exiting ultra-low power mode, high-speed data can still be received normally afterwards.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A control method for a display driver chip, characterized in that, The method includes: Before the MIPI bus enters ultra-low power mode, it monitors the status of the clock channel of the MIPI D-PHY in response to the sleep command sent by the host. When the state of the clock channel meets the preset conditions, a reset operation is performed to reset the display driver chip, and the display driver chip no longer receives or responds to the reset command sent by the host, so that the display driver chip cannot be triggered by the host to perform a reset operation. In response to the host changing the state of the clock channel to LP-11 when the MIPI bus exits the ultra-low power mode, the display driver chip identifies the LP-11 state of the clock channel and updates the state machine to be able to process high-speed data subsequently sent by the host.

2. The control method for the display driver chip according to claim 1, characterized in that, Before the MIPI bus enters ultra-low power mode, in response to receiving a sleep command from the host, the status of the MIPI D-PHY clock channel is monitored, including: Before the MIPI bus enters ultra-low power mode, it performs a sleep operation in response to receiving a sleep command from the host; After the hibernation operation is completed, monitor the status of the clock channel of the MIPI D-PHY.

3. The method according to claim 1 or 2, characterized in that, The host is the application processor in the mobile phone, and the display driver chip is an integrated touch and display driver chip.

4. The control method for the display driver chip according to claim 3, characterized in that, The hibernation operation includes at least one of the following: Stop displaying output; Stop touch scanning.

5. The control method for the display driver chip according to claim 1, characterized in that, The preset conditions include the clock channel being in the state of LP-00, or the clock channel being in the state of LP-00 for a preset period of time.

6. The control method for the display driver chip according to claim 1, characterized in that, The reset pin of the display driver chip is disconnected from the host, so that the display driver chip no longer receives the sent reset command.

7. A control system, characterized in that, The control system includes: a host computer and a display driver chip; The host is used to send hibernation commands; The display driver chip is used to receive the sleep command and monitor the status of the clock channel of the MIPI D-PHY; The host is used to control the state of the clock channel of the MIPI D-PHY to switch from LP-11 to LP-00 in order to enter the ultra-low power mode; The display driver chip is used to perform a reset operation to reset the display driver chip when the state of the clock channel meets the preset conditions; The host is used to control the state of the clock channel of the MIPI D-PHY to switch from LP-11 to LP-10, and then from LP-10 to LP-00, so as to exit the ultra-low power mode; The display driver chip is used to update the state machine when the clock channel is identified as being in the LP-11 state, so as to be able to process high-speed data subsequently sent by the host.

8. The control system according to claim 7, characterized in that, The reset pin of the display driver chip is open from the host.

9. A control device for a display driver chip, characterized in that, The device includes: The monitoring unit is used to monitor the status of the clock channel of the MIPI D-PHY in response to a sleep command sent by the host before the MIPI bus enters the ultra-low power mode. The reset unit is used to perform a reset operation to reset the display driver chip when the state of the clock channel meets the preset conditions, and the display driver chip no longer receives or responds to the reset command sent by the host, so that the display driver chip cannot be triggered by the host to perform a reset operation. An activation unit is used to respond to the situation where the host changes the state of the clock channel to LP-11 when the MIPI bus exits the ultra-low power mode. The display driver chip recognizes the LP-11 state of the clock channel and updates the state machine to be able to process high-speed data subsequently sent by the host.

10. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the control method of the display driver chip as described in any one of claims 1 to 6.

11. The electronic device according to claim 10, characterized in that, The electronic device is a mobile terminal, the host is an application processor in the mobile terminal, and the display driver chip is used to control the display screen of the mobile terminal; or, The electronic device is a vehicle, the host is a controller in the vehicle, and the display driver chip is used to control the vehicle's in-vehicle screen.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an executable program, which is executed by a processor to implement the control method of the display driver chip as described in any one of claims 1 to 6.

13. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the control method for the display driver chip as described in any one of claims 1 to 6.

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