Miniaturized ultra-wideband time delay device and digital control time delay system
By employing a design with opposite winding directions in the all-through network sub-unit, combined with spiral inductor and capacitor connections, the problem of time delay accuracy degradation in the high-frequency band is solved, realizing a miniaturized and highly reliable ultra-wideband time delay.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
- Filing Date
- 2026-03-25
- Publication Date
- 2026-07-07
AI Technical Summary
Existing time delayers based on coupled all-pass networks suffer from deteriorated delay accuracy at Ku-band and above frequencies, and traditional methods increase circuit area and process complexity, affecting reliability.
By employing all-through network sub-units with opposite winding directions to reduce inter-unit coupling, and combining the connection method of spiral inductors and capacitors, a mutual inductance coefficient is formed to broaden the bandwidth and achieve phase lag, thus designing a miniaturized ultrawideband delay timer.
It improves delay accuracy, reduces circuit area, lowers process complexity, and achieves miniaturization and high reliability of ultra-wideband delayers, making them suitable for beam control circuits.
Smart Images
Figure CN122348735A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic communications, specifically relating to a miniaturized ultrawideband delay device and a numerically controlled delay system. Background Technology
[0002] For long-wavelength time delay design, existing time delay structures based on coupled all-pass networks consist of a single, repeating all-pass sub-unit. In the Ku band and above, due to the inherent characteristics of the unit and harmful mutual coupling between units, the time delay accuracy deteriorates significantly. Currently, to address this degradation, shielded ground vias are often added between units to isolate some electromagnetic coupling. However, the effect is generally limited and it increases the circuit area. Large-area ground via designs place higher demands on manufacturing processes and increase reliability risks. Summary of the Invention
[0003] Purpose of the invention: The purpose of this invention is to provide a miniaturized ultrawideband delay device with a simple circuit topology, high process reliability, and high delay accuracy.
[0004] Another object of the present invention is to provide a numerically controlled delay system based on the miniaturized ultrawideband delayer.
[0005] Technical solution: To achieve the above objective, the present invention provides a miniaturized ultrawideband delayer, comprising a plurality of all-pass network sub-units connected in series, wherein at least two adjacent all-pass network sub-units have coupling inductor windings in opposite directions.
[0006] Another miniaturized ultrawideband delay device of the present invention includes a plurality of all-pass network sub-units connected in series in sequence, wherein the plurality of all-pass network sub-units are divided into at least two groups, the winding direction of the coupling inductor of the all-pass network sub-units within the group is the same, and the winding direction of the coupling inductor of the all-pass network sub-units between the groups is opposite.
[0007] Another miniaturized ultrawideband delay device of the present invention includes several all-pass network sub-units connected in series, wherein the winding directions of the coupling inductors of any two adjacent all-pass network sub-units are opposite.
[0008] Preferably, the all-through network subunit includes a first capacitive element, a second capacitive element, a first spiral inductor, and a second spiral inductor. Within each all-through network subunit, the first spiral inductor and the second spiral inductor are intertwined. The beginning of the first spiral inductor and the beginning of the second spiral inductor are connected through the first capacitive element, and the end of the first spiral inductor and the end of the second spiral inductor are connected. The connection point is grounded through the second capacitive element.
[0009] Preferably, the all-pass network subunit is an LC low-pass network unit or a transmission line unit.
[0010] Preferably, the plurality of sequentially connected all-through network sub-units are arranged in a straight line, a serpentine line, a ring, or an irregular line in physical space.
[0011] Preferably, capacitive, inductive, or resistive elements for adjustment and matching are connected in series or in parallel within or between the all-through network sub-units, and signal shielding grounding vias are added between the units.
[0012] Preferably, the first capacitive element is a physical capacitor, a distributed capacitor, or is formed by capacitive coupling between a first spiral inductor and a second spiral inductor.
[0013] Preferably, the second capacitive element is a physical capacitor, distributed capacitance, or parasitic capacitance.
[0014] Preferably, the winding shape of the first spiral inductor and the second spiral inductor includes: a zigzag shape, a square shape, a polygonal shape, or a circle.
[0015] Preferably, the coupling coefficients of the first spiral inductor and the second spiral inductor in each of the all-through network sub-units are 0.
[0016] The present invention relates to a numerically controlled delay system based on the ultra-wideband delayer, comprising a reference state module, an input single-pole double-throw switch module, and an output single-pole double-throw switch. The ultra-wideband delayer serves as the delay state module and is connected in parallel with the reference state module between the input single-pole double-throw switch module and the output single-pole double-throw switch.
[0017] Beneficial effects: The present invention has the following advantages:
[0018] 1. Based on a time delay unit using all-pass network sub-units, this invention weakens harmful coupling between adjacent units by introducing at least one pair of mutually coupled spiral inductors with all-pass network sub-units using opposite winding directions, thereby improving the time delay accuracy of the time delay unit in an ultra-wideband range. At the same time, the spacing between all-pass network sub-units with opposite winding directions is reduced, resulting in a compact overall structure, reduced circuit area, and miniaturization. Furthermore, no ground vias are required between all-pass network sub-units, ensuring high reliability.
[0019] 2. The miniaturized ultra-wideband delay circuit of this invention has good standing wave characteristics, small delay ripple, small insertion loss and parasitic amplitude modulation in the ultra-wideband frequency range, and can be widely used as a beam control circuit in broadband phased array systems.
[0020] 3. The numerically controlled delay system based on the miniaturized ultra-wideband delayer achieves multi-bit delay control through path selection. Attached Figure Description
[0021] Figure 1This is a circuit diagram of the miniaturized ultrawideband delayer in Embodiment 1 of the present invention;
[0022] Figure 2 This is a circuit topology diagram of the miniaturized ultrawideband delayer in Embodiment 2 of the present invention;
[0023] Figure 3 This is a comparison chart of the delay accuracy test curves of the miniaturized ultrawideband delayer of Embodiment 2 of the present invention and the traditional structure;
[0024] Figure 4 This is a circuit topology diagram of the miniaturized ultrawideband delayer in Embodiment 3 of the present invention;
[0025] Figure 5 This is a circuit topology diagram of the miniaturized ultrawideband delayer in Embodiment 4 of the present invention;
[0026] Figure 6 This is a circuit topology diagram of the miniaturized ultrawideband delayer in Embodiment 5 of the present invention;
[0027] Figure 7 This is a circuit topology diagram of the miniaturized ultrawideband delayer in Embodiment 6 of the present invention;
[0028] Figure 8 This is a circuit block diagram of the numerical control delay system in Embodiment 7 of the present invention.
[0029] Figure 9 This is a graph showing the 320ps bit group delay of the numerical control delay system operating at f0GHz-9*f0GHz numerical control delay timer as a function of frequency in Embodiment 7 of the present invention. Detailed Implementation
[0030] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading this invention, any modifications of the invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.
[0031] Example 1
[0032] This embodiment provides a miniaturized ultra-wideband delay device, comprising n (n≥2) sequentially connected all-pass network subunits APN1...APN. m APN m+1 ...APN nEach all-pass network subunit includes a first capacitor CS, a second capacitor CP, and a first spiral inductor LS1 and a second spiral inductor LS2 (by convention, in actual physical spatial layout, the spiral inductor closest to the input end of each all-pass network subunit is designated as the first spiral inductor LS1). The first and second spiral inductors of each unit are intertwined to form a mutual inductance coefficient k to broaden the bandwidth and achieve phase lag. The beginning ends of the first and second spiral inductors of each unit are connected through the first capacitor CS, and the ends of the first and second spiral inductors are connected to each other, with the connection point grounded through the second capacitor CP. Among the n all-pass network subunits, at least two adjacent subunits have coupling inductors with opposite winding directions.
[0033] With two adjacent subunits (APN) m APN m+1 Taking the case where the winding direction of the coupled inductor is opposite, for example, Figure 1 As shown, the structure of the ultra-wideband delayer in this embodiment is as follows: the input terminal of the first all-pass network subunit APN1 is connected to the input terminal of the circuit, and the output terminal of APN1 is sequentially connected in series to the (m-1)th all-pass network subunit APN. m-1 The input terminal of the (m-1)th unit is connected to the output terminal of the m-th all-pass network subunit APN. m First spiral inductor LS1 m The first end, the all-connection network subunit APN m The second spiral inductor LS2 m The first end is connected to the (m+1)th all-pass network subunit APN. m+1 The second spiral inductor LS2 m+1 The first end, the all-connection network subunit APN m+1 First spiral inductor LS1 m+1 The first end is connected to the input end of the (m+2)th all-pass network subunit, and the all-pass network subunit APN... m+2 The output terminals are connected in series to the input terminals of the nth all-pass network sub-unit, and the output terminal of the nth all-pass network sub-unit is connected to the output terminal of the circuit.
[0034] In this embodiment, among the n all-pass network sub-units of the ultra-wideband delayer, at least two adjacent sub-units APN are present. m With APN m+1 Spiral inductor LP1 m LP2 m With LP1 m+1 LP2 m+1With the winding direction reversed, the resulting coupled magnetic field direction is reversed, the harmful coupling between units is reduced, the dispersion of the time delay is reduced, and high-precision time delay performance is achieved. At the same time, the unit spacing is reduced, realizing the miniaturization design of the circuit.
[0035] Example 2
[0036] This embodiment provides another possible circuit layout for a broadband delayer, such as... Figure 2 As shown, the structure of the ultra-wideband delay device in this embodiment is as follows: it includes n fully connected network sub-units APN1...APN connected in series. m APN m+1 ...APN n Each all-pass network subunit includes a first capacitor CS, a second capacitor CP, a first spiral inductor LS1, and a second spiral inductor LS2. The first and second spiral inductors in each unit are intertwined to form a mutual inductance coefficient k to broaden the bandwidth and achieve phase lag. The beginning of the first spiral inductor and the beginning of the second spiral inductor in each unit are connected through the first capacitor CS, and the end of the first spiral inductor is connected to the end of the second spiral inductor. The connection is grounded through the second capacitor CP. The spiral inductors of adjacent all-pass network subunits are wound in opposite directions. Figure 2 The direction of the middle arrow represents the signal flow. It can be seen that the signal flow between adjacent units is opposite, and the induced magnetic field generated by them cancels each other out to a certain extent, weakening the harmful mutual coupling between units, improving the time delay accuracy, and effectively reducing the unit spacing, thus realizing the miniaturization of the circuit.
[0037] like Figure 3 The figure shows a comparison of the delay accuracy between the broadband delay device described in this embodiment and the traditional delay structure. In the figure, the group delay flatness of the ultra-wideband delay device in the frequency range of f0GHz-9*f0GHz implemented using the traditional delay structure is about 1.8ps, while the group delay flatness of the ultra-wideband delay device in the frequency range of f0GHz-9*f0GHz implemented using the broadband delay device described in this embodiment is less than 0.3ps, thus improving the delay accuracy. At the same time, the area of the delay device is reduced by 30%.
[0038] Example 3
[0039] This embodiment provides another possible circuit layout for a broadband delayer, such as... Figure 4 As shown, the structure of the ultra-wideband delay device in this embodiment is as follows: it includes n fully connected network sub-units APN1...APN connected in series. m APN m+1 ...APN nEach all-pass network sub-unit includes a first capacitor CS, a second capacitor CP, a first spiral inductor LS1, and a second spiral inductor LS2. The first and second spiral inductors in each unit are intertwined to form a mutual inductance coefficient k to broaden the bandwidth and achieve phase lag. The beginning of the first spiral inductor and the beginning of the second spiral inductor in each unit are connected through the first capacitor CS, and the end of the first spiral inductor is connected to the end of the second spiral inductor. The connection is grounded through the second capacitor CP. The n all-pass network sub-units are divided into at least two groups. The winding direction of the coupling inductors in the sub-units within the same group is the same, and the winding direction of the coupling inductors in the sub-units between groups is opposite.
[0040] The broadband delay device structure provided in this embodiment can achieve improved delay accuracy and reduced layout area compared to traditional structures. Furthermore, capacitive, inductive, and resistive components can be connected in series or parallel between or within cells to adjust the matching, thereby obtaining better performance.
[0041] Example 4
[0042] like Figure 5 As shown, based on the ultra-wideband delayer structure provided in Embodiment 1, when the coupling coefficient K between the first and second spiral inductors of each unit is 0 and the first capacitor is 0, the unit degenerates into a low-pass network unit. At this time, the adjacent units adopt opposite winding directions, which can still improve the delay accuracy.
[0043] Example 5
[0044] like Figure 6 As shown, based on the ultra-wideband delayer structure provided in Embodiment 1, when the coupling coefficient K between the first and second spiral inductors of each unit is 0, and the first capacitor and the second capacitor are both 0, the unit degenerates into a transmission line unit.
[0045] Example 6,
[0046] like Figure 7 As shown, based on the ultra-wideband delayer structure provided in Embodiment 2, the n all-pass network sub-units are connected in series in sequence, and adjacent sub-units adopt opposite coupling inductor winding directions. The n all-pass network sub-units are arranged in a zigzag shape in physical space, and can also be flexibly arranged into a straight line, serpentine line, ring or irregular line according to specific needs.
[0047] Example 7
[0048] like Figure 8 As shown, the ultra-wideband time delay device structure provided in Example 1 is used as a time delay state module, combined with a single-pole double-throw switch and a reference state module. The input and output signals are connected to the common terminal of the single-pole double-throw switch. The path selection between the reference state and the time delay state is realized by switching on and off, thereby realizing the numerical control time delay function.
[0049] The delay device described in this embodiment is fabricated using the gallium arsenide pHEMT process, such as... Figure 9 The figure shows the actual test results of a large wavelength 320ps delayer in an ultra-wide frequency range of f0GHz-9*f0GHz. It can be seen that high-precision delay effect is achieved in an ultra-wide frequency range, with a group delay error of only ±2.5ps, and the actual layout area is reduced by 30% compared with the traditional structure.
Claims
1. A miniaturized ultrawideband delay timer, characterized in that, It includes several fully connected network sub-units in series, wherein at least two adjacent fully connected network sub-units have their coupled inductor windings in opposite directions.
2. A miniaturized ultrawideband delay timer, characterized in that, It includes several fully connected in series sub-units of a network, wherein the several fully connected in series sub-units are divided into at least two groups, the winding direction of the coupled inductor of the fully connected inductor of the fully connected inductor of the group is the same, and the winding direction of the coupled inductor of the fully connected inductor of the group is opposite.
3. A miniaturized ultrawideband delay timer, characterized in that, It includes several fully connected network sub-units in series, wherein the winding directions of the coupled inductors of any two adjacent fully connected network sub-units are opposite.
4. The ultra-wideband delayer according to any one of claims 1 to 3, characterized in that, The all-through network subunit includes a first capacitive element, a second capacitive element, a first spiral inductor, and a second spiral inductor. Within each all-through network subunit, the first spiral inductor and the second spiral inductor are intertwined. The beginning of the first spiral inductor and the beginning of the second spiral inductor are connected through the first capacitive element, and the end of the first spiral inductor and the end of the second spiral inductor are connected. The connection point is grounded through the second capacitive element.
5. The ultra-wideband delayer according to any one of claims 1 to 3, characterized in that, The all-pass network subunit is an LC low-pass network unit or a transmission line unit.
6. The ultra-wideband delayer according to any one of claims 1 to 3, characterized in that, The several interconnected network sub-units are arranged in a linear, serpentine, circular, or irregular shape in physical space.
7. The ultra-wideband delayer according to claim 4, characterized in that, Within or between the sub-units of the all-through network, capacitive, inductive, or resistive elements for adjustment and matching are connected in series or in parallel, and signal shielding grounding vias are added between the units.
8. The ultra-wideband delayer according to claim 4, characterized in that, The first capacitive element is a physical capacitor, a distributed capacitor, or is formed by capacitive coupling between a first spiral inductor and a second spiral inductor.
9. The ultra-wideband delayer according to claim 4, characterized in that, The second capacitive element is a physical capacitor, distributed capacitance, or parasitic capacitance.
10. The ultra-wideband delayer according to claim 4, characterized in that, The winding shapes of the first spiral inductor and the second spiral inductor include: zigzag, square, polygonal, or circular.
11. The ultra-wideband delayer according to claim 4, characterized in that, The coupling coefficients of the first spiral inductor and the second spiral inductor in each of the all-through network sub-units are 0.
12. A numerically controlled delay system using the ultra-wideband delayer according to any one of claims 1 to 3, characterized in that, The numerical control delay system includes a reference state module, an input single-pole double-throw switch module, and an output single-pole double-throw switch. The ultra-wideband delayer serves as the delay state module and is connected in parallel with the reference state module between the input single-pole double-throw switch module and the output single-pole double-throw switch.