Passwordless transceiver jitter mitigation

Abstract

A system includes a crystal oscillator, a central switch transceiver coupled to the crystal oscillator, and a sensor transceiver. The central switch transceiver includes transmitter circuitry to generate a self- clocked signal carrying first data using a timing reference from the crystal oscillator, and clock and data recovery loop circuitry to operate at a first bandwidth to sample second data received from the sensor transceiver. The sensor transceiver includes reference clock recovery circuitry to decode a reference clock from the self- clocked signal. A phase-locked loop (PLL) circuit generates a transmission clock operating at a second bandwidth from the reference clock for generating the second data. The first bandwidth is greater than or equal to the second bandwidth of the PLL circuit to mitigate jitter experienced by the clock and data recovery loop circuitry due to jitter in the transmission clock.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Application No. 63 / 742,720, filed January 7, 2025, entitled “Method to Combat Jitter in Asymmetric Crystal Less Wire Line Transceiver,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to electronic data transmission systems over wired media, and more specifically to mitigating jitter in crystalless transceiver pairs, wherein one transceiver operates without a crystal timing reference. Background Technology

[0003] High-speed data communication systems typically employ transceivers that rely on crystal oscillators to provide a stable and accurate timing reference for data transmission and reception. Crystal oscillators are favored due to their high quality and ability to generate low-jitter clock signals that enable reliable high-frequency operation. In some transceiver designs, each transceiver includes its own crystal oscillator to maintain independent timing control and minimize dependence on external timing sources.

[0004] In many modern applications, such as automotive sensor networks, multiple sensor devices are distributed throughout the system and communicate with a central processing unit or switch. These applications often involve asymmetric data transmission requirements, where data rates differ significantly between the uplink and downlink directions. For example, sensor devices may need to send large amounts of high-rate sensor data to the central unit while simultaneously receiving relatively low-rate control or configuration data.

[0005] Including a separate crystal oscillator in each sensor device can present challenges in terms of cost, complexity, and reliability. Crystal components increase the cost of each sensor unit, and their mechanical properties can introduce potential points of failure in harsh operating environments. Furthermore, maintaining synchronization across multiple independent crystal-based timing sources can introduce system-level complexity.

[0006] To address these challenges, crystal-free transceiver architectures have been developed, in which one transceiver in a communication pair operates without a local crystal oscillator. In such systems, timing information is transmitted from the crystal-equipped transceiver to the crystal-free transceiver via a self-clocking signaling scheme, such as Manchester encoding, which embeds the clock information within the transmitted data stream. However, recovering or extracting the reference clock from the self-clocking signal often results in significant jitter that can propagate in the communication signal carrying sensor data back to the crystal-based transceiver. Attached Figure Description

[0007] Refer to the following figures to describe non-restrictive and non-exhaustive examples.

[0008] Figure 1 This is a block diagram of a system for reducing jitter in data communication between a central switch and multiple sensors, according to some embodiments.

[0009] Figure 2 This is a block diagram of a central switch transceiver in a communication system according to some embodiments.

[0010] Figure 3A A block diagram of a sensor transceiver in a crystalless configuration according to some embodiments is shown.

[0011] Figure 3B According to some embodiments Figure 3A A block diagram of a phase-locked loop (PLL) circuit.

[0012] Figure 3C This is an example of a reference clock recovery circuit configured to extract a reference clock from a Manchester-encoded signal, according to some embodiments.

[0013] Figure 4 It is a graph showing the PLL output jitter (measured and estimated) for various PLL reference clock input jitter and PLL loop bandwidth according to some embodiments.

[0014] Figure 5 It is a graph showing the relationship between reference jitter and residual jitter for various PLL and CDR bandwidths according to some embodiments.

[0015] Figure 6 A flowchart is depicted illustrating a method for mitigating jitter in a crystalless wired transceiver according to some embodiments. Detailed Implementation

[0016] The following description illustrates exemplary aspects of this disclosure. However, it should be understood that this description is not intended to limit the scope of this disclosure. Rather, the description includes combinations and modifications of those exemplary aspects described herein.

[0017] As discussed, recovering or extracting a reference clock from a timer signal typically results in significant jitter that can propagate through the communication signal sent back to a crystal-based transceiver. For example, recovering timing information from a timer signal can introduce timing uncertainties and jitter, potentially degrading system performance. The recovered clock signal typically exhibits greater jitter compared to a signal generated directly from a crystal oscillator. For instance, when this jittered reference clock is used to generate a high-frequency transmission clock via a phase-locked loop circuit, the jitter can propagate and affect the quality of the transmitted signal. The receiving or central exchange transceiver must then track and compensate for this jitter to maintain reliable data recovery, thus posing a challenge to maintaining an acceptable signal-to-noise ratio (SNR) in high-speed communication links.

[0018] This disclosure describes aspects, systems, and methods for mitigating jitter in crystal-less wired transceivers, which may be more apparent, and also for mitigating other drawbacks that are obvious to those skilled in the art. In such a system, a central switch may include a central switch transceiver and a common crystal oscillator coupled to the central switch transceiver. The common crystal oscillator may generate a timing reference, such as a reference clock. The central switch transceiver may generate a self-timing signal carrying the reference clock and data generated by the crystal oscillator. Each central switch transceiver may communicate with sensor transceivers operating without separate crystal oscillators, thereby reducing costs and improving reliability in applications such as automotive sensor networks.

[0019] Each central switch transceiver may include a clock and data recovery (CDR) loop circuit configured to operate at a first bandwidth to sample data received from the sensor transceiver. The CDR loop circuit can recover high-data-rate information transmitted by the sensor transceiver using a corresponding transmission clock generated by its phase-locked loop (PLL) circuit. The first bandwidth of the CDR loop determines its ability to track and compensate for timing variations in the signal received from the sensor transceiver.

[0020] The sensor transceiver in this system may include a reference clock recovery circuit configured to extract a reference clock from a self-timing signal received from a central switch transceiver. The self-timing signal may carry timing information embedded in the data transmission, enabling the sensor transceiver to derive a timing reference without using a local crystal oscillator. The reference clock recovery circuit can decode the timing information from the self-timing signal to generate the reference clock.

[0021] The sensor transceiver may also include a PLL circuit configured to generate a high-frequency transmission clock from a reference clock. The PLL circuit can use the reference clock as input to generate a higher-frequency clock signal (also referred to herein as the transmission clock) suitable for high-data-rate transmission back to the central switch transceiver. The PLL circuit may have a second bandwidth that affects how the PLL circuit responds to jitter present in the reference clock signal and how the CDR loop circuit can track the jitter to accurately decode data from high-data-rate transmissions.

[0022] In some embodiments, the first bandwidth of the CDR loop circuit is configured to be greater than or equal to the second bandwidth of the PLL circuit to mitigate jitter experienced by the CDR loop circuit. This bandwidth relationship enables the central switch transceiver to effectively track and compensate for jitter originating from the PLL circuit of the sensor transceiver. When the PLL circuit operates at a lower bandwidth relative to the first bandwidth, the jitter spectrum may be constrained to a lower frequency, at which the higher bandwidth CDR loop circuit may be able to track without reducing the signal-to-noise ratio.

[0023] A central switch transceiver can operate as a system component using a common crystal oscillator configured to generate a timing reference and transmitter circuitry configured to use that timing reference to generate a self-timing signal carrying low data rate information. The central switch transceiver may also include receiver circuitry that includes a CDR loop circuitry configured to operate at a first bandwidth to recover high data rate information from a sensor transceiver. In some embodiments, asymmetric data rates enable efficient communication, wherein low data rate control information flows from the central switch transceiver to the sensor transceiver, while high data rate sensor information and data flow from the sensor transceiver back to the central switch transceiver.

[0024] The sensor transceiver can operate as a system component including a reference clock recovery circuit configured to extract a reference clock from a self-timing signal received from a central switch transceiver. The sensor transceiver may also include a PLL circuit with a bandwidth that may be less than or equal to the bandwidth of the CDR loop circuit of the central switch transceiver. The sensor transceiver may include transmitter circuitry configured to transmit high data rate information using a high-frequency transmission clock generated by the PLL circuitry. This configuration enables crystal-free operation while maintaining acceptable jitter performance through coordinated bandwidth management between the central switch transceiver and the sensor transceiver. The ability to employ sensors with crystal-free sensor transceivers reduces system cost and complexity and increases system reliability. These and other advantages will be apparent to those skilled in the art of networked sensor design, such as in automotive and other vehicles or systems, given the detailed explanation of the various figures below.

[0025] refer to Figure 1 In some embodiments, such as in automotive applications, system 100 may be configured to reduce jitter in data communication between a central switch and multiple sensors. In these embodiments, the data communication is asymmetric in data rate, as will be explained, although not necessarily in situations where the value is realized through the principles described herein. System 100 may be designed for automotive applications, such as autonomous vehicles, where numerous sensors surround the vehicle and transmit data to a central or regional switch. In some cases, system 100 may implement the 803.2dm standard, which specifies an asymmetric electrical Ethernet physical layer (PHY) optimized for automotive applications, particularly for end-node cameras and displays.

[0026] System 100 may include a switch 110 and multiple sensors 120A, 120B to 120N (e.g., sensors 120A-120N). Switch 110 may include central switch transceivers 115A, 115B to 115N (e.g., central switch transceivers 115A-115N), each central switch transceiver communicating with a sensor via a corresponding communication link. Sensor 120A may include sensor transceiver 125A, sensor 120B may include sensor transceiver 125B, and sensor 120N may include sensor transceiver 125N. Central switch transceivers 115A-115N may be communicatively coupled to sensor transceivers 125A-125N via communication links to enable bidirectional data transmission.

[0027] exist Figure 1In the illustrated asymmetric data communication configuration, the central switch transceivers 115A-115N can use a self-timing signaling scheme to send low data rate (LDR) signals to the sensor transceivers 125A-125N. The sensor transceivers 125A-125N can then send high data rate (HDR) signals back to the central switch transceivers 115A-115N, where the high data rate can be higher than the low data rate. This asymmetric configuration enables efficient bandwidth utilization, where control information and timing references flow from the central switch transceivers 115A-115N to the sensor transceivers at a lower data rate, while sensor data flows from the sensor transceivers back to the central switch transceivers 115A-115N at a higher data rate.

[0028] The central switch 110 may also include a common crystal oscillator 101 for providing a stable timing reference, which can be transmitted to the sensor transceivers 125A-125N via a self-timing signal. Each of the sensor transceivers 125A-125N can operate without a separate crystal oscillator, instead deriving its timing reference from the self-timing signal received from the central switch transceivers 115A-115N. The self-timing signal can carry timing information embedded in the data transmission, enabling the sensor transceivers to extract both data and timing reference from the same signal. This architecture achieves cost-effective and reliable operation by eliminating the need for an individual crystal at each sensor location while maintaining synchronized operation across system 100.

[0029] refer to Figure 2 The central switch transceiver 215 can be configured to provide a stable timing reference and manage bidirectional communication within the system 100. The central switch transceiver 215 can be a central switch transceiver 115A-115N (…). Figure 1 Any one of the following. The central switch transceiver 215 can be coupled to a common crystal oscillator 201 (such as common crystal oscillator 101) that provides a timing reference (e.g., a clock reference or signal) for system 100. Although not shown, individual crystal oscillators can be integrated within each central switch transceiver 115A-115N or 215, although this is less cost-effective and may involve synchronization of all crystal oscillators. In some cases, crystal oscillator 201 can operate at a low frequency, such as 25-50 MHz, to generate a local clock synchronized with the switch clock. Crystal oscillator 201 can provide a stable and accurate timing reference, which serves as the basis for generating the self-timing signal sent to sensor transceivers 125A-125N.

[0030] Digital data source 204 can generate digital data for transmission to any of the sensor transceivers 125A-125N. Digital data source 204 may include framing and channel coding functions for higher-layer protocols, thereby achieving appropriate data structuring and error correction capabilities. Digital data from digital data source 204 can be provided to symbol mapper 208, which maps the digital data to symbols suitable for transmission using a timing signaling scheme. In some embodiments, symbol mapper 208 implements Manchester encoding to create a timing signal, wherein the timing signal includes Manchester encoding that embeds timing information within the data transmission.

[0031] The output of symbol mapper 208 can be connected to a transmission digital-to-analog converter (DAC) or TX DAC 212, which converts digital signals into analog signals for transmission. The TX DAC 212 can receive timing synchronization from a common crystal oscillator 201 to maintain accurate timing alignment during the digital-to-analog conversion process. Transmitter circuitry, which may include digital data source 204, symbol mapper 208, and TX DAC 212, can be configured to operate at a low data rate in an asymmetric communication configuration for transmission to a sensor transceiver.

[0032] The central switch transceiver 215 may also include a hybrid interface circuit 216, which enables transmission and reception via a single differential pair of conductive media. The hybrid interface circuit 216 can be connected to a TX DAC 212 for transmitting signals to any of the sensors 120A-120N and a receive analog-to-digital converter or RX ADC 222 for receiving signals from any of the sensors 120A-120N, thereby enabling full-duplex communication via a single differential pair. The hybrid interface circuit 216 can separate the transmitted and received signals to prevent interference between the transmit and receive paths, while allowing simultaneous bidirectional communication.

[0033] On the receiving path, the RX ADC 222 can receive analog signals from the hybrid interface circuit 216 and convert them into digital signals for processing. The RX ADC 222 can receive timing synchronization to maintain proper sampling of incoming high data rate signals from the sensor transceiver. The output of the RX ADC 222 can be provided to the equalizer 226, which processes the digital signal to remove inter-symbol interference and prepare the signal for data recovery.

[0034] The equalized signal from equalizer 226 can be provided to data limiter 232, which converts the digital signal into data symbols for further processing. CDR circuit 236 can detect phase errors in the received signal and generate a sampling rate adjustment control signal to maintain proper timing alignment. CDR circuit 236 can be part of CDR loop circuit 230, which includes RX ADC 222, equalizer 226, data limiter 232, and CDR circuit 236.

[0035] CDR loop circuit 230 can operate with a first bandwidth to recover high data rate information from any of the sensor transceivers 125A-125N. For example, the high data rate information may be used for data reception from the sensor transceivers 125A-125N, and the high data rate of this high data rate information is higher than the low data rate used to transmit to the sensor transceivers 125A-125N. The first bandwidth of CDR loop circuit 230 can be configured to track and compensate for bandwidth-limited jitter generated by the PLL circuitry of the sensor transceivers 125A-125N. In some cases, bandwidth-limited jitter may include low-frequency jitter components present due to low-pass filtering by the PLL bandwidth of the sensor transceivers 125A-125N. The recovered data symbols from data limiter 232 can be provided to digital data receiver 240 for further processing and consumption of the high data rate information received from the sensor transceivers 125A-125N.

[0036] In some embodiments, the first bandwidth of the CDR loop circuit 230 is configured to be greater than or equal to the second bandwidth of the PLL circuit. Figure 3A In the embodiment, PLL circuit 301 is used to mitigate jitter experienced by the CDR loop circuit 230. When the bandwidth is referred to herein as CDR, the CDR loop capability can be referenced to track the jitter frequency range up to a limit where the signal-to-noise ratio (SNR) loss in a jitter-limited receiver does not exceed 1 dB. This limit may be referred to as the 1 dB CDR bandwidth or simply the CDR bandwidth. This means that sinusoidal jitter with frequencies up to the CDR bandwidth, even if their amplitude is large enough to prevent normal receiver operation (if their frequency is outside the CDR bandwidth), can cause an SNR drop of no more than 1 dB. In this embodiment, PLL circuit 301 serves as a low-pass filter for input phase noise and a high-pass filter for phase noise from the voltage-controlled oscillator (VCO), which will refer to... Figures 3A-3B This will be discussed further. When referencing the PLL for bandwidth, it can reference the 3dB cutoff frequency for the aforementioned low-pass or high-pass transfer function. In this way, the PLL reference clock phase noise is low-pass filtered, while the VCO phase noise is high-pass filtered.

[0037] refer to Figure 3A The sensor transceiver 325 can be configured to operate without a crystal oscillator while maintaining a high data rate transmission capability. The sensor transceiver 325 can represent system 100 (see [link to system 100]). Figure 1 The sensor transceiver 325 may be any one of the sensor transceivers 125A, 125B, or 125N in the central switch transceiver 215. The sensor transceiver 325 may be designed to extract a timing reference from the self-timing signal received from the central switch transceiver 215 and generate a high-frequency transmission clock for transmitting sensor data back to the central switch transceiver 215.

[0038] Sensor transceiver 325 may include digital data source 304, which generates high-data-rate digital data for transmission to central switch transceiver 215. Digital data source 304 may include video sensors and LiDAR sensors, as examples of high-speed data-generating sensors for collecting information in automotive applications. Digital data source 304 may also include framing and channel coding functions for higher-layer protocols, implementing appropriate data structuring and error correction capabilities for high-data-rate transmission. Digital data source 304 may be connected to symbol mapper 308, which maps high-data-rate data symbols to a digital signal format suitable for transmission.

[0039] Symbol mapper 308 can output to TX DAC 312, which can be a transmit digital-to-analog converter (DAC) that converts high-data-rate digital signals into high-data-rate analog signals for transmission. TX DAC 312 may include DAC circuitry configured to use a transmission clock when generating high-data-rate data to be transmitted back to central exchange transceiver 215. TX DAC 312 can receive timing synchronization from PLL circuitry 301 to maintain accurate timing alignment during the DAC conversion process for high-data-rate transmission.

[0040] Sensor transceiver 325 may include a PLL circuit 301 that receives a reference clock from reference clock recovery circuit 305. Reference clock recovery circuit 305 can extract timing information from a Manchester-encoded signal received from central switch transceiver 215 via hybrid interface circuit 316, which communicates with hybrid interface circuit 216 of central switch transceiver 215. The Manchester-encoded signal may be a self-timing signal including Manchester encoding, where Manchester encoding embeds timing information within data transmission to achieve crystal-free operation. PLL circuit 301 can generate a transmission clock signal that can be distributed to digital data source 304, symbol mapper 308, and TX DAC 312 to synchronize transmission path operation.

[0041] The reference clock recovery circuit 305 may include a Manchester decoder configured to decode the Manchester encoding in the self-synchronization signal received from the central switch transceiver 215. The self-synchronization signal can be received from the central switch transceiver 215 at a low data rate, while high data rate information generated by the sensor transceiver 325 can be transmitted at a rate higher than the low data rate. This asymmetric data rate configuration enables efficient communication, where timing and control information flows to the sensor transceiver 325 at a lower data rate, while sensor data flows back from the sensor transceiver 325 to the central switch transceiver 215 at a higher data rate.

[0042] The sensor transceiver 325 may also include a hybrid interface circuit 316, which enables transmission and reception via a single differential pair of conductive media. The hybrid interface circuit 316 can be connected to both the TX DAC 312 for transmitting signals to the central switch transceiver 215 and the RX ADC 322 for receiving signals from the central switch transceiver 215, thereby enabling full-duplex communication via a single differential pair. The hybrid interface circuit 316 can separate the transmitted and received signals to prevent interference between the transmission and reception paths, while allowing bidirectional communication with the central switch transceiver 215.

[0043] The receiving path of sensor transceiver 325 may include RX ADC 322, which can be a receiving analog-to-digital converter that receives timing synchronization and converts incoming analog signals into digital form. RX ADC 322 can receive a self-timing signal via mixing interface circuitry 316 and convert the analog signal into a digital signal for processing by reference clock recovery circuitry 305. Equalizer 326 can be connected to the output of RX ADC 322 and can perform equalization to remove inter-symbol interference from received low data rate signals.

[0044] The equalized signal from equalizer 326 can be provided to data limiter 332, which recovers low-data-rate digital data from the received signal. Data limiter 332 can convert the equalized digital signal into data symbols for further processing. Data limiter 332 can output to digital data receiver 340, which processes the low-data-rate data received from central exchange transceiver 215. Digital data receiver 340 may include functions for frame boundary identification and channel decoding to appropriately process control and timing information received from central exchange transceiver 215.

[0045] refer to Figure 3B PLL circuit 301 ( Figure 3AThe PLL circuit 301 may include a detailed architecture configured to generate a high-frequency transmission clock from a reference clock extracted by the reference clock recovery circuit 305. The PLL circuit 301 may include a phase difference detector 354, a controller 358, an adjustable resonant oscillator 362, and a frequency divider 366. The phase difference detector 354 may receive a reference clock signal from the reference clock recovery circuit 305 and a feedback signal from the frequency divider 366 to identify the phase difference between the two input signals.

[0046] Phase difference detector 354 compares the phase of a reference clock with the frequency-divided output of adjustable resonator 362 and generates a phase error signal representing the timing difference between the reference signal and the feedback signal. The phase error signal from phase difference detector 354 can be provided to controller 358, which can be configured to adjust adjustable resonator 362 based on the phase difference. Controller 358 can process the phase difference information and generate a control signal that adjusts the frequency and phase of adjustable resonator 362 to minimize the phase error between the reference signal and the feedback signal.

[0047] The tunable oscillator 362 can generate a high-frequency output clock signal based on a control signal from the controller 358. In some embodiments, the tunable oscillator 362 is implemented as a voltage-controlled oscillator (VCO), which contributes inherent jitter to the system. The tunable oscillator 362 can use an LC / RC oscillator design, which can operate at high frequencies, but may be less stable compared to a crystal oscillator. The high-frequency output from the tunable oscillator 362 can be used as a transmission clock for the sensor transceiver 325 and can be distributed to the digital data source 304, the symbol mapper 308, and the TX DAC 312.

[0048] Frequency divider 366 can be located in the feedback path and can be configured to divide the output of tunable resonant oscillator 362 (or voltage-controlled oscillator output) by an integer factor. Frequency divider 366 can create a feedback signal that is provided to phase difference detector 354 for phase comparison with a reference clock. The integer division factor of frequency divider 366 can represent the ratio of the HDR clock rate to the recovered clock rate, thereby establishing a relationship between the high data rate transmission frequency and the low data rate reference clock frequency. In some cases, the transmission clock frequency can be equal to the integer factor multiplied by the recovered clock frequency.

[0049] The bandwidth of the PLL circuit 301 can be determined by the transfer function of the controller 358, the loop gain, and the rate of the reference clock. The controller 358 implements a transfer function that affects how the PLL circuit 301 responds to phase errors and timing variations in the reference clock signal. A higher reference clock rate results in a wider loop bandwidth, while the loop gain determines the responsiveness of the PLL circuit 301 to phase correction. The transfer function of the PLL circuit 301 can exhibit low-pass characteristics for reference jitter and high-pass characteristics for VCO jitter, where reference jitter can be filtered by the low-pass response, while VCO jitter can be passed through the high-pass response.

[0050] The second bandwidth of PLL circuit 301 can be configured to be less than or equal to the first bandwidth of CDR loop circuit 230 to achieve effective jitter mitigation. In some embodiments, the second bandwidth can be set low enough to filter out residual jitter measurable from the first bandwidth to the Nyquist frequency of PLL circuit 301. Residual jitter can represent the amount of jitter measured from the first bandwidth of CDR loop circuit 230 to the Nyquist frequency of PLL circuit 301, which, if not properly managed, can cause a decrease in signal-to-noise ratio in high data rate receivers. The Nyquist frequency can be defined as half the sampling rate of PLL circuit 301, representing the highest frequency that can be accurately represented without aliasing.

[0051] In some cases, the second bandwidth can be set as low as tens of kilohertz (kHz), while the PLL circuit 301 itself can operate at tens or hundreds of megahertz (MHz) to achieve the target jitter filtering characteristics. By constraining the second bandwidth to a lower value, the PLL circuit 301 can limit the jitter spectrum to a lower frequency that the CDR loop circuit 230 can effectively track and compensate for. When the second bandwidth is sufficiently lower than the first bandwidth, the jitter generated by the self-timing scheme can be bandwidth-constrained to frequencies that the higher-bandwidth CDR loop circuit 230 can track without causing a degradation in the signal-to-noise ratio of the receiver at the central switch transceiver 215.

[0052] refer to Figure 3C The reference clock recovery circuit 305 can be configured to extract timing information from the self-timing signal received from the central switch transceiver 215. The reference clock recovery circuit 305 may include an XOR gate 370, a delay circuit 374, and a D flip-flop 378, which work together to recover clock and data information from the Manchester-encoded signal.

[0053] A transition may always occur in the middle of a Manchester-encoded symbol. For example, a logic 1 can have a low-to-high transition, and a logic 0 can have a high-to-low transition. The XOR gate 370 can receive a timer signal at one input and an NRZ (the recovered binary non-return-to-zero value of the timer signal) at the other input. For example, when the recovered NRZ signal is logic 0, the Manchester-encoded signal can be directly output as a recovered reference clock. When the recovered NRZ signal is logic 1, the inverted Manchester-encoded signal can be output as a recovered reference clock. A transition in the middle of the current Manchester symbol can generate a clock edge on the D flip-flop 378 to recover the logic level of the next NRZ signal.

[0054] The delay of the delay circuit 374 can be set such that the D flip-flop 378 samples at a specific phase of the Manchester signal to recover the NRZ signal. This configuration allows the reference clock recovery circuit 305 to extract both the reference clock for timing synchronization and the NRZ data signal for data processing from the same self-timing signal received from the central switch transceiver 215. Manchester encoding can embed timing information into the data transmission by using signal conversion to represent both clock edges and data bits, allowing the sensor transceiver 325 to derive a timing reference without requiring a local crystal oscillator.

[0055] The reference clock recovery circuit 305 may experience jitter in the recovered reference clock due to several sources of interference and noise. Thermal noise in the receiver circuitry may introduce random variations during timing extraction, resulting in uncertainty in the recovered clock edges. Residual echoes from the output of the TX DAC 312 may interfere with the received auto-timing signal, where incomplete cancellation of the transmitted high data rate signal may cause timing interference during reference clock recovery. Inter-symbol interference (ISI) in the auto-timing signal may cause timing variations due to signal distortion from the transmission channel, where previous symbols may affect the timing extraction of the current symbol.

[0056] The jitter in the recovered reference clock can be approximately two orders of magnitude higher than that of the crystal clock reference, posing a challenge to maintaining timing accuracy in the sensor transceiver 325. A combination of thermal noise, residual echo, and inter-symbol interference can generate a white noise spectrum in the reference jitter, where the jitter power can be distributed over a wide frequency range. This white reference jitter can be used as an input to the PLL circuit 301, whose low-pass characteristic filters the jitter spectrum and constrains the output jitter to a lower frequency that the CDR loop circuit 230 can effectively track and compensate for.

[0057] exist Figure 4The graph illustrates the relationship between reference jitter and PLL output jitter for various PLL bandwidths, demonstrating how different bandwidth configurations affect jitter propagation through PLL circuit 301. The graph depicts PLL output jitter measured in picoseconds on the vertical axis and random jitter on a 50MHz reference clock measured in picoseconds on the horizontal axis. Multiple curves show both measured and estimated jitter values ​​for different PLL bandwidths (including 83kHz, 250kHz, 333kHz, and 1MHz configurations).

[0058] like Figure 4 As shown, the curves demonstrate that as random jitter on the reference clock increases, so does PLL output jitter, with higher PLL bandwidth typically resulting in larger output jitter for a given amount of input jitter. For each bandwidth configuration across the entire range of input jitter values, the measurements, indicated by circles and solid lines, are closely correlated with the estimates, indicated by x-marks and dashed lines. This correlation validates the predictive relationship between reference jitter input and PLL output jitter across different bandwidth settings.

[0059] The white-spectrum reference jitter from the reference clock recovery circuit 305 can be filtered by the low-pass transfer function of the PLL circuit 301, which acts as a low-pass filter for input phase noise and jitter. The low-pass filtering characteristics of the PLL circuit 301 can constrain the reference jitter contribution at the PLL output to frequencies below the second bandwidth of the PLL circuit 301. When the reference jitter exhibits a white noise spectrum with a uniform power distribution across the frequency range, the low-pass filtering effect can reduce the total jitter power propagating to the PLL output by limiting the frequency range of the jitter components.

[0060] The mathematical relationship between the input jitter and output jitter of PLL circuit 301 can be expressed by the formula: It means that J in Jout represents the input jitter in PLL circuit 301, and Jout represents the output jitter from PLL circuit 301. vco F represents the inherent jitter of the VCO contributed by the tunable resonant oscillator 362. pll This represents the second bandwidth of PLL circuit 301, while F signal This represents the Nyquist frequency of the clock edge signal. The Nyquist frequency can be defined as half the edge rate of the transmission clock generated by the PLL circuit 301.

[0061] This formula indicates that reducing the second bandwidth F of PLL circuit 301... pll The contribution of reference jitter at the PLL output can be reduced by using the square root relationship between the bandwidth ratio and the jitter scaling factor. When the second bandwidth is relative to the Nyquist frequency F... signalWhen it decreases, the ratio F pll / F signal Reduced, thus causing the jitter J applied to the input to decrease. in A smaller scaling factor. This mathematical relationship allows the system to minimize the effects of reference jitter from the reference clock recovery circuit 305 by appropriately selecting a sufficiently low second bandwidth for the PLL circuit 301.

[0062] The VCO inherent jitter (Jvco) from the tunable oscillator 362 can be represented as an additive jitter component that remains constant regardless of the reference jitter level configured for a given PLL bandwidth. Due to the thermal and phase noise characteristics of the LC / RC oscillator design used in the crystalless sensor transceiver 325, the tunable oscillator 362 can cause or contribute to this inherent jitter. The total output jitter (Jout) can be represented as a combination of the scaled reference jitter component and the VCO inherent jitter component, both of which can potentially affect the quality of the transmission clock used for high data rate transmissions.

[0063] In some embodiments, the second bandwidth can be set low enough to filter out residual jitter measurable from the first bandwidth of the CDR loop circuit 230 to the Nyquist frequency of the PLL circuit 301. Residual jitter can therefore represent the portion of the jitter spectrum that extends beyond the first bandwidth of the CDR loop circuit 230 and, if not properly managed, can lead to a decrease in signal-to-noise ratio. By setting the second bandwidth of the PLL circuit 301 to be lower than the first bandwidth, the PLL circuit 301 can constrain the jitter spectrum to frequencies that the CDR loop circuit 230 can effectively track and compensate for, thereby reducing residual jitter that affects the performance of high data rate receivers.

[0064] In various embodiments, the second bandwidth can be set to tens of kilohertz, while the PLL circuit 301 operates at tens or hundreds of megahertz to achieve effective jitter filtering while maintaining sufficient PLL performance for the sensor transceiver 325. This bandwidth range can provide sufficient jitter reduction without excessively increasing the contribution to VCO jitter from the tunable resonator 362, which can become more pronounced at very low PLL bandwidths. Selecting the second bandwidth of the PLL circuit 301 within this range balances the trade-off between reference jitter filtering and VCO jitter contribution to optimize the overall jitter performance of the transmission clock generated by the PLL circuit 301.

[0065] refer to Figure 5The graph illustrates the relationship between reference jitter and residual jitter for an example system with a high data rate of 10 gigabits per second (GBPS) over a 1-meter (m) cable, demonstrating how different combinations of PLL bandwidth and CDR loop bandwidth affect jitter performance in System 100. The graph depicts jitter at the Manchester clock extractor output, measured in picoseconds on the horizontal axis, ranging from 25 to 75 picoseconds, and residual jitter affecting the HDR receiver SNR, measured in picoseconds on the vertical axis, ranging from 1 to 11 picoseconds. Multiple curves representing different combinations of PLL bandwidth and CDR loop bandwidth configurations are plotted, with each curve showing how residual jitter changes as Manchester clock extractor output jitter increases.

[0066] System 100 can define residual jitter as the amount of jitter measured from the CDR loop bandwidth to the Nyquist frequency of PLL operation, which may cause a decrease in the signal-to-noise ratio at the receiver of the central switch transceiver 215. Residual jitter can represent the portion of the jitter spectrum that extends beyond the tracking capability of the CDR loop circuit 230 and can directly affect the quality of data recovery at the central switch transceiver 215. When the CDR loop circuit 230 cannot track jitter components above its bandwidth, these higher frequency jitter components may manifest as residual jitter, which reduces the SNR of high data rate signals received from sensor transceivers 125A-125N.

[0067] like Figure 5 As shown, the curves demonstrate that, for a given PLL bandwidth, increasing the CDR loop bandwidth can result in lower residual jitter values ​​across the range of Manchester clock extractor output jitter levels. The figure illustrates configurations with lower PLL bandwidth values ​​(such as 75 kHz, 100 kHz, and 150 kHz) that produce lower residual jitter compared to configurations with higher PLL bandwidth values ​​(such as 300 kHz). For each PLL bandwidth setting, three different CDR loop bandwidth values ​​are shown: 46 kHz, 88 kHz, and 175 kHz, where higher CDR loop bandwidth values ​​within each PLL bandwidth group can cause reduced residual jitter.

[0068] Figure 5 The curve in the graph indicates that as the Manchester clock extractor output jitter increases, the residual jitter affecting the CDR loop circuit 230 also increases. The rate of increase depends on the specific combination of PLL and CDR loop bandwidth used. A configuration where the CDR loop bandwidth is greater than or equal to the PLL bandwidth exhibits superior performance in minimizing residual jitter compared to a configuration where the CDR bandwidth may be lower than the PLL bandwidth. This relationship validates the method of setting the first bandwidth of the CDR loop circuit 230 to be greater than or equal to the second bandwidth of the PLL circuit 301 to achieve effective jitter mitigation.

[0069] Figure 5 The residual jitter performance shown is directly related to the signal-to-noise ratio (SNR) degradation experienced by the central switch transceiver 215 when receiving high data rate signals from the sensor transceiver 325. Lower residual jitter values ​​correspond to better SNR performance, resulting in more reliable data recovery and higher system performance. When the CDR loop circuit 230 operates with a bandwidth greater than or equal to the bandwidth of the PLL circuit 301, the CDR loop circuit 230 can effectively track the bandwidth-limited jitter generated by the PLL circuit 301, thereby reducing residual jitter that affects the performance of the HDR receiver.

[0070] refer to Figure 6 Method 600 can be configured to mitigate jitter in a crystal-free wired transceiver through coordinated bandwidth management between a central switch transceiver and a sensor transceiver. Method 600 can provide a system approach that manages jitter in a crystal-free transceiver system by coordinating bandwidth settings between a central switch transceiver 215 and a sensor transceiver 325 to achieve effective jitter tracking and compensation. Method 600 can be implemented in system 100 to achieve reliable high data rate communication while eliminating the need for an individual crystal oscillator at each sensor location.

[0071] Method 600 may begin with operation 610, in which a crystal oscillator 201 in the central switch transceiver 215 may be used to generate a timing signal carrying first data. The crystal oscillator 201 provides a stable timing reference, which serves as the basis for creating the timing signal transmitted to the sensor transceiver 325. The timing signal may include Manchester encoding that embeds timing information into the data transmission, enabling the sensor transceiver to extract both the data and the timing reference from the same signal. The first data carried by the timing signal may include control information and the timing reference flowing from the central switch transceiver 215 to the sensor transceiver 325 at a low data rate.

[0072] Method 600 can proceed to operation 620, in which the CDR loop circuit 230 of the central switch transceiver 215 can be operated with a first bandwidth. The first bandwidth determines the ability of the CDR loop circuit 230 to track and compensate for timing variations in signals received from the sensor transceivers 125A-125N. The CDR loop circuit 230 can be configured to recover high data rate information transmitted by the sensor transceivers using their respective transmission clocks generated by the PLL circuit 301. The first bandwidth can be selected to achieve effective tracking of bandwidth-limited jitter that may be generated by the PLL circuitry of the sensor transceivers.

[0073] Method 600 can continue to operation 630, wherein the reference clock recovery circuit 305 of the sensor transceiver 325 can decode a reference clock from the self-timing signal. The reference clock recovery circuit 305 can extract timing information from the Manchester-encoded signal received from the central switch transceiver 215 via XOR gate 370, delay circuit 374, and D flip-flop 378. The reference clock recovery circuit 305 may include a Manchester decoder (such as...) Figure 3C As shown, the Manchester decoder is configured to decode the Manchester code in the self-timing signal, enabling the sensor transceiver 325 to derive a timing reference without requiring a local crystal oscillator. The decoded reference clock can be used as an input to the PLL circuit 301 to generate a higher frequency transmission clock.

[0074] Method 600 can proceed to operation 640, in which a transmission clock can be generated from a reference clock using the PLL circuit 301 of the sensor transceiver 325. The PLL circuit 301 can use the reference clock as input to generate a higher-frequency clock signal suitable for high-data-rate transmission back to the central switch transceiver 215. The PLL circuit 301 may include a phase difference detector 354, a controller 358, an adjustable resonant oscillator 362, and a frequency divider 366 (FIG.3B), which work together to generate the transmission clock from the reference clock. The transmission clock can be distributed to the digital data source 304, the symbol mapper 308, and the TX DAC 312 to synchronize the transmission path operation for generating second data at a high data rate.

[0075] Method 600 can continue to operation 650, where the first bandwidth can be set to be greater than or equal to the second bandwidth of PLL circuit 301. This bandwidth relationship allows the central switch transceiver 215 to effectively track and compensate for jitter originating from the PLL circuit 301 of sensor transceiver 325. When PLL circuit 301 operates with a second bandwidth that may be lower than or equal to the first bandwidth, the jitter spectrum may be constrained to lower frequencies that the higher bandwidth CDR loop circuit 230 may be able to track without reducing the signal-to-noise ratio. The bandwidth relationship can mitigate the jitter experienced by CDR loop circuit 230 due to jitter in the transmission clock generated by PLL circuit 301.

[0076] Method 600 may optionally proceed to operation 660, wherein the second bandwidth can be set low enough to filter out residual jitter measurable at the Nyquist frequency from the first bandwidth to the PLL circuit 301. Residual jitter can represent a portion of the jitter spectrum that extends beyond the tracking capability of the CDR loop circuit 230 and can lead to SNR degradation if not properly managed. By setting the second bandwidth low enough, the PLL circuit 301 can constrain the jitter spectrum to frequencies that the CDR loop circuit 230 can effectively track and compensate for, thereby reducing residual jitter that affects the performance of high data rate receivers. In some cases, the second bandwidth can be set to tens of kHz, while the PLL circuit 301 operates at tens or hundreds of MHz to achieve effective jitter filtering while maintaining sufficient PLL performance for the sensor transceiver 325.

[0077] Method 600 enables system 100 to achieve reliable communication between central switch transceiver 215 and sensor transceiver 325, while eliminating the need for individual crystal oscillators at each sensor location. The coordinated bandwidth management method implemented by Method 600 reduces system cost and complexity by relating the first bandwidth of CDR loop circuit 230 to the second bandwidth of PLL circuit 301, while maintaining acceptable jitter performance. Method 600 is particularly suitable for automotive applications where numerous sensors surround the vehicle and transmit data to a central or zone switch, enabling cost-effective and reliable sensor network operation.

[0078] In various embodiments, functional interactions between the various components in a crystal-free transceiver system can be effectively mitigated through coordinated signal processing and bandwidth management. The signal flow can begin with a crystal oscillator 201 generating a stable timing reference, which serves as the basis for all timing operations within the central switch transceiver 215. The transmitter circuitry can use this timing reference to create a self-timing signal that carries both data and embedded timing information to the sensor transceivers 125A, 125B, 125N, and 325.

[0079] The self-timing transmission path can utilize Manchester encoding or other self-timing signaling schemes to embed timing information within the data stream transmitted at a low data rate to sensor transceiver 325. Manchester encoding ensures that timing conversion occurs within the data signal itself, allowing sensor transceiver 325 to extract both the data content and the timing reference from the same transmitted signal. The hybrid interface circuits 216 and 316 enable the self-timing signal to be transmitted via the same differential pair carrying a high data rate signal in opposite directions, facilitating efficient bidirectional communication, although the principles taught herein do not require bidirectional communication.

[0080] At sensor transceiver 325, reference clock recovery circuit 305 processes the received timing signal to extract the embedded timing information and generate a reference clock, which is kept synchronized with crystal oscillator 201 at central switch transceiver 215. This recovered reference clock can be used as the timing basis for the transmission operation of the sensor transceiver.

[0081] PLL circuit 301 can receive a recovered reference clock and generate a high-frequency transmission clock suitable for high data rate transmission back to central switch transceiver 215. PLL circuit 301 can multiply the frequency of the reference clock via its feedback control mechanism, where phase difference detector 354 compares the reference clock with a divided version of the output clock to maintain phase alignment. Controller 358 can adjust tunable resonant oscillator 362 based on phase error information to generate the desired high-frequency transmission clock, which synchronizes the data transmission operations of sensor transceiver 325.

[0082] The bandwidth configuration of PLL circuit 301 determines the parameters by which jitter from the reference clock recovery process propagates to the transmission clock output. When PLL circuit 301 operates with a lower bandwidth, the low-pass filtering characteristics constrain the reference jitter to a lower frequency while limiting the total jitter power reaching the transmission clock. This bandwidth-limited effect creates a jitter spectrum that concentrates energy at frequencies below the PLL bandwidth, thereby enabling more efficient tracking by the receiver circuitry at the central switch transceiver 215.

[0083] The high-bandwidth CDR loop 230 at the central switch transceiver 215 can track and compensate for bandwidth-limited jitter present in high data rate signals received from the sensor transceiver 325. The CDR loop circuit 230 can continuously adjust its sampling timing to follow timing variations in the received signal, thereby effectively tracking jitter components falling within its bandwidth. When the CDR loop bandwidth exceeds the PLL bandwidth of the sensor transceiver 325, the CDR loop circuit 230 can successfully track virtually all jitter components generated by the PLL circuit 301, thereby minimizing residual jitter that affects signal-to-noise ratio performance.

[0084] The coordinated bandwidth relationship between PLL circuit 301 and CDR loop circuit 230 enables system 100 to convert high-frequency white noise jitter from the reference clock recovery process into low-frequency bandwidth-limited jitter that can be tracked and compensated by the receiving circuitry system. PLL circuit 301 can act as a low-pass filter for the reference jitter, while CDR loop circuit 230 can act as a tracking filter that follows changes in bandwidth-limited jitter. This functional interaction allows system 100 to maintain acceptable signal quality, despite the inherent jitter introduced by the crystalless operation of sensor transceiver 325.

[0085] In some embodiments, system 100 may implement echo cancellation functionality to reduce residual echo in the HDR TX DAC 312 signal from the mixing interface circuitry to the LDR receive path. Echo cancellation can address interference that can occur when high-data-rate transmitted signals from sensor transceiver 325 leak into the low-data-rate receive path, potentially affecting the reference clock recovery process. The echo cancellation function can identify and subtract echo components from the received self-timing signal, thereby improving the quality of reference clock extraction and reducing jitter in the recovered timing reference.

[0086] Echo cancellation operates by monitoring the high-data-rate transmitted signal and generating a copy of the expected echo signal that will appear in the low-data-rate receive path. This echo copy can be subtracted from the received timing signal to remove interference caused by the transmitted high-data-rate signal. By reducing residual echo, echo cancellation improves the signal-to-noise ratio of the reference clock recovery process and reduces jitter introduced during timing extraction from the timing signal.

[0087] In some configurations, as an alternative to full-duplex operation, system 100 can operate via a half-duplex channel. Half-duplex operation utilizes separate time periods for sending and receiving, thereby eliminating the simultaneous bidirectional communication that occurs in a full-duplex system. During the transmission period, sensor transceiver 325 can send high-data-rate information to central switch transceiver 215 without receiving a timing signal. During the reception period, central switch transceiver 215 can send a timing signal to sensor transceiver 325 without receiving high-data-rate information.

[0088] Half-duplex operation reduces interference between the transmit and receive paths by separating transmit and receive activities in time. This time separation eliminates the need for the hybrid interface circuits 216, 316 and reduces the complexity of echo cancellation requirements because the transmit and receive signals do not occur simultaneously. Reference clock recovery and PLL operation can continue to function in the half-duplex configuration, where the sensor transceiver 325 can use a reference clock extracted during a previous receive time period to maintain timing synchronization during the transmit time period.

[0089] System 100 can also operate using a pair of half-duplex channels to provide bidirectional communication capability while maintaining temporal separation between transmitting and receiving activities. In this configuration, one half-duplex channel can be dedicated to low-data-rate transmissions from the central switch transceiver 215 to the sensor transceiver 325, while the other half-duplex channel can be dedicated to high-data-rate transmissions from the sensor transceiver 325 to the central switch transceiver 215. This dual half-duplex approach can provide the communication bandwidth of full-duplex operation while maintaining the interference reduction benefits of temporal separation between transmitting and receiving operations.

[0090] Although the operation of circuits and blocks is shown and described herein in a specific order, in some embodiments, the order of operation of each circuit / block may be changed so that certain operations can be performed in reverse order, or that certain operations can be performed at least partially simultaneously and / or in parallel with other operations. In other embodiments, instructions or sub-operations of different operations may be performed intermittently and / or alternately.

[0091] In the foregoing description, the invention has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A system comprising: Crystal oscillator; A central switch transceiver, coupled to the crystal oscillator, the central switch transceiver comprising: Transmitter circuitry is configured to generate a self-timing signal carrying first data using a timing reference from the crystal oscillator; and A clock and data recovery loop circuit is used to operate at a first bandwidth to sample second data received from the sensor transceiver; and The sensor transceiver includes: A reference clock recovery circuit is used to decode a reference clock from the self-timing signal; and A phase-locked loop (PLL) circuit is used to generate a transmission clock from the reference clock for generating the second data, wherein the first bandwidth is greater than or equal to the second bandwidth of the PLL circuit to mitigate jitter experienced by the clock and data recovery loop circuit due to jitter in the transmission clock.

2. The system according to claim 1, wherein, The second bandwidth is set low enough to filter out residual jitter measurable from the first bandwidth to the Nyquist frequency of the PLL circuit.

3. The system according to claim 1, wherein, The second bandwidth is set to tens of kilohertz, while the PLL circuit operates at tens or hundreds of megahertz.

4. The system according to claim 1, wherein, The sensor transceiver also includes a digital-to-analog converter circuit system configured to use the transmission clock when generating the second data.

5. The system according to claim 1, wherein, The central switch transceiver transmits at a low data rate (LDR), and the sensor transceiver receives at a high data rate (HDR) higher than the LDR.

6. The system according to claim 1, wherein, The self-timing signal includes Manchester encoding.

7. The system according to claim 1, wherein, The reference clock recovery circuit includes a Manchester decoder configured to decode the Manchester encoding in the self-timing signal.

8. A central switch, comprising: A crystal oscillator configured to generate a timing reference; as well as A central switch transceiver, coupled to the crystal oscillator, the central switch transceiver comprising: Transmitter circuitry, configured to generate a self-timing signal carrying low data rate information using the timing reference; and A receiver circuit including a clock and data recovery loop circuit configured to operate with a first bandwidth to recover high data rate information from a sensor transceiver, wherein the first bandwidth is configured to be greater than or equal to the phase-locked loop (PLL) bandwidth of the sensor transceiver to mitigate jitter experienced from the self-timing signal.

9. The central switch according to claim 8, wherein, The self-timing signal includes Manchester encoding.

10. The central switch according to claim 8, wherein, The transmitter circuit is configured to operate at a low data rate, and the receiver circuit is configured to recover high data rate information that is higher than the low data rate.

11. The central switch according to claim 10, wherein, In an asymmetric communication configuration, the low data rate is used for transmitting to the sensor transceiver, and the high data rate is used for receiving from the sensor transceiver.

12. The central switch according to claim 8, wherein, The first bandwidth is configured to track and compensate for bandwidth-limited jitter generated by the PLL circuitry of the sensor transceiver.

13. The central switch according to claim 12, wherein, The bandwidth-limited jitter includes a low-frequency jitter component, which is present in the low-pass filtering of the PLL bandwidth of the sensor transceiver.

14. The central switch according to claim 8, wherein, The central switch transceiver also includes a hybrid interface circuit configured to enable transmission and reception via a single differential pair of conductive media.

15. A sensor transceiver, comprising: A reference clock recovery circuit is configured to extract a reference clock from a self-timing signal received from a central switch transceiver. A phase-locked loop (PLL) circuit configured to generate a high-frequency transmission clock from the reference clock, the PLL circuit having a bandwidth less than or equal to the clock and data recovery (CDR) loop bandwidth of the central switch transceiver; as well as A transmitter circuit configured to use the high-frequency transmission clock to transmit high data rate information.

16. The sensor transceiver according to claim 15, wherein, The reference clock recovery circuit includes a Manchester decoder configured to decode the Manchester encoding in the self-timing signal.

17. The sensor transceiver according to claim 15, wherein, The self-timing signal is received at a low data rate, and the high data rate information is transmitted at a rate higher than the low data rate.

18. The sensor transceiver according to claim 15, wherein, The bandwidth is set low enough to filter out residual jitter measurable from the CDR loop bandwidth to the Nyquist frequency of the PLL circuit.

19. The sensor transceiver according to claim 15, wherein, The PLL circuit includes: A phase difference detector, configured to identify the phase difference between the reference clock and the frequency division output from the voltage-controlled oscillator; A controller configured to adjust the voltage-controlled oscillator based on the phase difference; and A frequency divider in the feedback path is configured to divide the voltage-controlled oscillator output by an integer factor, wherein the bandwidth of the PLL circuit is determined by the transfer function of the controller, the loop gain, and the rate of the reference clock.

20. The sensor transceiver of claim 15 further includes a hybrid interface circuit configured to enable transmission and reception via a single differential pair of a conductive medium.

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