Method and apparatus for operating a memory system

Abstract

Methods, apparatuses, devices, and systems for operating a memory system are provided. In one aspect, a memory system includes a memory device including a plurality of storage blocks and a memory controller coupled to the memory device. The memory controller is configured to identify a first storage block of the plurality of storage blocks, where the first storage block includes particular data that is invalid. The memory controller can be configured to increase a priority level of the first storage block of the plurality of storage blocks and perform a garbage collection on the memory device based on the priority levels of the plurality of storage blocks.

Description

Technical Field

[0001] This disclosure generally relates to memory devices and memory systems, and particularly to operational memory systems. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as programming (writing) or reading. The operations performed on flash memory can affect its temperature. Summary of the Invention

[0003] This disclosure relates to methods, apparatus, and systems for operating a memory system (e.g., managing clear commands in a memory system).

[0004] One aspect of this disclosure provides a memory device including a plurality of memory blocks and a memory controller coupled to the memory device. The memory controller is configured to identify a first memory block among the plurality of memory blocks, wherein the first memory block includes invalid specific data. The memory controller is also configured to elevate the priority level of the first memory block among the plurality of memory blocks and to perform garbage collection on the memory device based on the priority level of the plurality of memory blocks.

[0005] In some implementations, specific data includes replay protection block (RPMB) data.

[0006] In some implementations, the specific data becomes invalid when new data is written to the same logical address as the specific data.

[0007] In some implementations, the memory controller is configured to identify the first memory block by checking an indicator bit corresponding to it. This indicator bit indicates whether the first memory block contains invalid specific data.

[0008] In some implementations, the memory controller is configured to: increase the priority level of the first memory block by reducing the first effective page count (VPC) of the first memory block; and perform a first garbage collection operation on the first memory block before the second memory block has a second VPC that is larger than the first VPC.

[0009] In some implementations, the memory controller is configured to receive a clear command to erase invalid specific data in the memory device, and to send a response indicating that the invalid specific data in the memory device has been erased.

[0010] In some implementations, the memory controller is configured to erase invalid specific data in the corresponding memory block during garbage collection before receiving a wipe command.

[0011] In some implementations, the memory controller is configured to perform garbage collection on the memory device when the memory device is idle.

[0012] In some implementations, the memory controller is configured to perform a first garbage collection operation on the first memory block by sending one or more commands to migrate valid data from the first memory block to a target memory block of the memory device and to erase the first memory block.

[0013] Another aspect of this disclosure features a memory controller. The memory controller includes a processor and a first interface coupled to a memory device. The processor is configured to perform garbage collection on the memory device based on priority levels of a plurality of memory blocks within the memory device. The first interface is configured to send one or more read commands to read valid data from a first memory block among the plurality of memory blocks. The first memory block includes invalid specific data. The first memory block has an elevated priority level based on the fact that it includes invalid specific data. The first interface is also configured to send one or more write commands to write the valid data read from the first memory block to a target memory block of the memory device.

[0014] In some implementations, the processor is configured to: identify a first memory block from a plurality of memory blocks and increase the priority level of the first memory block among the plurality of memory blocks.

[0015] In some implementations, the processor is configured to: increase the priority level of the first memory block by reducing the first effective page count (VPC) of the first memory block; and perform a first garbage collection operation on the first memory block before the second memory block has a second VPC that is larger than the first VPC.

[0016] In some implementations, the memory controller includes a second interface coupled to a host. The second interface is configured to receive a erase command to erase invalid specific data in the memory device, and to send a response indicating that the invalid specific data in the memory device has been erased.

[0017] In some implementations, the processor is configured to erase invalid specific data in the corresponding storage block during garbage collection before receiving a wipe command.

[0018] In some implementations, the processor is configured to perform garbage collection on the memory device when the memory device is idle.

[0019] In some implementations, specific data includes replay protection block (RPMB) data.

[0020] In some implementations, the specific data becomes invalid when new data is written to the same logical address as the specific data.

[0021] In some implementations, the processor is configured to identify the first memory block by examining an indicator bit corresponding to the first memory block. This indicator bit indicates whether the first memory block contains invalid specific data.

[0022] In some implementations, the processor is configured to perform a first garbage collection operation on the first storage block by sending one or more commands to migrate valid data from the first storage block to a target storage block of the memory device and to erase the first storage block.

[0023] Another aspect of this disclosure is a method for operating a memory system. The method includes: identifying a first memory block among a plurality of memory blocks of a memory device in the memory system, wherein the first memory block includes invalid specific data; increasing the priority level of the first memory block among the plurality of memory blocks; and performing garbage collection on the memory device based on the priority level of the plurality of memory blocks.

[0024] Another aspect of this disclosure is a non-transitory computer-readable medium. This non-transitory computer-readable medium stores one or more instructions executable by a memory system to perform the following operations: identifying a first memory block among a plurality of memory blocks of a memory device of the memory system, wherein the first memory block includes invalid specific data; raising the priority level of the first memory block among the plurality of memory blocks; and performing garbage collection on the memory device based on the priority levels of the plurality of memory blocks.

[0025] While generally described as computer-implemented software embodied in the processing and transformation of corresponding data on a tangible medium, some or all aspects may be computer-implemented methods, or further included in a corresponding system or other apparatus for performing the described functions. These and other aspects of this disclosure, as well as details of embodiments, are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0026] Figure 1 A block diagram of an exemplary system having a memory device is shown.

[0027] Figures 2A-2B An example storage product is shown.

[0028] Figure 3An example of a schematic diagram of an exemplary memory device is shown.

[0029] Figure 4 Some exemplary peripheral circuits are shown.

[0030] Figure 5A A block diagram of an exemplary memory system including an exemplary memory controller is shown.

[0031] Figure 5B A block diagram of an exemplary memory controller is shown.

[0032] Figure 6 A swimlane diagram illustrating an exemplary process for handling a clear command is shown.

[0033] Figure 7 An exemplary technique for identifying storage blocks that contain invalid replay protected memory block (RPMB) data is shown.

[0034] Figure 8 An exemplary technique for performing garbage collection based on the priority level of storage blocks is shown.

[0035] Figure 9 A swimlane diagram illustrating another exemplary process for handling the clear command is shown.

[0036] The same reference numerals and names in the various figures denote the same elements. Detailed Implementation

[0037] This disclosure relates to memory devices, memory systems, and methods for processing erase commands. Replay Protected Block (RPMB) data is a type of security data that requires authentication upon access. A host can store sensitive and important information as RPMB data in a memory device. To further ensure the security of the RPMB data, the host can send an erase command to physically erase RPMB data that has become invalid from the memory device. In some cases, to process the erase command, the memory device needs to migrate valid data from a memory block containing invalid RPMB data to another memory block before erasing the block, which can be time-consuming.

[0038] Embodiments of this disclosure provide techniques for reducing the time required to process wipe commands. In some embodiments, the memory controller can be configured to identify memory blocks with invalid RPMB data and, for example, increase the priority level of such memory blocks by reducing their effective page count (VPC). The memory controller can be configured to perform garbage collection on the memory device based on the priority levels of multiple memory blocks in the memory device. Garbage collection can be performed when the memory device is idle and / or before a wipe command is received. Because memory blocks with invalid RPMB data have an increased priority level, more invalid RPMB data can be erased during garbage collection, resulting in less invalid RPMB data remaining to be erased when the memory controller receives a wipe command.

[0039] The described techniques can achieve one or more technical effects (e.g., technical advantages and / or benefits). For example, when the memory controller receives a erase command, there is less invalid RPMB data remaining to be erased compared to a case where the priority level of the memory block containing invalid RPMB data remains unchanged. This reduces the time spent processing the erase command. As another example, compared to a memory device allocating certain memory blocks to store only RPMB data, the described techniques allow RPMB data to be stored in the same memory block as normal data, which utilizes the memory space in the memory device more efficiently. Furthermore, the described techniques require no hardware modifications and minimal firmware changes in the memory controller, making them cost-effective. In some implementations, additional or different technical effects can be achieved.

[0040] This technology can be applied to various types of semiconductor devices, such as non-volatile memory (NVM) devices (e.g., NAND flash memory or NOR flash memory), volatile memory devices (e.g., DRAM memory devices), resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-torque-transfer (STT) magnetoresistive random access memory (MRAM), etc. It can also be applied to charge-trap-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate memory devices. This technology can be applied to three-dimensional (3D) memory devices. Furthermore, it can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Alternatively or concurrently, this technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), universal flash storage (UFS) or solid-state drives (SSD), embedded systems, etc.

[0041] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may include one or more processors of an electronic device. The processor may be a central processing unit (CPU) or a system-on-a-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data and commands to or receive data and commands from the memory system 102.

[0042] Memory device 104 can be any memory device disclosed in this disclosure, such as a NAND flash memory device. It should be noted that NAND flash memory is merely one example of a memory device for illustrative purposes. It can include any suitable solid-state non-volatile memory, such as NOR flash memory, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), spin-torque magnetic random access memory (STT-RAM), or resistive random access memory (RRAM), etc. In some embodiments, memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0043] The memory controller 106 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0044] According to some embodiments, memory controller 106 is coupled to memory device 104 and to host 108, and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and can communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as in SSDs or in embedded multimedia cards (eMMCs) used as data storage devices for mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, logical-to-physical mapping management, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) related to data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104.

[0045] The memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the external device through one or more interfaces using at least one of the following various interface protocols: USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), FireWire, etc. The memory controller 106 is configured to receive and send commands to the host 108, and to implement or perform various functions and operations provided in this disclosure, which will be described subsequently.

[0046] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices. For example, the memory controller 106 and one or more memory devices 104 can be packaged in a Universal Flash Storage (UFS) package or an eMMC package. Figure 2A In one example shown, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the memory card. In such a way... Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108 in the memory card 202. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202.

[0047] Figure 3 An example schematic diagram of a memory device 300 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are arranged in the form of an array of memory strings 308, each memory string 308 on a substrate ( Figure 3 (Not shown in the image) Extending vertically above. In some embodiments, each memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the storage layer of the memory cell 306. The logic state (i.e., data) of each memory cell 306 in the memory block 304 may be determined based on a threshold voltage Vth of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor or a charge-trap memory cell including a charge-trap transistor.

[0048] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible storage states capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than two storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to support a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0049] like Figure 3As shown, each memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 can be configured to activate the selected memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage or a deselection voltage to the corresponding SSG 310 via one or more SSG lines 315.

[0050] like Figure 3 As shown, the memory string 308 can be organized into multiple memory blocks 304, each of which can have a common SL 314 coupled to the ACS. In some embodiments, each memory block 304 can serve as a basic data unit for an erase operation, such that memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage can be used to bias the SL 314 coupled to both the selected and unselected memory blocks located in the same plane. For example, the erase voltage can be a high positive voltage (e.g., 20V or higher). In some embodiments, the erase operation can be performed at the half-block level, quarter-block level, or at any appropriate number of memory blocks or memory block fractions.

[0051] Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318. Word lines 318 can select which row of memory cells 306 is affected by read and program operations. Each word line 318 may include gate lines that are coupled to multiple control gates (gate electrodes) of multiple memory cells 306. Figure 3 The exemplary word lines shown are located between one or more DSG lines 313 and one or more SSG lines 315.

[0052] In some implementations, memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318. Word lines 318 can select which row of memory cells 306 is affected by read and program operations. In some implementations where memory cells 306 are SLC, a row of memory cells 306 can store one logical data page and therefore corresponds to one logical page. In some implementations where memory cells 306 are MLC, a row of memory cells 306 can store two logical data pages and therefore corresponds to two logical pages. In some implementations where memory cells 306 are TLC, a row of memory cells 306 can store three logical data pages and therefore corresponds to three logical pages. In some implementations where memory cells 306 are QLC, a row of memory cells 306 can store four logical data pages and therefore corresponds to four logical pages.

[0053] Each word line 318 may include a gate line coupled to a plurality of control gates (gate electrodes) of a plurality of memory cells 306. Figure 3 The exemplary word lines shown include WL0, WL1, ..., WLn-2, ​​WLn-1, and WLn located between DSG line 313 and SSG line 315. In some embodiments, the word lines may also include dummy word lines coupled to dummy memory cells.

[0054] Figure 4 Some exemplary peripheral circuitry 302 according to certain aspects of this disclosure is shown. Peripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, SL 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, SL 314, SSG line 315, and DSG line 313 and sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. Exemplary peripheral circuitry 302 includes a page buffer / sensing amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, a control logic unit 412, a register 414, an interface 416, and a data bus. In some examples, it may also include Figure 4 Additional peripheral circuitry not shown.

[0055] Page buffer / sensor amplifier 404 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 302 according to control signals from control logic unit 412. In one example, page buffer / sensor amplifier 404 can store a page of programming data (write data) to be programmed into memory cell array 301. In another example, page buffer / sensor amplifier 404 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 404 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 406 can be configured to be controlled by control logic unit 412 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 410.

[0056] The row decoder / word line driver 408 can be configured to be controlled by the control logic unit 412 and to select / deselect memory blocks 304 of the memory cell array 301 and word lines 318 of the memory blocks 304. The row decoder / word line driver 408 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 410. In some embodiments, the row decoder / word line driver 408 can also select / deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row decoder / word line driver 408 is configured to apply a programming voltage to the selected word line 318 during a programming operation on a memory cell 306 coupled to the selected word line 318.

[0057] Voltage generator 410 can be configured to be controlled by control logic unit 412 and generate word line voltages (e.g., read reference voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to provide to memory cell array 301.

[0058] Control logic unit 412 can be coupled to each of the aforementioned peripheral circuits and is configured to control the operation of each peripheral circuit. Register 414 can be coupled to control logic unit 412 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0059] Interface 416 can be coupled to control logic unit 412 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 412, as well as to buffer status information received from control logic unit 412 and relay it to the host. Interface 416 can also be coupled to column decoder / bit line driver 406 via data bus and acts as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 301.

[0060] Figure 5A This is a block diagram of an exemplary memory system 102, including an exemplary memory controller 106. The memory system 102 also includes a memory device 104. The memory system may be coupled to a host 108.

[0061] The memory controller 106 is configured to operate the memory device 104 upon request from the host 108. The memory controller 106 is configured to drive firmware for controlling the operation of the memory device 104. The memory controller 106 may include random access memory (RAM) 504, a processor 502, a front interface 506, error correction code (ECC) circuitry 507, and a back interface 508.

[0062] Memory controller 106 is configured to communicate with host 108 via front interface 506. For example, memory controller 106 can receive commands from host 108 and send responses to host 108 via front interface 506. Memory controller 106 is also configured to communicate with memory device 104 via rear interface 508. For example, memory controller 106 can send commands to memory device 104 and receive responses from memory device 104 via rear interface 508. Rear interface 508 may include a NAND flash memory interface or a NOR flash memory interface.

[0063] ECC circuit 507 is configured to process error correction codes associated with data read from or written to memory device 104. Exemplary error correction codes may include, but are not limited to, Hamming codes, Reed-Solomon codes, low-density parity-check (LDPC) codes, etc. In some embodiments, ECC circuit 507 includes an LPDC encoder configured to generate parity data based on LDPC codes for user data received from host 108, such that both user data and parity data can be sent to memory device 104 for storage. ECC circuit 507 may also include an LDPC decoder configured to decode data including user data and parity data. The ECC circuit can determine whether data stored in the block has been successfully read (e.g., without errors). If data stored in the block has been successfully read, the back interface 508 can forward the data to the front interface 506, so that the front interface 506 can return the data to host 108. However, if data stored in the memory block has not been successfully read, the back interface 508 can generate data describing read errors on the memory block.

[0064] RAM 504 is configured to serve as operating memory for processor 502, cache memory between memory device 104 and host 108, and / or buffer memory between memory device 104 and host 108.

[0065] Processor 502 is configured to control the operation of memory controller 106. Processor 502 is configured to control read operations, programming operations, erase operations, or other operations of memory device 104. In some embodiments, processor 502 may be used as flash translation layer (FTL) 510.

[0066] like Figure 5B As shown, the FTL 510 may include a bad block management module 512, an address translation module 514, a garbage collection (GC) module 516, and a wear leveling module 518. In some embodiments, the FTL 510 may include... Figure 5B Other modules not shown.

[0067] The bad block management module 512 can be configured to identify faulty memory blocks in the memory device 104 (e.g., by maintaining a bad block table). In some embodiments, memory blocks (e.g., Figure 3 The storage block (304) may fail due to various factors, including manufacturing defects, wear and tear from repeated use, or physical damage. During read or programming operations, the failed storage block can be skipped or replaced to prevent data corruption.

[0068] Address translation module 514 can be configured to translate or map (e.g., received from host 108) logical data blocks to physical space in memory device 104. In some embodiments, address translation module 514 can translate logical block addresses (LBAs) provided by host 108 into physical block addresses (PBAs) based on a logical-to-physical (L2P) mapping table. Various address mapping methods can exist for address translation module 514. Examples of address mapping methods include page mapping methods, block mapping methods, and hybrid mapping methods.

[0069] GC module 516 can be configured to migrate data from a source storage block to a target storage block, thereby erasing the source storage block for writing new data. For example, GC module 516 can be configured to select a source and a target storage block in memory device 104, read valid data from the source storage block by sending a read command to memory device 104, write valid data to the target storage block by sending a write command to memory device 104, and then erase the source storage block. In some embodiments, GC module 516 can be configured to perform foreground garbage collection on memory device 104, wherein garbage collection is performed when there are not enough storage blocks available for writing new data. In some embodiments, GC module 516 can perform background garbage collection on memory device 104, wherein garbage collection is performed when the memory device is idle (e.g., when there are no pending commands to be executed by the memory device).

[0070] In some implementations, GC module 516 performs garbage collection on memory device 104 based on the priority level of memory blocks in memory device 104. The priority level may be determined based on the effective page count (VPC) of the memory block, the number of erase / program (E / P) cycles the memory block has undergone, and / or other metrics. For example, garbage collection may migrate data from and erase a first memory block with a smaller VPC (which indicates that the first memory block has more invalid data) before migrating data from and erasing the second memory block.

[0071] Wear leveling module 518 can be configured to balance E / P cycles across storage blocks. For example, wear leveling module 518 can track the E / P cycle count for each storage block and write new data to the least used storage block first. Alternatively, wear leveling module 518 can move cold data (infrequently accessed data) to another storage block to ensure that different storage blocks wear out at a similar rate.

[0072] Figure 6 A swimlane diagram of an exemplary process 600 for processing commands (e.g., a clear command) is shown. Exemplary process 600 may be coupled to a host (e.g., Figure 1 and Figure 5A The memory system of the host 108 (e.g., Figure 1 The memory system 102 in the memory system executes the operation. The memory system may include a memory controller (e.g., Figures 1-2B and Figures 5A-5B The memory controller 106 in the memory and the memory block (e.g., Figure 3 The memory device (e.g., storage block 304) in the memory block 304) Figures 1-2B and Figure 5A The memory device 104 in, and Figures 3-4 (Memory device 300 in the middle).

[0073] At position 602, the host sends a command instructing the physical erasure of certain invalid data in the memory device. For example, this command could be a wipe command. When data is written to the memory device, the logical address of the data (e.g., LBA) is mapped to a physical address (e.g., PBA) in the physical space where the data is stored. When new data is written to replace previous data, the new data is associated with the same logical address, where the logical address is unmapped from the previous physical address, and the logical address is mapped to the physical address where the new data is stored. Thus, when new data is written to the same logical address, the data at the previous physical address becomes invalid.

[0074] In some implementations, a command (e.g., a clear command) instructs the physical erasure of specific invalid data (e.g., security data, authentication data, or priority data). In process 600, as an example, the command instructs the physical erasure of invalid Replay Protected Block (RPMB) data. RPMB data is a type of secure data that can be securely stored in a memory device (e.g., an eMMC or UFS memory device). Sensitive information (e.g., public keys, serial numbers, passwords, authentication credentials, etc., associated with fingerprint payments) can be stored as RPMB data in the memory device.

[0075] At step 604, the memory controller identifies a storage block containing invalid RPMB data as a source storage block. The memory device needs to perform an erase operation on the source storage block to physically erase the invalid RPMB data. In some implementations, RPMB data and normal data are stored together. That is, a storage block can store both RPMB data and normal data. Since the erase operation is typically performed at the block level, the memory device needs to migrate valid data (e.g., normal data) from the source storage block to another storage block (referred to as the target storage block) before erasing the invalid RPMB data by performing an erase operation on the source storage block.

[0076] At 606, the memory controller sends one or more read commands to read valid data from the source memory block. In response to receiving one or more read commands, the memory device sends valid data to the memory controller.

[0077] At 608, the memory controller sends one or more write commands to write valid data to one or more target memory blocks (e.g., free memory blocks). In response to receiving one or more write commands, the memory device programs the valid data into one or more target memory blocks.

[0078] At 610, the memory device erases the source memory block. In this way, invalid RPMB data is physically erased.

[0079] At 612, the memory controller sends a response to notify the host that invalid RPMB data has been erased and that the command (e.g., a clear command) has been completed.

[0080] In some cases, other commands received by the memory system may be delayed or rejected while a wipe command is still being processed (e.g., between operations 602 and 612). By erasing invalid RPMB data from multiple memory blocks, the memory system may need a considerable amount of time to process the wipe command, potentially causing a prolonged pause in normal operation of the memory system. In some cases, a wipe command may be executed on the memory device during background garbage collection, where garbage collection is performed when the memory device is idle (e.g., when there are no pending commands to be executed by the memory device).

[0081] Figure 7 Exemplary techniques for identifying memory blocks containing invalid RPMB data are illustrated. In some implementations, the memory controller may record an indicator bit (e.g., a purge_data_bit) corresponding to each memory block, wherein the indicator bit indicates whether the corresponding memory block has invalid RPMB data. For example, an indicator bit of 1 indicates that the corresponding memory block has invalid RPMB data, while an indicator bit of 0 indicates that the corresponding memory block does not have invalid RPMB data.

[0082] For example, first RPMB data (e.g., a password) is associated with logical address LBA0 and written to the first memory block (block A). Second RPMB data (e.g., an updated password) is written to the same logical address LBA0 to replace the first RPMB data. That is, the second RPMB data is also associated with logical address LBA0. The second RPMB data is then written to the second memory block (block B). This invalidates the first RPMB data, and the indicator bit corresponding to the first memory block is toggled from 0 to 1.

[0083] In some embodiments, indication bits corresponding to storage blocks in a memory device (e.g., in the form of a bitmap) are stored in a storage medium of a memory controller (e.g., Figure 5A the RAM 504 therein). The indication bits can be periodically sent to the memory device for storage to prevent data loss due to unexpected power outages.

[0084] In some embodiments, the indication bits can be used to indicate whether the corresponding storage block has other types of invalid specific data (e.g., security data, authentication data, or priority data) in addition to RPMB data.

[0085] Figure 8 An exemplary technique for performing garbage collection based on the priority level of storage blocks is shown. In some embodiments, the memory controller can identify a storage block having invalid RPMB data by checking the indication bits. The memory controller can further increase the priority level of the storage block. Thus, when the memory controller performs garbage collection based on the priority level of the storage blocks, the storage block with the increased priority level has a greater chance of being erased, and / or can be erased earlier than the storage blocks with lower priority.

[0086] For example, the memory controller performs garbage collection based on the VPC of the storage blocks, where the storage block with a smaller VPC is erased earlier than the storage block with a larger VPC. As Figure 8 shown, by checking the indication bits, the memory controller identifies the first storage block (block A) as a storage block having invalid RPMB data and the second storage block (block B) as a storage block not having invalid RPMB data. The VPCs of the first storage block and the second storage block are a% and b% respectively, where a > b. The memory controller increases the priority of block A by reducing the VPC value Δ of block A such that the VPC of block A becomes (a% - Δ). In some embodiments, the memory controller can decide whether to perform garbage operation on block A or block B first by comparing the difference between a% and b% (i.e., (a% - b%)) and the threshold Δ. If (a% - b%) < Δ, the memory controller performs garbage collection on block A before block B. After erasing block A, the indication bit corresponding to block A flips from 1 to 0. If (a% - b%) ≥ Δ, the memory controller performs garbage collection on block B before block A. In some embodiments, the memory controller can decide whether to perform garbage operation on block A or block B first by comparing (a% - Δ) and b%. If (a% - Δ) < b%, the memory controller performs garbage collection on block A before block B. After erasing block A, the indication bit corresponding to block A flips from 1 to 0. If (a% - Δ) ≥ b%, the memory controller performs garbage collection on block B before block A.

[0087] The VPC of all memory blocks with invalid RPMB data can be reduced by the same value Δ. Thus, when the memory controller determines the order in which memory blocks to perform garbage collection, the memory block with invalid RPMB data can typically be moved up in the order. In some implementations, to determine the next memory block to perform garbage collection, the memory controller can select the memory block with the smallest VPC from a first group of memory blocks with corresponding indicator bits set to 1 (e.g., block C, whose VPC is c%), and select the memory block with the smallest VPC from a second group of memory blocks with corresponding indicator bits set to 0 (e.g., block D, whose VPC is d%). By comparing (c% - Δ) and d%, the memory controller can determine the next memory block to perform garbage collection. In some implementations, to determine the next memory block to perform garbage collection, the memory controller can reduce the VPC of all memory blocks with indicator bits set to 1 by Δ, and select the lowest VPC from the two groups of memory blocks.

[0088] The value Δ can be predetermined by taking into account factors such as the lifetime of the memory device (e.g., E / P cycles) and performance (e.g., read and write speeds). For example, the value Δ can be set between 5% and 10%, or set to other appropriate percentages or numbers. In some implementations, the memory controller can adjust the value Δ over time, for example, as the memory device enters a later E / P cycle.

[0089] Figure 9 A swimlane diagram of an exemplary process 900 for processing commands (e.g., a clear command) is shown. The exemplary process 900 may be coupled to a host (e.g., Figure 1 and Figure 5A The memory system of the host 108 (e.g., Figure 1 The memory system 102 in the memory system executes the operation. The memory system may include a memory controller (e.g., Figures 1-2B and Figures 5A-5B The memory controller 106 and the memory device (e.g., Figures 1-2B and Figure 5A The memory device 104 in, and Figures 3-4 The memory device 300 includes multiple memory blocks (e.g., memory devices 30 ... Figure 3 (Storage block 304 in the middle).

[0090] The operations shown in process 900 may not be exhaustive; other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 9 The different sequences of execution are shown. In some implementations, some operations may be performed by one or more components of the device or system, such as the memory controller or peripheral circuitry of the memory device.

[0091] At 902, the memory controller identifies the first memory block with invalid RPMB data, for example, by checking the indicator bits corresponding to the multiple memory blocks.

[0092] At position 904, the memory controller increases the priority level of the first memory block. The memory controller can perform garbage collection based on the priority levels of multiple memory blocks, where memory blocks with higher priority levels are erased earlier than memory segments with lower priority levels. In some implementations, priority levels are determined based on the VPC of each memory block. Memory blocks with smaller VPCs have higher priority levels. The memory controller can increase the priority level of the first memory block by decreasing its VPC.

[0093] At 906, the memory controller performs garbage collection (e.g., background garbage collection) on the memory device based on the priority levels of multiple memory blocks. Thus, a first memory block with an increased priority level has a greater chance of being erased during garbage collection compared to a case where the priority level of the first memory block remains unchanged. In some implementations, to perform garbage collection on the first memory block, the memory controller sends one or more read commands to read valid data from the first memory block and sends one or more write commands to write valid data to a target memory block (e.g., a free memory block). The first memory block can then be erased. During the process of migrating data from the first memory block to the target memory block, the VPC of the first memory block is updated to reflect the amount of valid data remaining in the first memory block. If the current garbage collection duration is insufficient to migrate all valid data from the first memory block, the priority level of the first memory block will be increased in the next garbage collection because the VPC of the first memory block will decrease.

[0094] At 908, the host sends a command instructing the physical erasure of certain invalid data (e.g., invalid RPMB data) in the memory device. For example, this command could be a wipe command. Since the memory block containing invalid RPMB data (e.g., the first memory block) has a greater chance of being erased before the command is received during garbage collection at operation 906, there is less invalid RPMB data remaining to be erased after the command is received. This reduces the time required to process the command.

[0095] In some implementations, during garbage collection at operation 906 (e.g., when the memory device is idle and / or before a erase command is received), all invalid RPMB data is erased, causing the indicator bits for all memory blocks to show 0, indicating that no memory block has invalid RPMB data. In this case, at 910, the memory controller sends a response to the host to notify the host that invalid RPMB data has been erased and that the command received at 908 has been completed.

[0096] In some implementations, a portion of the invalid RPMB data is erased during garbage collection at operation 906, while another portion remains to be erased. The indicator bit corresponding to the memory block that no longer contains invalid RPMB data is displayed as 0. The indicator bit corresponding to the memory block that still contains invalid RPMB data is displayed as 1. In this case, the memory controller can migrate valid data from the memory block with the indicator bit set to 1 to one or more target memory blocks and erase these memory blocks. After erasing all invalid RPMB data, at 910, the memory controller sends a response to the host to notify the host that the invalid RPMB data has been erased and that the command received at 908 has been completed.

[0097] This disclosure also provides a non-transitory computer-readable storage medium. This non-transitory computer-readable storage medium stores one or more instructions (e.g., firmware of a memory controller) executable by a computer system. When executed by a computer system, the instructions in the storage medium can be implemented as described in the reference. Figures 1-9 The methods discussed are for processing commands (e.g., clear commands) in a memory system.

[0098] The non-transitory computer-readable storage medium can be the internal storage of any of the devices described in the foregoing embodiments. For example, the non-transitory computer-readable storage medium can be a hard disk or the device's internal memory. The non-transitory computer-readable storage medium can also be an external storage device of the device, such as an insertable hard disk, a smart media card (SMC), a secure digital card (SD), a flash memory card, etc. Furthermore, the non-transitory computer-readable storage medium can also include both internal storage and external storage devices.

[0099] While this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of the claims, but rather as descriptions of features that may be implemented for particular embodiments. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any sub-combination in multiple embodiments. Furthermore, although the foregoing features may be described as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0100] As used in this disclosure, unless the context clearly indicates otherwise, the terms "a" or "described" are used to include one or more. Unless otherwise specified, the term "or" is used to mean a non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". Furthermore, the wording or terms used in this disclosure unless otherwise defined are for descriptive purposes only and not for limiting purposes. Any use of section headings is intended to aid in reading this document and should not be construed as limiting; information relating to section headings may appear within or outside that particular section.

[0101] As used in this disclosure, the terms “about” or “approximately” may allow for a degree of variability in the value or range, for example, within 10%, 5%, or 1% of the limits of the stated value or range.

[0102] As used in this disclosure, the term “substantially” means majority or most, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999%, or greater.

[0103] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical values ​​explicitly stated as the limits of the range, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly stated. For example, a range of “0.1% to about 5%” or “0.1% to 5%” should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise specified, the statement “X to Y” has the same meaning as “about X to about Y”. Similarly, unless otherwise specified, the statement “X, Y, or Z” has the same meaning as “about X, about Y, or about Z”.

[0104] Specific embodiments of the subject matter have been described. Other embodiments, alternatives, and substitutions of the described embodiments will be apparent to those skilled in the art and fall within the scope of the following claims. Although operations are depicted in a specific order in the drawings and claims, it is not required that these operations be performed in the specific order or sequential order shown, or that all of the shown operations be performed (some operations may be considered optional), in order to achieve the desired results. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and implemented where deemed appropriate.

[0105] Furthermore, the separation or integration of various system modules and components in the foregoing embodiments is not necessary in all embodiments, and the described components and systems can generally be integrated together or packaged into multiple products.

[0106] Therefore, the foregoing exemplary embodiments do not limit or restrict this disclosure. Other changes, substitutions, and modifications are also possible without departing from the spirit and scope of this disclosure.

Claims

1. A memory system, comprising: A memory device comprising a plurality of memory blocks; as well as A memory controller coupled to the memory device, wherein the memory controller is configured to: Identify a first storage block among the plurality of storage blocks, wherein the first storage block includes invalid specific data; Increase the priority level of the first storage block among the plurality of storage blocks; and Garbage collection is performed on the memory device based on the priority levels of the plurality of storage blocks.

2. The memory system of claim 1, wherein, The specific data includes replay protected memory block (RPMB) data.

3. The memory system according to claim 1 or 2, wherein, When new data is written to the same logical address as the specific data, the specific data becomes invalid.

4. The memory system according to any one of claims 1 to 3, wherein, The memory controller is configured to: The first storage block is identified by checking the indicator bit corresponding to the first storage block. The indicator bit indicates whether the first storage block contains invalid specific data.

5. The memory system according to any one of claims 1 to 4, wherein, The memory controller is configured to: The priority level of the first storage block is increased by reducing the first effective page count (VPC) of the first storage block; and Before the second storage block has a second VPC that is larger than the first VPC, a first garbage collection operation is performed on the first storage block.

6. The memory system according to any one of claims 1 to 5, wherein, The memory controller is configured to: Receive a clear command to erase invalid specific data in the memory device; and Send a response indicating that the invalid specific data in the memory device has been erased.

7. The memory system according to claim 6, wherein, The memory controller is configured to: Before receiving the erase command, the invalid specific data in the corresponding storage block is erased during the garbage collection.

8. The memory system according to any one of claims 1 to 7, wherein, The memory controller is configured to: When the memory device is idle, the garbage collection is performed on the memory device.

9. The memory system according to any one of claims 1 to 8, wherein, The memory controller is configured to: A first garbage collection operation is performed on the first storage block by sending one or more commands to migrate valid data from the first storage block to a target storage block of the memory device and to erase the first storage block.

10. A memory controller, comprising: processor; as well as A first interface, configured to be coupled to a memory device. The processor is configured to perform garbage collection on the memory device based on the priority levels of multiple memory blocks within the memory device, and The first interface is configured as follows: Send one or more read commands to read valid data from a first storage block among the plurality of storage blocks, wherein the first storage block includes invalid specific data, and wherein, among the plurality of storage blocks, the first storage block has an elevated priority level based on the fact that the first storage block includes the invalid specific data; and Send one or more write commands to write the valid data read from the first storage block into the target storage block of the memory device.

11. The memory controller according to claim 10, wherein, The processor is configured to: Identify the first storage block from the plurality of storage blocks; and Increase the priority level of the first storage block among the plurality of storage blocks.

12. The memory controller according to claim 11, wherein, The processor is configured to: The priority level of the first storage block is increased by reducing the first effective page count (VPC) of the first storage block; and Before the second storage block has a second VPC that is larger than the first VPC, a first garbage collection operation is performed on the first storage block.

13. The memory controller according to any one of claims 10 to 12, wherein, The memory controller includes a second interface coupled to the host, wherein the second interface is configured to: Receive a clear command to erase invalid specific data in the memory device; and Send a response indicating that the invalid specific data in the memory device has been erased.

14. The memory controller according to claim 13, wherein, The processor is configured to erase the invalid specific data in the corresponding storage block during the garbage collection process before receiving the erase command.

15. The memory controller according to any one of claims 10 to 14, wherein, The processor is configured to perform the garbage collection on the memory device when the memory device is idle.

16. The memory controller according to any one of claims 10 to 15, wherein, The specific data includes replay protected memory block (RPMB) data.

17. The memory controller according to any one of claims 10 to 16, wherein, When new data is written to the same logical address as the specific data, the specific data becomes invalid.

18. The memory controller according to any one of claims 10 to 17, wherein, The processor is configured to: The first storage block is identified by examining an indicator bit corresponding to it, wherein the indicator bit indicates whether the first storage block contains invalid specific data.

19. The memory controller according to any one of claims 10 to 18, wherein, The processor is configured to: A first garbage collection operation is performed on the first storage block by sending one or more commands to migrate valid data from the first storage block to a target storage block of the memory device and to erase the first storage block.

20. A method of operating a memory system, comprising: Identify a first storage block among a plurality of storage blocks of the memory device of the memory system, wherein the first storage block includes invalid specific data; Increase the priority level of the first storage block among the plurality of storage blocks; and Garbage collection is performed on the memory device based on the priority levels of the plurality of storage blocks.

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