An FPGA programming fixture

Abstract

The application provides an FPGA programming fixture, which comprises a programming motherboard and a replaceable sub-module; the programming motherboard comprises a main controller, an upper computer communication interface and a plug-in surge protection structure; the plug-in surge protection structure comprises a physical connection detection module, a timing control module and a surge absorption unit; the physical connection detection module is used for detecting the physical connection state between the replaceable sub-module and a mainboard to be programmed; the timing control module is connected with the main controller and the physical connection detection module respectively, and is connected with a standard interface slot through a ground wire path, a power supply path and a signal path, and is used for controlling the on-off timing of the ground wire path, the power supply path and the signal path according to the physical connection state between the replaceable sub-module and the mainboard to be programmed; the surge absorption unit is connected in series with the power supply path and is used for absorbing the inrush current at the power-on moment; and the replaceable sub-module comprises a standard interface end, a target interface end and a level conversion unit.

Description

Technical Field

[0001] This invention relates to the field of chip programming technology, and in particular to an FPGA programming fixture. Background Technology

[0002] During the research, development, mass production, and repair of FPGAs (Field-Programmable Gate Arrays), they need to be integrated onto PCBs (Printed Circuit Boards) for in-circuit programming. Traditional programming methods involve connecting a general-purpose programmer using jumper wires. This method is prone to inrush current when hot-plugging the programming wires, and since the I / O ports of FPGA chips have limited voltage tolerance, inrush current can easily damage the internal ESD protection diodes or I / O banks, leading to chip damage. Furthermore, while some FPGA-specific programming fixtures exist, these fixtures are only compatible with a single motherboard. Therefore, different dedicated programming fixtures are required for different FPGAs, resulting in a large number of different dedicated programming fixtures being needed by the R&D and production departments, leading to high costs and management difficulties. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a highly adaptable FPGA programming fixture that can avoid damage from surge current during hot-plugging.

[0004] To address the aforementioned technical problems, this invention provides an FPGA programming fixture, comprising a programming motherboard and replaceable sub-modules; The programming master board includes: Main controller; The host computer communication interface is connected to the main controller and is used to communicate with the host computer to receive and burn data. A standard interface slot for connecting the replaceable submodule; The surge protection structure includes a physical connection detection module, a timing control module, and a surge absorption unit. The physical connection detection module detects the physical connection status between the replaceable submodule and the motherboard to be programmed. The timing control module is connected to the main controller and the physical connection detection module, and is connected to the standard interface slot through a ground path, a power path, and a signal path. It controls the on / off timing of the ground path, the power path, and the signal path according to the physical connection status between the replaceable submodule and the motherboard to be programmed. The surge absorption unit is connected in series with the power path to absorb the surge current at the moment of power-on. The replaceable submodule includes: The standard interface terminal is used to connect to the standard interface slot of the programming motherboard and receive programming data sent by the main controller. The target interface is used to connect to the motherboard to be programmed and send the programming data to the motherboard for programming. The level conversion unit is connected to the standard interface and the target interface respectively. It receives the level configuration command of the motherboard through the standard interface, converts the first level output by the main controller into the second level required by the motherboard to be programmed, and outputs it to the motherboard to be programmed through the target interface.

[0005] Furthermore, the timing control module controls the on / off timing of the ground path, the power path, and the signal path as follows: When the physical connection between the replaceable submodule and the motherboard to be programmed is in place, the ground path is first connected, the power path is connected after a first preset delay, and the signal path is connected after a second preset delay. When the physical connection between the replaceable submodule and the motherboard to be programmed is disconnected, the signal path is first cut off, the power path is cut off after a third preset delay, and the ground path is cut off after a fourth preset delay.

[0006] Furthermore, the programming motherboard includes a submodule information identification unit, which is connected to the main controller and the standard interface slot respectively. It is used to identify the identification information, supported level range information and programming timing parameter information of the replaceable submodules connected to the standard interface slot, and send them to the main controller.

[0007] Furthermore, the physical connection detection module includes a micro switch, which is located on the programming motherboard at the position of the replaceable sub-module.

[0008] Furthermore, the surge absorption unit includes a transient voltage suppression diode and a power inductor, wherein the power inductor is connected in series with the power supply path and the transient voltage suppression diode is connected in parallel with the power inductor.

[0009] This invention offers the following advantages: The FPGA programming fixture employs a programming motherboard and replaceable sub-modules, allowing a single programming motherboard to be adapted to sub-modules with different programming interfaces, thus accommodating different FPGA motherboards. During the programming process, when hot-plugging replaceable sub-modules, the surge protection structure, through physical detection and timing control, achieves an ideal hot-plug sequence of grounding first, then power, and finally signal. Combined with the surge absorption unit, it effectively suppresses current surges during insertion and removal, significantly reducing the FPGA programming failure rate. Attached Figure Description

[0010] Figure 1 This is a connection frame diagram of the FPGA programming fixture.

[0011] Explanation of reference numerals in the attached diagram: 1. Programming motherboard; 2. Replaceable sub-module; 3. Motherboard to be programmed; 11. Main controller; 12. Host computer communication interface; 13. Standard interface slot; 14. Anti-plugging surge structure; 15. Sub-module information identification unit; 141. Physical connection detection module; 142. Timing control module; 143. Surge absorption unit; 144. Ground path; 145. Power path; 146. Signal path; 21. Standard interface terminal; 22. Target interface terminal; 23. Level conversion unit. Detailed Implementation

[0012] The present invention will be further described in detail below with reference to specific embodiments.

[0013] This embodiment provides an FPGA programming fixture, such as Figure 1 As shown, the FPGA programming fixture includes a programming motherboard 1 and a replaceable sub-module 2. The programming motherboard 1 and the replaceable sub-module 2 are interconnected, and the replaceable sub-module 2 is used to connect to the motherboard 3 to be programmed. The connection between the programming motherboard 1 and the replaceable sub-module 2 is detachable. There are multiple types of replaceable sub-module 2, each corresponding to different types of FPGA motherboards 3 to be programmed. The replaceable sub-module 2 can be detached from the programming motherboard 1 and replaced with different types of replaceable sub-module 2, thereby changing the connection to different types of motherboards 3 to be programmed.

[0014] The programming motherboard 1 includes a main controller 11, a host computer communication interface 12, a standard interface slot 13, a surge protection structure 14, and a submodule information identification unit 15. Specifically, the main controller 11 is a master control MCU (Microcontroller Unit) used to parse programming data and control signal routing. The host computer communication interface 12 is specifically a USB 3.0 interface or an Ethernet interface, connected to the main controller 11, used to communicate with the host computer and receive programming data sent by the programming software. The standard interface slot 13 adopts a PCIe gold finger structure or a high-density pin header structure, used to connect replaceable submodules 2. The submodule information identification unit 15 is connected to both the main controller 11 and the standard interface slot 13, used to identify the identification information, supported voltage level range information, and programming timing parameter information of the replaceable submodule 2 connected to the standard interface slot 13, and send this information to the main controller 11.

[0015] The surge protection structure 14 includes a physical connection detection module 141, a timing control module 142, and a surge absorption unit 143. The physical connection detection module 141 specifically includes a microswitch located on the motherboard 1 at the position where the replaceable sub-module 2 is engaged. Specifically, it is installed on the edge of the slot for inserting the replaceable sub-module 2 and is used to detect the physical connection status between the replaceable sub-module 2 and the motherboard 3 to be programmed. The timing control module 142 is connected to the main controller 11 and the physical connection detection module 141, and is connected to the standard interface slot 13 via a ground path 144, a power path 145, and a signal path 146. The surge absorption unit 143 is connected in series with the power path 145 and specifically includes a transient voltage suppression diode and a power inductor. The power inductor is connected in series with the power path 145, and the transient voltage suppression diode is connected in parallel with the power inductor, used to absorb the surge current at the moment of power-on.

[0016] The timing control module 142 is used to control the on / off timing of the ground path 144, power path 145, and signal path 146 according to the physical connection status between the replaceable submodule 2 and the motherboard 3 to be programmed. Specifically, when the physical connection status between the replaceable submodule 2 and the motherboard 3 to be programmed is "connected in place", the ground path 144 is connected first, the power path 145 is connected after a first preset delay (e.g., 5ms), and the signal path 146 is connected after a second preset delay (e.g., 10ms). When the physical connection status between the replaceable submodule 2 and the motherboard 3 to be programmed is "disconnected", the signal path 146 is disconnected first, the power path 145 is disconnected after a third preset delay (e.g., 10ms), and the ground path 144 is disconnected after a fourth preset delay (e.g., 5ms).

[0017] The replaceable submodule 2 includes a standard interface terminal 21, a target interface terminal 22, and a level conversion unit 23. The standard interface terminal 21 connects to the standard interface slot 13 of the programming motherboard 1. It adopts a PCIe-style gold finger structure or a high-density pin header structure corresponding to the standard interface slot 13, and receives programming data from the main controller 11 through the standard interface slot 13. The target interface terminal 22 connects to the motherboard 3 to be programmed, and sends programming data to the motherboard 3 for programming. The level conversion unit 23 is specifically an onboard programmable level conversion chip, which connects to both the standard interface terminal 21 and the target interface terminal 22. It receives the level configuration command from the programming motherboard 1 through the standard interface terminal 21, converts the default first level (generally 3.3V) output by the main controller 11 to the second level required by the motherboard 3 to be programmed (commonly 1.8V or 5V), and outputs it to the motherboard 3 to be programmed for configuration through the target interface terminal 22. The replaceable submodule 2 has a built-in EEPROM, which is used to store the identification information of the replaceable submodule 2, the supported level range information, and the programming timing parameter information. The main controller 11 reads this information through the submodule information identification unit 15, the standard interface slot 13, and the standard interface terminal 21 to automatically complete the configuration.

[0018] In this embodiment, during the use of the FPGA programming fixture, the operator selects the corresponding replaceable submodule 2 according to the programming port type of the motherboard 3 to be programmed (e.g., a 10-pin 1.27mm JTAG interface with a 1.8V level). First, the motherboard 3 to be programmed is inserted into the target interface terminal 22 of the replaceable submodule 2, and then the standard interface terminal 21 of the replaceable submodule 2 is inserted into the standard interface slot 13 of the programming motherboard 1. After the programming motherboard 1 is powered on, the main controller 11 reads the identification information, supported level range information, and programming timing parameter information of the replaceable submodule 2 through the submodule information identification unit 15, the standard interface slot 13, and the standard interface terminal 21. After the main controller 11 parses the required level (1.8V) of the replaceable submodule 2, the main controller 11 then controls the enable pin of the level conversion unit 23 to set its output voltage to 1.8V, so that the level of the main controller 11 is compatible with that of the motherboard 3 to be programmed. At this time, the physical connection detection module 141 on the programming motherboard 1 is physically triggered by the edge of the motherboard 3 to be programmed, and sends a "connection in place" signal to the timing control module 142. After receiving the signal, the timing control module 142 executes the following timing sequence: first, the ground path 144 is turned on; after 5ms, the power path 145 is turned on, so that the transient voltage suppression diode in the surge absorption unit 143 enters the standby state, and the power inductor is pre-magnetized. At this time, since the ground path 144 has been turned on first and the surge absorption unit 143 has been activated, any surge current generated by contact jitter or capacitor charging is limited and absorbed by the surge absorption unit 143 and will not impact the power pin of the FPGA; after another 10ms, the signal path 146 is turned on. At this time, the main controller 11 performs the programming operation, and transmits the programming data sent by the host computer to the motherboard 3 to be programmed on the replaceable submodule 2 through the stable signal path 146 for programming. After the programming is completed, the operator can directly unplug the replaceable submodule 2 or the motherboard 3 to be programmed. When the physical connection detection module 141 detects the disconnection, the timing control module 142 sends a "connection disconnected" signal to the timing control module 142. After receiving the signal, the timing control module 142 executes the following timing sequence: first, the signal path 146 is cut off, then the power path 145 is cut off after 10ms, and then the ground path 144 is cut off after 5ms, to ensure that no induced electromotive force is generated when the module is unplugged.

[0019] This embodiment of the FPGA programming fixture adopts a structure of programming motherboard 1 and replaceable sub-modules 2, so that one programming motherboard 1 can be adapted to replaceable sub-modules 2 with different programming interfaces to adapt to different FPGA motherboards. During the programming process, when the replaceable sub-modules 2 are hot-plugged, the anti-plug surge structure 14 can achieve an ideal hot-plug sequence of ground first, then power, and then signal through physical detection and timing control. In conjunction with the surge absorption unit 143, it can effectively suppress the current surge at the moment of insertion and removal, and can effectively reduce the FPGA programming damage rate.

[0020] The above description is merely an embodiment of the present invention and does not limit the scope of patent protection. Any non-substantial changes or substitutions made by those skilled in the art based on the present invention will still fall within the scope of patent protection.

Claims

1. An FPGA programming fixture, characterized in that, Includes a programming motherboard (1) and replaceable sub-modules (2); The programming motherboard (1) includes: Main controller (11); The host computer communication interface (12) is connected to the main controller (11) and is used to communicate with the host computer to receive and burn data. Standard interface slot (13) for connecting the replaceable submodule (2); The surge protection structure (14) includes a physical connection detection module (141), a timing control module (142), and a surge absorption unit (143). The physical connection detection module (141) is used to detect the physical connection status between the replaceable submodule (2) and the motherboard (3) to be programmed. The timing control module (142) is connected to the main controller (11) and the physical connection detection module (141) respectively, and is connected to the standard interface slot (13) through a ground path (144), a power path (145), and a signal path (146). It is used to control the on / off timing of the ground path (144), the power path (145), and the signal path (146) according to the physical connection status between the replaceable submodule (2) and the motherboard (3) to be programmed. The surge absorption unit (143) is connected in series with the power path (145) to absorb the surge current at the moment of power-on. The replaceable submodule (2) includes: The standard interface terminal (21) is used to connect to the standard interface slot (13) of the programming motherboard (1) and receive programming data sent by the main controller (11); The target interface (22) is used to connect to the motherboard (3) to be programmed and send the programming data to the motherboard (3) to be programmed. The level conversion unit (23) is connected to the standard interface terminal (21) and the target interface terminal (22) respectively. It receives the level configuration command of the motherboard (1) through the standard interface terminal (21), converts the first level output by the main controller (11) into the second level required by the motherboard (3) to be burned, and outputs it to the motherboard (3) to be burned through the target interface terminal (22).

2. The FPGA programming fixture according to claim 1, characterized in that, The timing control module (142) controls the on / off timing of the ground path (144), the power path (145), and the signal path (146) as follows: When the physical connection between the replaceable submodule (2) and the motherboard to be programmed (3) is in place, the ground path (144) is first connected, the power path (145) is connected after the first preset delay, and the signal path (146) is connected after the second preset delay. When the physical connection between the replaceable submodule (2) and the motherboard to be programmed (3) is disconnected, the signal path (146) is cut off first, the power path (145) is cut off after a third preset delay, and the ground path (144) is cut off after a fourth preset delay.

3. The FPGA programming fixture according to claim 1, characterized in that, The programming motherboard (1) includes a sub-module information identification unit (15), which is connected to the main controller (11) and the standard interface slot (13) respectively. It is used to identify the identification information, supported level range information and programming timing parameter information of the replaceable sub-module (2) connected to the standard interface slot (13), and send it to the main controller (11).

4. The FPGA programming fixture according to claim 1, characterized in that, The physical connection detection module (141) includes a micro switch, which is located on the programming motherboard (1) in conjunction with the replaceable submodule (2).

5. The FPGA programming fixture according to claim 1, characterized in that, The surge absorption unit (143) includes a transient voltage suppression diode and a power inductor, the power inductor being connected in series with the power supply path (145), and the transient voltage suppression diode being connected in parallel with the power inductor.

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