Chip failure analysis method, system and electronic device

Abstract

This application provides a chip failure analysis method, system, and electronic device. The method includes: obtaining first data and second data of an abnormal chip; the first data characterizing the electrical abnormality features of the abnormal chip; the second data characterizing the three-dimensional structure of the abnormal chip; determining the failure region distribution based on the first and second data; the failure region distribution characterizing the probability region distribution of abnormal points within the abnormal chip; the abnormal point being the location of a physical defect in the three-dimensional structure that causes the electrical abnormality features; obtaining a first image of the abnormal chip; the first image being a three-dimensional image; and determining the abnormal structure involved in the abnormal points in the abnormal chip through failure analysis based on the failure region distribution and the first image.

Description

Technical Field

[0001] This application relates to the field of chip manufacturing technology, and in particular to a chip failure analysis method, system, and electronic device. Background Technology

[0002] In the process of chip failure analysis, it is necessary to accurately determine the location of the defect that causes the chip abnormality in order to carry out subsequent root cause analysis and verification. However, existing failure analysis methods have problems such as a wide analysis range and unclear target area when locating abnormal locations, resulting in insufficient accuracy in failure location. Summary of the Invention

[0003] In view of this, this application provides a chip failure analysis method, system, and electronic device to overcome the shortcomings of the prior art.

[0004] According to a first aspect of this application, a chip failure analysis method is provided, comprising: obtaining first data and second data of an abnormal chip; the first data characterizing the electrical abnormality features of the abnormal chip; the second data characterizing the three-dimensional structure of the abnormal chip; determining the failure region distribution based on the first data and the second data; the failure region distribution characterizing the probability region distribution of abnormal points within the abnormal chip; the abnormal point being the location of a physical defect in the three-dimensional structure that causes the electrical abnormality features; obtaining a first image of the abnormal chip; the first image being a three-dimensional image; and determining the abnormal structure involved in the abnormal point in the abnormal chip through failure analysis based on the failure region distribution and the first image.

[0005] A second aspect of this application provides a chip failure analysis system for implementing the aforementioned chip failure analysis method, comprising: a data acquisition module for acquiring first data and second data of an abnormal chip; the first data characterizing the electrical abnormality features of the abnormal chip; the second data characterizing the three-dimensional structure of the abnormal chip; a distribution determination module for determining the failure region distribution based on the first data and the second data; the failure region distribution characterizing the probability region distribution of abnormal points within the abnormal chip; the abnormal point being the location of a physical defect in the three-dimensional structure that causes the electrical abnormality features; an image acquisition module for acquiring a first image of the abnormal chip; the first image being a three-dimensional image; and a structure determination module for determining the abnormal structure involved in the abnormal points in the abnormal chip through failure analysis based on the failure region distribution and the first image.

[0006] A third aspect of this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a failure analysis method for any of the chips described above.

[0007] The beneficial effects of this application are at least as follows:

[0008] By adopting the technical solution of this application, firstly, first data characterizing the electrical abnormality features of the abnormal chip and secondly, secondly, secondly, the three-dimensional structure of the abnormal chip are obtained. Then, based on the first and second data, the distribution of failure regions is determined. This distribution of failure regions characterizes the probability distribution of abnormal points within the abnormal chip. Thus, before failure analysis, the regions where abnormal points may exist can be narrowed from the entire chip range to specific regions with higher probabilities based on the correlation between electrical abnormality features and the three-dimensional structure, effectively reducing the analysis scope and clarifying the target region. Furthermore, after obtaining the first image of the abnormal chip, the first image is analyzed in a targeted manner based on the determined distribution of failure regions. This allows the failure analysis process to focus on regions with higher probabilities rather than performing indiscriminate searches across the entire chip, significantly improving the efficiency of failure localization. At the same time, since the distribution of failure regions integrates electrical abnormality features and three-dimensional structural information, the finally determined abnormal structure can simultaneously satisfy electrical correlation and spatial rationality, thereby improving the accuracy of failure localization and solving the problems of wide analysis scope, unclear target regions, low failure localization efficiency, and insufficient accuracy in existing failure analysis methods.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0010] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a schematic flowchart of a chip failure analysis method provided in an embodiment of this application;

[0012] Figure 2 An X-ray imaging image of a chip's three-dimensional structure provided in this application embodiment;

[0013] Figure 3 A partial enlarged view of a candidate abnormal connected body provided in an embodiment of this application;

[0014] Figure 4 A cross-sectional view of an abnormal conduction structure provided in an embodiment of this application;

[0015] Figure 5 A high-resolution cross-sectional view after physical verification is provided for an embodiment of this application;

[0016] Figure 6 A schematic diagram of the structure of a chip failure analysis system provided in an embodiment of the present invention;

[0017] Figure 7 This is a schematic diagram of the physical structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0018] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0019] Figure 1 A flowchart illustrating a chip failure analysis method provided in an embodiment of this application is shown.

[0020] like Figure 1 As shown, the failure analysis method for this chip includes steps S101 to S104.

[0021] Step S101: Obtain first data and second data of the abnormal chip; the first data characterizes the electrical abnormality characteristics of the abnormal chip; the second data characterizes the three-dimensional structure of the abnormal chip.

[0022] Step S102: Determine the failure region distribution based on the first data and the second data; the failure region distribution characterizes the probability region distribution of abnormal points within the abnormal chip; abnormal points are the physical defect locations in the three-dimensional structure that cause electrical abnormalities.

[0023] Step S103: Obtain the first image of the abnormal chip; the first image is a three-dimensional image;

[0024] Step S104: Based on the failure area distribution and the first image, the abnormal structure involved in the abnormal point in the abnormal chip is determined through failure analysis.

[0025] In step S101, the abnormal chip refers to a chip sample that has been found to have functional abnormalities, performance abnormalities, or reliability abnormalities after preliminary screening or testing. It can be understood as an object to be analyzed that needs to undergo failure analysis to determine the cause of the abnormality.

[0026] For example, the abnormal chip may include, but is not limited to, chip products in various packaging forms such as system-in-package chips, multilayer substrate packaged chips, flip chips, and three-dimensional stacked chips, and may also include chip samples that have failed in reliability testing, mass production or actual application.

[0027] Among them, the first data of the abnormal chip refers to the measurement data or test results that can reflect the abnormal electrical performance of the abnormal chip.

[0028] For example, the first data of the abnormal chip may include, but is not limited to: resistance test data between pins, current and voltage characteristic curve data, electrical parameter data under different temperature conditions, specific pin location information for short circuit or open circuit, identification information of abnormal network, etc.

[0029] Similarly, the second data of the abnormal chip refers to the information describing the internal physical structure and layout of the abnormal chip. It can be understood as a data description of the spatial structure such as the internal interconnect structure, hierarchical relationship, wiring path, and via location.

[0030] The second data can come from chip design data, layout data, packaging structure data, or structural information obtained through reverse engineering.

[0031] In one feasible implementation, an electrical test can be performed on the malfunctioning chip to obtain first data. This electrical test can be performed using a parameter analyzer, semiconductor tester, or dedicated testing equipment to measure parameters such as voltage, current, and resistance at each pin of the malfunctioning chip. Relevant data characterizing the electrical malfunction can be extracted from the test results. Then, second data can be obtained from the chip's design documents, manufacturing data, or existing structural database. This second data includes three-dimensional structural information such as the chip's internal network connection relationships, routing levels, and interconnect node positions.

[0032] In step S102, the failure area distribution refers to the distribution of the probability of failure at each location in the three-dimensional space of the abnormal chip. It can be understood as a quantitative representation of the probability of abnormal points appearing at different spatial locations inside the chip, and is used to indicate which areas should be focused on during subsequent failure analysis.

[0033] The failure region distribution characterizes the probability region distribution of abnormal points within the abnormal chip. That is, it identifies the degree of correlation between different locations in the three-dimensional structure and electrical abnormality features through probability values ​​or weight values. Regions with higher probability values ​​or weight values ​​indicate that the physical defects that cause electrical abnormalities are more likely to exist at that location.

[0034] Anomalies refer to the specific locations of defects within the chip's three-dimensional structure that actually cause electrical anomalies. They can be understood as the spatial coordinates of physical defects that cause electrical anomalies such as short circuits, leakage, and open circuits, and are used to identify target locations that require physical verification or further analysis.

[0035] An anomaly is a physical defect location in a three-dimensional structure that causes abnormal electrical characteristics. This physical defect may be located in one or more layers within the chip and may involve different structural units such as metal traces, insulating layers, vias, and solder joints. For example, anomalies may include, but are not limited to: abnormal conduction points between metal layers, locations where insulating layers are broken, voids or cracks in vias, short circuits formed by solder bridging, locations where metal traces are broken, voids caused by electromigration, and delamination defects within the packaging substrate.

[0036] In one feasible implementation, based on the electrical anomaly characteristics reflected in the first data and combined with the three-dimensional structural information described in the second data, it can be analyzed which networks or traces have abnormal connections. Then, the location of these related networks or traces and their surrounding areas can be determined in three-dimensional space. These areas are identified as candidate areas for possible failure, and different probability values ​​are assigned according to factors such as the severity of the electrical anomaly and the spatial distance between networks, thereby forming a failure area distribution.

[0037] In another feasible implementation, the type and characteristics of electrical anomalies can be determined based on the first data, such as whether it is a hard short circuit or a soft short circuit, a single-point failure or a multi-point failure, a temperature-sensitive failure or a non-temperature-sensitive failure. Then, combined with the structural layout and hierarchical relationship in the second data, the corresponding easy-to-fail areas can be determined for different types of failure characteristics. For example, for hard short circuits, the focus can be on areas where the metal layers are close together, and for temperature-sensitive failures, the focus can be on high current density areas with electromigration risk. The above method generates a failure area distribution that can reflect the characteristics of the failure type.

[0038] It should be noted that the failure region distribution does not simply point out a specific failure point, but rather provides a probabilistic distribution map within the entire three-dimensional space of the chip. This distribution map reflects the correlation strength between different locations and the current electrical anomaly, thus providing spatial priority guidance for subsequent image analysis and anomaly structure identification. In addition, the process of determining the failure region distribution comprehensively considers the dual constraints of electrical test results and three-dimensional structural layout. Compared with relying on only a single piece of information for judgment, it can more accurately delineate the range of possible failure locations, and is applicable to chip failure analysis scenarios with various complex packaging structures and multi-layer interconnect structures.

[0039] In step S103, the first image refers to image data obtained after scanning or photographing the abnormal chip using an imaging device. It can be understood as image information reflecting the actual physical structure of the abnormal chip's interior. The first image is a three-dimensional image, meaning it contains structural information at different depths or levels within the chip, showcasing its internal spatial structure rather than merely its surface two-dimensional appearance. The three-dimensional image can be three-dimensional volume data reconstructed through layer-by-layer scanning, an image sequence containing multiple cross-sections at different depths, or stereoscopic image data with depth information.

[0040] In one feasible implementation, an X-ray microscopy device can be used to scan the abnormal chip to obtain a first image. This X-ray microscopy device can penetrate the chip packaging material and internal structure, and obtain image information at different depths inside the chip without damaging it. After scanning from multiple angles or multiple layers, a three-dimensional image can be reconstructed. This three-dimensional image can present the spatial distribution of the chip's internal metal traces, solder joints, vias, layers, and other structures.

[0041] In step S104, the abnormal structure refers to the physical defect structure that actually exists inside the abnormal chip and causes electrical abnormalities. It can be understood as the specific structural morphology or structural feature that can be observed in the first image corresponding to the abnormal point.

[0042] Abnormal structures can be a single defect morphology or a combination of multiple related defect structures. In the first image, they manifest as image features that differ from normal structures, such as abnormal brightness contrast, shape changes, and abnormal connectivity.

[0043] In one feasible implementation, the failure region distribution can be spatially registered with the first image so that the probability information in the failure region distribution corresponds to the spatial location in the first image. Then, the first image is analyzed and inspected preferentially in the regions with higher probability values ​​in the failure region distribution. Structural anomalies that match the electrical anomaly characteristics are searched in these key regions. For example, when the electrical anomaly manifests as a short circuit, structural features that may cause a short circuit, such as abnormal connections between metal traces, solder bridging, and metal residues, are searched in high-probability regions. Once an abnormal structure that matches the failure characteristics is observed in the first image, the structure can be identified as the abnormal structure involved in the anomaly point.

[0044] In another feasible implementation, the first image can be partitioned according to the distribution of the failure area, dividing the first image into high-probability areas, medium-probability areas, and low-probability areas. During the failure analysis, each area is inspected and defect identified in descending order of probability. When a suspected defect structure is found in a high-probability area, it is further verified by combining it with the electrical anomaly features in the first data to determine whether the location, type, and shape of the suspected defect structure can reasonably explain the observed electrical anomaly. If it can explain it, the suspected defect structure is determined to be the anomaly structure involved in the anomaly point. If it cannot fully explain it, the inspection continues in other probability areas until an anomaly structure that can simultaneously satisfy spatial location matching and electrical feature matching is found.

[0045] It should be noted that failure analysis based on the distribution of the failure area and the first image can significantly reduce the inspection scope and improve the analysis efficiency compared to directly scanning the entire first image. At the same time, since the distribution of the failure area has integrated electrical abnormality features and three-dimensional structural information, the abnormal structures identified in the first image are more targeted and accurate.

[0046] By employing the technical solution of this application, data characterizing the electrical anomalies of the abnormal chip and data characterizing its three-dimensional structure are used to correlate and analyze information from two dimensions: electrical performance and spatial structural layout. This allows for the identification of the probability of failure at different locations within the chip's three-dimensional space. Before entering the image analysis stage, the range of potential anomalies is narrowed from the entire chip to specific areas with higher probabilities, clearly identifying the target areas that should be focused on. In subsequent failure analysis based on the failure area distribution and the three-dimensional image, the failure area distribution already indicates the location of high-probability areas, allowing the inspection and analysis of the three-dimensional image to focus on these key areas rather than indiscriminately scanning the entire image. This reduces the actual analysis scope and significantly improves the efficiency of failure localization. Simultaneously, the process of determining the abnormal structure is constrained by both the failure area distribution and the three-dimensional image—it must simultaneously meet the spatial location requirements determined based on electrical anomalies and the three-dimensional structure, as well as the observability of corresponding physical defect features in the three-dimensional image. This ensures that the final determined abnormal structure can both theoretically explain the electrical anomalies and is physically confirmed in the actual image, significantly improving the accuracy of failure localization.

[0047] Based on the above embodiments, as an optional embodiment, step S101 may further include the following steps.

[0048] Obtain the electrical test data of the abnormal chip, and determine the first data based on the electrical test data.

[0049] Electrical test data refers to the measurement results obtained after measuring the electrical parameters of each pin or network of the faulty chip. It can be understood as the numerical records of parameters such as voltage, current, and resistance directly acquired by the test equipment. Electrical test data may include, but is not limited to, raw data information such as pin-to-pin resistance values, pin-to-ground resistance values, current-voltage scan curves, conduction impedance under different bias conditions, data sequences of repeated measurements, and measurement results under different ambient temperatures.

[0050] In one feasible implementation, each pin of the malfunctioning chip can be scanned and tested one by one, measuring the resistance between each pin and ground as well as between pins, and recording the current response data of each pin when different voltages are applied, forming a test data set containing the electrical characteristics of each pin; for pin pairs that are found to be abnormally conducting, further fine measurement of the current-voltage characteristic curves is performed to obtain the current values ​​of the pin pair at multiple voltage points, constituting complete electrical test data.

[0051] Optionally, the first data includes a combination of at least one or more of the following:

[0052] Abnormal pin data is used to characterize the pins in the abnormal chip that have electrical abnormalities and their corresponding short-circuit target networks;

[0053] On-time linearity is used to characterize the linearity of the current-voltage characteristics corresponding to an abnormal chip.

[0054] Temperature response data is used to characterize the response characteristics of abnormal chips under temperature change conditions.

[0055] Abnormal pin data refers to the information of pins exhibiting abnormal behavior identified from electrical test data, along with their associated network information. It can be understood as the identification and recording of pins with abnormally low resistance or unexpected conduction paths discovered during testing. Abnormal pin data includes not only the pin number where the abnormality occurred, but also information such as which target network the pin has an abnormal connection to, and the resistance range of the abnormal connection.

[0056] Conductivity linearity refers to a quantitative index of linearity obtained by analyzing the current-voltage characteristic curves in electrical test data. It is used to determine whether abnormal conduction paths exhibit ohmic contact characteristics. A high conductivity linearity value indicates a good linear relationship between current and voltage, and the corresponding abnormal conduction path is closer to direct metallic contact. A low conductivity linearity value indicates significant nonlinearity in the current-voltage characteristic curves, and the corresponding abnormal conduction path may involve semiconductor characteristics, tunneling effects, or unstable contacts. Conductivity linearity can be obtained by calculating the goodness of fit after linearly fitting multiple measured voltage and current data points.

[0057] Temperature response data refers to the parameter changes as a function of temperature obtained after electrical testing of the faulty chip under different temperature conditions. It can be understood as information characterizing the temperature sensitivity of the faulty conduction path. Temperature response data may include the trend of resistance changes between faulty pin pairs as temperature increases, the shift of current-voltage characteristic curves at different temperatures, and the stability of the faulty conduction phenomenon during temperature cycling.

[0058] In one feasible implementation, the obtained electrical test data can be processed and feature extracted. First, the measured resistance value of each pin is compared with the design expectation value of that pin, and pins with resistance values ​​that deviate significantly from the normal range are screened out. The pin numbers, abnormal resistance values, and the target network identifiers with which they are abnormally connected are extracted to form abnormal pin data. Then, the current-voltage characteristic curves of pin pairs with abnormal conduction are linearly fitted and analyzed to calculate the deviation between the fitted line and the actual measurement point. The conduction linearity value is determined based on the magnitude of the deviation. Further, for multiple sets of electrical test data obtained under different temperature conditions, the resistance value or current-voltage characteristics of abnormal pin pairs at each temperature point are extracted, and the variation law of these parameters with temperature is analyzed to form temperature response data. The above abnormal pin data, conduction linearity, and temperature response data are integrated as the first data.

[0059] By adopting the technical solution of this application, the electrical test data is processed and abnormal pin data, conduction linearity and temperature response data are extracted to form the first data. The original measured values ​​are transformed into characteristic parameters with clear physical meaning. The abnormal pin data identifies the location of the abnormality and the network objects involved. The conduction linearity reflects the electrical contact characteristics of the abnormal conduction path. The temperature response data reflects the degree of dependence of the abnormal phenomenon on environmental conditions. The above parameters can provide multi-dimensional constraints for subsequent determination of the failure area distribution.

[0060] Based on the above embodiments, as an optional embodiment, step S102 may further include the following steps.

[0061] Step S201: Determine the network connection relationship of the abnormal chip based on the second data; the network connection relationship characterizes the topological relationship of the internal interconnection structure of the abnormal chip;

[0062] Step S202: Based on the network connection relationship and the abnormal pin data in the first data, determine the candidate path set; the candidate path set represents the spatial position and adjacent area of ​​the abnormal pin and the corresponding short-circuit target network in the three-dimensional structure.

[0063] Step S203: Generate a spatial prior distribution based on the spatial distribution of the candidate path set in the 3D structure; the spatial prior distribution characterizes the proximity of the spatial location in the 3D structure to the candidate path set.

[0064] Step S204: Modulate the spatial prior distribution of electrical anomaly features in the first data to determine the distribution of failure regions.

[0065] In step S201, the network connection relationship refers to the network topology formed by the interconnection of various electrical nodes within the malfunctioning chip through conductive structures. It describes the structured information of which pins, pads, traces, vias, and other nodes within the chip are interconnected through metal conductors. The network connection relationship characterizes the topological relationship of the interconnection structure within the malfunctioning chip and may include information such as the identifier of each network node, the connection path between nodes, the hierarchical position traversed by the connection path, and the spatial coordinates of the connection path.

[0066] In one feasible implementation, the design netlist data, placement and routing data, or package structure data of the abnormal chip can be extracted from the second data. Based on this data, the node distribution of each network inside the chip can be identified, the connection path of each pin from the outside of the package to the inside of the chip can be traced, and the structural units such as trace segments, vias, and pads along the path, as well as their level and spatial position, can be recorded. All interconnected nodes in the same network can be grouped together, and the connection relationship mapping between nodes can be established to form a complete network connection relationship.

[0067] In step S202, the candidate path set refers to the set of spatial paths that may lead to abnormal conduction, determined based on the actual layout position of the abnormal pin and its short-circuit target network within the chip. These are the paths within three-dimensional space where the network to which the abnormal pin belongs and the short-circuit target network are close, adjacent, or overlapping. The candidate path set characterizes the spatial position and adjacent region of the abnormal pin and its corresponding short-circuit target network in the three-dimensional structure, and can identify the spatial range where short-circuit conditions can occur in the physical structure.

[0068] In one feasible implementation, the pin number of the abnormal pin and the identifier of the short-circuited target network can be obtained from the abnormal pin data in the first data. The complete connection path of the network to which the abnormal pin belongs and the complete connection path of the short-circuited target network can be found in the network connection relationship. The three-dimensional spatial coordinate information of each node on the two network paths can be extracted respectively. The spatial distance between each node on the two network paths can be calculated. Node pairs with a distance less than a preset threshold can be selected. These node pairs and their surrounding areas can be identified as candidate paths. All candidate paths can be summarized to form a candidate path set.

[0069] In step S203, the spatial prior distribution refers to the probability distribution data generated in the three-dimensional structure space of the chip based on the spatial location information of the candidate path set. It can be understood as the distance between each location in the three-dimensional space and the candidate path set. The spatial prior distribution characterizes the proximity of a spatial location in the three-dimensional structure to the candidate path set, where spatial locations closer to the candidate path set have higher probability values, and spatial locations farther away from the candidate path set have lower probability values.

[0070] In one feasible implementation, a spatial coordinate grid can be established in the three-dimensional structural space of the chip. For each spatial location point in the grid, the shortest distance from the spatial location point to each candidate path in the candidate path set is calculated. The prior probability value of the spatial location point is determined based on the distance value. The closer the distance, the higher the prior probability value, and the farther the distance, the lower the prior probability value. The prior probability values ​​of all location points in the three-dimensional space are normalized to generate a spatial prior distribution covering the entire three-dimensional structural space.

[0071] In step S204, modulating the spatial prior distribution of electrical anomaly features in the first data means adjusting the probability value of the spatial prior distribution based on the anomaly characteristics reflected in the electrical test results. This can be understood as applying information such as the severity and type of electrical anomaly as weighting factors to the spatial prior distribution, so that the failure area distribution reflects not only spatial proximity relationships but also the influence of electrical anomaly features.

[0072] In one feasible implementation, the resistance value of abnormal conduction can be extracted based on the abnormal pin data in the first data. When the resistance value is low, a larger modulation weight is determined, and when the resistance value is high, a smaller modulation weight is determined. The modulation weight is multiplied by the prior probability value of each spatial location in the spatial prior distribution to obtain the modulated probability value. Optionally, the conduction linearity in the first data can also be combined. When the conduction linearity is high, the probability value of the region adjacent to the metal layer is increased, and when the conduction linearity is low, the probability value of the location adjacent to the insulating layer or semiconductor region is increased. Optionally, temperature response data can also be combined. When the temperature response data shows that abnormal conduction is sensitive to temperature, the probability value of the thermal stress concentration region or the region with high current density is increased. The probability value after the above modulation processing is used as the failure probability of each spatial location in the failure region distribution.

[0073] It should be noted that the spatial prior distribution is a preliminary probability distribution established based on the geometric proximity of network connections, which only considers spatial distance factors. The process of modulating electrical anomaly characteristics integrates information such as failure type and failure severity contained in the electrical test results into the spatial probability distribution, so that the final determined failure area distribution can simultaneously reflect both spatial structural constraints and electrical performance constraints. Compared with determining the failure area based solely on spatial proximity, it can more accurately identify high-probability failure areas that correspond to the current electrical anomaly phenomenon.

[0074] By adopting the technical solution of this application, the network connection relationship is determined using the structural information in the second data, and the spatial path between the abnormal network and the short-circuit target network is located in the network connection relationship by combining the abnormal pin data. This narrows the failure search space of the entire chip to a local area covered by the candidate path set, avoiding indiscriminate analysis of the entire three-dimensional space of the chip. When generating the spatial prior distribution, the proximity of each spatial location to the candidate path set is quantified, establishing a mapping from network topology to three-dimensional spatial probability distribution, providing prior constraints based on structural layout for the subsequent determination of failure areas. Furthermore, by modulating the spatial prior distribution with electrical anomaly features, the failure area distribution not only reflects the structural proximity relationship but also reflects the indicative role of electrical test results on the failure location. When the electrical anomaly manifests as a strong short circuit, it can highlight areas with close metal layer distances; when the electrical anomaly manifests as a temperature-sensitive failure, it can highlight areas affected by thermal stress, thereby significantly improving the accuracy of the failure area distribution in pointing to the true failure location.

[0075] Based on the above embodiments, as an optional embodiment, step S203 may further include the following steps.

[0076] Step S301: For any target location in the three-dimensional structure, calculate the spatial distance between the target location and each path in the candidate path set;

[0077] Step S302: Process each path based on spatial distance to obtain the neighbor intensity value corresponding to each path; the neighbor intensity value is negatively correlated with the spatial distance.

[0078] Step S303: Determine the prior probability value of the target location based on the proximity intensity value corresponding to each path;

[0079] Step S304: Generate a spatial prior distribution based on the prior probability values ​​of each target location in the three-dimensional structure.

[0080] In step S301, the target position refers to the spatial coordinate point in the three-dimensional structural space used to calculate the prior probability. It can be understood as a discrete position point in the three-dimensional space of the chip divided according to certain rules or any position point in the continuous space.

[0081] For chips with multilayer substrate structures, the target location can be distributed in various metal layers, dielectric layers, via areas, or the interface area between the chip and the substrate inside the chip; for system-in-package (SoC) chips, the target location can be distributed in redistribution layers, solder ball connection areas, chip stack gaps, or the interlayer structure of the packaging substrate.

[0082] Spatial distance refers to the geometric distance between the target location and a certain path in the candidate path set. It can be understood as the straight-line distance from the target location to the nearest point on the candidate path or the weighted distance after considering the chip hierarchy.

[0083] In one feasible implementation, the three-dimensional structural space can be divided into a regular grid according to a preset spatial resolution. This spatial resolution can be determined according to the feature size of the chip. For example, for a chip with line width and line spacing in the micrometer range, the grid spacing can be set to the sub-micrometer or micrometer range. Each grid node in the grid is taken as the target position. For each target position, each candidate path in the candidate path set is traversed, and the distance between the target position coordinates and the coordinates of each node on the candidate path is calculated. The minimum distance value is taken as the spatial distance between the target position and the candidate path, thereby obtaining the spatial distance data between the target position and each path in the candidate path set.

[0084] In step S302, the proximity strength value refers to a numerical value characterizing the proximity between the target location and the candidate path. It can be understood as a quantitative index reflecting the degree of proximity calculated based on spatial distance. The proximity strength value is negatively correlated with spatial distance; that is, the smaller the spatial distance, the larger the proximity strength value, and the larger the spatial distance, the smaller the proximity strength value. This negative correlation reflects the objective law in chip failure analysis that locations closer to abnormal network paths or short-circuit target network paths are more prone to abnormal conduction.

[0085] In one feasible implementation, an exponential decay function can be used to convert spatial distance to obtain the proximity intensity value. The spatial distance between the target location and a candidate path is substituted into the exponential decay function for calculation. The proximity intensity value reaches its maximum when the spatial distance is zero. As the spatial distance increases, the proximity intensity value decays exponentially. The proximity intensity value is calculated for each path in the candidate path set. The decay coefficient of the exponential decay function can be set according to the chip's process characteristics. For high-density packaged chips with small linewidths and spacing and thin interlayer dielectrics, a larger decay coefficient can be set to make the proximity intensity decay rapidly with distance, highlighting the importance of the extremely close area. For packaged chips with large linewidths and spacing and relatively sparse structures, a smaller decay coefficient can be set to ensure that a certain proximity intensity value is maintained over a larger area.

[0086] In step S303, the prior probability value refers to the preliminary probability value of the target location failing, determined based on the spatial distribution of the candidate path set. It can be understood as the probability quantification result obtained after comprehensively processing the proximity strength values ​​of the target location and each candidate path. The prior probability value reflects the likelihood of abnormal conduction at a certain location within the chip, considering only the network spatial layout.

[0087] In one feasible implementation, the proximity intensity values ​​of each candidate path corresponding to the target location can be summed, and the summation result can be used as the initial prior probability value of the target location. This initial prior probability value is then normalized to obtain the actual prior probability value of the target location. This summation operation can comprehensively consider the combined influence of multiple trace paths from the network to which the abnormal pin belongs, as well as multiple trace paths from the short-circuited target network, on the target location. When the target location is simultaneously close to multiple paths from both networks, its prior probability value will be significantly increased due to the superposition of multiple proximity intensity values.

[0088] Optionally, different weighting coefficients can be assigned to the proximity strength values ​​of different candidate paths before summing them. The weighting coefficients can be determined based on factors such as the hierarchical position of the candidate path, the importance of nodes on the candidate path, or the length of the candidate path.

[0089] For example, candidate paths located between adjacent metal layers can be assigned a higher weighting factor because interlayer short circuits are more likely to occur when there is only one dielectric layer between adjacent layers; candidate paths passing through densely populated via regions can be assigned a higher weighting factor because the metal plating around the vias, the via wall structure, or the dielectric between the vias are high-risk areas for failure; candidate paths passing through chip edges or corners can be assigned a higher weighting factor because these locations are susceptible to packaging stress or process defects.

[0090] In step S304, all target positions in the three-dimensional structure can be traversed, and the prior probability value of each target position can be calculated in the manner described above. Each target position and its corresponding prior probability value are then associated and stored to form prior probability value distribution data covering the three-dimensional structure space. This distribution data is the spatial prior distribution. The spatial prior distribution exhibits a spatial distribution pattern of probability values ​​in the three-dimensional space of the chip. Probability peaks are formed in areas where the candidate path set is dense or where multiple candidate paths intersect, while the probability values ​​approach zero in areas far from the candidate path set.

[0091] For example, for any target position x in the three-dimensional structure, let the candidate path set be:

[0092]

[0093] in, Let M represent the j-th path in the candidate path set, and M represent the number of candidate paths.

[0094] Then the target position x and the j-th path Spatial distance is defined as:

[0095]

[0096] Based on the spatial distance, each path is processed to obtain the proximity intensity value corresponding to each path:

[0097]

[0098] in, This represents the distance attenuation parameter, used to characterize the degree of influence of spatial distance on the intensity value of neighboring areas.

[0099] Based on the proximity intensity values ​​corresponding to each path, the prior probability value of the target location is determined:

[0100]

[0101] A spatial prior distribution is generated based on the prior probability values ​​of each target location in the aforementioned three-dimensional structure:

[0102]

[0103] Wherein, Ω represents the spatial region corresponding to the three-dimensional structure.

[0104] It should be noted that by calculating the spatial distance between the target location and each path in the candidate path set, the geometric proximity relationship between the target location and the spatial region where a short circuit may occur can be quantified. By converting the spatial distance into a proximity intensity value, a mapping from distance metric to probability weight is achieved, so that the closer the location is to the candidate path, the higher the weight is obtained. By comprehensively processing the proximity intensity values ​​corresponding to multiple candidate paths, the combined influence of multiple possible contact areas between the anomalous network and the short-circuit target network on the target location can be considered simultaneously, avoiding omissions that may occur if the judgment is based on a single path.

[0105] By employing the technical solution of this application, the spatial distance between each target location in the three-dimensional structure and each path in the candidate path set is calculated, thereby quantifying the distance relationship between the target location and the candidate paths. This distance calculation method is applicable to complex multilayer interconnect structures and heterogeneous packaging structures within chips. After converting the above spatial distance into proximity intensity values, the distance information is transformed into probability information. Since the proximity intensity value is negatively correlated with the spatial distance, the closer the location is to the candidate path, the greater the probability of failure.

[0106] Furthermore, the prior probability value of the target location is determined by combining the proximity intensity values ​​corresponding to each candidate path. This prior probability value reflects the comprehensive proximity of the target location to multiple candidate paths. When the target location is located in an area where multiple paths intersect or in a densely populated area of ​​vias, the prior probability value of the target location will increase accordingly due to the superposition of multiple proximity intensity values, thus enabling more accurate identification of areas prone to abnormal conduction.

[0107] Based on the above embodiments, as an optional embodiment, step S204 may further include the following steps.

[0108] Step S401: Determine the failure mechanism type based on the electrical anomaly characteristics in the first data;

[0109] Step S402: Determine the modulation parameters based on the failure mechanism type; different failure mechanism types have different modulation parameters;

[0110] Step S403: The prior probability values ​​at each location in the spatial prior distribution are weighted and modulated according to the modulation parameters to obtain the modulation probability values ​​at each location in the spatial prior distribution.

[0111] Step S404: Generate the failure region distribution based on the modulation probability values ​​at each location in the spatial prior distribution.

[0112] In step S401, the failure mechanism type refers to the category of physical defects that cause chip failure, determined based on the electrical abnormality characteristics. The failure mechanism type reflects the specific physical cause of abnormal conduction within the chip, and different failure mechanism types correspond to different defect structural characteristics and spatial distribution patterns.

[0113] For example, failure mechanism types may include, but are not limited to: metal bridging short circuit type, dielectric breakdown short circuit type, short circuit type caused by electromigration, solder bridging short circuit type, crack conduction short circuit type, leakage current type caused by contamination, etc.

[0114] Among them, metal bridging short circuits are usually caused by process residues, metal sputtering, or conductive particles; dielectric breakdown short circuits are usually caused by over-stress or electric field concentration in weak dielectric areas; electromigration short circuits usually occur in high current density areas; solder bridging short circuits usually occur in dense solder joint areas or in locations where reflow process control is inadequate; and crack conduction short circuits are usually caused by stress concentration, thermal cycling, or packaging deformation.

[0115] In one feasible implementation, the resistance value range of abnormal conduction can be extracted based on the abnormal pin data in the first data. When the resistance value is less than the preset low resistance threshold, it is judged to be a metal bridging short circuit or a solder bridging short circuit. When the resistance value is in the medium resistance range, it is judged to be a dielectric breakdown short circuit or a crack conduction short circuit. When the resistance value is high but significantly lower than the normal insulation resistance value, it is judged to be a leakage current caused by pollution.

[0116] Furthermore, the conduction linearity in the first data can be used to make a judgment. When the conduction linearity is high, it tends to be judged as a metal bridging short circuit or a solder bridging short circuit. When the conduction linearity is low and the current-voltage characteristic curve shows non-linear characteristics, it tends to be judged as a dielectric breakdown short circuit or a leakage current caused by contamination.

[0117] Optionally, the temperature response data in the first data can also be used for judgment. When the temperature response data shows that the resistance value of abnormal conduction decreases significantly with the increase of temperature, it tends to be judged as a short circuit caused by electromigration or a short circuit caused by crack conduction. When the temperature response data shows that abnormal conduction is not sensitive to temperature, it tends to be judged as a short circuit caused by metal bridging or a short circuit caused by solder bridging. The failure mechanism type is determined by comprehensively analyzing the above judgment results.

[0118] In step S402, the modulation parameters refer to the set of parameters determined according to the failure mechanism type for adjusting the spatial prior distribution. These can be understood as weighting coefficients or adjustment factors set for the spatial distribution characteristics of different failure mechanism types. The modulation parameters can reflect the susceptibility characteristics of different failure mechanism types in the three-dimensional structure of the chip. Adjusting the spatial prior distribution through the modulation parameters can make the failure region distribution more consistent with the actual spatial distribution pattern of that failure mechanism type.

[0119] For example, the modulation parameters may include hierarchical weight parameters, region type weight parameters, structural feature weight parameters, etc. The hierarchical weight parameters are used to weight the prior probability values ​​of different hierarchical locations. For instance, for metal bridging short circuits, a higher hierarchical weight can be assigned to the region between adjacent metal layers, and for solder bridging short circuits, a higher hierarchical weight can be assigned to the layer where the solder joint is located. The region type weight parameters are used to weight the prior probability values ​​of different functional regions.

[0120] For example, for short circuits caused by electromigration, higher region type weights can be assigned to high current density regions; structural feature weight parameters are used to weight the prior probability values ​​of locations with specific structural features. For example, for crack-conducting short circuits, higher structural feature weights can be assigned to stress concentration locations, encapsulation edge locations, or material interface locations.

[0121] In one feasible implementation, a mapping table between failure mechanism types and modulation parameters can be established in advance. This mapping table stores the hierarchical weight parameter values, regional type weight parameter values, and structural feature weight parameter values ​​corresponding to each failure mechanism type. Once the failure mechanism type is determined, the corresponding modulation parameter values ​​are retrieved from the mapping table.

[0122] Optionally, the modulation parameter values ​​can be dynamically adjusted according to the specific packaging form, process generation, or application scenario of the abnormal chip. For example, for high-density interconnect chips with advanced packaging, the weight of the interlayer region corresponding to the dielectric breakdown short circuit type can be increased, and for chips in high-power application scenarios, the weight of the high-current region corresponding to the short circuit type caused by electromigration can be increased.

[0123] In step S403, weighted modulation refers to using the modulation parameters as weighting factors and calculating the prior probability values ​​at each position in the spatial prior distribution.

[0124] In one feasible implementation, for each target location in the spatial prior distribution, firstly, the hierarchical position of the target location can be determined, and the hierarchical weight value of the target location can be obtained according to the hierarchical weight parameter corresponding to the failure mechanism type; then, the region type to which the target location belongs can be determined, and the region weight value of the target location can be obtained according to the region type weight parameter corresponding to the failure mechanism type; further, it can be determined whether the target location has specific structural features, and the structural weight value of the target location can be obtained according to the structural feature weight parameter corresponding to the failure mechanism type; the prior probability value of the target location can be multiplied by the hierarchical weight value, the region weight value, and the structural weight value respectively to obtain the modulation probability value of the target location.

[0125] Optionally, the hierarchical weight value, regional weight value, and structural weight value can be combined to obtain a comprehensive weight value, and then the prior probability value can be multiplied with the comprehensive weight value to obtain the modulation probability value.

[0126] In step S404, the modulation probability values ​​obtained after weighted modulation of all target positions in the spatial prior distribution can be normalized so that the sum of all modulation probability values ​​satisfies the normalization condition of the probability distribution. The normalized modulation probability values ​​are used as the failure probability of each target position in the failure region distribution, thereby generating the failure region distribution.

[0127] For example, the failure mechanism type determined based on the electrical anomaly characteristics in the first data can be denoted as m, and the modulation parameter determined based on the failure mechanism type can be denoted as m. Then, based on the modulation parameters, the prior probability values ​​at each location in the spatial prior distribution are weighted and modulated to obtain the modulation probability value at each location:

[0128]

[0129] Furthermore, the failure region distribution generated based on the modulation probability values ​​at each location in the spatial prior distribution can be expressed as:

[0130]

[0131] In the formula, u represents any position in the spatial region Ω.

[0132] It should be noted that different failure mechanisms have different spatial distribution characteristics and prone areas in the three-dimensional structure of a chip. For example, metal bridging short circuits usually occur in parallel traces with small metal layer spacing or in overlapping and intersecting areas of metal layers; dielectric breakdown short circuits usually occur in locations where the dielectric layer is thin, the electric field strength is high, or there are dielectric defects; short circuits caused by electromigration usually occur in thin lines or at current corners where the current density exceeds the safety limit; solder bridging short circuits usually occur in areas where the solder joint spacing is small or the pad design is inappropriate; and crack conduction short circuits usually occur at material interfaces with mismatched thermal expansion coefficients or at structural corners subjected to high stress.

[0133] By determining targeted modulation parameters based on the failure mechanism type and weighting the spatial prior distribution, the characteristics of the prone areas corresponding to the failure mechanism type can be integrated into the failure area distribution. This allows the failure area distribution to not only reflect the spatial proximity relationship of the network, but also the objective distribution law of the failure mechanism type in the chip structure, thereby improving the accuracy of the failure area distribution in pointing to the actual failure location.

[0134] By adopting the technical solution of this application, the failure mechanism type is determined based on the electrical anomaly characteristics in the first data, and the multi-dimensional information such as resistance value, conduction linearity, and temperature response contained in the electrical test results is transformed into a type judgment of the physical cause of failure. By determining different modulation parameters for different failure mechanism types, a correlation is established between the failure mechanism type and the prone area in the three-dimensional structure of the chip, so that the modulation parameters can reflect the spatial distribution law of the failure mechanism type. By weighting and modulating the prior probability values ​​of each position in the spatial prior distribution according to the modulation parameters, the prior probability value determined only based on network proximity is adjusted to a modulation probability value that considers the characteristics of the failure mechanism type. When a position is close to the candidate path set and is in the prone area of ​​the failure mechanism type, it can obtain an increased probability value. When a position is close to the candidate path set but does not meet the spatial distribution characteristics of the failure mechanism type, its probability value will be appropriately suppressed.

[0135] Based on the above embodiments, as an optional embodiment, step S104 may further include the following steps.

[0136] Step S501: Identify the internal structure of the abnormal chip based on the first image to obtain structural distribution data;

[0137] Step S502: Extract a set of candidate abnormal connected components within the abnormal chip based on the structural distribution data; the candidate abnormal connected components are abnormal conductive structures that connect different networks in the three-dimensional structure.

[0138] Step S503: Based on the distribution of the failure region, each candidate abnormal connected component in the candidate abnormal connected component set is correlated and scored to obtain the scoring result; the scoring result characterizes the degree of correlation between each candidate abnormal connected component and the electrical abnormality feature.

[0139] Step S504: Based on the scoring results, determine the abnormal structure involved in the abnormal point in the candidate abnormal connected component set.

[0140] In step S501, the structural distribution data refers to the spatial location, geometric shape, and material property information of various structures inside the abnormal chip identified and extracted from the first image. This data serves as a structured description of each component within the chip's three-dimensional structure. The structural distribution data reflects the distribution and connection relationships of structural units such as metal layers, dielectric layers, vias, solder joints, and the chip body within the chip in three-dimensional space.

[0141] For example, the structural distribution data includes: the location coordinates, width, thickness and direction information of metal traces; the location, thickness and material type information of dielectric layers; the location, diameter and connection level information of vias; the location, shape and connection object information of solder joints; the outline boundary and material region information of the chip body; and the hierarchical relationship and connectivity information between each structural unit.

[0142] In one feasible implementation, the first image is segmented. Based on the grayscale differences or contrast characteristics of different materials in X-ray imaging, the pixels in the first image are classified into categories such as metallic materials, dielectric materials, semiconductor materials, or voids and defects. Connectivity analysis is performed on each segmented category region to merge adjacent pixels belonging to the same material category into the same structural unit. Geometric features such as boundary contours, centroid coordinates, volume, and shape parameters of each structural unit are extracted. The hierarchical position of the structural unit is determined based on its appearance in different level slice images.

[0143] The connection relationship between structural units is determined based on the positional correspondence of structural units in adjacent layer images. For example, when the projection position of a certain metal structural unit in an adjacent layer image overlaps with another metal structural unit or is connected through a via structural unit, it is determined that there is an electrical connection relationship between the two metal structural units. The structural unit information, geometric feature information, layer position information and connection relationship information obtained above are summarized to form structural distribution data.

[0144] In step S502, a candidate abnormal connectivity refers to an abnormal conductive structure in the three-dimensional structure of the chip that connects different networks. It is an unexpected conductive path or conductive material that appears between two networks that should be mutually insulated in a normal design. A candidate abnormal connectivity is a physical defect structure that causes abnormal conductivity to be detected in electrical testing. Its morphology may manifest as a metal bridge, conductive particles, crack penetration path, solder overflow, or dielectric breakdown channel, etc.

[0145] For example, a candidate abnormal connectivity may be: a metal bridging structure connecting adjacent metal traces, a vertical conductive channel connecting metals of different layers, a solder bridge located between solder joints, a conductive path formed along a crack path, or a conductive filament structure formed in a dielectric layer.

[0146] In one feasible implementation, network affiliation information of each metal structural unit is extracted from the structural distribution data. This network affiliation information is obtained by matching the structural distribution data with the network connection relationship in the second data, that is, by searching for the network identifier to which the position should belong in the network connection relationship based on the spatial location and hierarchical information of the metal structural unit.

[0147] Search for structural unit combinations in the structural distribution data that spatially connect two different network identifiers of metal structural units. When a structural unit is found to be in contact or connected with metal structural units of two different networks at the same time, and the structural unit should not exist in the design data, the structural unit is identified as a candidate abnormal connected body.

[0148] Optionally, candidate anomalous connected components are identified by detecting whether there is abnormal material filling the gaps between metal structural units. Specifically, image features of the gap region between metal structural units of two different networks are extracted. When the grayscale value, contrast, or texture features of the gap region are significantly different from those of the normal medium material, it is determined that there is abnormal material in the gap region, and the structural unit corresponding to the abnormal material is identified as a candidate anomalous connected component. All identified candidate anomalous connected components are summarized to form a set of candidate anomalous connected components.

[0149] It should be noted that multiple candidate abnormal connected components may exist in the three-dimensional structure of a chip. These candidate abnormal connected components may be distributed in different levels and regions of the chip, and may connect different network pairs. However, not all candidate abnormal connected components are the actual failure structures causing the current electrical anomaly. Some candidate abnormal connected components may be misjudged by image recognition, and some may be potential defects that have not yet caused an electrical anomaly. Therefore, it is necessary to evaluate and screen each candidate abnormal connected component in the set.

[0150] In step S503, the correlation score refers to the process of quantitatively evaluating the correlation between candidate abnormal connected components and electrical abnormal features based on the distribution of failure regions. This score is used to assess whether a candidate abnormal connected component is the actual failure structure causing the electrical abnormality detected in the first data. The score result characterizes the correlation between each candidate abnormal connected component and the electrical abnormal feature; a higher score value indicates that the candidate abnormal connected component is more likely to be the actual failure structure causing the current electrical abnormality.

[0151] In one feasible implementation, for each candidate abnormal connected component in the candidate abnormal connected component set, the spatial coordinates of the candidate abnormal connected component in the three-dimensional structure are extracted; the failure probability value corresponding to the spatial coordinates is queried in the failure region distribution; and the failure probability value is used as the basic score of the candidate abnormal connected component.

[0152] Furthermore, it is determined whether the network pair connected to the candidate abnormal connected entity matches the abnormal network pair indicated by the abnormal pin data in the first data. When the network pair matches, the base score is multiplied by a matching coefficient greater than 1. When the network pair does not match, the base score is multiplied by a penalty coefficient less than 1.

[0153] Optionally, the base score can be adjusted based on the geometric characteristics of the candidate anomalous connected bodies. For example, the score can be increased when the size, shape, or material characteristics of the candidate anomalous connected bodies match the failure mechanism type, and decreased when the geometric characteristics of the candidate anomalous connected bodies do not match the failure mechanism type. The score after the above adjustment is taken as the final score of the candidate anomalous connected body, and the final scores of all candidate anomalous connected bodies constitute the scoring result.

[0154] In step S504, the score values ​​of each candidate abnormal connected component in the scoring results are sorted, and one or more candidate abnormal connected components with the highest score values ​​are selected as the abnormal structures involved in the abnormal point.

[0155] Optionally, a scoring threshold is set to identify candidate abnormal connected components whose scores exceed the scoring threshold as abnormal structures involved in the abnormal points.

[0156] Optionally, the judgment is made based on the difference between the highest score and the second highest score. When the highest score is significantly higher than the second highest score, the candidate abnormal connected component with the highest score is determined as the only abnormal structure. When the scores of multiple candidate abnormal connected components are close, these multiple candidate abnormal connected components are determined to constitute the abnormal structure involved in the abnormal point.

[0157] It should be noted that after scoring candidate anomalous connected components based on the distribution of failure regions, the comprehensive probability information based on electrical anomaly characteristics, network connectivity, and failure mechanism type in the failure region distribution is applied to the screening and evaluation of candidate anomalous connected components. Candidate anomalous connected components that are highly correlated with electrical anomaly characteristics, located in high failure probability regions, and have matching network pairs receive higher scores, while pseudo-candidate anomalous connected components generated by image recognition misjudgments or potential defects unrelated to the current electrical anomaly receive lower scores. Therefore, the true failure structure causing the current electrical anomaly can be accurately located among numerous candidate anomalous connected components.

[0158] By adopting the technical solution of this application, structural distribution data is obtained based on the internal structure of the first image recognition anomaly chip, and the pixel information in the first image is transformed into structured structural unit description data. Based on the structural distribution data, a set of candidate abnormal connected components is extracted within the anomaly chip. After searching for abnormal conductive structures connecting different networks in the three-dimensional structure of the chip, the failure search range converges from the entire chip structure to a limited number of candidate abnormal connected components, avoiding point-by-point investigation of massive image data. After associating and scoring each candidate abnormal connected component in the set of candidate abnormal connected components based on the failure region distribution, the failure probability information in the failure region distribution is correlated with the spatial location information of the candidate abnormal connected components. Candidate abnormal connected components located in high failure probability regions receive higher scores. Therefore, the abnormal structures most relevant to electrical abnormal characteristics can be accurately screened from the set of candidate abnormal connected components, improving the accuracy of failure analysis.

[0159] Based on the above embodiments, as an optional embodiment, step S504 may further include the following steps.

[0160] Step S601: For the target candidate abnormal connected component in the candidate abnormal connected component set, extract the morphological feature data of the target candidate abnormal connected component; the morphological feature data characterizes the geometric morphological features of the target candidate abnormal connected component.

[0161] Step S602: Determine the failure mechanism matching degree of the target candidate abnormal connected body based on the morphological feature data; the failure mechanism matching degree characterizes the degree of consistency between the morphological features of the target candidate abnormal connected body and the failure mechanism type determined based on the first data;

[0162] Step S603: Determine the spatial matching degree based on the position of the target candidate abnormal connected component in the distribution of the failed region; the spatial matching degree characterizes the spatial proximity between the target candidate abnormal connected component and the candidate path set.

[0163] Step S604: Determine the association score value of the target candidate abnormal connected entity based on the failure mechanism matching degree and spatial matching degree.

[0164] In step S601, the morphological feature data is data that describes the appearance features of the target candidate abnormal connected body, such as its geometric shape, size, and spatial distribution.

[0165] In one feasible implementation, the set of voxels occupied by the target candidate abnormal connected components can be extracted from the structural distribution data, and the volume, length dimensions along different directions, and aspect ratio parameters of the voxel set can be calculated to form size feature data.

[0166] In step S602, the failure mechanism matching degree is the similarity between the morphological features of the target candidate abnormal connected component and the typical morphological features corresponding to the expected failure mechanism type. The failure mechanism matching degree characterizes the degree of consistency between the morphological features of the target candidate abnormal connected component and the failure mechanism type determined based on the first data. When the matching degree is high, it indicates that the morphological features of the candidate abnormal connected component conform to the characteristics of the failure mechanism type. When the matching degree is low, it indicates that the candidate abnormal connected component may not be a defect corresponding to the failure mechanism type.

[0167] In one feasible implementation, a typical morphological feature description corresponding to the failure mechanism type can be obtained based on the failure mechanism type determined by the first data. The morphological feature data of the target candidate abnormal connected body is compared with the typical morphological feature description, and the similarity between the two is calculated as the failure mechanism matching degree.

[0168] For example, when the failure mechanism type is metal bridging short circuit, the typical morphological characteristics are small volume, gray value close to conductor gray value, and relatively regular shape of the connected body. At this time, it can be judged whether its average gray value is close to the conductor gray value range based on the gray value characteristic data of the target candidate abnormal connected body, and whether its sphericity or regularity is higher than the preset threshold based on the shape characteristic data. The higher the degree of satisfaction of the above conditions, the higher the failure mechanism matching degree value is assigned.

[0169] For example, when the failure mechanism type is crack conduction short circuit type, the typical morphological features are slender, flat, and low gray-scale contrast connected bodies. At this time, it can be determined whether the slenderness parameter is higher than the preset threshold based on the shape feature data of the target candidate abnormal connected body, and whether the gray-scale contrast is lower than the preset threshold based on the gray-scale feature data. The higher the degree of satisfaction of the above conditions, the higher the failure mechanism matching degree value is assigned.

[0170] Optionally, when the failure mechanism type is solder bridging short circuit type, it can be further determined whether the target candidate abnormal connected body is located in a dense solder joint area or the level where the solder joint is located. If it is located in this area, the failure mechanism matching degree value is increased.

[0171] In step S603, spatial matching degree is the degree to which the position of the target candidate abnormal connected component in the three-dimensional structure overlaps with the high-probability region in the failure region distribution. Spatial matching degree characterizes the spatial proximity of the target candidate abnormal connected component and the candidate path set; the closer the candidate abnormal connected component is to the region covered by the candidate path set, the higher the spatial matching degree.

[0172] In one feasible implementation, the spatial coordinates of the target candidate abnormal connected body can be extracted, and the failure probability value corresponding to the spatial location in the failure area distribution can be queried. This failure probability value is used as the basic value of the spatial matching degree. The overlap volume between the voxel set occupied by the target candidate abnormal connected body and the high-probability area in the failure area distribution can also be calculated. The larger the overlap volume, the higher the degree of spatial overlap between the candidate abnormal connected body and the theoretical high-risk area, and the spatial matching degree value is increased accordingly. The combined result of the above basic value and the overlap volume is used as the spatial matching degree.

[0173] Optionally, the shortest distance between the target candidate abnormal connected component and each candidate path in the candidate path set can also be calculated. The smaller the shortest distance, the higher the spatial matching degree value, so that the spatial matching degree can more directly reflect the spatial proximity relationship between the candidate abnormal connected component and the abnormal network and the short-circuited target network path.

[0174] In step S604, the correlation score can be calculated by weighted summation. Weight coefficients are set for the failure mechanism matching degree and the spatial matching degree respectively. The failure mechanism matching degree is multiplied by its corresponding weight coefficient to obtain the morphology score component. The spatial matching degree is multiplied by its corresponding weight coefficient to obtain the location score component. The morphology score component and the location score component are added together to obtain the correlation score value.

[0175] Optionally, the weighting coefficients can be dynamically adjusted based on the confidence level of the electrical anomaly features. When the electrical anomaly features in the first data are clear and stable, a weighting coefficient with a high degree of matching with the failure mechanism can be assigned to emphasize the consistency between the morphological features of the candidate anomaly connected body and the failure mechanism type. When the electrical anomaly features fluctuate or are uncertain, a weighting coefficient with a high degree of matching with the spatial mechanism can be assigned to rely more on the spatial location constraints determined based on the network topology.

[0176] For example, for a target candidate abnormal connected component Q in the set of candidate abnormal connected components, let its morphological feature data be... Let m be the failure mechanism type determined based on the first data, and let the standard morphological feature data corresponding to failure mechanism type m be... The failure mechanism matching degree of the target candidate abnormal connected component can be defined as:

[0177]

[0178] In the formula, This represents the attenuation parameter of morphological feature differences, used to characterize the degree of influence of morphological feature differences on the degree of matching of failure mechanisms.

[0179] Based on the location of the target candidate abnormal connected component in the distribution of the failure region, the spatial matching degree can be expressed as:

[0180]

[0181] In the formula, This represents the distribution value of the failure area at location x.

[0182] Furthermore, the association score of the target candidate abnormal connected component can be expressed as:

[0183]

[0184] in, In the formula, and For scoring weights.

[0185] By employing the technical solution of this application, morphological feature data is extracted for each target candidate abnormal connected body in the candidate abnormal connected body set, obtaining a quantitative description of the geometric morphological features of each candidate abnormal connected body. Based on the morphological feature data, the failure mechanism matching degree is determined. The matching degree is calculated by comparing the actual morphological features of the candidate abnormal connected body with the expected morphological features of the failure mechanism type determined based on electrical anomaly features, thereby evaluating the morphological rationality of the candidate abnormal connected body. Based on the location of the target candidate abnormal connected body in the failure region distribution, the spatial matching degree is determined. The matching degree is calculated by comparing the spatial location of the candidate abnormal connected body with the theoretical high-risk area determined based on network connectivity and electrical anomaly features, thereby evaluating the location rationality of the candidate abnormal connected body. Finally, based on the failure mechanism matching degree and spatial matching degree, the correlation score is determined. The evaluation results of the morphological and positional dimensions are integrated, so that the correlation score can comprehensively reflect the degree of correlation between the candidate abnormal connected body and the current electrical anomaly.

[0186] Based on the above embodiments, as an optional embodiment, the failure analysis method for the chip may further include the following steps.

[0187] Step S701: Obtain the spatial location of the abnormal structure;

[0188] Step S702: Generate verification parameters based on the spatial location of the anomalous structure; the verification parameters are used to physically verify the sample preparation coordinates and cross-sectional orientation information of the anomalous structure.

[0189] Step S703: Obtain verification feedback data for the abnormal structure; the verification feedback data is the observation results after performing physical verification based on the verification parameters;

[0190] Step S704: Correct the failure area distribution based on the verification feedback data to obtain the corrected failure area distribution;

[0191] Step S705: Based on the corrected failure region distribution and the first image, redetermine the abnormal structure involved in the abnormal point in the abnormal chip.

[0192] In step S702, the verification parameters refer to operational parameters such as the sample preparation position and cutting direction required to guide the destructive physical verification of the abnormal structure.

[0193] In one feasible implementation, the three-dimensional coordinates of the abnormal structure can be converted into relative positions with respect to the external feature points of the chip package to form sample preparation coordinate information based on the spatial location of the abnormal structure. The cross-sectional normal vector perpendicular to its main extension direction can be determined as cross-sectional direction information based on the shape characteristics of the abnormal structure. The sample preparation coordinate information and cross-sectional direction information are then combined to form verification parameters.

[0194] In step S703, the abnormal chip can be sampled according to the verification parameters and observed using a microscopic observation device to determine whether defect features are observed at the expected location. The judgment result and the observed structural information are then used to form verification feedback data.

[0195] In step S704, when the verification feedback data indicates that no abnormal structure was observed at the expected location, the failure probability value of the region corresponding to the verification location in the failure region distribution is reduced, and the adjusted failure probability value is normalized to obtain the corrected failure region distribution.

[0196] In step S705, the corrected failure region distribution can be used to re-associate and score other candidate abnormal connected components in the candidate abnormal connected component set, and the candidate abnormal connected component with the highest score can be selected as the re-determined abnormal structure based on the recalculated association score value.

[0197] It should be noted that by obtaining verification feedback data and correcting the distribution of failure areas based on this feedback data, the actual observation information obtained during the physical verification process can be fed back into the failure location analysis process. When the abnormal structure initially identified does not find the expected defect after physical verification, by reducing the failure probability value of the verified area and redetermining the abnormal structure, the focus of the analysis can be shifted to other candidate areas that are more likely to have real defects, thus forming an iterative failure location analysis process.

[0198] By adopting the technical solution of this application, the verification parameters generated based on the spatial location of the abnormal structure provide accurate positioning guidance for destructive physical verification. The failure area distribution is corrected based on the verification feedback data, realizing the optimization of the failure area distribution based on the actual verification results. Furthermore, the abnormal structure is re-determined based on the corrected failure area distribution, forming an iterative failure positioning analysis process, which significantly improves the ability to successfully locate the real failure location when the first verification fails.

[0199] To more clearly illustrate the technical solutions in the above embodiments, the image data and structural features involved in the embodiments are described below with reference to the accompanying drawings.

[0200] Figure 2 An X-ray imaging image of a chip three-dimensional structure provided in an embodiment of this application.

[0201] like Figure 2 As shown, this image is the first image obtained by scanning an abnormal chip using an X-ray imaging device. The image displays the three-dimensional structure inside the chip, including multilayer metal traces, vias, solder joints, and other structural units. Bright areas in the image correspond to high-density materials such as metal structures, while dark areas correspond to low-density materials such as dielectric layers and semiconductor materials. Structural identification of this first image allows for the extraction of structural distribution data, providing a data foundation for subsequent extraction of candidate abnormal connected components. Figure 2 The scale in the image shows the field of view, and the complex multilayer interconnect structure inside the chip and the spatial distribution of metal traces at each level can be observed in the image.

[0202] Figure 3 This is a partial enlarged view of a candidate abnormal connected body provided in an embodiment of this application.

[0203] like Figure 3 As shown, this image is a magnified view of a candidate anomalous interconnectivity identified and extracted from the first image. The image reveals two parallel metal trace layers and an anomalous conductive structure connecting them. This anomalous conductive structure exhibits a curved bridging shape, and its grayscale characteristics are similar to the surrounding normal metal structure, indicating that it may be composed of metallic material. The morphological features of this candidate anomalous interconnectivity include geometric parameters such as its length, width, extension direction, and boundary morphology, as well as structural relationship parameters such as its contact position and contact angle with adjacent metal traces.

[0204] Figure 4 This is a cross-sectional view of an abnormal conduction structure provided in an embodiment of this application.

[0205] like Figure 4As shown, this image is a cross-sectional view of an abnormal conductive structure, revealing the vertical structural relationship between two metal layers. The dark areas at the top and bottom of the image represent the dielectric layer, while the bright rectangular area in the middle represents the metal structure. This image reflects the distribution of the abnormal conductive structure in the interlayer direction. This cross-sectional image allows us to determine whether the abnormal conductive structure penetrates the dielectric layer to achieve an abnormal connection between different metal layers.

[0206] Figure 5 A high-resolution cross-sectional view after physical verification is provided for an embodiment of this application.

[0207] like Figure 5 As shown, this image is a high-resolution cross-sectional image obtained after physical verification based on the verification parameters. The image was obtained through focused ion beam sample preparation and scanning electron microscopy imaging, achieving a resolution significantly higher than X-ray imaging. The rough area at the top of the image represents the protective layer formed by focused ion beam etching. The cross-sectional structure of the metal layer is shown in the center of the image, clearly revealing its thickness, boundary morphology, and the distribution of the interlayer medium. This high-resolution image confirms the existence of the anomalous conductive structure and, combined with energy dispersive spectroscopy (EDS) analysis, determines its material composition. This verification feedback data can be used to correct the distribution of the failure region and improve the accuracy of anomalous structure identification.

[0208] Figure 6 This is a schematic diagram of the structure of a chip failure analysis system provided in an embodiment of this application, as shown below. Figure 2 As shown, the failure analysis system for this chip includes:

[0209] The data acquisition module is used to obtain first data and second data of the abnormal chip; the first data characterizes the electrical abnormality characteristics of the abnormal chip; the second data characterizes the three-dimensional structure of the abnormal chip.

[0210] The distribution determination module is used to determine the failure region distribution based on the first data and the second data; the failure region distribution characterizes the probability region distribution of abnormal points within the abnormal chip; the abnormal point is the location of a physical defect in the three-dimensional structure that causes electrical abnormality features;

[0211] The image acquisition module is used to obtain a first image of the faulty chip; the first image is a three-dimensional image.

[0212] The structure determination module is used to determine the abnormal structure involved in the abnormal point in the abnormal chip through failure analysis based on the failure region distribution and the first image.

[0213] Based on the above embodiments, as an optional embodiment, the data acquisition module is further configured to obtain electrical test data of the abnormal chip; determine first data based on the electrical test data; the first data includes at least one or more of the following combinations: abnormal pin data, used to characterize the pins in the abnormal chip that have electrical abnormalities and their corresponding short-circuit target networks; conduction linearity, used to characterize the linearity of the current-voltage characteristics corresponding to the abnormal chip; temperature response data, used to characterize the response characteristics of the abnormal chip under temperature change conditions.

[0214] Based on the above embodiments, as an optional embodiment, the distribution determination module is further configured to determine the network connection relationship of the abnormal chip based on the second data; the network connection relationship characterizes the topological relationship of the internal interconnection structure of the abnormal chip; based on the network connection relationship and the abnormal pin data in the first data, a candidate path set is determined; the candidate path set characterizes the spatial position and adjacent region of the abnormal pin and the corresponding short-circuit target network in the three-dimensional structure; a spatial prior distribution is generated based on the spatial distribution of the candidate path set in the three-dimensional structure; the spatial prior distribution characterizes the proximity of the spatial position in the three-dimensional structure to the candidate path set; the spatial prior distribution is modulated by the electrical abnormality features in the first data to determine the failure region distribution.

[0215] Based on the above embodiments, as an optional embodiment, the distribution determination module is further configured to calculate the spatial distance between any target location in the three-dimensional structure and each path in the candidate path set; process each path based on the spatial distance to obtain the proximity intensity value corresponding to each path; the proximity intensity value is negatively correlated with the spatial distance; determine the prior probability value of the target location based on the proximity intensity value corresponding to each path; and generate a spatial prior distribution based on the prior probability value of each target location in the three-dimensional structure.

[0216] Based on the above embodiments, as an optional embodiment, the distribution determination module is further configured to determine the failure mechanism type based on the electrical anomaly characteristics in the first data; determine the modulation parameters based on the failure mechanism type; different failure mechanism types have different modulation parameters; perform weighted modulation on the prior probability values ​​of each position in the spatial prior distribution according to the modulation parameters to obtain the modulation probability values ​​of each position in the spatial prior distribution; and generate the failure region distribution based on the modulation probability values ​​of each position in the spatial prior distribution.

[0217] Based on the above embodiments, as an optional embodiment, the structure determination module is further configured to identify the internal structure of the abnormal chip based on the first image to obtain structural distribution data; extract a set of candidate abnormal connected components within the abnormal chip based on the structural distribution data; the candidate abnormal connected components are abnormal conductive structures connecting different networks in a three-dimensional structure; perform correlation scoring on each candidate abnormal connected component in the set of candidate abnormal connected components based on the distribution of the failure region to obtain a scoring result; the scoring result characterizes the degree of correlation between each candidate abnormal connected component and electrical abnormal features; and determine the abnormal structure involved in the abnormal point in the set of candidate abnormal connected components based on the scoring result.

[0218] Based on the above embodiments, as an optional embodiment, the structure determination module is further configured to extract morphological feature data of the target candidate abnormal connected components in the candidate abnormal connected component set; the morphological feature data characterizes the geometric morphological features of the target candidate abnormal connected components; determine the failure mechanism matching degree of the target candidate abnormal connected components based on the morphological feature data; the failure mechanism matching degree characterizes the degree of consistency between the morphological features of the target candidate abnormal connected components and the failure mechanism type determined based on the first data; determine the spatial matching degree based on the position of the target candidate abnormal connected components in the failure region distribution; the spatial matching degree characterizes the spatial proximity of the target candidate abnormal connected components to the candidate path set; and determine the association score value of the target candidate abnormal connected components based on the failure mechanism matching degree and the spatial matching degree.

[0219] Figure 7 This is a schematic diagram of the physical structure of an electronic device provided in an embodiment of this application, such as... Figure 7 As shown, the electronic device may include a processor 710, a communications interface 720, a memory 730, and a communication bus 740. The processor 710, communications interface 720, and memory 730 communicate with each other via the communication bus 740. The processor 710 can call logic instructions from the memory 730 to execute chip failure analysis methods.

[0220] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0221] On the other hand, this application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the chip failure analysis methods provided by the above methods.

[0222] In another aspect, this application also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the failure analysis methods for chips provided by the methods described above.

[0223] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0224] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0225] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A chip failure analysis method, characterized in that, include: Obtain first and second data of the abnormal chip; the first data characterizes the electrical abnormality features of the abnormal chip; The second data characterizes the three-dimensional structure of the abnormal chip; The distribution of failure areas is determined based on the first data and the second data; The failure region distribution characterizes the probability region distribution of abnormal points within the abnormal chip; the abnormal point is the physical defect location in the three-dimensional structure that causes the electrical abnormality feature; Obtain a first image of the abnormal chip; the first image is a three-dimensional image; Based on the failure region distribution and the first image, the abnormal structure involved in the abnormal point in the abnormal chip is determined through failure analysis.

2. The chip failure analysis method according to claim 1, characterized in that, The first data obtained from the abnormal chip includes: Obtain electrical test data of the malfunctioning chip; First data is determined based on the electrical test data; the first data includes a combination of at least one or more of the following: Abnormal pin data is used to characterize the pins in the abnormal chip that have experienced electrical abnormalities and their corresponding short-circuit target networks; Conduction linearity is used to characterize the linearity of the current-voltage characteristics corresponding to the abnormal chip. Temperature response data is used to characterize the response characteristics of the abnormal chip under temperature change conditions.

3. The chip failure analysis method according to claim 1, characterized in that, The step of determining the distribution of failure areas based on the first data and the second data includes: The network connectivity relationship of the malfunctioning chip is determined based on the second data; the network connectivity relationship characterizes the topological relationship of the internal interconnection structure of the malfunctioning chip. Based on the network connection relationship and the abnormal pin data in the first data, a candidate path set is determined; the candidate path set represents the spatial position and adjacent area of ​​the abnormal pin and the corresponding short-circuit target network in the three-dimensional structure. A spatial prior distribution is generated based on the spatial distribution of the candidate path set in the three-dimensional structure; the spatial prior distribution characterizes the proximity of the spatial location in the three-dimensional structure to the candidate path set. The spatial prior distribution is modulated based on the electrical anomaly features in the first data to determine the distribution of the failure region.

4. The chip failure analysis method according to claim 3, characterized in that, The generation of a spatial prior distribution based on the spatial distribution of the candidate path set in the three-dimensional structure includes: For any target location in the three-dimensional structure, calculate the spatial distance between the target location and each path in the candidate path set; Each path is processed based on the spatial distance to obtain the proximity intensity value corresponding to each path; the proximity intensity value is negatively correlated with the spatial distance; The prior probability value of the target location is determined based on the proximity intensity value corresponding to each path; A spatial prior distribution is generated based on the prior probability values ​​of each target location in the three-dimensional structure.

5. The chip failure analysis method according to claim 3, characterized in that, Modulating the spatial prior distribution with electrical anomaly features from the first data to determine the failure region distribution includes: The failure mechanism type is determined based on the electrical anomaly characteristics in the first data; The modulation parameters are determined based on the failure mechanism type; different failure mechanism types have different modulation parameters. The prior probability values ​​at each position in the spatial prior distribution are weighted and modulated according to the modulation parameters to obtain the modulation probability values ​​at each position in the spatial prior distribution. The failure region distribution is generated based on the modulation probability values ​​at each location in the spatial prior distribution.

6. The chip failure analysis method according to claim 1, characterized in that, The step of determining the abnormal structure involved in the abnormal point in the abnormal chip through failure analysis based on the failure region distribution and the first image includes: Based on the first image, the internal structure of the abnormal chip is identified to obtain structural distribution data; Based on the structural distribution data, a set of candidate abnormal connected components is extracted within the abnormal chip; the candidate abnormal connected components are abnormal conductive structures that connect different networks in the three-dimensional structure. Based on the distribution of the failure region, each candidate abnormal connected component in the candidate abnormal connected component set is correlated and scored to obtain a scoring result; the scoring result characterizes the degree of correlation between each candidate abnormal connected component and the electrical abnormality feature. Based on the scoring results, the abnormal structure involved in the abnormal point is determined from the set of candidate abnormal connected components.

7. The chip failure analysis method according to claim 6, characterized in that, The association scoring of each candidate abnormal connected component in the candidate abnormal connected component set based on the distribution of the failure region yields the scoring results, including: For the target candidate abnormal connected component in the set of candidate abnormal connected components, extract the morphological feature data of the target candidate abnormal connected component; the morphological feature data characterizes the geometric morphological features of the target candidate abnormal connected component; The failure mechanism matching degree of the target candidate abnormal connected component is determined based on the morphological feature data; the failure mechanism matching degree characterizes the degree of consistency between the morphological features of the target candidate abnormal connected component and the failure mechanism type determined based on the first data; The spatial matching degree is determined based on the position of the target candidate abnormal connected component in the distribution of the failure region; the spatial matching degree characterizes the spatial proximity between the target candidate abnormal connected component and the candidate path set. The association score of the target candidate abnormal connected component is determined based on the failure mechanism matching degree and the spatial matching degree.

8. The chip failure analysis method according to claim 1, characterized in that, Also includes: Obtain the spatial location of the abnormal structure; Verification parameters are generated based on the spatial location of the abnormal structure. The verification parameters are used to physically verify the sample preparation coordinates and cross-sectional orientation information of the abnormal structure. Obtain verification feedback data for the abnormal structure; The verification feedback data is the observation result after performing physical verification based on the verification parameters; The failure region distribution is corrected based on the verification feedback data to obtain the corrected failure region distribution. Based on the corrected failure region distribution and the first image, the abnormal structure involved in the abnormal point is re-determined in the abnormal chip.

9. A chip failure analysis system, characterized in that, include: The data acquisition module is used to obtain first data and second data of the abnormal chip; the first data characterizes the electrical abnormality features of the abnormal chip. The second data characterizes the three-dimensional structure of the abnormal chip; A distribution determination module is used to determine the distribution of failure areas based on the first data and the second data; The failure region distribution characterizes the probability region distribution of abnormal points within the abnormal chip; the abnormal point is the physical defect location in the three-dimensional structure that causes the electrical abnormality feature; An image acquisition module is used to obtain a first image of the abnormal chip; the first image is a three-dimensional image. The structure determination module is used to determine the abnormal structure involved in the abnormal point in the abnormal chip through failure analysis based on the distribution of the failure area and the first image.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the chip failure analysis method as described in any one of claims 1-8.

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