A system on chip

Abstract

The application is suitable for the field of embedded systems, and provides a system on chip, which comprises a bus, a memory controller and a memory, the memory controller being connected to the memory; the bus comprises a first interface, the memory controller comprises a second interface, the first interface is connected to the second interface through a single port; the first interface comprises a plurality of first request queues, the second interface comprises a plurality of second request queues, and an access request in a single first request queue enters a corresponding single second request queue after being transmitted through the port; the first interface comprises a queue state tracking unit, and the queue state tracking unit is used for controlling the transmission of the corresponding first request queue according to the state of the second request queue.

Description

Technical Field

[0001] This application belongs to the field of embedded systems, and in particular relates to a system-on-a-chip. Background Technology

[0002] A System-on-a-Chip (SoC) is a chip integration that integrates the core components of an information system onto a single chip. A SoC can include multiple processing units, such as microprocessors, digital signal processors, graphics processing units, and neural network processors, which often share memory.

[0003] In a system-on-a-chip (SoC), a memory controller is typically included. The memory controller connects to both the bus and the memory, and is used to handle access requests from various processing units transmitted via the bus. In related technologies, the connection between the memory controller and the bus can be either a single-port or multi-port mode.

[0004] In single-port mode, the memory controller is connected to the bus through a single port. Access requests from different processing units are transmitted through this port. These requests may have different priorities. Single-port transmission generally sorts these requests directly according to time order, which often causes head-blocking problems. That is, the lower priority requests that are ranked earlier are blocked on the common transmission path because the low priority access queue in the memory controller is full. Even if the high priority access queue in the memory controller is not full, the higher priority requests that are ranked later are blocked by the lower priority requests that are ranked earlier and cannot be transmitted.

[0005] In multi-port mode, the memory controller is connected to the bus through multiple ports. Different ports can independently receive different access requests, achieving parallelism and isolation of access requests with different priorities by adding hardware ports. However, the increase in the number of ports leads to a significant increase in the number of traces between the bus and the memory controller in the chip, requiring wider trace channels, thereby increasing chip area and the risk of timing convergence. Therefore, the connection method between the memory controller and the bus in related technologies still needs optimization. Summary of the Invention

[0006] This application provides a system-on-a-chip that can solve the problem that the connection method between the memory controller and the bus in related technologies still needs to be optimized.

[0007] In a first aspect, embodiments of this application provide a system-on-a-chip (SoC) including a bus, a memory controller, and memory, with the memory controller connected to the memory; the bus includes a first interface, and the memory controller includes a second interface, with the first interface connected to the second interface via a single port; the first interface includes multiple first request queues, and the second interface includes multiple second request queues, with access requests in a single first request queue entering the corresponding single second request queue after transmission through the port; the first interface includes a queue status tracking unit, which is used to control the transmission of the corresponding first request queue according to the status of the second request queue.

[0008] In one possible implementation of the first aspect, the queue state tracking unit is used to output an enable signal corresponding to the second request queue. The enable signal is used to control the transmission of the corresponding first request queue, and the value of the enable signal changes with the state of the corresponding second request queue.

[0009] In one possible implementation of the first aspect, the first interface further includes multiple logic gates and an arbitration unit. Each logic gate corresponds one-to-one with a first request queue. The input of each logic gate is connected to the corresponding first request queue and an enable signal. The output of each logic gate is connected to the input of the arbitration unit, and the output of the arbitration unit is connected to a port. When the value of the enable signal indicates that transmission is allowed, the output of the corresponding logic gate is the same as the input first request queue. When the value of the enable signal indicates that transmission is not allowed, the output of the corresponding logic gate is a set value. The arbitration unit is used to select one input signal output according to a preset arbitration strategy.

[0010] In one possible implementation of the first aspect, the first interface further includes an arbitration unit, the input of which is connected to each first request queue and an enable signal; the arbitration unit is used to determine whether the corresponding first request queue is allowed to transmit based on the enable signal, and to select one output from the first request queue that is allowed to transmit according to a preset arbitration strategy.

[0011] In one possible implementation of the first aspect, the queue status tracking unit is used to receive a status update signal from the second request queue, the status update signal being used to indicate whether there is an empty slot in the second request queue.

[0012] In one possible implementation of the first aspect, when the status update signal indicates that there is no empty space in the second request queue, the value of the enable signal indicates that transmission is not allowed; when the status update signal indicates that there is an empty space in the second request queue, the value of the enable signal indicates that transmission is allowed.

[0013] In one possible implementation of the first aspect, the state update signal includes the number of empty slots in the second request queue.

[0014] In one possible implementation of the first aspect, the value of the enable signal indicates that the allowed transmission duration is positively correlated with the number of available slots.

[0015] In one possible implementation of the first aspect, the request attributes of different second request queues are different.

[0016] In one possible implementation of the first aspect, the request attributes include at least one of access type, priority, and request source.

[0017] Secondly, embodiments of this application provide a vehicle that includes the system-on-a-chip provided in the first aspect of this application.

[0018] The beneficial effects of this application embodiment compared with the prior art are as follows: By providing a system-on-a-chip (SoC) including a bus, a memory controller, and memory, with the memory controller connected to the memory; the bus includes a first interface, and the memory controller includes a second interface, with the first interface connected to the second interface via a single port; the first interface includes multiple first request queues, and the second interface includes multiple second request queues, with access requests in a single first request queue entering the corresponding single second request queue after transmission through the port; the first interface includes a queue status tracking unit, which controls the transmission of the corresponding first request queue according to the status of the second request queue. In this embodiment, the queue status tracking unit in the first interface of the bus can control the transmission of the corresponding first request queue according to the status of the second request queue. If there is no empty space in the second request queue, the transmission of the corresponding first request queue is not allowed. In the scenario where head blocking occurs in the original single-port mode, the low-priority first request queue will not be allowed to transmit because its corresponding first request queue is full, and will not participate in the port sorting / arbitration, thus not affecting the transmission of the high-priority first request queue. Compared with the single-port mode, this solves the problem of transmission congestion and greatly improves the system throughput. Compared to multi-port mode, this approach only requires a single port to handle the parallelism and isolation of different types of access requests. Without affecting overall throughput, it significantly reduces the number of traces between the bus and the memory controller, thereby reducing chip area and improving timing closure. Therefore, the on-chip system provided in this embodiment combines the advantages of both single-port and dual-port solutions while avoiding their respective disadvantages. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the structure of the bus and memory controller connection part provided in one embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the bus and memory controller connection part provided in another embodiment of this application. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Figure 1 The diagram shown is a partial structure of the on-chip system provided in one embodiment of this application. (See reference...) Figure 1 The system-on-a-chip includes a processor 10, a bus 20, a memory controller 30, and a memory 40.

[0030] Those skilled in the art will understand that Figure 1 The structure of the system-on-a-chip shown does not constitute a limitation on the system-on-a-chip and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0031] The following is combined with Figure 1-3 The various components of the system-on-a-chip are described in detail.

[0032] The processor 10 can specifically be a central processing unit (CPU), or other general-purpose processors, microcontroller units (MCUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be any conventional processor.

[0033] Processor 10 is one type of processing unit included in a system on chip. In addition to processor 10, the system on chip may also include other processing units, such as digital signal processors, graphics processing units, neural network processors, etc.

[0034] Memory 40, also known as main memory, is a high-speed random access memory (RAM) that can be directly addressed and accessed by various processing units, including processor 10, to temporarily store data required and generated by the executing program. Memory 40 may include at least one of static RAM (SRAM) and dynamic RAM (DRAM). Due to cost and power consumption considerations, DRAM is commonly used as main memory.

[0035] Each processing unit, including the processor 10, is connected to the bus 20 and accesses the memory 40 through the bus 20.

[0036] The memory controller 30 is connected to the bus 20 and the memory 40 respectively, and is used to process access requests (hereinafter referred to as access requests) to the memory 40 from each processing unit and transmitted through the bus 20.

[0037] like Figure 2 As shown, bus 20 includes a first interface 21, and memory controller 30 includes a second interface 31. The first interface 21 is connected to the second interface 31 through a single port 23. Memory controller 30 also includes a memory scheduling module 32, which is connected to the second interface 31 and memory 40 respectively, and is used to perform corresponding operations on memory 40 according to memory access requests transmitted by the second interface 31.

[0038] The operating frequency of memory 40 is significantly lower than that of bus 20 and processing unit, therefore the first interface 21 and the second interface 31 include request queues for temporarily storing access requests. Figure 2 The direction of access requests is indicated by a solid line with an arrow. In this embodiment, the first interface 21 includes multiple first request queues 211, and the second interface 31 includes multiple second request queues 311. Each first request queue 211 corresponds to only one second request queue 311, meaning that an access request in a single first request queue 211 enters its corresponding single second request queue 311 after being transmitted through port 23. Conversely, the number of first request queues 211 corresponding to a single second request queue 311 can be one or more. That is, the number of first request queues 211 is greater than or equal to the number of second request queues 311.

[0039] Different second request queues 311 have different request attributes, which may include at least one of access type, priority, and request source. Access type may include read and write, and request source may refer to the processing unit that initiated the access request, such as processor 10, digital signal processor, graphics processing unit, neural network processor, etc.

[0040] For example, Figure 2The first and second request queues 311 shown are divided into four types according to priority and access type: high-priority read, low-priority read, high-priority write, and low-priority write. In practice, the first and second request queues 311 can be divided in other ways.

[0041] The first interface 21 includes a queue status tracking unit 212, which controls the transmission of the corresponding first request queue 211 according to the status of the second request queue 311. Specifically, the queue status tracking unit 212 allows the transmission of the corresponding first request queue 211 when there is an empty slot in the second request queue 311, and disallows the transmission of the corresponding first request queue 211 when there is no empty slot in the second request queue 311.

[0042] The queue status tracking unit 212 can output an enable signal corresponding to the second request queue 311. The enable signal is used to control the transmission of the corresponding first request queue 211. The value of the enable signal changes with the status change of the corresponding second request queue 311. Figure 2 The direction of the enable signal is indicated by a dotted line with an arrow. The number of output terminals of the queue status tracking unit 212 can be the same as the number of the first request queue 211 or the number of the second request queue 311; there is no restriction here.

[0043] The enable signal is generally a digital signal, and its value can be a first value and a second value. The first value indicates that transmission is allowed, and the second value indicates that transmission is not allowed. One of the first value and the second value is 1, and the other is 0. When there is an empty slot in the corresponding second request queue 311, the queue status tracking unit 212 controls the enable signal to be the first value; when there is no empty slot in the corresponding second request queue 311, the queue status tracking unit 212 controls the enable signal to be the second value.

[0044] The queue status tracking unit 212 can receive status update signals from the second request queue 311 and control the value of the corresponding enable signal according to the status update signals. The status update signals are used to indicate whether there are empty slots in the second request queue 311. Figure 2 The direction of the state update signal is indicated by a dashed line with an arrowhead.

[0045] Specifically, when the status update signal indicates that there is no empty slot in the second request queue 311, the value of the enable signal indicates that transmission is not allowed, i.e., the second value; when the status update signal indicates that there is an empty slot in the second request queue 311, the value of the enable signal indicates that transmission is allowed, i.e., the first value.

[0046] Using the time required for the memory controller 30 to process a single access request as a single transmission cycle, assuming all second request queues 311 are full (i.e., no empty slots), each transmission cycle adds an empty slot to one of the second request queues 311. Correspondingly, the access request at the front of the corresponding first request queue 211 is allowed to be transmitted. It can be seen that a status update signal indicating whether there is an empty slot in the second request queue 311 generally needs to be transmitted to the queue status tracking unit 212 at a high frequency, or the queue status tracking unit 212 needs to read the status update signal at a high frequency and control the value of the corresponding enable signal based on the status update signal, for example, updating it once per transmission cycle.

[0047] Optionally, the status update signal includes the number of available slots in the second request queue 311, also known as the availability depth. The value of the corresponding enable signal indicates that the allowed transmission duration is positively correlated with the number of available slots, for example, it can be the product of the transmission period and the number of available slots. In this case, the period of the transmission status update signal / the period that controls the value of the corresponding enable signal based on the aforementioned status update signal can be made longer, for example, it can be the product of the transmission period and the actual maximum value or the allowed maximum value of the number of available slots.

[0048] To enable control of the transmission of the first request queue 211 based on the enable signal, refer to... Figure 2 The first interface 21 also includes multiple logic gates 214 and an arbitration unit 213. Each logic gate 214 corresponds one-to-one with a first request queue 211. The input of each logic gate 214 is connected to the corresponding first request queue 211 and an enable signal. The output of each logic gate 214 is connected to the input of the arbitration unit 213, and the output of the arbitration unit 213 is connected to port 23. The arbitration unit 213 is used to select one input signal for output according to a preset arbitration strategy. The specific arbitration strategy is not limited here.

[0049] When the enable signal value indicates that transmission is allowed (i.e., the first value), the output of the corresponding logic gate 214 is the same as the input first request queue 211. When the enable signal value indicates that transmission is not allowed (i.e., the second value), the output of the corresponding logic gate 214 is a set value, such as 0. For example, logic gate 214 can be an AND gate, with the first value being 1 and the second value being 0; or, logic gate 214 can be an OR gate, with the first value being 0 and the second value being 1.

[0050] Figure 2 In the illustrated embodiment, the logic gate 214 responsible for processing the enable signal is a device independent of the arbitration unit 213. In another specific embodiment of this application, the arbitration unit 213 can perform the processing of the enable signal and the arbitration of the request queue. Figure 3As shown, the first interface 21 also includes an arbitration unit 213. The input of the arbitration unit 213 is connected to each first request queue 211 and an enable signal. The arbitration unit 213 is used to determine whether the corresponding first request queue 211 is allowed to transmit based on the enable signal, and select one output from the first request queue 211 that is allowed to transmit according to a preset arbitration strategy.

[0051] Through the implementation of this embodiment, the queue status tracking unit in the first interface of the bus can control the transmission of the corresponding first request queue according to the status of the second request queue. Transmission of the corresponding first request queue is not allowed if the second request queue has no available slots; transmission of the corresponding first request queue is only allowed if the second request queue has available slots. In scenarios where head-end blocking occurs in the original single-port mode, low-priority first request queues will not be allowed to transmit because their corresponding first request queues are full, and will not participate in port sorting / arbitration. Therefore, it will not affect the transmission of high-priority first request queues. Compared to the single-port mode, this solves the transmission congestion problem and greatly improves the system throughput. Compared to the multi-port mode, only a single port is needed to complete the parallelism and isolation of different types of access requests. Without affecting the overall throughput, it significantly reduces the number of traces between the bus and the memory controller, thereby reducing the chip area and also facilitating timing convergence. Therefore, the on-chip system provided in this embodiment combines the advantages of both single-port and dual-port solutions while avoiding their respective disadvantages.

[0052] This application also provides a vehicle, specifically a wheeled vehicle powered by electricity, fossil fuels, or other similar sources. This vehicle includes the system-on-a-chip (SoC) provided in the foregoing embodiments, which controls the operation of the vehicle.

[0053] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0054] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0055] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0056] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0057] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A system-on-a-chip, characterized in that, The system-on-a-chip includes a bus, a memory controller, and memory, with the memory controller connected to the memory. The bus includes a first interface, and the memory controller includes a second interface, wherein the first interface is connected to the second interface via a single port; The first interface includes multiple first request queues, and the second interface includes multiple second request queues. An access request in a single first request queue is transmitted through the port and then enters the corresponding single second request queue. The first interface includes a queue status tracking unit, which is used to control the transmission of the corresponding first request queue according to the status of the second request queue.

2. The system-on-a-chip as described in claim 1, characterized in that, The queue status tracking unit is used to output an enable signal corresponding to the second request queue. The enable signal is used to control the transmission of the corresponding first request queue. The value of the enable signal changes with the status of the corresponding second request queue.

3. The system-on-a-chip as described in claim 2, characterized in that, The first interface further includes multiple logic gates and an arbitration unit. Each logic gate corresponds to a first request queue. The input of each logic gate is connected to the corresponding first request queue and the enable signal. The output of each logic gate is connected to the input of the arbitration unit. The output of the arbitration unit is connected to the port. The value of the enable signal indicates that when transmission is allowed, the output of the corresponding logic gate is the same as the input of the first request queue; the value of the enable signal indicates that when transmission is not allowed, the output of the corresponding logic gate is a set value. The arbitration unit is used to select one of the input terminals for signal output according to a preset arbitration strategy.

4. The system-on-a-chip as described in claim 2, characterized in that, The first interface further includes an arbitration unit, the input of which is connected to each of the first request queues and the enable signal; The arbitration unit is used to determine whether the corresponding first request queue is allowed to be transmitted based on the enable signal, and to select one output from the first request queue that is allowed to be transmitted according to the preset arbitration strategy.

5. The system-on-a-chip as described in any one of claims 2-4, characterized in that, The queue status tracking unit is used to receive a status update signal from the second request queue, and the status update signal is used to indicate whether there is an empty slot in the second request queue.

6. The system-on-a-chip as described in claim 5, characterized in that, When the status update signal indicates that there is no empty slot in the second request queue, the value of the enable signal indicates that transmission is not allowed; when the status update signal indicates that there is an empty slot in the second request queue, the value of the enable signal indicates that transmission is allowed.

7. The system-on-a-chip as described in claim 5, characterized in that, The status update signal includes the number of empty slots in the second request queue.

8. The system-on-a-chip as described in claim 7, characterized in that, The value of the enable signal indicates that the allowed transmission duration is positively correlated with the number of available slots.

9. The system-on-a-chip as described in any one of claims 1-4, characterized in that, Different second request queues have different request attributes.

10. The system-on-a-chip as claimed in claim 9, characterized in that, The request attributes include at least one of access type, priority, and request source.

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