Temperature-dependent analytical method for threshold voltage of symmetric bilayer double-gate strained-silicon mosfet

Abstract

This invention discloses a temperature-dependent analytical method for the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET, relating to the field of semiconductor technology. The method includes: substituting the approximate expression of the potential energy of strained silicon in the vertical direction into the first boundary condition and the structural symmetry condition to obtain a two-dimensional channel potential energy expression; substituting the two-dimensional channel potential energy expression into the Poisson equation and setting the coordinates perpendicular to the channel direction to 0 to obtain a temperature-dependent surface potential equation; solving the surface potential energy equation using the second, third, fourth, and fifth boundary conditions to obtain an analytical expression for the surface potential; obtaining the minimum surface potential by taking the first derivative of the analytical expression; and obtaining a temperature model for the threshold voltage based on the minimum surface potential and the definition of the threshold voltage; and solving the temperature model to obtain the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET. This method improves the analytical accuracy of the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a temperature-dependent method for analyzing the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET. Background Technology

[0002] As the feature sizes of Metal-Oxide-Semiconductor (MOS) devices have entered the deep submicron and nanometer ranges, the theory of proportional scaling has led to the emergence of microscopic physical effects, with the short-channel effect becoming increasingly prominent. Researchers have conducted extensive studies on gate engineering and channel engineering to suppress the short-channel effect and improve carrier mobility.

[0003] In channel engineering, the tensile or compressive strain effects generated by lattice mismatch in silicon (Si) and silicon-germanium (SiGe) materials are utilized to obtain strained materials with special properties, significantly enhancing the mobility of electrons and holes in strained silicon. Symmetrical dual-material dual-gate strained silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) combine the advantages of dual-gate, heterogate, and strained silicon technologies, continuously driving improvements in device performance.

[0004] To reduce computational complexity, existing analytical methods for the threshold voltage of symmetric dual-material dual-gate strained silicon MOSFETs typically simplify the complex coupling mechanism of dual-material dual-gate strained silicon MOSFETs, which leads to lower analytical accuracy of the threshold voltage of symmetric dual-material dual-gate strained silicon MOSFETs. Summary of the Invention

[0005] Therefore, it is necessary to provide a temperature-dependent method for resolving the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET, addressing the aforementioned technical problems. This method improves the accuracy of threshold voltage resolution for symmetrical dual-material dual-gate strained silicon MOSFETs.

[0006] The following technical solution is adopted in this specification: This specification provides a temperature-dependent analytical method for the threshold voltage of a symmetric dual-material dual-gate strained silicon MOSFET, including: Substituting the approximate expression for the potential energy of strained silicon in the vertical direction into the first boundary condition and the structural symmetry condition respectively, we obtain the two-dimensional channel potential energy expression. The first boundary condition is used to describe the continuity of the electric flux between the strained silicon layer and the gate dielectric layer. The structural symmetry condition is used to describe the electric flux characteristics at 1 / 2 thickness of the strained silicon channel. Substituting the two-dimensional channel potential energy expression into the Poisson equation, and letting the coordinates perpendicular to the channel direction... yWhen the value is 0, the temperature-dependent surface potential equation is obtained; Solving the surface potential energy equation using the second, third, fourth, and fifth boundary conditions yields the analytical expression for the surface potential. The second boundary condition describes the continuity of the surface potential at the boundary between the two regions of the strained silicon channel; the third boundary condition describes the continuity of the electric field at the boundary between the two regions of the strained silicon channel; the fourth boundary condition describes the continuity of the surface potential at the source end; and the fifth boundary condition describes the continuity of the surface potential at the drain end. The first derivative of the surface potential expression is obtained to obtain the minimum surface potential. Based on the minimum surface potential and the definition of threshold voltage, the threshold voltage temperature model is obtained. The threshold voltage temperature model was solved to obtain the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET.

[0007] Optionally, the approximate expression for the potential energy of strained silicon in the vertical direction is: ; in, For strained silicon in the vertical direction y The potential energy on the surface is approximately represented as follows: To determine the front surface potential of the two regions of the strain silicon channel, j =1,2, , All are with and T The relevant functions, y The coordinate axes are perpendicular to the direction of the channel. x The coordinate axes are parallel to the direction of the channel.

[0008] Optionally, the first boundary condition is: ; in, The dielectric constant of the gate dielectric layer is . The dielectric constant of the channel is . Gate-source voltage, This refers to the corrected flat-band voltage between the strained silicon layer and the control gate M1 / shielding gate M2. The thickness of the gate dielectric layer, , T For temperature; The structural symmetry condition is: ; in, This refers to the channel thickness.

[0009] Optionally, the expression for the two-dimensional channel potential energy is: .

[0010] Alternatively, the Poisson equation is: ; in, For strained silicon in the vertical direction y The potential energy on the surface is approximately represented as follows: The channel doping concentration, The charge of electrons, , For the first j- The length of a region, For the first j The length of each region The dielectric constant of the channel is . y The coordinate axes are perpendicular to the direction of the channel. x The coordinate axes are parallel to the direction of the channel; The temperature-dependent surface potential equation is: ; ; ; in, To determine the front surface potential of the two regions of the strain silicon channel, j =1,2, For the channel thickness, The thickness of the gate dielectric layer, The dielectric constant of the gate dielectric layer is . The dielectric constant of the gate dielectric layer is . The corrected flat band voltage between the strained silicon layer and the control gate M1 / shielding gate M2.

[0011] Alternatively, the second boundary condition is: ; in, To measure the surface potential of the strain silicon channel near the source region, i.e., region I, at the boundary between the two regions. To determine the surface potential at the interface between the two regions, i.e., region II, near the drain end of the strain silicon channel. T For temperature, The length of region I of channel; The third boundary condition is: ; in, To compensate for the channel potential in the region near the source end of the silicon channel, i.e., region I, To compensate for the channel potential of the silicon channel near the drain region, i.e., region II; The fourth boundary condition is: ; in, For the source end surface potential of the strain silicon channel, This is the built-in potential between the strain silicon layer and the source or drain terminal; The fifth boundary condition is: in, To the surface potential at the drain end of the strain silicon channel, This is the drain-source voltage.

[0012] Alternatively, the analytical expression for the surface potential is: ; in, , , , , , , , , , L=L 1 +L 2 The length of the channel. The length of region I of channel is The length of region II of the channel. , .

[0013] Optionally, the minimum surface potential is: ; in, This represents the minimum surface potential.

[0014] Optionally, the threshold voltage is defined as satisfying Gate-source voltage at that time; in, , , for Fermi potential within the region, , This is a correction value for the minimum surface potential of the strained silicon layer. k Boltzmann's constant, T For temperature, The intrinsic doping concentration of bulk silicon, The strain is the Fermi potential. The strain is the bandgap width of silicon. For bulk silicon, the valence band state density The valence band density of strained silicon is given.

[0015] Optionally, the formula corresponding to the threshold voltage-temperature model is: ; ; ; ; ; in, Threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET T For temperature, , This is the drain-source voltage.

[0016] This specification provides a temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage resolution device, comprising: The first determining module is used to substitute the approximate expression of the potential energy of strained silicon in the vertical direction into the first boundary condition and the structural symmetry condition to obtain the two-dimensional channel potential energy expression; the first boundary condition is used to describe the continuity of the electric flux between the strained silicon layer and the gate dielectric layer; the structural symmetry condition is used to describe the electric flux characteristics at 1 / 2 thickness of the strained silicon channel. The second determining module is used to substitute the two-dimensional channel potential energy expression into the Poisson equation, and to define the coordinates perpendicular to the channel direction. y When the value is 0, the temperature-dependent surface potential equation is obtained; The third determining module is used to solve the surface potential energy equation using the second, third, fourth, and fifth boundary conditions to obtain the analytical expression for the surface potential. The second boundary condition is used to describe the continuity of the surface potential at the junction of the two regions of the strained silicon channel; the third boundary condition is used to describe the continuity of the electric field at the junction of the two regions of the strained silicon channel; the fourth boundary condition is used to describe the continuity of the surface potential at the source end; and the fifth boundary condition is used to describe the continuity of the surface potential at the drain end. The fourth determination module is used to calculate the first derivative of the surface potential analytical expression to obtain the minimum surface potential, and based on the definition of the minimum surface potential and the threshold voltage, to obtain the threshold voltage temperature model. The calculation module is used to solve the threshold voltage temperature model to obtain the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET.

[0017] This specification provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method.

[0018] This specification provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the above-described method for constructing an analytical expression for a temperature-dependent MOSFET threshold voltage.

[0019] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects: In the temperature-dependent analytical method for the threshold voltage of a symmetric dual-material dual-gate strained silicon MOSFET provided in this specification, a two-dimensional channel potential energy expression is obtained based on the first boundary condition, the structural symmetry condition, and the approximate expression for the potential energy of strained silicon in the vertical direction. Substituting this two-dimensional channel potential energy expression into the Poisson equation, and letting… y The surface potential equation is obtained by setting the boundary condition to 0, which is temperature-dependent. The surface potential energy equation is solved using the second, third, fourth, and fifth boundary conditions to obtain the analytical expression for the surface potential. The first derivative of the analytical expression is taken to obtain the minimum surface potential value. Based on the minimum surface potential value and the definition of the threshold voltage, the temperature-dependent analytical expression for the threshold voltage is obtained. This invention considers the influence of temperature when constructing the temperature-dependent analytical expression for the threshold voltage. Compared to traditional modeling methods that do not account for temperature effects, this accurately reflects the actual electrical characteristics of the device under different temperature conditions, effectively improving the analytical accuracy of the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0021] Figure 1 This document provides a schematic flowchart of a temperature-dependent analytical method for the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET. Figure 2 A schematic diagram of the symmetrical dual-material dual-gate strained silicon nMOSFET device structure provided by the present invention; Figure 3 This is a schematic diagram showing the surface potential energy distribution along the channel length at different temperatures, as provided by the present invention. Figure 4 This is a schematic diagram illustrating the threshold voltage distribution along the channel length at different temperatures, as provided by the present invention. Figure 5 The threshold voltage versus temperature curve provided by this invention; Figure 6 A schematic diagram of a temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage resolution device provided in this specification; Figure 7 This specification provides a schematic diagram of a computer device for implementing a temperature-dependent analytical method for the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without creative effort are within the scope of protection of this application.

[0023] The server mentioned in this manual can be a server set up on a business platform, or a device such as a desktop computer or laptop computer capable of executing the solution described in this manual. For ease of explanation, the following description will only focus on the server as the execution subject.

[0024] In gate engineering, double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) enhance the gate voltage's control over the channel electric field, exhibiting a more ideal subthreshold slope, reduced drain-induced barrier lowering effect, and improved carrier mobility. Dual-material-gate (DMG) MOSFETs introduce a stepped distribution into the channel surface potential, resulting in a stronger source-end electric field that suppresses short-channel effects and improves carrier efficiency.

[0025] As feature sizes approach physical limits, temperature-induced device parameter drift becomes increasingly prominent. However, a temperature model for the threshold voltage of strained silicon devices is still lacking. Temperature affects several physical parameters of strained silicon conductive channels, including the bandgap, Fermi potential, intrinsic doping concentration, flat-band voltage, and built-in potential, inevitably influencing the channel surface potential and the device's threshold voltage and other electrical characteristics. Increased temperature causes threshold voltage drift, which has significant impacts on precision analog circuits and high-temperature applications. With the increasing use of strained silicon MOSFETs in high-temperature fields such as automotive and aerospace, studying the temperature effects on the device's electrical characteristics and establishing accurate temperature models are crucial for reliable circuit design.

[0026] A symmetrical dual-material, dual-gate strained silicon MOSFET device structure is proposed, employing a partitioned parabolic potential approximation method, general boundary conditions, and structural symmetry conditions to solve the two-dimensional Poisson equation. The flat-band voltage and built-in potential are corrected by incorporating a heterogeneous gate and strained silicon channel. Considering the effects of temperature on various physical parameters such as the bandgap of the strained silicon channel, Fermi potential, intrinsic doping concentration of the channel, flat-band voltage, and built-in potential, a temperature model for the surface potential and threshold voltage under full depletion conditions is established. The model considers various physical quantities, including strain of the strained silicon, channel doping concentration, and gate dielectric constant, and analyzes in detail the impact of temperature variations within the 300K-600K range on the threshold voltage, providing valuable reference for device design.

[0027] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic diagram of a temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method described in this specification, which specifically includes the following steps: S101: Substitute the approximate expression of the potential energy of strained silicon in the vertical direction into the first boundary condition and the structural symmetry condition respectively to obtain the two-dimensional channel potential energy expression; the first boundary condition is used to describe the continuity of the electric flux between the strained silicon layer and the gate dielectric layer; the structural symmetry condition is used to describe the electric flux characteristics at 1 / 2 thickness of the strained silicon channel.

[0029] A schematic diagram of a symmetrical dual-material dual-gate strained silicon nMOSFET device structure is shown below. Figure 2 As shown. The top and bottom grids of this structure are symmetrical, both consisting of a work function of... The control gate M1 and the work function are The shielding grid M2 is composed of work function. Greater than The conductive channel is a strained silicon channel with a channel doping concentration of [missing information]. N A Based on the characteristics of the heterogeneous gate, the channel is divided into two regions, I and II, with corresponding channel lengths L1 and L2, respectively. The channel length L = L1 + L2. The channel thickness is... The thickness of the gate dielectric layer is Assuming the direction parallel to the channel is x The axis, perpendicular to the channel direction is y For the axis, the Poisson equation for the surface potential energy, which depends on temperature, is established in regions I and II of the channel, as shown in formula (1):

[0030] (1); in, For strained silicon in the vertical direction y The potential energy on the surface is approximately represented as follows: For the firstj- The length of a region, For the first j The length of each region The channel doping concentration, The charge of electrons, , The dielectric constant of the channel is . y The coordinate axes are perpendicular to the direction of the channel. x The coordinate axes are parallel to the direction of the channel.

[0031] The potential energy of strained silicon in the vertical direction can be approximately expressed by formula (2): (2); in, For strained silicon in the vertical direction y The potential energy on the surface is approximately represented as follows: To determine the front surface potential of the two regions of the strain silicon channel, j =1,2, , All are with and T The relevant functions, y The coordinate axes are perpendicular to the direction of the channel. x The coordinate axes are parallel to the direction of the channel.

[0032] The first boundary condition is given by formula (3): (3); in, The dielectric constant of the gate dielectric layer is . The dielectric constant of the channel is . Gate-source voltage, This refers to the corrected flat-band voltage between the strained silicon layer and the control gate M1 / shielding gate M2. The thickness of the gate dielectric layer, , T For temperature.

[0033] and These are the corrected flat-band voltages between the strained silicon layer and the control gate M1 / shielding gate M2, taking strain into account. For formula (4): (4); in, It is the electron affinity of bulk silicon materials. It is the bandgap of bulk silicon. It is the intrinsic doping concentration of bulk silicon. N A The channel doping concentration is .

[0034] For formula (5): (5); in, , , , X For strained silicon, For bulk silicon, the valence band state density The valence band density of strained silicon is given.

[0035] The formula for calculating the bandgap of bulk silicon is formula (6): (6); in, The bandgap of bulk silicon.

[0036] The formula for calculating the intrinsic doping concentration of bulk silicon is formula (7): (7); in, The intrinsic doping concentration of bulk silicon, and The effective density of electrons and holes.

[0037] Effective density of electrons The calculation formula is formula (8): (8); Effective density of holes The calculation formula is formula (9): (9); It is a built-in potential correction between the strained silicon layer and the source or drain terminals. For formula (10): (10); in, .

[0038] Based on the first boundary condition, the second boundary condition, and the structural symmetry condition By combining the approximate expression for potential energy (formula (2)), we obtain the expression for channel potential energy.

[0039] S102: Substitute the two-dimensional channel potential energy expression into the Poisson equation, and let the coordinates perpendicular to the channel direction... y The value is 0, which gives the temperature-dependent surface potential equation.

[0040] Substitute the channel potential energy expression into formula (1), and let The temperature-dependent surface potential equation is obtained as formula (11): (11); in, , .

[0041] S103: Solve the surface potential energy equation using the second, third, fourth, and fifth boundary conditions to obtain the analytical expression for the surface potential. The second boundary condition describes the continuity of the surface potential at the junction of the two regions of the strained silicon channel. The third boundary condition describes the continuity of the electric field at the junction of the two regions of the strained silicon channel. The fourth boundary condition describes the continuity of the surface potential at the source end. The fifth boundary condition describes the continuity of the surface potential at the drain end.

[0042] The surface potential and electric field are continuous at the boundary between the two regions, and the second boundary condition is given by formula (12): (12); in, To measure the surface potential of the strain silicon channel near the source region, i.e., region I, at the boundary between the two regions. To determine the surface potential at the interface between the two regions, i.e., region II, near the drain end of the strain silicon channel. T For temperature, The length of region I of channel is given.

[0043] The third boundary condition is given by formula (13): (13); in, To compensate for the channel potential in the region near the source end of the silicon channel, i.e., region I, The channel potential of the strain silicon channel is located in region II, near the drain end.

[0044] The fourth boundary condition is given by formula (14): (14); The fifth boundary condition is given by formula (15): (15); The fourth boundary condition is the source region boundary condition, and the fifth boundary condition is the leak region boundary condition.

[0045] The solution to the surface potential equation is given by formula (16): (16); in, .

[0046] The expression is solved using the boundary conditions of formulas (12)-(15), resulting in formulas (17)-(20): (17); (18); (19); (20); in, , , .

[0047] S104: Take the first derivative of the surface potential analytical expression to obtain the minimum surface potential, and based on the minimum surface potential and the definition of threshold voltage, obtain the threshold voltage temperature model.

[0048] The threshold voltage is determined by the control gate M1 with the higher work function. This is solved using equation (16). The location of the minimum surface potential is calculated using formula (20):

[0049] (20); The minimum surface potential is estimated by formula (21): (twenty one); Threshold voltage is defined as equal Twice the Fermi potential of the region, that is The gate-source voltage at that time. The minimum value of the strained silicon layer surface potential is corrected to formula (22):

[0050] (twenty two); in, .

[0051] Substituting formula (22) into formula (21), we obtain the expression for the threshold voltage-temperature model as formula (23): (twenty three); in, , , , , , .

[0052] in, Threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET T For temperature, , This is the drain-source voltage.

[0053] S105: Solve the threshold voltage temperature model to obtain the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET.

[0054] In an exemplary embodiment, the surface potential temperature model and the threshold temperature voltage model were analyzed and discussed using the following parameters. The gate is assigned a work function. and Metallic materials, gate-source voltage Drain-source voltage Channel doping concentration Source / drain doping concentration gate dielectric layer thickness Strained silicon layer thickness The dielectric constant of the gate dielectric layer ditch length .

[0055] Figure 3 The surface potential energy distribution along the channel length at different temperatures is shown, such as... Figure 3 As shown, the surface potential decreases with increasing temperature. For nMOSFETs, the intrinsic carrier concentration increases with increasing temperature, leading to a decrease in Fermi potential. In the case of weak inversion, the surface potential will also decrease accordingly. Due to the different work functions of the control gate and the shield gate, a potential step distribution is generated at the heterogeneous material gate interface of the channel potential, which is beneficial to further improve the carrier mobility.

[0056] Figure 4 The threshold voltage distribution along the channel length at different temperatures is described. Figure 4 It can be seen that the threshold voltage decreases with increasing temperature. As temperature rises, the surface potential decreases, making it easier to reach the conditions for inversion layer formation, thus lowering the threshold voltage. Increased temperature also enhances carrier thermal motion, significantly lowering the drain-induced barrier and making the short-channel effect more pronounced.

[0057] Figure 5 The curves showing the change of threshold voltage with temperature for different strains are presented. Figure 5It can be seen that the threshold voltage of strained silicon devices decreases with increasing temperature. At the same temperature, the threshold voltage decreases with increasing strain in the conductive channel. This is because the bandgap further decreases, the electron affinity increases, and both the intrinsic carrier concentration and the channel electron areal density increase, leading to a decrease in the threshold voltage. Compared with conventional silicon devices, the threshold voltage change of strained silicon devices is slightly more affected by temperature as the temperature rises. This is because strain narrows the bandgap, reduces the effective mass of carriers, and makes the carrier transport characteristics sensitive to temperature changes, resulting in a more significant threshold voltage drift.

[0058] Based on the two-dimensional Poisson equation, and through general boundary conditions and structural symmetry conditions, an analytical model of the threshold voltage temperature of a symmetric dual-material dual-gate strained silicon MOSFET was accurately solved. The results show that as temperature increases, the surface potential decreases, the threshold voltage decreases, and the short-channel effect becomes significant. The threshold voltage drift of strained silicon devices increases with increasing temperature. Increasing the channel doping concentration reduces the temperature sensitivity of the threshold voltage. Changing the gate dielectric constant does not significantly alter the temperature sensitivity of the threshold voltage. This model provides valuable reference for the design of MOSFET devices at different temperatures.

[0059] When applying the temperature-dependent analytical method for the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET provided in this specification, it is not necessary to consider... Figure 1 The steps shown are executed in sequence. The specific execution order of each step can be determined as needed, and this manual does not impose any restrictions on it.

[0060] The above describes a temperature-dependent method for resolving the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET, as provided in one or more embodiments of this specification. Based on the same idea, this specification also provides a corresponding temperature-dependent apparatus for resolving the threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET, such as... Figure 6 As shown.

[0061] Figure 6 A schematic diagram of a temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage resolution device provided in this specification includes: The first determining module 601 is used to substitute the approximate expression of the potential energy of strained silicon in the vertical direction into the first boundary condition and the structural symmetry condition to obtain the two-dimensional channel potential energy expression; the first boundary condition is used to describe the continuity of the electric flux between the strained silicon layer and the gate dielectric layer; the structural symmetry condition is used to describe the characteristics of the electric flux at 1 / 2 thickness of the strained silicon channel.

[0062] The second determining module 602 is used to substitute the two-dimensional channel potential energy expression into the Poisson equation, and to set the coordinates perpendicular to the channel direction... y The value is 0, which gives the temperature-dependent surface potential equation.

[0063] The third determining module 603 is used to solve the surface potential energy equation from the second boundary condition, the third boundary condition, the fourth boundary condition, and the fifth boundary condition to obtain the analytical expression of the surface potential. The second boundary condition is used to describe the continuity of the surface potential at the junction of the two regions of the strained silicon channel. The third boundary condition is used to describe the continuity of the electric field at the junction of the two regions of the strained silicon channel. The fourth boundary condition is used to describe the continuity of the surface potential at the source end. The fifth boundary condition is used to describe the continuity of the surface potential at the drain end.

[0064] The fourth determining module 604 is used to calculate the first derivative of the surface potential analytical expression to obtain the minimum surface potential, and based on the definition of the minimum surface potential and the threshold voltage, to obtain the threshold voltage temperature model. The calculation module 605 is used to solve the threshold voltage temperature model to obtain the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET.

[0065] Specific limitations regarding the temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis device can be found in the limitations of the temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method described above, and will not be repeated here. Each module in the aforementioned temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the operations corresponding to each module.

[0066] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described... Figure 1 A temperature-dependent analytical method for the threshold voltage of a symmetric dual-material dual-gate strained silicon MOSFET is provided.

[0067] This instruction manual also provides Figure 7 The schematic diagram of the computer device shown is as follows: Figure 7 At the hardware level, the computer device includes a processor, internal bus, network interface, memory, and non-volatile memory, and may also include other hardware required for business operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then runs it to achieve the above-mentioned functions. Figure 1 A temperature-dependent analytical method for the threshold voltage of a symmetric dual-material dual-gate strained silicon MOSFET is provided.

[0068] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0069] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A temperature-dependent analytical method for the threshold voltage of a symmetric dual-material dual-gate strained silicon MOSFET, characterized in that, include: Substituting the approximate expression for the potential energy of strained silicon in the vertical direction into the first boundary condition and the structural symmetry condition, respectively, we obtain the expression for the potential energy of the two-dimensional channel. The first boundary condition is used to describe the continuity of electrical flux between the strained silicon layer and the gate dielectric layer; The structural symmetry condition is used to describe the electrical flux characteristics at 1 / 2 thickness of the strained silicon channel. Substituting the two-dimensional channel potential energy expression into the Poisson equation, and letting the coordinates perpendicular to the channel direction... y When the value is 0, the temperature-dependent surface potential equation is obtained; The surface potential energy equation is solved using the second, third, fourth, and fifth boundary conditions to obtain the analytical expression for the surface potential. The second boundary condition describes the continuity of the surface potential at the boundary between the two regions of the strained silicon channel; the third boundary condition describes the continuity of the electric field at the boundary between the two regions of the strained silicon channel; the fourth boundary condition describes the continuity of the surface potential at the source end; and the fifth boundary condition describes the continuity of the surface potential at the drain end. The first derivative of the surface potential is obtained by taking the first derivative of the analytical expression of the surface potential, and the minimum value of the surface potential is obtained based on the minimum value of the surface potential and the definition of the threshold voltage. The threshold voltage temperature model is then obtained. The threshold voltage temperature model is solved to obtain the threshold voltage of the symmetrical dual-material dual-gate strained silicon MOSFET.

2. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 1, characterized in that, The approximate expression for the potential energy of the strained silicon in the vertical direction is: ； in, For strained silicon in the vertical direction y The potential energy on the surface is approximately represented as follows: To determine the front surface potential of the two regions of the strain silicon channel, j =1,2, , All are with and T The relevant functions, y The coordinate axes are perpendicular to the direction of the channel. x The coordinate axes are parallel to the direction of the channel.

3. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 2, characterized in that, The first boundary condition is: ； in, The dielectric constant of the gate dielectric layer is . The dielectric constant of the channel is . Gate-source voltage, This refers to the corrected flat-band voltage between the strained silicon layer and the control gate M1 / shielding gate M2. The thickness of the gate dielectric layer, , T For temperature; The structural symmetry condition is: ； in, This refers to the channel thickness.

4. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 3, characterized in that, The expression for the two-dimensional channel potential energy is: 。 5. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 1, characterized in that, The Poisson equation is: ； in, For strained silicon in the vertical direction y The potential energy on the surface is approximately represented as follows: The channel doping concentration, The charge of electrons, , For the first j- The length of a region, For the first j The length of each region The dielectric constant of the channel is . y The coordinate axes are perpendicular to the direction of the channel. x The coordinate axes are parallel to the direction of the channel; The temperature-dependent surface potential equation is: ； ； ； in, To determine the front surface potential of the two regions of the strain silicon channel, j =1,2, For the channel thickness, The thickness of the gate dielectric layer, The dielectric constant of the gate dielectric layer is . The dielectric constant of the gate dielectric layer is . The corrected flat band voltage between the strained silicon layer and the control gate M1 / shielding gate M2.

6. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 5, characterized in that, The second boundary condition is: ； in, To measure the surface potential of the strain silicon channel near the source region, i.e., region I, at the boundary between the two regions. To determine the surface potential at the interface between the two regions, i.e., region II, near the drain end of the strain silicon channel. T For temperature, The length of region I of channel; The third boundary condition is: ； in, To compensate for the channel potential in the region near the source end of the silicon channel, i.e., region I, To compensate for the channel potential of the silicon channel near the drain region, i.e., region II; The fourth boundary condition is: ； in, For the source end surface potential of the strain silicon channel, This is the built-in potential between the strain silicon layer and the source or drain terminal; The fifth boundary condition is: in, To the surface potential at the drain end of the strain silicon channel, This is the drain-source voltage.

7. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 6, characterized in that, The analytical expression for the surface potential is: ； in, , , , , , , , , , L=L 1 +L 2 The length of the channel. The length of region I of channel is The length of region II of the channel. , .

8. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 7, characterized in that, The minimum surface potential value is: ； in, This represents the minimum surface potential.

9. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 8, characterized in that, The threshold voltage is defined as satisfying Gate-source voltage at that time; in, , , for Fermi potential within the region, , This is a correction value for the minimum surface potential of the strained silicon layer. k Boltzmann's constant, T For temperature, The intrinsic doping concentration of bulk silicon, The strain is the Fermi potential. The strain is the bandgap width of silicon. For bulk silicon, the valence band state density The valence band density of strained silicon is given.

10. The temperature-dependent symmetric dual-material dual-gate strained silicon MOSFET threshold voltage analysis method as described in claim 9, characterized in that, The formula corresponding to the threshold voltage-temperature model is: ； ； ； ； ； in, Threshold voltage of a symmetrical dual-material dual-gate strained silicon MOSFET T For temperature, , This is the drain-source voltage.

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